LLVM  14.0.0git
ARMInstrInfo.cpp
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1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMInstrInfo.h"
14 #include "ARM.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCInst.h"
29 using namespace llvm;
30 
32  : ARMBaseInstrInfo(STI), RI() {}
33 
34 /// Return the noop instruction to use for a noop.
36  MCInst NopInst;
37  if (hasNOP()) {
38  NopInst.setOpcode(ARM::HINT);
39  NopInst.addOperand(MCOperand::createImm(0));
41  NopInst.addOperand(MCOperand::createReg(0));
42  } else {
43  NopInst.setOpcode(ARM::MOVr);
44  NopInst.addOperand(MCOperand::createReg(ARM::R0));
45  NopInst.addOperand(MCOperand::createReg(ARM::R0));
47  NopInst.addOperand(MCOperand::createReg(0));
48  NopInst.addOperand(MCOperand::createReg(0));
49  }
50  return NopInst;
51 }
52 
53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54  switch (Opc) {
55  default:
56  break;
57  case ARM::LDR_PRE_IMM:
58  case ARM::LDR_PRE_REG:
59  case ARM::LDR_POST_IMM:
60  case ARM::LDR_POST_REG:
61  return ARM::LDRi12;
62  case ARM::LDRH_PRE:
63  case ARM::LDRH_POST:
64  return ARM::LDRH;
65  case ARM::LDRB_PRE_IMM:
66  case ARM::LDRB_PRE_REG:
67  case ARM::LDRB_POST_IMM:
68  case ARM::LDRB_POST_REG:
69  return ARM::LDRBi12;
70  case ARM::LDRSH_PRE:
71  case ARM::LDRSH_POST:
72  return ARM::LDRSH;
73  case ARM::LDRSB_PRE:
74  case ARM::LDRSB_POST:
75  return ARM::LDRSB;
76  case ARM::STR_PRE_IMM:
77  case ARM::STR_PRE_REG:
78  case ARM::STR_POST_IMM:
79  case ARM::STR_POST_REG:
80  return ARM::STRi12;
81  case ARM::STRH_PRE:
82  case ARM::STRH_POST:
83  return ARM::STRH;
84  case ARM::STRB_PRE_IMM:
85  case ARM::STRB_PRE_REG:
86  case ARM::STRB_POST_IMM:
87  case ARM::STRB_POST_REG:
88  return ARM::STRBi12;
89  }
90 
91  return 0;
92 }
93 
94 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
95  MachineFunction &MF = *MI->getParent()->getParent();
96  const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
97  const TargetMachine &TM = MF.getTarget();
98 
99  if (!Subtarget.useMovt()) {
100  if (TM.isPositionIndependent())
101  expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
102  else
103  expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
104  return;
105  }
106 
107  if (!TM.isPositionIndependent()) {
108  expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
109  return;
110  }
111 
112  const GlobalValue *GV =
113  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
114 
115  if (!Subtarget.isGVIndirectSymbol(GV)) {
116  expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
117  return;
118  }
119 
120  MachineBasicBlock &MBB = *MI->getParent();
121  DebugLoc DL = MI->getDebugLoc();
122  Register Reg = MI->getOperand(0).getReg();
124 
125  MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
127  auto Flags = MachineMemOperand::MOLoad |
131  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, Align(4));
132  MIB.addMemOperand(MMO);
133  BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
135  .addImm(0)
136  .cloneMemRefs(*MI)
137  .add(predOps(ARMCC::AL));
138 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:431
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
ARMMachineFunctionInfo.h
MachineJumpTableInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::ARMBaseInstrInfo::expandLoadStackGuardBase
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
Definition: ARMBaseInstrInfo.cpp:4889
MachineRegisterInfo.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
ARMConstantPoolValue.h
llvm::ARMInstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: ARMInstrInfo.cpp:53
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:428
MCInst.h
LiveVariables.h
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1017
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMInstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: ARMInstrInfo.cpp:35
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ARMInstrInfo::ARMInstrInfo
ARMInstrInfo(const ARMSubtarget &STI)
Definition: ARMInstrInfo.cpp:31
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ARMII::MO_NONLAZY
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
Definition: ARMBaseInfo.h:284
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
ARM.h
llvm::MachineFunction
Definition: MachineFunction.h:234
ARMAddressingModes.h
MCAsmInfo.h
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
ARMInstrInfo.h
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:630
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
MachineFrameInfo.h
GlobalVariable.h
Function.h
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::ARMBaseInstrInfo::hasNOP
bool hasNOP() const
Definition: ARMBaseInstrInfo.cpp:5353
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:356
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:540
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
ARMTargetMachine.h
llvm::MachineInstrBundleIterator< MachineInstr >