LLVM  14.0.0git
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 
15 #include "ARMCallLowering.h"
16 #include "ARMLegalizerInfo.h"
17 #include "ARMRegisterBankInfo.h"
18 #include "ARMSubtarget.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/ADT/Twine.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/Support/CodeGen.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "arm-subtarget"
44 
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "ARMGenSubtargetInfo.inc"
48 
49 static cl::opt<bool>
50 UseFusedMulOps("arm-use-mulops",
51  cl::init(true), cl::Hidden);
52 
53 enum ITMode {
57 };
58 
59 static cl::opt<ITMode>
60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
62  cl::values(clEnumValN(DefaultIT, "arm-default-it",
63  "Generate IT block based on arch"),
64  clEnumValN(RestrictedIT, "arm-restrict-it",
65  "Disallow deprecated IT based on ARMv8"),
66  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
67  "Allow IT blocks based on ARMv7")));
68 
69 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
70 /// currently supported (for testing only).
71 static cl::opt<bool>
72 ForceFastISel("arm-force-fast-isel",
73  cl::init(false), cl::Hidden);
74 
75 static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
76  cl::init(false), cl::Hidden);
77 
78 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
79 /// so that we can use initializer lists for subtarget initialization.
81  StringRef FS) {
82  initializeEnvironment();
83  initSubtargetFeatures(CPU, FS);
84  return *this;
85 }
86 
87 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
88  StringRef FS) {
90  if (STI.isThumb1Only())
91  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
92 
93  return new ARMFrameLowering(STI);
94 }
95 
96 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
97  const std::string &FS,
98  const ARMBaseTargetMachine &TM, bool IsLittle,
99  bool MinSize)
100  : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
101  UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
102  IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
103  FrameLowering(initializeFrameLowering(CPU, FS)),
104  // At this point initializeSubtargetDependencies has been called so
105  // we can query directly.
106  InstrInfo(isThumb1Only()
108  : !isThumb()
111  TLInfo(TM, *this) {
112 
113  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
114  Legalizer.reset(new ARMLegalizerInfo(*this));
115 
116  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
117 
118  // FIXME: At this point, we can't rely on Subtarget having RBI.
119  // It's awkward to mix passing RBI and the Subtarget; should we pass
120  // TII/TRI as well?
121  InstSelector.reset(createARMInstructionSelector(
122  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
123 
124  RegBankInfo.reset(RBI);
125 }
126 
128  return CallLoweringInfo.get();
129 }
130 
132  return InstSelector.get();
133 }
134 
136  return Legalizer.get();
137 }
138 
140  return RegBankInfo.get();
141 }
142 
144  // We don't currently suppport Thumb, but Windows requires Thumb.
145  return hasV6Ops() && hasARMOps() && !isTargetWindows();
146 }
147 
148 void ARMSubtarget::initializeEnvironment() {
149  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
150  // directly from it, but we can try to make sure they're consistent when both
151  // available.
155  assert((!TM.getMCAsmInfo() ||
158  "inconsistent sjlj choice between CodeGen and MC");
159 }
160 
161 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
162  if (CPUString.empty()) {
163  CPUString = "generic";
164 
165  if (isTargetDarwin()) {
166  StringRef ArchName = TargetTriple.getArchName();
167  ARM::ArchKind AK = ARM::parseArch(ArchName);
168  if (AK == ARM::ArchKind::ARMV7S)
169  // Default to the Swift CPU when targeting armv7s/thumbv7s.
170  CPUString = "swift";
171  else if (AK == ARM::ArchKind::ARMV7K)
172  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
173  // ARMv7k does not use SjLj exception handling.
174  CPUString = "cortex-a7";
175  }
176  }
177 
178  // Insert the architecture feature derived from the target triple into the
179  // feature string. This is important for setting features that are implied
180  // based on the architecture version.
181  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
182  if (!FS.empty()) {
183  if (!ArchFS.empty())
184  ArchFS = (Twine(ArchFS) + "," + FS).str();
185  else
186  ArchFS = std::string(FS);
187  }
188  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
189 
190  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
191  // Assert this for now to make the change obvious.
192  assert(hasV6T2Ops() || !hasThumb2());
193 
194  // Execute only support requires movt support
195  if (genExecuteOnly()) {
196  NoMovt = false;
197  assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
198  }
199 
200  // Keep a pointer to static instruction cost data for the specified CPU.
201  SchedModel = getSchedModelForCPU(CPUString);
202 
203  // Initialize scheduling itinerary for the specified CPU.
204  InstrItins = getInstrItineraryForCPU(CPUString);
205 
206  // FIXME: this is invalid for WindowsCE
207  if (isTargetWindows())
208  NoARM = true;
209 
210  if (isAAPCS_ABI())
211  stackAlignment = Align(8);
212  if (isTargetNaCl() || isAAPCS16_ABI())
213  stackAlignment = Align(16);
214 
215  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
216  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
217  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
218  // support in the assembler and linker to be used. This would need to be
219  // fixed to fully support tail calls in Thumb1.
220  //
221  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
222  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
223  // means if we need to reload LR, it takes extra instructions, which outweighs
224  // the value of the tail call; but here we don't know yet whether LR is going
225  // to be used. We take the optimistic approach of generating the tail call and
226  // perhaps taking a hit if we need to restore the LR.
227 
228  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
229  // but we need to make sure there are enough registers; the only valid
230  // registers are the 4 used for parameters. We don't currently do this
231  // case.
232 
234 
235  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
236  SupportsTailCall = false;
237 
238  switch (IT) {
239  case DefaultIT:
240  RestrictIT = hasV8Ops() && !hasMinSize();
241  break;
242  case RestrictedIT:
243  RestrictIT = true;
244  break;
245  case NoRestrictedIT:
246  RestrictIT = false;
247  break;
248  }
249 
250  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
251  const FeatureBitset &Bits = getFeatureBits();
252  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
255 
256  if (isRWPI())
257  ReserveR9 = true;
258 
259  // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
260  if (MVEVectorCostFactor == 0)
262 
263  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
264  switch (ARMProcFamily) {
265  case Others:
266  case CortexA5:
267  break;
268  case CortexA7:
270  break;
271  case CortexA8:
273  break;
274  case CortexA9:
277  break;
278  case CortexA12:
279  break;
280  case CortexA15:
284  break;
285  case CortexA17:
286  case CortexA32:
287  case CortexA35:
288  case CortexA53:
289  case CortexA55:
290  case CortexA57:
291  case CortexA72:
292  case CortexA73:
293  case CortexA75:
294  case CortexA76:
295  case CortexA77:
296  case CortexA78:
297  case CortexA78C:
298  case CortexA710:
299  case CortexR4:
300  case CortexR4F:
301  case CortexR5:
302  case CortexR7:
303  case CortexM3:
304  case CortexM7:
305  case CortexR52:
306  case CortexX1:
307  break;
308  case Exynos:
311  if (!isThumb())
313  break;
314  case Kryo:
315  break;
316  case Krait:
318  break;
319  case NeoverseN1:
320  case NeoverseN2:
321  case NeoverseV1:
322  break;
323  case Swift:
328  break;
329  }
330 }
331 
333 
337 }
342 }
346 }
347 
348 bool ARMSubtarget::isROPI() const {
349  return TM.getRelocationModel() == Reloc::ROPI ||
351 }
352 bool ARMSubtarget::isRWPI() const {
353  return TM.getRelocationModel() == Reloc::RWPI ||
355 }
356 
358  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
359  return true;
360 
361  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
362  // the section that is being relocated. This means we have to use o load even
363  // for GVs that are known to be local to the dso.
365  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
366  return true;
367 
368  return false;
369 }
370 
371 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
372  return isTargetELF() && TM.isPositionIndependent() &&
373  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
374 }
375 
378 }
379 
381  // The MachineScheduler can increase register usage, so we use more high
382  // registers and end up with more T2 instructions that cannot be converted to
383  // T1 instructions. At least until we do better at converting to thumb1
384  // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
385  // Machine scheduler, relying on the DAG register pressure scheduler instead.
386  if (isMClass() && hasMinSize())
387  return false;
388  // Enable the MachineScheduler before register allocation for subtargets
389  // with the use-misched feature.
390  return useMachineScheduler();
391 }
392 
395  return EnableSubRegLiveness;
396  // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
397  // and q subregs for qqqqpr regs.
398  return hasMVEIntegerOps();
399 }
400 
401 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
404  return false;
406  return false;
407  // Thumb1 cores will generally not benefit from post-ra scheduling
408  return !isThumb1Only();
409 }
410 
412  if (!enableMachineScheduler())
413  return false;
415  return false;
416  return !isThumb1Only();
417 }
418 
420 
422  // For general targets, the prologue can grow when VFPs are allocated with
423  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
424  // format which it's more important to get right.
425  return isTargetWatchABI() ||
427 }
428 
429 bool ARMSubtarget::useMovt() const {
430  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
431  // immediates as it is inherently position independent, and may be out of
432  // range otherwise.
433  return !NoMovt && hasV8MBaselineOps() &&
435 }
436 
438  // Enable fast-isel for any target, for testing only.
439  if (ForceFastISel)
440  return true;
441 
442  // Limit fast-isel to the targets that are or have been tested.
443  if (!hasV6Ops())
444  return false;
445 
446  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
447  return TM.Options.EnableFastISel &&
448  ((isTargetMachO() && !isThumb1Only()) ||
449  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
450 }
451 
453  // The GPR register class has multiple possible allocation orders, with
454  // tradeoffs preferred by different sub-architectures and optimisation goals.
455  // The allocation orders are:
456  // 0: (the default tablegen order, not used)
457  // 1: r14, r0-r13
458  // 2: r0-r7
459  // 3: r0-r7, r12, lr, r8-r11
460  // Note that the register allocator will change this order so that
461  // callee-saved registers are used later, as they require extra work in the
462  // prologue/epilogue (though we sometimes override that).
463 
464  // For thumb1-only targets, only the low registers are allocatable.
465  if (isThumb1Only())
466  return 2;
467 
468  // Allocate low registers first, so we can select more 16-bit instructions.
469  // We also (in ignoreCSRForAllocationOrder) override the default behaviour
470  // with regards to callee-saved registers, because pushing extra registers is
471  // much cheaper (in terms of code size) than using high registers. After
472  // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
473  // can return with the pop, don't need an extra "bx lr") and then the rest of
474  // the high registers.
475  if (isThumb2() && MF.getFunction().hasMinSize())
476  return 3;
477 
478  // Otherwise, allocate in the default order, using LR first because saving it
479  // allows a shorter epilogue sequence.
480  return 1;
481 }
482 
484  unsigned PhysReg) const {
485  // To minimize code size in Thumb2, we prefer the usage of low regs (lower
486  // cost per use) so we can use narrow encoding. By default, caller-saved
487  // registers (e.g. lr, r12) are always allocated first, regardless of
488  // their cost per use. When optForMinSize, we prefer the low regs even if
489  // they are CSR because usually push/pop can be folded into existing ones.
490  return isThumb2() && MF.getFunction().hasMinSize() &&
491  ARM::GPRRegClass.contains(PhysReg);
492 }
llvm::ARMSubtarget::SupportsTailCall
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:272
llvm::ARMSubtarget::CortexA17
@ CortexA17
Definition: ARMSubtarget.h:54
ARMSubtarget.h
llvm::ARMSubtarget::UseSjLjEH
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:476
llvm::ARMBaseTargetMachine::ARM_ABI_APCS
@ ARM_ABI_APCS
Definition: ARMTargetMachine.h:31
llvm::ARMSubtarget::TM
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:549
llvm::ARMSubtarget::CortexR7
@ CortexR7
Definition: ARMSubtarget.h:78
llvm::ARMSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
Definition: ARMSubtarget.cpp:393
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:153
llvm::ARMSubtarget::hasARMOps
bool hasARMOps() const
Definition: ARMSubtarget.h:673
llvm::GlobalValue::hasCommonLinkage
bool hasCommonLinkage() const
Definition: GlobalValue.h:455
llvm::createARMInstructionSelector
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
Definition: ARMInstructionSelector.cpp:160
MCTargetOptions.h
llvm::ARMSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: ARMSubtarget.cpp:135
ARMMCTargetDesc.h
llvm::ARMSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
Definition: ARMSubtarget.cpp:380
llvm::ARMSubtarget::NoARM
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:260
llvm::ARMSubtarget::CortexA57
@ CortexA57
Definition: ARMSubtarget.h:60
ARMGenSubtargetInfo
ARMCallLowering.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
StringRef.h
llvm::ARMSubtarget::getMispredictionPenalty
unsigned getMispredictionPenalty() const
Definition: ARMSubtarget.cpp:376
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS
@ ARM_ABI_AAPCS
Definition: ARMTargetMachine.h:32
llvm::ARMSubtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:153
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::ARMSubtarget::hasV6T2Ops
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:632
llvm::ARMSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:769
llvm::ARMSubtarget::isRWPI
bool isRWPI() const
Definition: ARMSubtarget.cpp:352
llvm::ARMSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:70
llvm::ARMSubtarget::hasThumb2
bool hasThumb2() const
Definition: ARMSubtarget.h:833
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:587
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
InstructionSelect.h
llvm::Reloc::ROPI_RWPI
@ ROPI_RWPI
Definition: CodeGen.h:22
llvm::ARMSubtarget::CortexM7
@ CortexM7
Definition: ARMSubtarget.h:73
Thumb1InstrInfo.h
llvm::ARMSubtarget::hasMVEIntegerOps
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:650
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
DefaultIT
@ DefaultIT
Definition: ARMSubtarget.cpp:54
Thumb1FrameLowering.h
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16
@ ARM_ABI_AAPCS16
Definition: ARMTargetMachine.h:33
llvm::ARMSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: ARMSubtarget.h:775
TargetParser.h
llvm::ARMSubtarget::Kryo
@ Kryo
Definition: ARMSubtarget.h:82
llvm::ARMSubtarget::isTargetWatchABI
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:774
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
llvm::ARMSubtarget::OptMinSize
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:528
CommandLine.h
llvm::ARMSubtarget::NeoverseN1
@ NeoverseN1
Definition: ARMSubtarget.h:83
llvm::Thumb1FrameLowering
Definition: Thumb1FrameLowering.h:19
llvm::ARMLegalizerInfo
This class provides the information for the target register banks.
Definition: ARMLegalizerInfo.h:27
llvm::ARMSubtarget::CortexA73
@ CortexA73
Definition: ARMSubtarget.h:63
GlobalValue.h
llvm::MCSchedModel::MispredictPenalty
unsigned MispredictPenalty
Definition: MCSchedule.h:297
llvm::ARMSubtarget::CortexR5
@ CortexR5
Definition: ARMSubtarget.h:76
llvm::ARMSubtarget::NeoverseN2
@ NeoverseN2
Definition: ARMSubtarget.h:84
llvm::ARMBaseTargetMachine::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMTargetMachine.h:64
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("arm-enable-subreg-liveness", cl::init(false), cl::Hidden)
llvm::ARMSubtarget::SchedModel
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:537
llvm::ARMSubtarget::disablePostRAScheduler
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:827
llvm::ARMSubtarget::enableAtomicExpand
bool enableAtomicExpand() const override
Definition: ARMSubtarget.cpp:419
llvm::ARMSubtarget::MaxInterleaveFactor
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:505
llvm::Legalizer
Definition: Legalizer.h:30
llvm::ARMSubtarget::CortexA72
@ CortexA72
Definition: ARMSubtarget.h:62
Twine.h
llvm::ARMSubtarget::DoubleIssue
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:140
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:429
llvm::ARMSubtarget::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMSubtarget.cpp:332
llvm::ARMSubtarget::isAAPCS16_ABI
bool isAAPCS16_ABI() const
Definition: ARMSubtarget.cpp:343
llvm::ARMSubtarget::CortexA55
@ CortexA55
Definition: ARMSubtarget.h:59
llvm::TargetOptions::ExceptionModel
ExceptionHandling ExceptionModel
What exception model to use.
Definition: TargetOptions.h:420
llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:402
llvm::ARMSubtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:519
llvm::ARMSubtarget::CortexA78C
@ CortexA78C
Definition: ARMSubtarget.h:68
llvm::Triple::getArchName
StringRef getArchName() const
Get the architecture (first) component of the triple.
Definition: Triple.cpp:1047
llvm::ARMSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:402
llvm::ARMSubtarget::hasV6Ops
bool hasV6Ops() const
Definition: ARMSubtarget.h:629
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:28
llvm::ARMSubtarget::CortexA7
@ CortexA7
Definition: ARMSubtarget.h:61
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:139
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::X86AS::FS
@ FS
Definition: X86.h:188
ITMode
ITMode
Definition: ARMSubtarget.cpp:53
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::ARMSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:534
llvm::ARMSubtarget::CortexA9
@ CortexA9
Definition: ARMSubtarget.h:71
llvm::cl::opt< bool >
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:697
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:831
llvm::ARMSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:540
llvm::ARMSubtarget::LdStMultipleTiming
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:512
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
NoRestrictedIT
@ NoRestrictedIT
Definition: ARMSubtarget.cpp:56
llvm::ARMSubtarget::ARMSubtarget
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Definition: ARMSubtarget.cpp:96
llvm::ARMSubtarget::CortexA75
@ CortexA75
Definition: ARMSubtarget.h:64
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:834
llvm::ARMSubtarget::stackAlignment
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:500
llvm::ARMSubtarget::initializeSubtargetDependencies
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: ARMSubtarget.cpp:80
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::ARMSubtarget::isTargetIOS
bool isTargetIOS() const
Definition: ARMSubtarget.h:772
llvm::ARMSubtarget::CPUString
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:503
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:781
llvm::ARMSubtarget::NoMovt
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:267
llvm::ARMSubtarget::MVEVectorCostFactor
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:524
llvm::ARMSubtarget::Options
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:547
llvm::ARMSubtarget::RestrictIT
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:457
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:348
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::ARMSubtarget::CortexA77
@ CortexA77
Definition: ARMSubtarget.h:66
llvm::ARMSubtarget::enablePostRAMachineScheduler
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:411
llvm::Reloc::ROPI
@ ROPI
Definition: CodeGen.h:22
llvm::ARMSubtarget::CortexM3
@ CortexM3
Definition: ARMSubtarget.h:72
ARM.h
llvm::ARMSubtarget::useFastISel
bool useFastISel() const
True if fast-isel is used.
Definition: ARMSubtarget.cpp:437
llvm::TargetOptions::EnableFastISel
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
Definition: TargetOptions.h:230
llvm::ARMRegisterBankInfo
This class provides the information for the target register banks.
Definition: ARMRegisterBankInfo.h:31
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ARMSubtarget::Exynos
@ Exynos
Definition: ARMSubtarget.h:80
Triple.h
TargetOptions.h
llvm::Reloc::RWPI
@ RWPI
Definition: CodeGen.h:22
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:208
llvm::ARMSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: ARMSubtarget.cpp:127
IT
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
MCAsmInfo.h
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:595
llvm::ARMSubtarget::CortexR4F
@ CortexR4F
Definition: ARMSubtarget.h:75
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::ARMSubtarget::useMachineScheduler
bool useMachineScheduler() const
Definition: ARMSubtarget.h:826
llvm::ARMSubtarget::PartialUpdateClearance
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:508
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:672
llvm::ARMSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: ARMSubtarget.cpp:131
llvm::ARMSubtarget::UseNEONForSinglePrecisionFP
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:222
llvm::TargetMachine::shouldAssumeDSOLocal
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Definition: TargetMachine.cpp:94
ARMInstrInfo.h
llvm::ARMSubtarget::CortexA15
@ CortexA15
Definition: ARMSubtarget.h:53
llvm::ARMSubtarget::PreISelOperandLatencyAdjustment
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:516
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:778
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:371
llvm::ARMSubtarget::ignoreCSRForAllocationOrder
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMSubtarget.cpp:483
llvm::ARMSubtarget::Swift
@ Swift
Definition: ARMSubtarget.h:86
llvm::ARMSubtarget::CortexR4
@ CortexR4
Definition: ARMSubtarget.h:74
llvm::ARMSubtarget::CortexR52
@ CortexR52
Definition: ARMSubtarget.h:77
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:104
ARMFrameLowering.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:771
llvm::ARMSubtarget::Krait
@ Krait
Definition: ARMSubtarget.h:81
Thumb2InstrInfo.h
llvm::ARMSubtarget::isAPCS_ABI
bool isAPCS_ABI() const
Definition: ARMSubtarget.cpp:334
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
ARMRegisterBankInfo.h
Function.h
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:782
llvm::ARMSubtarget::isAAPCS_ABI
bool isAAPCS_ABI() const
Definition: ARMSubtarget.cpp:338
llvm::Thumb2InstrInfo
Definition: Thumb2InstrInfo.h:22
llvm::ARMSubtarget::NeoverseV1
@ NeoverseV1
Definition: ARMSubtarget.h:85
llvm::ARMSubtarget::Others
@ Others
Definition: ARMSubtarget.h:50
llvm::ARMCallLowering
Definition: ARMCallLowering.h:30
llvm::ARMSubtarget::CortexX1
@ CortexX1
Definition: ARMSubtarget.h:79
llvm::ARMSubtarget::SingleIssuePlusExtras
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:148
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::ARMBaseTargetMachine::TargetABI
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
CodeGen.h
llvm::ARMInstrInfo
Definition: ARMInstrInfo.h:22
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
llvm::ARMSubtarget::CortexA8
@ CortexA8
Definition: ARMSubtarget.h:70
ForceFastISel
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
llvm::ARMSubtarget::CortexA12
@ CortexA12
Definition: ARMSubtarget.h:52
RestrictedIT
@ RestrictedIT
Definition: ARMSubtarget.cpp:55
llvm::ARMSubtarget::CortexA76
@ CortexA76
Definition: ARMSubtarget.h:65
llvm::ARMSubtarget::ReserveR9
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:263
llvm::ARMSubtarget::CortexA35
@ CortexA35
Definition: ARMSubtarget.h:56
llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN
@ ARM_ABI_UNKNOWN
Definition: ARMTargetMachine.h:30
llvm::ARMSubtarget::CortexA78
@ CortexA78
Definition: ARMSubtarget.h:67
llvm::ARMSubtarget::hasMinSize
bool hasMinSize() const
Definition: ARMSubtarget.h:830
llvm::ARMSubtarget::CortexA53
@ CortexA53
Definition: ARMSubtarget.h:58
llvm::GlobalValue::isDeclarationForLinker
bool isDeclarationForLinker() const
Definition: GlobalValue.h:540
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:357
llvm::ARMSubtarget::hasV8MBaselineOps
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:647
llvm::TargetOptions::UnsafeFPMath
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Definition: TargetOptions.h:161
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:658
llvm::ARMSubtarget::CortexA5
@ CortexA5
Definition: ARMSubtarget.h:57
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1143
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMSubtarget::CortexA32
@ CortexA32
Definition: ARMSubtarget.h:55
llvm::ARMSubtarget::isThumb2
bool isThumb2() const
Definition: ARMSubtarget.h:832
llvm::ARMSubtarget::CortexA710
@ CortexA710
Definition: ARMSubtarget.h:69
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ARMSubtarget::getGPRAllocationOrder
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:452
ARMLegalizerInfo.h
ARMTargetMachine.h
llvm::ARMSubtarget::useWideStrideVFP
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:729
MachineFunction.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::ARMSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: ARMSubtarget.h:776
llvm::ARMSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: ARMSubtarget.cpp:143
llvm::ARMSubtarget::hasAnyDataBarrier
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:701
llvm::ARMSubtarget::useStride4VFPs
bool useStride4VFPs() const
Definition: ARMSubtarget.cpp:421
llvm::ARMSubtarget::genExecuteOnly
bool genExecuteOnly() const
Definition: ARMSubtarget.h:748
llvm::ARMSubtarget::isThumb
bool isThumb() const
Definition: ARMSubtarget.h:829
llvm::ARMSubtarget::hasV8Ops
bool hasV8Ops() const
Definition: ARMSubtarget.h:634
UseFusedMulOps
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)