LLVM  16.0.0git
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 
15 #include "ARMCallLowering.h"
16 #include "ARMLegalizerInfo.h"
17 #include "ARMRegisterBankInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/Support/CodeGen.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "arm-subtarget"
45 
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
49 
50 static cl::opt<bool>
51 UseFusedMulOps("arm-use-mulops",
52  cl::init(true), cl::Hidden);
53 
54 enum ITMode {
57 };
58 
59 static cl::opt<ITMode>
60  IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
61  cl::values(clEnumValN(DefaultIT, "arm-default-it",
62  "Generate any type of IT block"),
63  clEnumValN(RestrictedIT, "arm-restrict-it",
64  "Disallow complex IT blocks")));
65 
66 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
67 /// currently supported (for testing only).
68 static cl::opt<bool>
69 ForceFastISel("arm-force-fast-isel",
70  cl::init(false), cl::Hidden);
71 
72 static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
73  cl::init(false), cl::Hidden);
74 
75 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
76 /// so that we can use initializer lists for subtarget initialization.
78  StringRef FS) {
79  initializeEnvironment();
80  initSubtargetFeatures(CPU, FS);
81  return *this;
82 }
83 
84 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
85  StringRef FS) {
87  if (STI.isThumb1Only())
88  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
89 
90  return new ARMFrameLowering(STI);
91 }
92 
93 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
94  const std::string &FS,
95  const ARMBaseTargetMachine &TM, bool IsLittle,
96  bool MinSize)
97  : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
98  UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
99  IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
100  FrameLowering(initializeFrameLowering(CPU, FS)),
101  // At this point initializeSubtargetDependencies has been called so
102  // we can query directly.
103  InstrInfo(isThumb1Only()
105  : !isThumb()
108  TLInfo(TM, *this) {
109 
110  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
111  Legalizer.reset(new ARMLegalizerInfo(*this));
112 
113  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
114 
115  // FIXME: At this point, we can't rely on Subtarget having RBI.
116  // It's awkward to mix passing RBI and the Subtarget; should we pass
117  // TII/TRI as well?
118  InstSelector.reset(createARMInstructionSelector(
119  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
120 
121  RegBankInfo.reset(RBI);
122 }
123 
125  return CallLoweringInfo.get();
126 }
127 
129  return InstSelector.get();
130 }
131 
133  return Legalizer.get();
134 }
135 
137  return RegBankInfo.get();
138 }
139 
141  // We don't currently suppport Thumb, but Windows requires Thumb.
142  return hasV6Ops() && hasARMOps() && !isTargetWindows();
143 }
144 
145 void ARMSubtarget::initializeEnvironment() {
146  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
147  // directly from it, but we can try to make sure they're consistent when both
148  // available.
152  assert((!TM.getMCAsmInfo() ||
155  "inconsistent sjlj choice between CodeGen and MC");
156 }
157 
158 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
159  if (CPUString.empty()) {
160  CPUString = "generic";
161 
162  if (isTargetDarwin()) {
163  StringRef ArchName = TargetTriple.getArchName();
164  ARM::ArchKind AK = ARM::parseArch(ArchName);
165  if (AK == ARM::ArchKind::ARMV7S)
166  // Default to the Swift CPU when targeting armv7s/thumbv7s.
167  CPUString = "swift";
168  else if (AK == ARM::ArchKind::ARMV7K)
169  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
170  // ARMv7k does not use SjLj exception handling.
171  CPUString = "cortex-a7";
172  }
173  }
174 
175  // Insert the architecture feature derived from the target triple into the
176  // feature string. This is important for setting features that are implied
177  // based on the architecture version.
178  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
179  if (!FS.empty()) {
180  if (!ArchFS.empty())
181  ArchFS = (Twine(ArchFS) + "," + FS).str();
182  else
183  ArchFS = std::string(FS);
184  }
185  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
186 
187  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
188  // Assert this for now to make the change obvious.
189  assert(hasV6T2Ops() || !hasThumb2());
190 
191  // Execute only support requires movt support
192  if (genExecuteOnly()) {
193  NoMovt = false;
194  assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
195  }
196 
197  // Keep a pointer to static instruction cost data for the specified CPU.
198  SchedModel = getSchedModelForCPU(CPUString);
199 
200  // Initialize scheduling itinerary for the specified CPU.
201  InstrItins = getInstrItineraryForCPU(CPUString);
202 
203  // FIXME: this is invalid for WindowsCE
204  if (isTargetWindows())
205  NoARM = true;
206 
207  if (isAAPCS_ABI())
208  stackAlignment = Align(8);
209  if (isTargetNaCl() || isAAPCS16_ABI())
210  stackAlignment = Align(16);
211 
212  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
213  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
214  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
215  // support in the assembler and linker to be used. This would need to be
216  // fixed to fully support tail calls in Thumb1.
217  //
218  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
219  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
220  // means if we need to reload LR, it takes extra instructions, which outweighs
221  // the value of the tail call; but here we don't know yet whether LR is going
222  // to be used. We take the optimistic approach of generating the tail call and
223  // perhaps taking a hit if we need to restore the LR.
224 
225  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
226  // but we need to make sure there are enough registers; the only valid
227  // registers are the 4 used for parameters. We don't currently do this
228  // case.
229 
230  SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
231 
232  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
233  SupportsTailCall = false;
234 
235  switch (IT) {
236  case DefaultIT:
237  RestrictIT = false;
238  break;
239  case RestrictedIT:
240  RestrictIT = true;
241  break;
242  }
243 
244  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
245  const FeatureBitset &Bits = getFeatureBits();
246  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
248  HasNEONForFP = true;
249 
250  if (isRWPI())
251  ReserveR9 = true;
252 
253  // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
254  if (MVEVectorCostFactor == 0)
256 
257  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
258  switch (ARMProcFamily) {
259  case Others:
260  case CortexA5:
261  break;
262  case CortexA7:
264  break;
265  case CortexA8:
267  break;
268  case CortexA9:
271  break;
272  case CortexA12:
273  break;
274  case CortexA15:
278  break;
279  case CortexA17:
280  case CortexA32:
281  case CortexA35:
282  case CortexA53:
283  case CortexA55:
284  case CortexA57:
285  case CortexA72:
286  case CortexA73:
287  case CortexA75:
288  case CortexA76:
289  case CortexA77:
290  case CortexA78:
291  case CortexA78C:
292  case CortexA710:
293  case CortexR4:
294  case CortexR4F:
295  case CortexR5:
296  case CortexR7:
297  case CortexM3:
298  case CortexM7:
299  case CortexR52:
300  case CortexX1:
301  case CortexX1C:
302  break;
303  case Exynos:
306  if (!isThumb())
308  break;
309  case Kryo:
310  break;
311  case Krait:
313  break;
314  case NeoverseN1:
315  case NeoverseN2:
316  case NeoverseV1:
317  break;
318  case Swift:
323  break;
324  }
325 }
326 
328 
332 }
337 }
341 }
342 
343 bool ARMSubtarget::isROPI() const {
344  return TM.getRelocationModel() == Reloc::ROPI ||
346 }
347 bool ARMSubtarget::isRWPI() const {
348  return TM.getRelocationModel() == Reloc::RWPI ||
350 }
351 
353  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
354  return true;
355 
356  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
357  // the section that is being relocated. This means we have to use o load even
358  // for GVs that are known to be local to the dso.
360  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
361  return true;
362 
363  return false;
364 }
365 
366 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
367  return isTargetELF() && TM.isPositionIndependent() &&
368  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
369 }
370 
373 }
374 
376  // The MachineScheduler can increase register usage, so we use more high
377  // registers and end up with more T2 instructions that cannot be converted to
378  // T1 instructions. At least until we do better at converting to thumb1
379  // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
380  // Machine scheduler, relying on the DAG register pressure scheduler instead.
381  if (isMClass() && hasMinSize())
382  return false;
383  // Enable the MachineScheduler before register allocation for subtargets
384  // with the use-misched feature.
385  return useMachineScheduler();
386 }
387 
390  return EnableSubRegLiveness;
391  // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
392  // and q subregs for qqqqpr regs.
393  return hasMVEIntegerOps();
394 }
395 
397  // Enable the MachinePipeliner before register allocation for subtargets
398  // with the use-mipipeliner feature.
399  return getSchedModel().hasInstrSchedModel() && useMachinePipeliner();
400 }
401 
402 bool ARMSubtarget::useDFAforSMS() const { return false; }
403 
404 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
407  return false;
408  if (disablePostRAScheduler())
409  return false;
410  // Thumb1 cores will generally not benefit from post-ra scheduling
411  return !isThumb1Only();
412 }
413 
415  if (!enableMachineScheduler())
416  return false;
417  if (disablePostRAScheduler())
418  return false;
419  return !isThumb1Only();
420 }
421 
423  // For general targets, the prologue can grow when VFPs are allocated with
424  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
425  // format which it's more important to get right.
426  return isTargetWatchABI() ||
427  (useWideStrideVFP() && !OptMinSize);
428 }
429 
430 bool ARMSubtarget::useMovt() const {
431  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
432  // immediates as it is inherently position independent, and may be out of
433  // range otherwise.
434  return !NoMovt && hasV8MBaselineOps() &&
435  (isTargetWindows() || !OptMinSize || genExecuteOnly());
436 }
437 
439  // Enable fast-isel for any target, for testing only.
440  if (ForceFastISel)
441  return true;
442 
443  // Limit fast-isel to the targets that are or have been tested.
444  if (!hasV6Ops())
445  return false;
446 
447  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
448  return TM.Options.EnableFastISel &&
449  ((isTargetMachO() && !isThumb1Only()) ||
450  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
451 }
452 
454  // The GPR register class has multiple possible allocation orders, with
455  // tradeoffs preferred by different sub-architectures and optimisation goals.
456  // The allocation orders are:
457  // 0: (the default tablegen order, not used)
458  // 1: r14, r0-r13
459  // 2: r0-r7
460  // 3: r0-r7, r12, lr, r8-r11
461  // Note that the register allocator will change this order so that
462  // callee-saved registers are used later, as they require extra work in the
463  // prologue/epilogue (though we sometimes override that).
464 
465  // For thumb1-only targets, only the low registers are allocatable.
466  if (isThumb1Only())
467  return 2;
468 
469  // Allocate low registers first, so we can select more 16-bit instructions.
470  // We also (in ignoreCSRForAllocationOrder) override the default behaviour
471  // with regards to callee-saved registers, because pushing extra registers is
472  // much cheaper (in terms of code size) than using high registers. After
473  // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
474  // can return with the pop, don't need an extra "bx lr") and then the rest of
475  // the high registers.
476  if (isThumb2() && MF.getFunction().hasMinSize())
477  return 3;
478 
479  // Otherwise, allocate in the default order, using LR first because saving it
480  // allows a shorter epilogue sequence.
481  return 1;
482 }
483 
485  unsigned PhysReg) const {
486  // To minimize code size in Thumb2, we prefer the usage of low regs (lower
487  // cost per use) so we can use narrow encoding. By default, caller-saved
488  // registers (e.g. lr, r12) are always allocated first, regardless of
489  // their cost per use. When optForMinSize, we prefer the low regs even if
490  // they are CSR because usually push/pop can be folded into existing ones.
491  return isThumb2() && MF.getFunction().hasMinSize() &&
492  ARM::GPRRegClass.contains(PhysReg);
493 }
494 
496  const Function &F = MF.getFunction();
497  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() ||
498  !F.needsUnwindTableEntry())
499  return false;
500  const MachineFrameInfo &MFI = MF.getFrameInfo();
501  return MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF);
502 }
llvm::ARMSubtarget::SupportsTailCall
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:172
llvm::ARMSubtarget::CortexA17
@ CortexA17
Definition: ARMSubtarget.h:54
ARMSubtarget.h
llvm::ARMSubtarget::UseSjLjEH
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:179
llvm::ARMBaseTargetMachine::ARM_ABI_APCS
@ ARM_ABI_APCS
Definition: ARMTargetMachine.h:31
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
llvm::ARMSubtarget::TM
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:228
llvm::ARMSubtarget::CortexR7
@ CortexR7
Definition: ARMSubtarget.h:78
llvm::ARMSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
Definition: ARMSubtarget.cpp:388
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:142
llvm::ARMSubtarget::hasARMOps
bool hasARMOps() const
Definition: ARMSubtarget.h:326
llvm::GlobalValue::hasCommonLinkage
bool hasCommonLinkage() const
Definition: GlobalValue.h:527
llvm::createARMInstructionSelector
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
Definition: ARMInstructionSelector.cpp:160
MCTargetOptions.h
llvm::ARMSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: ARMSubtarget.cpp:132
ARMMCTargetDesc.h
llvm::ARMSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
Definition: ARMSubtarget.cpp:375
llvm::ARMSubtarget::CortexA57
@ CortexA57
Definition: ARMSubtarget.h:60
ARMGenSubtargetInfo
ARMCallLowering.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMSubtarget::CortexX1C
@ CortexX1C
Definition: ARMSubtarget.h:80
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::Function
Definition: Function.h:60
StringRef.h
llvm::ARMSubtarget::getMispredictionPenalty
unsigned getMispredictionPenalty() const
Definition: ARMSubtarget.cpp:371
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS
@ ARM_ABI_AAPCS
Definition: ARMTargetMachine.h:32
llvm::ARMSubtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:157
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
IT
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
llvm::ARMSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:359
llvm::ARMSubtarget::isRWPI
bool isRWPI() const
Definition: ARMSubtarget.cpp:347
llvm::ARMSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:68
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:266
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::X86AS::FS
@ FS
Definition: X86.h:200
InstructionSelect.h
llvm::Reloc::ROPI_RWPI
@ ROPI_RWPI
Definition: CodeGen.h:22
llvm::ARMSubtarget::CortexM7
@ CortexM7
Definition: ARMSubtarget.h:73
Thumb1InstrInfo.h
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
DefaultIT
@ DefaultIT
Definition: ARMSubtarget.cpp:55
Thumb1FrameLowering.h
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16
@ ARM_ABI_AAPCS16
Definition: ARMTargetMachine.h:33
llvm::ARMSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: ARMSubtarget.h:366
TargetParser.h
llvm::ARMSubtarget::Kryo
@ Kryo
Definition: ARMSubtarget.h:83
llvm::ARMSubtarget::isTargetWatchABI
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:364
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
llvm::ARMSubtarget::OptMinSize
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:211
F
#define F(x, y, z)
Definition: MD5.cpp:55
CommandLine.h
llvm::ARMSubtarget::NeoverseN1
@ NeoverseN1
Definition: ARMSubtarget.h:84
llvm::Thumb1FrameLowering
Definition: Thumb1FrameLowering.h:19
llvm::ARMLegalizerInfo
This class provides the information for the target register banks.
Definition: ARMLegalizerInfo.h:27
InstrInfo
return InstrInfo
Definition: RISCVInsertVSETVLI.cpp:668
llvm::ARMSubtarget::CortexA73
@ CortexA73
Definition: ARMSubtarget.h:63
GlobalValue.h
llvm::MCSchedModel::MispredictPenalty
unsigned MispredictPenalty
Definition: MCSchedule.h:297
llvm::ARMSubtarget::CortexR5
@ CortexR5
Definition: ARMSubtarget.h:76
llvm::ARMSubtarget::NeoverseN2
@ NeoverseN2
Definition: ARMSubtarget.h:85
llvm::ARMBaseTargetMachine::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMTargetMachine.h:64
EnableSubRegLiveness
static cl::opt< bool > EnableSubRegLiveness("arm-enable-subreg-liveness", cl::init(false), cl::Hidden)
llvm::ARMSubtarget::SchedModel
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:220
llvm::ARMSubtarget::MaxInterleaveFactor
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:188
llvm::Legalizer
Definition: Legalizer.h:36
llvm::ARMSubtarget::CortexA72
@ CortexA72
Definition: ARMSubtarget.h:62
Twine.h
llvm::ARMSubtarget::DoubleIssue
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:139
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:430
llvm::ARMSubtarget::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMSubtarget.cpp:327
llvm::ARMSubtarget::isAAPCS16_ABI
bool isAAPCS16_ABI() const
Definition: ARMSubtarget.cpp:338
llvm::ARMSubtarget::CortexA55
@ CortexA55
Definition: ARMSubtarget.h:59
llvm::TargetOptions::ExceptionModel
ExceptionHandling ExceptionModel
What exception model to use.
Definition: TargetOptions.h:439
llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:142
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:403
llvm::ARMSubtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:202
llvm::ARMSubtarget::CortexA78C
@ CortexA78C
Definition: ARMSubtarget.h:68
llvm::Triple::getArchName
StringRef getArchName() const
Get the architecture (first) component of the triple.
Definition: Triple.cpp:1141
llvm::ARMSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:405
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:468
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:29
llvm::ARMSubtarget::CortexA7
@ CortexA7
Definition: ARMSubtarget.h:61
llvm::ARMSubtarget::useMachinePipeliner
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:418
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:136
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
ITMode
ITMode
Definition: ARMSubtarget.cpp:54
llvm::ARMSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:217
llvm::ARMSubtarget::CortexA9
@ CortexA9
Definition: ARMSubtarget.h:71
llvm::cl::opt< bool >
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:705
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:420
llvm::ARMSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:223
llvm::ARMSubtarget::LdStMultipleTiming
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:195
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
llvm::ARMSubtarget::ARMSubtarget
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Definition: ARMSubtarget.cpp:93
llvm::ARMSubtarget::CortexA75
@ CortexA75
Definition: ARMSubtarget.h:64
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:422
llvm::ARMSubtarget::stackAlignment
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:183
llvm::ARMSubtarget::initializeSubtargetDependencies
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: ARMSubtarget.cpp:77
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::ARMSubtarget::isTargetIOS
bool isTargetIOS() const
Definition: ARMSubtarget.h:362
llvm::ARMSubtarget::CPUString
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:186
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:372
ARMTargetParser.h
llvm::ARMSubtarget::MVEVectorCostFactor
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:207
llvm::ARMSubtarget::Options
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:226
llvm::ARMSubtarget::RestrictIT
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:176
llvm::ARMSubtarget::useDFAforSMS
bool useDFAforSMS() const override
Definition: ARMSubtarget.cpp:402
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:117
llvm::ARMSubtarget::splitFramePointerPush
bool splitFramePointerPush(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:495
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:343
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::ARMSubtarget::CortexA77
@ CortexA77
Definition: ARMSubtarget.h:66
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::ARMSubtarget::enablePostRAMachineScheduler
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:414
llvm::Reloc::ROPI
@ ROPI
Definition: CodeGen.h:22
llvm::ARMSubtarget::CortexM3
@ CortexM3
Definition: ARMSubtarget.h:72
ARM.h
llvm::ARMSubtarget::useFastISel
bool useFastISel() const
True if fast-isel is used.
Definition: ARMSubtarget.cpp:438
llvm::TargetOptions::EnableFastISel
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
Definition: TargetOptions.h:232
llvm::ARMRegisterBankInfo
This class provides the information for the target register banks.
Definition: ARMRegisterBankInfo.h:31
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMSubtarget::Exynos
@ Exynos
Definition: ARMSubtarget.h:81
Triple.h
TargetOptions.h
llvm::Reloc::RWPI
@ RWPI
Definition: CodeGen.h:22
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:204
llvm::ARMSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: ARMSubtarget.cpp:124
MCAsmInfo.h
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:274
llvm::ARMSubtarget::CortexR4F
@ CortexR4F
Definition: ARMSubtarget.h:75
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::ARMSubtarget::useMachineScheduler
bool useMachineScheduler() const
Definition: ARMSubtarget.h:417
llvm::ARMSubtarget::PartialUpdateClearance
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:191
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:680
llvm::ARMSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: ARMSubtarget.cpp:128
llvm::TargetMachine::shouldAssumeDSOLocal
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Definition: TargetMachine.cpp:88
ARMInstrInfo.h
llvm::ARMSubtarget::CortexA15
@ CortexA15
Definition: ARMSubtarget.h:53
llvm::ARMSubtarget::PreISelOperandLatencyAdjustment
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:199
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:369
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:366
llvm::ARMSubtarget::ignoreCSRForAllocationOrder
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMSubtarget.cpp:484
llvm::ARMSubtarget::Swift
@ Swift
Definition: ARMSubtarget.h:87
llvm::ARMSubtarget::CortexR4
@ CortexR4
Definition: ARMSubtarget.h:74
llvm::ARMSubtarget::CortexR52
@ CortexR52
Definition: ARMSubtarget.h:77
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:96
ARMFrameLowering.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:361
llvm::ARMSubtarget::Krait
@ Krait
Definition: ARMSubtarget.h:82
Thumb2InstrInfo.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
MachineFrameInfo.h
llvm::ARMSubtarget::isAPCS_ABI
bool isAPCS_ABI() const
Definition: ARMSubtarget.cpp:329
llvm::Thumb1InstrInfo
Definition: Thumb1InstrInfo.h:22
ARMRegisterBankInfo.h
Function.h
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:373
llvm::ARMSubtarget::isAAPCS_ABI
bool isAAPCS_ABI() const
Definition: ARMSubtarget.cpp:333
llvm::Thumb2InstrInfo
Definition: Thumb2InstrInfo.h:22
llvm::ARMSubtarget::NeoverseV1
@ NeoverseV1
Definition: ARMSubtarget.h:86
llvm::ARMSubtarget::Others
@ Others
Definition: ARMSubtarget.h:50
llvm::ARMCallLowering
Definition: ARMCallLowering.h:30
llvm::ARMSubtarget::CortexX1
@ CortexX1
Definition: ARMSubtarget.h:79
llvm::ARMSubtarget::SingleIssuePlusExtras
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:147
llvm::ARMSubtarget::enableMachinePipeliner
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
Definition: ARMSubtarget.cpp:396
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::ARMBaseTargetMachine::TargetABI
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
CodeGen.h
llvm::ARMInstrInfo
Definition: ARMInstrInfo.h:22
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
llvm::ARMSubtarget::CortexA8
@ CortexA8
Definition: ARMSubtarget.h:70
ForceFastISel
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::ARMSubtarget::CortexA12
@ CortexA12
Definition: ARMSubtarget.h:52
RestrictedIT
@ RestrictedIT
Definition: ARMSubtarget.cpp:56
llvm::ARMSubtarget::CortexA76
@ CortexA76
Definition: ARMSubtarget.h:65
llvm::ARMSubtarget::CortexA35
@ CortexA35
Definition: ARMSubtarget.h:56
llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN
@ ARM_ABI_UNKNOWN
Definition: ARMTargetMachine.h:30
llvm::ARMSubtarget::CortexA78
@ CortexA78
Definition: ARMSubtarget.h:67
llvm::ARMSubtarget::hasMinSize
bool hasMinSize() const
Definition: ARMSubtarget.h:419
llvm::ARMSubtarget::CortexA53
@ CortexA53
Definition: ARMSubtarget.h:58
llvm::GlobalValue::isDeclarationForLinker
bool isDeclarationForLinker() const
Definition: GlobalValue.h:614
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:352
llvm::TargetOptions::UnsafeFPMath
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Definition: TargetOptions.h:163
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
llvm::ARMSubtarget::CortexA5
@ CortexA5
Definition: ARMSubtarget.h:57
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMSubtarget::CortexA32
@ CortexA32
Definition: ARMSubtarget.h:55
llvm::ARMSubtarget::isThumb2
bool isThumb2() const
Definition: ARMSubtarget.h:421
llvm::ARMSubtarget::CortexA710
@ CortexA710
Definition: ARMSubtarget.h:69
llvm::cl::desc
Definition: CommandLine.h:413
llvm::ARMSubtarget::getGPRAllocationOrder
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:453
ARMLegalizerInfo.h
ARMTargetMachine.h
MachineFunction.h
llvm::MCAsmInfo::usesWindowsCFI
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:793
llvm::CallLowering
Definition: CallLowering.h:44
llvm::ARMSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: ARMSubtarget.h:367
llvm::ARMSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: ARMSubtarget.cpp:140
llvm::ARMSubtarget::useStride4VFPs
bool useStride4VFPs() const
Definition: ARMSubtarget.cpp:422
UseFusedMulOps
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)