LLVM 19.0.0git
ARMSubtarget.cpp
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1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARM.h"
14
15#include "ARMCallLowering.h"
16#include "ARMFrameLowering.h"
17#include "ARMInstrInfo.h"
18#include "ARMLegalizerInfo.h"
19#include "ARMRegisterBankInfo.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
23#include "Thumb1FrameLowering.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb2InstrInfo.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/Twine.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/GlobalValue.h"
33#include "llvm/MC/MCAsmInfo.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "arm-subtarget"
44
45#define GET_SUBTARGETINFO_TARGET_DESC
46#define GET_SUBTARGETINFO_CTOR
47#include "ARMGenSubtargetInfo.inc"
48
49static cl::opt<bool>
50UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
52
53enum ITMode {
56};
57
58static cl::opt<ITMode>
59 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
60 cl::values(clEnumValN(DefaultIT, "arm-default-it",
61 "Generate any type of IT block"),
62 clEnumValN(RestrictedIT, "arm-restrict-it",
63 "Disallow complex IT blocks")));
64
65/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66/// currently supported (for testing only).
67static cl::opt<bool>
68ForceFastISel("arm-force-fast-isel",
69 cl::init(false), cl::Hidden);
70
71/// initializeSubtargetDependencies - Initializes using a CPU and feature string
72/// so that we can use initializer lists for subtarget initialization.
74 StringRef FS) {
75 initializeEnvironment();
76 initSubtargetFeatures(CPU, FS);
77 return *this;
78}
79
80ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81 StringRef FS) {
83 if (STI.isThumb1Only())
84 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85
86 return new ARMFrameLowering(STI);
87}
88
89ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90 const std::string &FS,
91 const ARMBaseTargetMachine &TM, bool IsLittle,
92 bool MinSize)
93 : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
94 UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
95 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
96 FrameLowering(initializeFrameLowering(CPU, FS)),
97 // At this point initializeSubtargetDependencies has been called so
98 // we can query directly.
99 InstrInfo(isThumb1Only()
100 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
101 : !isThumb()
102 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
103 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
104 TLInfo(TM, *this) {
105
106 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
107 Legalizer.reset(new ARMLegalizerInfo(*this));
108
109 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
110
111 // FIXME: At this point, we can't rely on Subtarget having RBI.
112 // It's awkward to mix passing RBI and the Subtarget; should we pass
113 // TII/TRI as well?
114 InstSelector.reset(createARMInstructionSelector(
115 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
116
117 RegBankInfo.reset(RBI);
118}
119
121 return CallLoweringInfo.get();
122}
123
125 return InstSelector.get();
126}
127
129 return Legalizer.get();
130}
131
133 return RegBankInfo.get();
134}
135
137 // We don't currently suppport Thumb, but Windows requires Thumb.
138 return hasV6Ops() && hasARMOps() && !isTargetWindows();
139}
140
141void ARMSubtarget::initializeEnvironment() {
142 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
143 // directly from it, but we can try to make sure they're consistent when both
144 // available.
148 assert((!TM.getMCAsmInfo() ||
151 "inconsistent sjlj choice between CodeGen and MC");
152}
153
154void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
155 if (CPUString.empty()) {
156 CPUString = "generic";
157
158 if (isTargetDarwin()) {
160 ARM::ArchKind AK = ARM::parseArch(ArchName);
161 if (AK == ARM::ArchKind::ARMV7S)
162 // Default to the Swift CPU when targeting armv7s/thumbv7s.
163 CPUString = "swift";
164 else if (AK == ARM::ArchKind::ARMV7K)
165 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
166 // ARMv7k does not use SjLj exception handling.
167 CPUString = "cortex-a7";
168 }
169 }
170
171 // Insert the architecture feature derived from the target triple into the
172 // feature string. This is important for setting features that are implied
173 // based on the architecture version.
174 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
175 if (!FS.empty()) {
176 if (!ArchFS.empty())
177 ArchFS = (Twine(ArchFS) + "," + FS).str();
178 else
179 ArchFS = std::string(FS);
180 }
181 ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
182
183 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
184 // Assert this for now to make the change obvious.
185 assert(hasV6T2Ops() || !hasThumb2());
186
187 if (genExecuteOnly()) {
188 // Execute only support for >= v8-M Baseline requires movt support
189 if (hasV8MBaselineOps())
190 NoMovt = false;
191 if (!hasV6MOps())
192 report_fatal_error("Cannot generate execute-only code for this target");
193 }
194
195 // Keep a pointer to static instruction cost data for the specified CPU.
196 SchedModel = getSchedModelForCPU(CPUString);
197
198 // Initialize scheduling itinerary for the specified CPU.
199 InstrItins = getInstrItineraryForCPU(CPUString);
200
201 // FIXME: this is invalid for WindowsCE
202 if (isTargetWindows())
203 NoARM = true;
204
205 if (isAAPCS_ABI())
207 if (isTargetNaCl() || isAAPCS16_ABI())
208 stackAlignment = Align(16);
209
210 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
211 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
212 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
213 // support in the assembler and linker to be used. This would need to be
214 // fixed to fully support tail calls in Thumb1.
215 //
216 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
217 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
218 // means if we need to reload LR, it takes extra instructions, which outweighs
219 // the value of the tail call; but here we don't know yet whether LR is going
220 // to be used. We take the optimistic approach of generating the tail call and
221 // perhaps taking a hit if we need to restore the LR.
222
223 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
224 // but we need to make sure there are enough registers; the only valid
225 // registers are the 4 used for parameters. We don't currently do this
226 // case.
227
228 SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
229
230 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
231 SupportsTailCall = false;
232
233 switch (IT) {
234 case DefaultIT:
235 RestrictIT = false;
236 break;
237 case RestrictedIT:
238 RestrictIT = true;
239 break;
240 }
241
242 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
243 const FeatureBitset &Bits = getFeatureBits();
244 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
246 HasNEONForFP = true;
247
248 if (isRWPI())
249 ReserveR9 = true;
250
251 // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
252 if (MVEVectorCostFactor == 0)
254
255 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
256 switch (ARMProcFamily) {
257 case Others:
258 case CortexA5:
259 break;
260 case CortexA7:
262 break;
263 case CortexA8:
265 break;
266 case CortexA9:
269 break;
270 case CortexA12:
271 break;
272 case CortexA15:
276 break;
277 case CortexA17:
278 case CortexA32:
279 case CortexA35:
280 case CortexA53:
281 case CortexA55:
282 case CortexA57:
283 case CortexA72:
284 case CortexA73:
285 case CortexA75:
286 case CortexA76:
287 case CortexA77:
288 case CortexA78:
289 case CortexA78AE:
290 case CortexA78C:
291 case CortexA710:
292 case CortexR4:
293 case CortexR5:
294 case CortexR7:
295 case CortexM3:
296 case CortexM7:
297 case CortexR52:
298 case CortexR52plus:
299 case CortexX1:
300 case CortexX1C:
301 break;
302 case Exynos:
305 if (!isThumb())
307 break;
308 case Kryo:
309 break;
310 case Krait:
312 break;
313 case NeoverseV1:
314 break;
315 case Swift:
320 break;
321 }
322}
323
325
329}
334}
338}
339
341 return TM.getRelocationModel() == Reloc::ROPI ||
343}
345 return TM.getRelocationModel() == Reloc::RWPI ||
347}
348
350 if (!TM.shouldAssumeDSOLocal(GV))
351 return true;
352
353 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
354 // the section that is being relocated. This means we have to use o load even
355 // for GVs that are known to be local to the dso.
358 return true;
359
360 return false;
361}
362
364 return isTargetELF() && TM.isPositionIndependent() && !GV->isDSOLocal();
365}
366
369}
370
372 // The MachineScheduler can increase register usage, so we use more high
373 // registers and end up with more T2 instructions that cannot be converted to
374 // T1 instructions. At least until we do better at converting to thumb1
375 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
376 // Machine scheduler, relying on the DAG register pressure scheduler instead.
377 if (isMClass() && hasMinSize())
378 return false;
379 // Enable the MachineScheduler before register allocation for subtargets
380 // with the use-misched feature.
381 return useMachineScheduler();
382}
383
385 // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
386 // and q subregs for qqqqpr regs.
387 return hasMVEIntegerOps();
388}
389
391 // Enable the MachinePipeliner before register allocation for subtargets
392 // with the use-mipipeliner feature.
393 return getSchedModel().hasInstrSchedModel() && useMachinePipeliner();
394}
395
396bool ARMSubtarget::useDFAforSMS() const { return false; }
397
398// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
401 return false;
402 if (disablePostRAScheduler())
403 return false;
404 // Thumb1 cores will generally not benefit from post-ra scheduling
405 return !isThumb1Only();
406}
407
410 return false;
411 if (disablePostRAScheduler())
412 return false;
413 return !isThumb1Only();
414}
415
417 // For general targets, the prologue can grow when VFPs are allocated with
418 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
419 // format which it's more important to get right.
420 return isTargetWatchABI() ||
421 (useWideStrideVFP() && !OptMinSize);
422}
423
425 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
426 // immediates as it is inherently position independent, and may be out of
427 // range otherwise.
428 return !NoMovt && hasV8MBaselineOps() &&
429 (isTargetWindows() || !OptMinSize || genExecuteOnly());
430}
431
433 // Enable fast-isel for any target, for testing only.
434 if (ForceFastISel)
435 return true;
436
437 // Limit fast-isel to the targets that are or have been tested.
438 if (!hasV6Ops())
439 return false;
440
441 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
442 return TM.Options.EnableFastISel &&
443 ((isTargetMachO() && !isThumb1Only()) ||
444 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
445}
446
448 // The GPR register class has multiple possible allocation orders, with
449 // tradeoffs preferred by different sub-architectures and optimisation goals.
450 // The allocation orders are:
451 // 0: (the default tablegen order, not used)
452 // 1: r14, r0-r13
453 // 2: r0-r7
454 // 3: r0-r7, r12, lr, r8-r11
455 // Note that the register allocator will change this order so that
456 // callee-saved registers are used later, as they require extra work in the
457 // prologue/epilogue (though we sometimes override that).
458
459 // For thumb1-only targets, only the low registers are allocatable.
460 if (isThumb1Only())
461 return 2;
462
463 // Allocate low registers first, so we can select more 16-bit instructions.
464 // We also (in ignoreCSRForAllocationOrder) override the default behaviour
465 // with regards to callee-saved registers, because pushing extra registers is
466 // much cheaper (in terms of code size) than using high registers. After
467 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
468 // can return with the pop, don't need an extra "bx lr") and then the rest of
469 // the high registers.
470 if (isThumb2() && MF.getFunction().hasMinSize())
471 return 3;
472
473 // Otherwise, allocate in the default order, using LR first because saving it
474 // allows a shorter epilogue sequence.
475 return 1;
476}
477
479 unsigned PhysReg) const {
480 // To minimize code size in Thumb2, we prefer the usage of low regs (lower
481 // cost per use) so we can use narrow encoding. By default, caller-saved
482 // registers (e.g. lr, r12) are always allocated first, regardless of
483 // their cost per use. When optForMinSize, we prefer the low regs even if
484 // they are CSR because usually push/pop can be folded into existing ones.
485 return isThumb2() && MF.getFunction().hasMinSize() &&
486 ARM::GPRRegClass.contains(PhysReg);
487}
488
490 const Function &F = MF.getFunction();
491 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() ||
492 !F.needsUnwindTableEntry())
493 return false;
494 const MachineFrameInfo &MFI = MF.getFrameInfo();
495 return MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF);
496}
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for ARM.
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
ITMode
@ RestrictedIT
@ DefaultIT
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:693
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
This class provides the information for the target register banks.
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
Definition: ARMSubtarget.h:312
bool useMovt() const
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:129
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool hasARMOps() const
Definition: ARMSubtarget.h:265
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:298
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:113
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:122
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:162
bool isThumb1Only() const
Definition: ARMSubtarget.h:364
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:91
bool isThumb2() const
Definition: ARMSubtarget.h:365
bool useDFAforSMS() const override
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
bool isTargetWindows() const
Definition: ARMSubtarget.h:308
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:141
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:200
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:154
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:120
unsigned getMispredictionPenalty() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:151
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:300
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:208
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:157
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:145
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:110
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies and functions, in log2(bytes).
Definition: ARMSubtarget.h:136
bool isROPI() const
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:117
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:125
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
InstructionSelector * getInstructionSelector() const override
bool isAPCS_ABI() const
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
bool hasMinSize() const
Definition: ARMSubtarget.h:363
bool splitFramePointerPush(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isTargetIOS() const
Definition: ARMSubtarget.h:301
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:306
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:303
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:160
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:76
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:73
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:81
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:362
bool isAAPCS_ABI() const
bool useMachineScheduler() const
Definition: ARMSubtarget.h:361
bool isRWPI() const
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
Definition: ARMSubtarget.h:305
bool isMClass() const
Definition: ARMSubtarget.h:366
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:106
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:133
bool isTargetHardFloat() const
bool isTargetELF() const
Definition: ARMSubtarget.h:311
Container class for subtarget features.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:685
bool isDSOLocal() const
Definition: GlobalValue.h:304
bool isDeclarationForLinker() const
Definition: GlobalValue.h:617
bool hasCommonLinkage() const
Definition: GlobalValue.h:531
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:799
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:780
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool isPositionIndependent() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
TargetOptions Options
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
ExceptionHandling ExceptionModel
What exception model to use.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
StringRef getArchName() const
Get the architecture (first) component of the triple.
Definition: Triple.cpp:1299
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
ArchKind parseArch(StringRef Arch)
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ ROPI_RWPI
Definition: CodeGen.h:25
@ FS
Definition: X86.h:206
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:718
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
unsigned MispredictPenalty
Definition: MCSchedule.h:306