LLVM 19.0.0git
Public Member Functions | List of all members
llvm::ARMInstrInfo Class Reference

#include "Target/ARM/ARMInstrInfo.h"

Inheritance diagram for llvm::ARMInstrInfo:
Inheritance graph

Public Member Functions

 ARMInstrInfo (const ARMSubtarget &STI)
MCInst getNop () const override
 Return the noop instruction to use for a noop.
unsigned getUnindexedOpcode (unsigned Opc) const override
const ARMRegisterInfogetRegisterInfo () const override
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
- Public Member Functions inherited from llvm::ARMBaseInstrInfo
bool hasNOP () const
virtual unsigned getUnindexedOpcode (unsigned Opc) const =0
MachineInstrconvertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
virtual const ARMBaseRegisterInfogetRegisterInfo () const =0
const ARMSubtargetgetSubtarget () const
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
ScheduleHazardRecognizerCreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool isPredicated (const MachineInstr &MI) const override
std::string createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
ARMCC::CondCodes getPredicate (const MachineInstr &MI) const
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isPredicable (const MachineInstr &MI) const override
 isPredicable - Return true if the specified instruction can be predicated.
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Returns the size of the specified MachineInstr.
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
Register isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
void copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool expandPostRAPseudo (MachineInstr &MI) const override
bool shouldSink (const MachineInstr &MI) const override
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
MachineInstrduplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
const MachineInstrBuilderAddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
bool produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
unsigned extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override
unsigned predictBranchSizeForIfCvt (MachineInstr &MI) const override
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
 foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
unsigned getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
std::optional< unsignedgetOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
std::optional< unsignedgetOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
std::pair< uint16_t, uint16_tgetExecutionDomain (const MachineInstr &MI) const override
 VFP/NEON execution domains.
void setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
unsigned getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
void breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
unsigned getNumLDMAddresses (const MachineInstr &MI) const
 Get the number of addresses by LDM or VLDM or zero for unknown.
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 ARM supports the MachineOutliner.
std::optional< outliner::OutlinedFunctiongetOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
void mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override
outliner::InstrType getOutliningTypeImpl (MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
 Enable outlining by default at -Oz.
bool isUnspillableTerminatorImpl (const MachineInstr *MI) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfoanalyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
bool isFpMLxInstruction (unsigned Opcode) const
 isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
 isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
bool canCauseFpMLxStall (unsigned Opcode) const
 canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
bool isSwiftFastImmShift (const MachineInstr *MI) const
 Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
unsigned getFramePred (const MachineInstr &MI) const
 Returns predicate register associated with the given frame instruction.
std::optional< RegImmPairisAddImmediate (const MachineInstr &MI, Register Reg) const override
unsigned getUndefInitOpcode (unsigned RegClassID) const override

Additional Inherited Members

- Static Public Member Functions inherited from llvm::ARMBaseInstrInfo
static bool isCPSRDefined (const MachineInstr &MI)
- Protected Member Functions inherited from llvm::ARMBaseInstrInfo
 ARMBaseInstrInfo (const ARMSubtarget &STI)
void expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
 Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
 Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
 Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction.
std::optional< DestSourcePairisCopyInstrImpl (const MachineInstr &MI) const override
 If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
std::optional< ParamLoadedValuedescribeLoadedValue (const MachineInstr &MI, Register Reg) const override
 Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Detailed Description

Definition at line 22 of file ARMInstrInfo.h.

Constructor & Destructor Documentation

◆ ARMInstrInfo()

ARMInstrInfo::ARMInstrInfo ( const ARMSubtarget STI)

Definition at line 31 of file ARMInstrInfo.cpp.

Member Function Documentation

◆ getNop()

MCInst ARMInstrInfo::getNop ( ) const

◆ getRegisterInfo()

const ARMRegisterInfo & llvm::ARMInstrInfo::getRegisterInfo ( ) const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::ARMBaseInstrInfo.

Definition at line 38 of file ARMInstrInfo.h.

◆ getUnindexedOpcode()

unsigned ARMInstrInfo::getUnindexedOpcode ( unsigned  Opc) const

Implements llvm::ARMBaseInstrInfo.

Definition at line 52 of file ARMInstrInfo.cpp.

The documentation for this class was generated from the following files: