LLVM 22.0.0git
ARMMCTargetDesc.h
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1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15
17#include "llvm/MC/MCInstrDesc.h"
18#include <memory>
19#include <string>
20
21namespace llvm {
23class MCAsmBackend;
24class MCCodeEmitter;
25class MCContext;
26class MCInstrInfo;
27class MCInstPrinter;
29class MCObjectWriter;
30class MCRegisterInfo;
31class MCSubtargetInfo;
32class MCStreamer;
33class MCTargetOptions;
36class StringRef;
37class Target;
38class Triple;
39
40namespace ARM_MC {
41std::string ParseARMTriple(const Triple &TT, StringRef CPU);
43
44bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
45bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
46
47template<class Inst>
48bool isLDMBaseRegInList(const Inst &MI) {
49 auto BaseReg = MI.getOperand(0).getReg();
50 for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
51 const auto &Op = MI.getOperand(I);
52 if (Op.isReg() && Op.getReg() == BaseReg)
53 return true;
54 }
55 return false;
56}
57
59 int64_t Imm);
60
61/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
62/// do not need to go through TargetRegistry.
64 StringRef FS);
65}
66
67MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
68MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
69 formatted_raw_ostream &OS,
70 MCInstPrinter *InstPrint);
71MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
72 const MCSubtargetInfo &STI);
73MCTargetStreamer *createARMObjectTargetELFStreamer(MCStreamer &S);
74MCTargetStreamer *createARMObjectTargetMachOStreamer(MCStreamer &S);
75MCTargetStreamer *createARMObjectTargetWinCOFFStreamer(MCStreamer &S);
76
77MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
78 MCContext &Ctx);
79
80MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
81 MCContext &Ctx);
82
83MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
84 const MCRegisterInfo &MRI,
85 const MCTargetOptions &Options);
86
87MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
88 const MCRegisterInfo &MRI,
89 const MCTargetOptions &Options);
90
91// Construct a PE/COFF machine code streamer which will generate a PE/COFF
92// object file.
93MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
94 std::unique_ptr<MCAsmBackend> &&MAB,
95 std::unique_ptr<MCObjectWriter> &&OW,
96 std::unique_ptr<MCCodeEmitter> &&Emitter);
97
98/// Construct an ELF Mach-O object writer.
99std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
100
101/// Construct an ARM Mach-O object writer.
102std::unique_ptr<MCObjectTargetWriter>
103createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
104 uint32_t CPUSubtype);
105
106/// Construct an ARM PE/COFF object writer.
107std::unique_ptr<MCObjectTargetWriter>
109
110/// Construct ARM Mach-O relocation info.
111MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
112
113namespace ARM {
118inline bool isVpred(OperandType op) {
119 return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
120}
121inline bool isVpred(uint8_t op) {
122 return isVpred(static_cast<OperandType>(op));
123}
124
125bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
126
127} // end namespace ARM
128
129} // End llvm namespace
130
131// Defines symbolic names for ARM registers. This defines a mapping from
132// register name to register number.
133//
134#define GET_REGINFO_ENUM
135#include "ARMGenRegisterInfo.inc"
136
137// Defines symbolic names for the ARM instructions.
138//
139#define GET_INSTRINFO_ENUM
140#define GET_INSTRINFO_MC_HELPER_DECLS
141#include "ARMGenInstrInfo.inc"
142
143#define GET_SUBTARGETINFO_ENUM
144#include "ARMGenSubtargetInfo.inc"
145
146#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
dxil DXContainer Global Emitter
#define op(i)
IRTranslator LLVM IR MI
static LVOptions Options
Definition LVOptions.cpp:25
#define I(x, y, z)
Definition MD5.cpp:58
#define T
Generic interface to target specific assembler backends.
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
Definition MCContext.h:83
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
Base class for classes that define behaviour that is specific to both the target and the object forma...
Defines the object file and target independent interfaces used by the assembler backend to write nati...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Create MCExprs from relocations found in an object file.
Streaming machine code generation interface.
Definition MCStreamer.h:220
Generic base class for all target subtargets.
Target specific streamer interface.
Definition MCStreamer.h:93
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
bool isLDMBaseRegInList(const Inst &MI)
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ OPERAND_FIRST_TARGET
Definition MCInstrDesc.h:80
This is an optimization pass for GlobalISel generic memory operations.
MCTargetStreamer * createARMObjectTargetMachOStreamer(MCStreamer &S)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an ARM Mach-O object writer.
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
MCTargetStreamer * createARMObjectTargetELFStreamer(MCStreamer &S)
DWARFExpression::Operation Op
std::unique_ptr< MCObjectTargetWriter > createARMELFObjectWriter(uint8_t OSABI)
Construct an ELF Mach-O object writer.
MCTargetStreamer * createARMObjectTargetWinCOFFStreamer(MCStreamer &S)
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
std::unique_ptr< MCObjectTargetWriter > createARMWinCOFFObjectWriter()
Construct an ARM PE/COFF object writer.
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)