35#define GET_REGINFO_MC_DESC
36#include "ARMGenRegisterInfo.inc"
41 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 15) &&
42 (
MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) &&
45 (
MI.getOperand(3).isImm() &&
MI.getOperand(3).getImm() == 7)) {
46 if ((
MI.getOperand(5).isImm() &&
MI.getOperand(5).getImm() == 4)) {
47 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 5) {
48 Info =
"deprecated since v7, use 'isb'";
54 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 10) {
55 Info =
"deprecated since v7, use 'dsb'";
61 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 10 &&
62 (
MI.getOperand(5).isImm() &&
MI.getOperand(5).getImm() == 5)) {
63 Info =
"deprecated since v7, use 'dmb'";
68 ((
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 10) ||
69 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 11))) {
70 Info =
"since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
80 ((
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 10) ||
81 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 11))) {
82 Info =
"since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
92 "cannot predicate thumb instructions");
94 assert(
MI.getNumOperands() >= 4 &&
"expected >= 4 arguments");
95 for (
unsigned OI = 4, OE =
MI.getNumOperands(); OI < OE; ++OI) {
96 assert(
MI.getOperand(OI).isReg() &&
"expected register");
97 if (
MI.getOperand(OI).getReg() == ARM::PC) {
98 Info =
"use of PC in the list is deprecated";
108 "cannot predicate thumb instructions");
110 assert(
MI.getNumOperands() >= 4 &&
"expected >= 4 arguments");
111 bool ListContainsPC =
false, ListContainsLR =
false;
112 for (
unsigned OI = 4, OE =
MI.getNumOperands(); OI < OE; ++OI) {
113 assert(
MI.getOperand(OI).isReg() &&
"expected register");
114 switch (
MI.getOperand(OI).getReg()) {
118 ListContainsLR =
true;
121 ListContainsPC =
true;
126 if (ListContainsPC && ListContainsLR) {
127 Info =
"use of LR and PC simultaneously in the list is deprecated";
134#define GET_INSTRINFO_MC_DESC
135#define ENABLE_INSTR_PREDICATE_VERIFIER
136#include "ARMGenInstrInfo.inc"
138#define GET_SUBTARGETINFO_MC_DESC
139#include "ARMGenSubtargetInfo.inc"
142 std::string ARMArchFeature;
145 if (ArchID != ARM::ArchKind::INVALID && (CPU.
empty() || CPU ==
"generic"))
149 if (!ARMArchFeature.empty())
150 ARMArchFeature +=
",";
151 ARMArchFeature +=
"+thumb-mode,+v4t";
155 if (!ARMArchFeature.empty())
156 ARMArchFeature +=
",";
157 ARMArchFeature +=
"+nacl-trap";
160 if (TT.isOSWindows()) {
161 if (!ARMArchFeature.empty())
162 ARMArchFeature +=
",";
163 ARMArchFeature +=
"+noarm";
166 return ARMArchFeature;
171 int PredOpIdx =
Desc.findFirstPredOperandIdx();
172 return PredOpIdx != -1 &&
MI.getOperand(PredOpIdx).getImm() !=
ARMCC::AL;
177 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
180 Desc.operands()[
I].isOptionalDef())
209 ArchFS = (
Twine(ArchFS) +
"," + FS).str();
211 ArchFS = std::string(FS);
214 return createARMMCSubtargetInfoImpl(TT, CPU, CPU, ArchFS);
219 InitARMMCInstrInfo(
X);
225 static const struct {
229 {codeview::RegisterId::ARM_R0, ARM::R0},
230 {codeview::RegisterId::ARM_R1, ARM::R1},
231 {codeview::RegisterId::ARM_R2, ARM::R2},
232 {codeview::RegisterId::ARM_R3, ARM::R3},
233 {codeview::RegisterId::ARM_R4, ARM::R4},
234 {codeview::RegisterId::ARM_R5, ARM::R5},
235 {codeview::RegisterId::ARM_R6, ARM::R6},
236 {codeview::RegisterId::ARM_R7, ARM::R7},
237 {codeview::RegisterId::ARM_R8, ARM::R8},
238 {codeview::RegisterId::ARM_R9, ARM::R9},
239 {codeview::RegisterId::ARM_R10, ARM::R10},
240 {codeview::RegisterId::ARM_R11, ARM::R11},
241 {codeview::RegisterId::ARM_R12, ARM::R12},
242 {codeview::RegisterId::ARM_SP, ARM::SP},
243 {codeview::RegisterId::ARM_LR, ARM::LR},
244 {codeview::RegisterId::ARM_PC, ARM::PC},
245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
246 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
247 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
248 {codeview::RegisterId::ARM_FS0, ARM::S0},
249 {codeview::RegisterId::ARM_FS1, ARM::S1},
250 {codeview::RegisterId::ARM_FS2, ARM::S2},
251 {codeview::RegisterId::ARM_FS3, ARM::S3},
252 {codeview::RegisterId::ARM_FS4, ARM::S4},
253 {codeview::RegisterId::ARM_FS5, ARM::S5},
254 {codeview::RegisterId::ARM_FS6, ARM::S6},
255 {codeview::RegisterId::ARM_FS7, ARM::S7},
256 {codeview::RegisterId::ARM_FS8, ARM::S8},
257 {codeview::RegisterId::ARM_FS9, ARM::S9},
258 {codeview::RegisterId::ARM_FS10, ARM::S10},
259 {codeview::RegisterId::ARM_FS11, ARM::S11},
260 {codeview::RegisterId::ARM_FS12, ARM::S12},
261 {codeview::RegisterId::ARM_FS13, ARM::S13},
262 {codeview::RegisterId::ARM_FS14, ARM::S14},
263 {codeview::RegisterId::ARM_FS15, ARM::S15},
264 {codeview::RegisterId::ARM_FS16, ARM::S16},
265 {codeview::RegisterId::ARM_FS17, ARM::S17},
266 {codeview::RegisterId::ARM_FS18, ARM::S18},
267 {codeview::RegisterId::ARM_FS19, ARM::S19},
268 {codeview::RegisterId::ARM_FS20, ARM::S20},
269 {codeview::RegisterId::ARM_FS21, ARM::S21},
270 {codeview::RegisterId::ARM_FS22, ARM::S22},
271 {codeview::RegisterId::ARM_FS23, ARM::S23},
272 {codeview::RegisterId::ARM_FS24, ARM::S24},
273 {codeview::RegisterId::ARM_FS25, ARM::S25},
274 {codeview::RegisterId::ARM_FS26, ARM::S26},
275 {codeview::RegisterId::ARM_FS27, ARM::S27},
276 {codeview::RegisterId::ARM_FS28, ARM::S28},
277 {codeview::RegisterId::ARM_FS29, ARM::S29},
278 {codeview::RegisterId::ARM_FS30, ARM::S30},
279 {codeview::RegisterId::ARM_FS31, ARM::S31},
280 {codeview::RegisterId::ARM_ND0, ARM::D0},
281 {codeview::RegisterId::ARM_ND1, ARM::D1},
282 {codeview::RegisterId::ARM_ND2, ARM::D2},
283 {codeview::RegisterId::ARM_ND3, ARM::D3},
284 {codeview::RegisterId::ARM_ND4, ARM::D4},
285 {codeview::RegisterId::ARM_ND5, ARM::D5},
286 {codeview::RegisterId::ARM_ND6, ARM::D6},
287 {codeview::RegisterId::ARM_ND7, ARM::D7},
288 {codeview::RegisterId::ARM_ND8, ARM::D8},
289 {codeview::RegisterId::ARM_ND9, ARM::D9},
290 {codeview::RegisterId::ARM_ND10, ARM::D10},
291 {codeview::RegisterId::ARM_ND11, ARM::D11},
292 {codeview::RegisterId::ARM_ND12, ARM::D12},
293 {codeview::RegisterId::ARM_ND13, ARM::D13},
294 {codeview::RegisterId::ARM_ND14, ARM::D14},
295 {codeview::RegisterId::ARM_ND15, ARM::D15},
296 {codeview::RegisterId::ARM_ND16,
ARM::D16},
297 {codeview::RegisterId::ARM_ND17, ARM::D17},
298 {codeview::RegisterId::ARM_ND18, ARM::D18},
299 {codeview::RegisterId::ARM_ND19, ARM::D19},
300 {codeview::RegisterId::ARM_ND20, ARM::D20},
301 {codeview::RegisterId::ARM_ND21, ARM::D21},
302 {codeview::RegisterId::ARM_ND22, ARM::D22},
303 {codeview::RegisterId::ARM_ND23, ARM::D23},
304 {codeview::RegisterId::ARM_ND24, ARM::D24},
305 {codeview::RegisterId::ARM_ND25, ARM::D25},
306 {codeview::RegisterId::ARM_ND26, ARM::D26},
307 {codeview::RegisterId::ARM_ND27, ARM::D27},
308 {codeview::RegisterId::ARM_ND28, ARM::D28},
309 {codeview::RegisterId::ARM_ND29, ARM::D29},
310 {codeview::RegisterId::ARM_ND30, ARM::D30},
311 {codeview::RegisterId::ARM_ND31, ARM::D31},
312 {codeview::RegisterId::ARM_NQ0, ARM::Q0},
313 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
314 {codeview::RegisterId::ARM_NQ2, ARM::Q2},
315 {codeview::RegisterId::ARM_NQ3, ARM::Q3},
316 {codeview::RegisterId::ARM_NQ4, ARM::Q4},
317 {codeview::RegisterId::ARM_NQ5, ARM::Q5},
318 {codeview::RegisterId::ARM_NQ6, ARM::Q6},
319 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
320 {codeview::RegisterId::ARM_NQ8, ARM::Q8},
321 {codeview::RegisterId::ARM_NQ9, ARM::Q9},
322 {codeview::RegisterId::ARM_NQ10, ARM::Q10},
323 {codeview::RegisterId::ARM_NQ11, ARM::Q11},
324 {codeview::RegisterId::ARM_NQ12, ARM::Q12},
325 {codeview::RegisterId::ARM_NQ13, ARM::Q13},
326 {codeview::RegisterId::ARM_NQ14, ARM::Q14},
327 {codeview::RegisterId::ARM_NQ15, ARM::Q15},
329 for (
const auto &
I : RegMap)
330 MRI->mapLLVMRegToCVReg(
I.Reg,
static_cast<int>(
I.CVReg));
335 InitARMMCRegisterInfo(
X, ARM::LR, 0, 0, ARM::PC);
353 unsigned Reg =
MRI.getDwarfRegNum(ARM::SP,
true);
360 std::unique_ptr<MCAsmBackend> &&MAB,
361 std::unique_ptr<MCObjectWriter> &&OW,
362 std::unique_ptr<MCCodeEmitter> &&
Emitter) {
364 Ctx, std::move(MAB), std::move(OW), std::move(
Emitter),
371 std::unique_ptr<MCObjectWriter> &&OW,
372 std::unique_ptr<MCCodeEmitter> &&
Emitter,
373 bool DWARFMustBeAtTheEnd) {
375 std::move(
Emitter), DWARFMustBeAtTheEnd);
379 unsigned SyntaxVariant,
383 if (SyntaxVariant == 0)
390 if (TT.isOSBinFormatMachO())
421 for (
unsigned OpNum = 0; OpNum <
Desc.getNumOperands(); ++OpNum) {
432 std::optional<uint64_t>
439static std::optional<uint64_t>
443 if (MemOpIndex + 1 >=
Desc.getNumOperands())
451 int32_t OffImm = (int32_t)MO2.
getImm();
453 if (OffImm == INT32_MIN)
455 return Addr + OffImm;
458static std::optional<uint64_t>
461 if (MemOpIndex + 2 >=
Desc.getNumOperands())
474 return Addr - ImmOffs;
475 return Addr + ImmOffs;
478static std::optional<uint64_t>
481 if (MemOpIndex + 1 >=
Desc.getNumOperands())
493 return Addr - ImmOffs * 4;
494 return Addr + ImmOffs * 4;
497static std::optional<uint64_t>
500 if (MemOpIndex + 1 >=
Desc.getNumOperands())
512 return Addr - ImmOffs * 2;
513 return Addr + ImmOffs * 2;
516static std::optional<uint64_t>
520 if (MemOpIndex + 1 >=
Desc.getNumOperands())
528 int32_t OffImm = (int32_t)MO2.
getImm();
529 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
532 if (OffImm == INT32_MIN)
534 return Addr + OffImm;
537static std::optional<uint64_t>
545 int32_t OffImm = (int32_t)MO1.
getImm();
548 if (OffImm == INT32_MIN)
550 return Addr + OffImm;
553static std::optional<uint64_t>
560std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
626 return new ARMMCInstrAnalysis(
Info);
unsigned const MachineRegisterInfo * MRI
static std::optional< uint64_t > evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static std::optional< uint64_t > evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool DWARFMustBeAtTheEnd)
static std::optional< uint64_t > evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static std::optional< uint64_t > evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static MCStreamer * createELFStreamer(const Triple &T, MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)
static MCInstrInfo * createARMMCInstrInfo()
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
dxil DXContainer Global Emitter
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class represents an Operation in the Expression.
This class is intended to be used as a base class for asm properties and features specific to the tar...
void addInitialFrameState(const MCCFIInstruction &Inst)
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Context object for machine code objects.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
const MCOperand & getOperand(unsigned i) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const
Given an instruction tries to get the address of a memory operand.
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Create MCExprs from relocations found in an object file.
Streaming machine code generation interface.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
IndexMode
ARM Index Modes.
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
AddrOpc getAM5Op(unsigned AM5Opc)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
StringRef getArchName(ArchKind AK)
ArchKind parseArch(StringRef Arch)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ D16
Only 16 D registers.
This is an optimization pass for GlobalISel generic memory operations.
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool IsThumb, bool IsAndroid)
Target & getTheThumbBETarget()
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Target & getTheARMLETarget()
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool IncrementalLinkerCompatible)
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
Description of the encoding of one expression Op.
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.