LLVM  16.0.0git
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/TargetRegistry.h"
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38 
40  std::string &Info) {
41  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44  // Checks for the deprecated CP15ISB encoding:
45  // mcr p15, #0, rX, c7, c5, #4
46  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49  Info = "deprecated since v7, use 'isb'";
50  return true;
51  }
52 
53  // Checks for the deprecated CP15DSB encoding:
54  // mcr p15, #0, rX, c7, c10, #4
55  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56  Info = "deprecated since v7, use 'dsb'";
57  return true;
58  }
59  }
60  // Checks for the deprecated CP15DMB encoding:
61  // mcr p15, #0, rX, c7, c10, #5
62  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64  Info = "deprecated since v7, use 'dmb'";
65  return true;
66  }
67  }
68  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72  "point instructions";
73  return true;
74  }
75  return false;
76 }
77 
79  std::string &Info) {
80  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84  "point instructions";
85  return true;
86  }
87  return false;
88 }
89 
91  std::string &Info) {
92  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
93  "cannot predicate thumb instructions");
94 
95  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
96  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
97  assert(MI.getOperand(OI).isReg() && "expected register");
98  if (MI.getOperand(OI).getReg() == ARM::PC) {
99  Info = "use of PC in the list is deprecated";
100  return true;
101  }
102  }
103  return false;
104 }
105 
107  std::string &Info) {
108  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
109  "cannot predicate thumb instructions");
110 
111  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
112  bool ListContainsPC = false, ListContainsLR = false;
113  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
114  assert(MI.getOperand(OI).isReg() && "expected register");
115  switch (MI.getOperand(OI).getReg()) {
116  default:
117  break;
118  case ARM::LR:
119  ListContainsLR = true;
120  break;
121  case ARM::PC:
122  ListContainsPC = true;
123  break;
124  }
125  }
126 
127  if (ListContainsPC && ListContainsLR) {
128  Info = "use of LR and PC simultaneously in the list is deprecated";
129  return true;
130  }
131 
132  return false;
133 }
134 
135 #define GET_INSTRINFO_MC_DESC
136 #define ENABLE_INSTR_PREDICATE_VERIFIER
137 #include "ARMGenInstrInfo.inc"
138 
139 #define GET_SUBTARGETINFO_MC_DESC
140 #include "ARMGenSubtargetInfo.inc"
141 
142 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
143  std::string ARMArchFeature;
144 
145  ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
146  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
147  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
148 
149  if (TT.isThumb()) {
150  if (!ARMArchFeature.empty())
151  ARMArchFeature += ",";
152  ARMArchFeature += "+thumb-mode,+v4t";
153  }
154 
155  if (TT.isOSNaCl()) {
156  if (!ARMArchFeature.empty())
157  ARMArchFeature += ",";
158  ARMArchFeature += "+nacl-trap";
159  }
160 
161  if (TT.isOSWindows()) {
162  if (!ARMArchFeature.empty())
163  ARMArchFeature += ",";
164  ARMArchFeature += "+noarm";
165  }
166 
167  return ARMArchFeature;
168 }
169 
170 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
171  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
172  int PredOpIdx = Desc.findFirstPredOperandIdx();
173  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
174 }
175 
176 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
177  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
178  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
179  const MCOperand &MO = MI.getOperand(I);
180  if (MO.isReg() && MO.getReg() == ARM::CPSR &&
181  Desc.OpInfo[I].isOptionalDef())
182  return true;
183  }
184  return false;
185 }
186 
188  uint64_t Addr, int64_t Imm) {
189  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
190  // is 4 bytes.
191  uint64_t Offset =
192  ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
193 
194  // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
195  // which is 32-bit aligned. The target address for the case is calculated as
196  // targetAddress = Align(PC,4) + imm32;
197  // where
198  // Align(x, y) = y * (x DIV y);
199  if (InstDesc.getOpcode() == ARM::tBLXi)
200  Addr &= ~0x3;
201 
202  return Addr + Imm + Offset;
203 }
204 
206  StringRef CPU, StringRef FS) {
207  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
208  if (!FS.empty()) {
209  if (!ArchFS.empty())
210  ArchFS = (Twine(ArchFS) + "," + FS).str();
211  else
212  ArchFS = std::string(FS);
213  }
214 
215  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
216 }
217 
219  MCInstrInfo *X = new MCInstrInfo();
220  InitARMMCInstrInfo(X);
221  return X;
222 }
223 
225  // Mapping from CodeView to MC register id.
226  static const struct {
227  codeview::RegisterId CVReg;
228  MCPhysReg Reg;
229  } RegMap[] = {
230  {codeview::RegisterId::ARM_R0, ARM::R0},
231  {codeview::RegisterId::ARM_R1, ARM::R1},
232  {codeview::RegisterId::ARM_R2, ARM::R2},
233  {codeview::RegisterId::ARM_R3, ARM::R3},
234  {codeview::RegisterId::ARM_R4, ARM::R4},
235  {codeview::RegisterId::ARM_R5, ARM::R5},
236  {codeview::RegisterId::ARM_R6, ARM::R6},
237  {codeview::RegisterId::ARM_R7, ARM::R7},
238  {codeview::RegisterId::ARM_R8, ARM::R8},
239  {codeview::RegisterId::ARM_R9, ARM::R9},
240  {codeview::RegisterId::ARM_R10, ARM::R10},
241  {codeview::RegisterId::ARM_R11, ARM::R11},
242  {codeview::RegisterId::ARM_R12, ARM::R12},
243  {codeview::RegisterId::ARM_SP, ARM::SP},
244  {codeview::RegisterId::ARM_LR, ARM::LR},
245  {codeview::RegisterId::ARM_PC, ARM::PC},
246  {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
247  {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
248  {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
249  {codeview::RegisterId::ARM_FS0, ARM::S0},
250  {codeview::RegisterId::ARM_FS1, ARM::S1},
251  {codeview::RegisterId::ARM_FS2, ARM::S2},
252  {codeview::RegisterId::ARM_FS3, ARM::S3},
253  {codeview::RegisterId::ARM_FS4, ARM::S4},
254  {codeview::RegisterId::ARM_FS5, ARM::S5},
255  {codeview::RegisterId::ARM_FS6, ARM::S6},
256  {codeview::RegisterId::ARM_FS7, ARM::S7},
257  {codeview::RegisterId::ARM_FS8, ARM::S8},
258  {codeview::RegisterId::ARM_FS9, ARM::S9},
259  {codeview::RegisterId::ARM_FS10, ARM::S10},
260  {codeview::RegisterId::ARM_FS11, ARM::S11},
261  {codeview::RegisterId::ARM_FS12, ARM::S12},
262  {codeview::RegisterId::ARM_FS13, ARM::S13},
263  {codeview::RegisterId::ARM_FS14, ARM::S14},
264  {codeview::RegisterId::ARM_FS15, ARM::S15},
265  {codeview::RegisterId::ARM_FS16, ARM::S16},
266  {codeview::RegisterId::ARM_FS17, ARM::S17},
267  {codeview::RegisterId::ARM_FS18, ARM::S18},
268  {codeview::RegisterId::ARM_FS19, ARM::S19},
269  {codeview::RegisterId::ARM_FS20, ARM::S20},
270  {codeview::RegisterId::ARM_FS21, ARM::S21},
271  {codeview::RegisterId::ARM_FS22, ARM::S22},
272  {codeview::RegisterId::ARM_FS23, ARM::S23},
273  {codeview::RegisterId::ARM_FS24, ARM::S24},
274  {codeview::RegisterId::ARM_FS25, ARM::S25},
275  {codeview::RegisterId::ARM_FS26, ARM::S26},
276  {codeview::RegisterId::ARM_FS27, ARM::S27},
277  {codeview::RegisterId::ARM_FS28, ARM::S28},
278  {codeview::RegisterId::ARM_FS29, ARM::S29},
279  {codeview::RegisterId::ARM_FS30, ARM::S30},
280  {codeview::RegisterId::ARM_FS31, ARM::S31},
281  {codeview::RegisterId::ARM_ND0, ARM::D0},
282  {codeview::RegisterId::ARM_ND1, ARM::D1},
283  {codeview::RegisterId::ARM_ND2, ARM::D2},
284  {codeview::RegisterId::ARM_ND3, ARM::D3},
285  {codeview::RegisterId::ARM_ND4, ARM::D4},
286  {codeview::RegisterId::ARM_ND5, ARM::D5},
287  {codeview::RegisterId::ARM_ND6, ARM::D6},
288  {codeview::RegisterId::ARM_ND7, ARM::D7},
289  {codeview::RegisterId::ARM_ND8, ARM::D8},
290  {codeview::RegisterId::ARM_ND9, ARM::D9},
291  {codeview::RegisterId::ARM_ND10, ARM::D10},
292  {codeview::RegisterId::ARM_ND11, ARM::D11},
293  {codeview::RegisterId::ARM_ND12, ARM::D12},
294  {codeview::RegisterId::ARM_ND13, ARM::D13},
295  {codeview::RegisterId::ARM_ND14, ARM::D14},
296  {codeview::RegisterId::ARM_ND15, ARM::D15},
297  {codeview::RegisterId::ARM_ND16, ARM::D16},
298  {codeview::RegisterId::ARM_ND17, ARM::D17},
299  {codeview::RegisterId::ARM_ND18, ARM::D18},
300  {codeview::RegisterId::ARM_ND19, ARM::D19},
301  {codeview::RegisterId::ARM_ND20, ARM::D20},
302  {codeview::RegisterId::ARM_ND21, ARM::D21},
303  {codeview::RegisterId::ARM_ND22, ARM::D22},
304  {codeview::RegisterId::ARM_ND23, ARM::D23},
305  {codeview::RegisterId::ARM_ND24, ARM::D24},
306  {codeview::RegisterId::ARM_ND25, ARM::D25},
307  {codeview::RegisterId::ARM_ND26, ARM::D26},
308  {codeview::RegisterId::ARM_ND27, ARM::D27},
309  {codeview::RegisterId::ARM_ND28, ARM::D28},
310  {codeview::RegisterId::ARM_ND29, ARM::D29},
311  {codeview::RegisterId::ARM_ND30, ARM::D30},
312  {codeview::RegisterId::ARM_ND31, ARM::D31},
313  {codeview::RegisterId::ARM_NQ0, ARM::Q0},
314  {codeview::RegisterId::ARM_NQ1, ARM::Q1},
315  {codeview::RegisterId::ARM_NQ2, ARM::Q2},
316  {codeview::RegisterId::ARM_NQ3, ARM::Q3},
317  {codeview::RegisterId::ARM_NQ4, ARM::Q4},
318  {codeview::RegisterId::ARM_NQ5, ARM::Q5},
319  {codeview::RegisterId::ARM_NQ6, ARM::Q6},
320  {codeview::RegisterId::ARM_NQ7, ARM::Q7},
321  {codeview::RegisterId::ARM_NQ8, ARM::Q8},
322  {codeview::RegisterId::ARM_NQ9, ARM::Q9},
323  {codeview::RegisterId::ARM_NQ10, ARM::Q10},
324  {codeview::RegisterId::ARM_NQ11, ARM::Q11},
325  {codeview::RegisterId::ARM_NQ12, ARM::Q12},
326  {codeview::RegisterId::ARM_NQ13, ARM::Q13},
327  {codeview::RegisterId::ARM_NQ14, ARM::Q14},
328  {codeview::RegisterId::ARM_NQ15, ARM::Q15},
329  };
330  for (const auto &I : RegMap)
331  MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
332 }
333 
336  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
338  return X;
339 }
340 
342  const Triple &TheTriple,
343  const MCTargetOptions &Options) {
344  MCAsmInfo *MAI;
345  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
346  MAI = new ARMMCAsmInfoDarwin(TheTriple);
347  else if (TheTriple.isWindowsMSVCEnvironment())
348  MAI = new ARMCOFFMCAsmInfoMicrosoft();
349  else if (TheTriple.isOSWindows())
350  MAI = new ARMCOFFMCAsmInfoGNU();
351  else
352  MAI = new ARMELFMCAsmInfo(TheTriple);
353 
354  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
356 
357  return MAI;
358 }
359 
361  std::unique_ptr<MCAsmBackend> &&MAB,
362  std::unique_ptr<MCObjectWriter> &&OW,
363  std::unique_ptr<MCCodeEmitter> &&Emitter,
364  bool RelaxAll) {
365  return createARMELFStreamer(
366  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
367  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
368  T.isAndroid());
369 }
370 
371 static MCStreamer *
372 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
373  std::unique_ptr<MCObjectWriter> &&OW,
374  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
375  bool DWARFMustBeAtTheEnd) {
376  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
377  std::move(Emitter), false, DWARFMustBeAtTheEnd);
378 }
379 
381  unsigned SyntaxVariant,
382  const MCAsmInfo &MAI,
383  const MCInstrInfo &MII,
384  const MCRegisterInfo &MRI) {
385  if (SyntaxVariant == 0)
386  return new ARMInstPrinter(MAI, MII, MRI);
387  return nullptr;
388 }
389 
391  MCContext &Ctx) {
392  if (TT.isOSBinFormatMachO())
393  return createARMMachORelocationInfo(Ctx);
394  // Default to the stock relocation info.
395  return llvm::createMCRelocationInfo(TT, Ctx);
396 }
397 
398 namespace {
399 
400 class ARMMCInstrAnalysis : public MCInstrAnalysis {
401 public:
402  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
403 
404  bool isUnconditionalBranch(const MCInst &Inst) const override {
405  // BCCs with the "always" predicate are unconditional branches.
406  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
407  return true;
409  }
410 
411  bool isConditionalBranch(const MCInst &Inst) const override {
412  // BCCs with the "always" predicate are unconditional branches.
413  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
414  return false;
416  }
417 
418  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
419  uint64_t &Target) const override {
420  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
421 
422  // Find the PC-relative immediate operand in the instruction.
423  for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
424  if (Inst.getOperand(OpNum).isImm() &&
425  Desc.OpInfo[OpNum].OperandType == MCOI::OPERAND_PCREL) {
426  int64_t Imm = Inst.getOperand(OpNum).getImm();
428  return true;
429  }
430  }
431  return false;
432  }
433 
434  Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
435  const MCSubtargetInfo *STI,
436  uint64_t Addr,
437  uint64_t Size) const override;
438 };
439 
440 } // namespace
441 
442 static Optional<uint64_t>
443 // NOLINTNEXTLINE(readability-identifier-naming)
445  unsigned MemOpIndex, uint64_t Addr) {
446  if (MemOpIndex + 1 >= Desc.getNumOperands())
447  return None;
448 
449  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
450  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
451  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
452  return None;
453 
454  int32_t OffImm = (int32_t)MO2.getImm();
455  // Special value for #-0. All others are normal.
456  if (OffImm == INT32_MIN)
457  OffImm = 0;
458  return Addr + OffImm;
459 }
460 
462  const MCInstrDesc &Desc,
463  unsigned MemOpIndex,
464  uint64_t Addr) {
465  if (MemOpIndex + 2 >= Desc.getNumOperands())
466  return None;
467 
468  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
469  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
470  const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
471  if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
472  return None;
473 
474  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
476 
477  if (Op == ARM_AM::sub)
478  return Addr - ImmOffs;
479  return Addr + ImmOffs;
480 }
481 
483  const MCInstrDesc &Desc,
484  unsigned MemOpIndex,
485  uint64_t Addr) {
486  if (MemOpIndex + 1 >= Desc.getNumOperands())
487  return None;
488 
489  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
490  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
491  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
492  return None;
493 
494  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
496 
497  if (Op == ARM_AM::sub)
498  return Addr - ImmOffs * 4;
499  return Addr + ImmOffs * 4;
500 }
501 
502 static Optional<uint64_t>
504  unsigned MemOpIndex, uint64_t Addr) {
505  if (MemOpIndex + 1 >= Desc.getNumOperands())
506  return None;
507 
508  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
509  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
510  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
511  return None;
512 
513  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
515 
516  if (Op == ARM_AM::sub)
517  return Addr - ImmOffs * 2;
518  return Addr + ImmOffs * 2;
519 }
520 
521 static Optional<uint64_t>
522 // NOLINTNEXTLINE(readability-identifier-naming)
524  unsigned MemOpIndex, uint64_t Addr) {
525  if (MemOpIndex + 1 >= Desc.getNumOperands())
526  return None;
527 
528  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
529  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
530  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
531  return None;
532 
533  int32_t OffImm = (int32_t)MO2.getImm();
534  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
535 
536  // Special value for #-0. All others are normal.
537  if (OffImm == INT32_MIN)
538  OffImm = 0;
539  return Addr + OffImm;
540 }
541 
542 static Optional<uint64_t>
543 // NOLINTNEXTLINE(readability-identifier-naming)
545  unsigned MemOpIndex, uint64_t Addr) {
546  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
547  if (!MO1.isImm())
548  return None;
549 
550  int32_t OffImm = (int32_t)MO1.getImm();
551 
552  // Special value for #-0. All others are normal.
553  if (OffImm == INT32_MIN)
554  OffImm = 0;
555  return Addr + OffImm;
556 }
557 
558 static Optional<uint64_t>
559 // NOLINTNEXTLINE(readability-identifier-naming)
561  unsigned MemOpIndex, uint64_t Addr) {
562  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
563 }
564 
565 Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
566  const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
567  uint64_t Size) const {
568  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
569 
570  // Only load instructions can have PC-relative memory addressing.
571  if (!Desc.mayLoad())
572  return None;
573 
574  // PC-relative addressing does not update the base register.
575  uint64_t TSFlags = Desc.TSFlags;
576  unsigned IndexMode =
579  return None;
580 
581  // Find the memory addressing operand in the instruction.
582  unsigned OpIndex = Desc.NumDefs;
583  while (OpIndex < Desc.getNumOperands() &&
585  ++OpIndex;
586  if (OpIndex == Desc.getNumOperands())
587  return None;
588 
589  // Base address for PC-relative addressing is always 32-bit aligned.
590  Addr &= ~0x3;
591 
592  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
593  // is 4 bytes.
594  switch (Desc.TSFlags & ARMII::FormMask) {
595  default:
596  Addr += 8;
597  break;
598  case ARMII::ThumbFrm:
599  Addr += 4;
600  break;
601  // VLDR* instructions share the same opcode (and thus the same form) for Arm
602  // and Thumb. Use a bit longer route through STI in that case.
603  case ARMII::VFPLdStFrm:
604  Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8;
605  break;
606  }
607 
608  // Eveluate the address depending on the addressing mode
609  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
610  switch (AddrMode) {
611  default:
612  return None;
613  case ARMII::AddrMode_i12:
614  return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
615  case ARMII::AddrMode3:
616  return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
617  case ARMII::AddrMode5:
618  return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
620  return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr);
622  return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
624  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
625  case ARMII::AddrModeT1_s:
626  return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
627  }
628 }
629 
631  return new ARMMCInstrAnalysis(Info);
632 }
633 
634 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
635  // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
636  // to rely on feature bits.
637  if (Coproc >= 8)
638  return false;
639  return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
640 }
641 
642 // Force static initialization.
646  // Register the MC asm info.
648 
649  // Register the MC instruction info.
651 
652  // Register the MC register info.
654 
655  // Register the MC subtarget info.
658 
662 
663  // Register the obj target streamer.
666 
667  // Register the asm streamer.
669 
670  // Register the null TargetStreamer.
672 
673  // Register the MCInstPrinter.
675 
676  // Register the MC relocation info.
678  }
679 
680  // Register the MC instruction analyzer.
684 
685  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
688  }
689  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
692  }
693 }
getARMStoreDeprecationInfo
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:90
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::ARMMCAsmInfoDarwin
Definition: ARMMCAsmInfo.h:23
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
evaluateMemOpAddrForAddrMode5
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:482
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
ARMTargetInfo.h
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2008
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:142
createARMMachOStreamer
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
Definition: ARMMCTargetDesc.cpp:372
ARMMCTargetDesc.h
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::ARM::getArchName
StringRef getArchName(ArchKind AK)
Definition: ARMTargetParser.cpp:323
llvm::ARMII::AddrModeT2_pc
@ AddrModeT2_pc
Definition: ARMBaseInfo.h:202
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
ARMInstPrinter.h
MCCodeEmitter.h
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::createARMObjectTargetStreamer
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: ARMTargetStreamer.cpp:323
llvm::createARMNullTargetStreamer
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
Definition: ARMELFStreamer.cpp:1479
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition: MCRelocationInfo.h:24
ErrorHandling.h
llvm::createARMBEAsmBackend
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1320
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::createARMLEAsmBackend
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1313
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1038
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:881
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
llvm::ARM_MC::isCPSRDefined
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:176
R4
#define R4(n)
llvm::createMachOStreamer
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition: MCMachOStreamer.cpp:566
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:205
llvm::ARM_AM::getAM5FP16Op
AddrOpc getAM5FP16Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:517
llvm::Optional< uint64_t >
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:627
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:988
createARMMCInstPrinter
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: ARMMCTargetDesc.cpp:380
llvm::ARMII::IndexMode
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:177
OpIndex
unsigned OpIndex
Definition: SPIRVModuleAnalysis.cpp:46
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1005
MCELFStreamer.h
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:592
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:201
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:204
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
R2
#define R2(n)
llvm::ARMII::ThumbFrm
@ ThumbFrm
Definition: ARMBaseInfo.h:360
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
Emitter
dxil DXContainer Global Emitter
Definition: DXContainerGlobals.cpp:67
llvm::ARM_AM::AddrOpc
AddrOpc
Definition: ARMAddressingModes.h:37
llvm::ARM_MC::evaluateBranchTarget
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
Definition: ARMMCTargetDesc.cpp:187
ARMBaseInfo.h
MCAsmBackend.h
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:170
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:517
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:315
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:686
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:48
llvm::ARMII::IndexModeMask
@ IndexModeMask
Definition: ARMBaseInfo.h:309
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::X86AS::FS
@ FS
Definition: X86.h:200
createARMMCRelocationInfo
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: ARMMCTargetDesc.cpp:390
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
evaluateMemOpAddrForAddrModeT2_i8s4
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:523
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
getMRCDeprecationInfo
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:78
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:29
CodeView.h
llvm::ARMCOFFMCAsmInfoMicrosoft
Definition: ARMMCAsmInfo.h:39
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1178
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
createARMMCInstrInfo
static MCInstrInfo * createARMMCInstrInfo()
Definition: ARMMCTargetDesc.cpp:218
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:595
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:435
evaluateMemOpAddrForAddrMode3
static Optional< uint64_t > evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:461
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:935
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:1009
evaluateMemOpAddrForAddrMode5FP16
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:503
uint64_t
getARMLoadDeprecationInfo
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:106
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:44
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::ARMELFMCAsmInfo
Definition: ARMMCAsmInfo.h:30
evaluateMemOpAddrForAddrModeT1_s
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:560
llvm::createARMTargetAsmStreamer
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: ARMELFStreamer.cpp:1472
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::ARMII::AddrModeT1_s
@ AddrModeT1_s
Definition: ARMBaseInfo.h:196
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1044
MCRegisterInfo.h
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:224
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:519
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
evaluateMemOpAddrForAddrModeT2_pc
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:544
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:908
R6
#define R6(n)
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
Triple.h
llvm::createARMELFStreamer
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb, bool IsAndroid)
Definition: ARMELFStreamer.cpp:1487
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
MCInstrAnalysis.h
ARMAddressingModes.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::Triple::thumb
@ thumb
Definition: Triple.h:83
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMII::VFPLdStFrm
@ VFPLdStFrm
Definition: ARMBaseInfo.h:355
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::createARMMachORelocationInfo
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
Definition: ARMMachORelocationInfo.cpp:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:211
llvm::createARMWinCOFFStreamer
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: ARMWinCOFFStreamer.cpp:69
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:582
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:890
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:875
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:1001
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:96
createARMMCAsmInfo
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: ARMMCTargetDesc.cpp:341
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
uint16_t
llvm::ARMII::IndexModeNone
@ IndexModeNone
Definition: ARMBaseInfo.h:178
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:895
llvm::ARMInstPrinter
Definition: ARMInstPrinter.h:21
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1013
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
llvm::ARM_MC::createARMMCSubtargetInfo
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Definition: ARMMCTargetDesc.cpp:205
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1033
evaluateMemOpAddrForAddrMode_i12
static Optional< uint64_t > evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:444
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ARM_AM::getAM5FP16Offset
unsigned char getAM5FP16Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:514
getMCRDeprecationInfo
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:39
LLVMInitializeARMTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()
Definition: ARMMCTargetDesc.cpp:643
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
llvm::Triple::thumbeb
@ thumbeb
Definition: Triple.h:84
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ARMCOFFMCAsmInfoGNU
Definition: ARMMCAsmInfo.h:46
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2013
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:634
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::ARMII::IndexModeShift
@ IndexModeShift
Definition: ARMBaseInfo.h:308
createARMMCRegisterInfo
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Definition: ARMMCTargetDesc.cpp:334
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition: TargetRegistry.h:1058
createARMMCInstrAnalysis
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
Definition: ARMMCTargetDesc.cpp:630
ARMMCAsmInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69