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13 #ifndef LLVM_AVR_INSTR_INFO_H
14 #define LLVM_AVR_INSTR_INFO_H
20 #define GET_INSTRINFO_HEADER
21 #include "AVRGenInstrInfo.inc"
22 #undef GET_INSTRINFO_HEADER
76 bool KillSrc)
const override;
95 bool AllowModify =
false)
const override;
99 int *BytesAdded =
nullptr)
const override;
101 int *BytesRemoved =
nullptr)
const override;
108 int64_t BrOffset)
const override;
121 #endif // LLVM_AVR_INSTR_INFO_H
This is an optimization pass for GlobalISel generic memory operations.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
TOF
Specifies a target operand flag.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned const TargetRegisterInfo * TRI
@ COND_SH
Unsigned same or higher.
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Describe properties that are true of each instruction in the target description file.
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
@ COND_GE
Greater than or equal.
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
CondCodes
AVR specific condition codes.
Representation of each machine instruction.
Utilities relating to AVR registers.
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
@ MO_NEG
On a symbol operand, this represents it has to be negated.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Wrapper class representing virtual and physical registers.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const AVRRegisterInfo & getRegisterInfo() const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Utilities related to the AVR instruction set.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ MO_LO
On a symbol operand, this represents the lo part.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Wrapper class representing physical registers. Should be passed by value.
@ MO_HI
On a symbol operand, this represents the hi part.