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33 #define GET_INSTRINFO_CTOR_DTOR
34 #include "AVRGenInstrInfo.inc"
50 if (AVR::DREGSRegClass.
contains(DestReg, SrcReg)) {
51 if (STI.
hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
55 Register DestLo, DestHi, SrcLo, SrcHi;
57 TRI.splitReg(DestReg, DestLo, DestHi);
58 TRI.splitReg(SrcReg, SrcLo, SrcHi);
67 if (AVR::GPR8RegClass.
contains(DestReg, SrcReg)) {
69 }
else if (SrcReg == AVR::SP && AVR::DREGSRegClass.
contains(DestReg)) {
71 }
else if (DestReg == AVR::SP && AVR::DREGSRegClass.
contains(SrcReg)) {
84 switch (
MI.getOpcode()) {
87 if (
MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() &&
88 MI.getOperand(2).getImm() == 0) {
90 return MI.getOperand(0).getReg();
103 switch (
MI.getOpcode()) {
105 case AVR::STDWPtrQRr: {
106 if (
MI.getOperand(0).isFI() &&
MI.getOperand(1).isImm() &&
107 MI.getOperand(1).getImm() == 0) {
109 return MI.getOperand(2).getReg();
132 if (
MI !=
MBB.end()) {
133 DL =
MI->getDebugLoc();
145 Opcode = AVR::STDPtrQRr;
146 }
else if (
TRI->isTypeLegalForClass(*RC,
MVT::i16)) {
147 Opcode = AVR::STDWPtrQRr;
165 if (
MI !=
MBB.end()) {
166 DL =
MI->getDebugLoc();
179 Opcode = AVR::LDDRdPtrQ;
180 }
else if (
TRI->isTypeLegalForClass(*RC,
MVT::i16)) {
183 Opcode = AVR::LDDWRdYQ;
199 return get(AVR::BREQk);
201 return get(AVR::BRNEk);
203 return get(AVR::BRGEk);
205 return get(AVR::BRLTk);
207 return get(AVR::BRSHk);
209 return get(AVR::BRLOk);
211 return get(AVR::BRMIk);
213 return get(AVR::BRPLk);
267 bool AllowModify)
const {
273 while (
I !=
MBB.begin()) {
275 if (
I->isDebugInstr()) {
281 if (!isUnpredicatedTerminator(*
I)) {
287 if (!
I->getDesc().isBranch()) {
293 if (
I->getOpcode() == AVR::RJMPk) {
297 TBB =
I->getOperand(0).getMBB();
302 while (std::next(
I) !=
MBB.end()) {
303 std::next(
I)->eraseFromParent();
310 if (
MBB.isLayoutSuccessor(
I->getOperand(0).getMBB())) {
312 I->eraseFromParent();
314 UnCondBrIter =
MBB.end();
319 TBB =
I->getOperand(0).getMBB();
332 if (AllowModify && UnCondBrIter !=
MBB.end() &&
333 MBB.isLayoutSuccessor(TargetBB)) {
356 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
360 OldInst->eraseFromParent();
361 UnCondBrIter->eraseFromParent();
364 UnCondBrIter =
MBB.end();
370 TBB =
I->getOperand(0).getMBB();
382 if (TBB !=
I->getOperand(0).getMBB()) {
388 if (OldBranchCode == BranchCode) {
403 int *BytesAdded)
const {
404 if (BytesAdded) *BytesAdded = 0;
407 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
409 "AVR branch conditions have one component!");
412 assert(!FBB &&
"Unconditional branch with multiple successors!");
438 int *BytesRemoved)
const {
439 if (BytesRemoved) *BytesRemoved = 0;
444 while (
I !=
MBB.begin()) {
446 if (
I->isDebugInstr()) {
451 if (
I->getOpcode() != AVR::RJMPk &&
458 I->eraseFromParent();
468 assert(
Cond.size() == 1 &&
"Invalid AVR branch condition!");
477 unsigned Opcode =
MI.getOpcode();
486 case TargetOpcode::IMPLICIT_DEF:
487 case TargetOpcode::KILL:
488 case TargetOpcode::DBG_VALUE:
497 return TII.getInlineAsmLength(
MI.getOperand(0).getSymbolName(),
505 switch (
MI.getOpcode()) {
520 return MI.getOperand(0).getMBB();
523 return MI.getOperand(1).getMBB();
533 int64_t BrOffset)
const {
543 return isIntN(13, BrOffset);
554 return isIntN(7, BrOffset);
unsigned getOpcode() const
Return the opcode number for this descriptor.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
return AArch64::GPR64RegClass contains(Reg)
A generic AVR implementation.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A description of a memory reference used in the backend.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned const TargetRegisterInfo * TRI
@ COND_SH
Unsigned same or higher.
@ INLINEASM
INLINEASM - Represents an inline asm block.
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
TargetInstrInfo - Interface to description of machine instruction set.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static MachineOperand CreateImm(int64_t Val)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
A specific AVR target MCU.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const AVRInstrInfo * getInstrInfo() const override
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
@ COND_GE
Greater than or equal.
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addFrameIndex(int Idx) const
CondCodes
AVR specific condition codes.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Utilities relating to AVR registers.
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
void setHasSpills(bool B)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Should compile to something r4 addze r3 instead we get
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
@ MOStore
The memory access writes data.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const AVRRegisterInfo * getRegisterInfo() const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Contains AVR-specific information for each MachineFunction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Wrapper class representing physical registers. Should be passed by value.