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16 #ifndef LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
17 #define LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
29 class MachineBasicBlock;
30 class MachineFunction;
33 class MachineRegisterInfo;
34 class RegisterClassInfo;
35 class TargetInstrInfo;
36 class TargetRegisterClass;
37 class TargetRegisterInfo;
53 const unsigned NumTargetRegs;
60 std::vector<unsigned> GroupNodes;
66 std::vector<unsigned> GroupNodeIndices;
69 std::multimap<unsigned, RegisterReference> RegRefs;
73 std::vector<unsigned> KillIndices;
77 std::vector<unsigned> DefIndices;
89 std::multimap<unsigned, RegisterReference>&
GetRegRefs() {
return RegRefs; }
93 unsigned GetGroup(
unsigned Reg);
99 std::vector<unsigned> &Regs,
100 std::multimap<
unsigned,
105 unsigned UnionGroups(
unsigned Reg1,
unsigned Reg2);
110 unsigned LeaveGroup(
unsigned Reg);
113 bool IsLive(
unsigned Reg);
142 unsigned BreakAntiDependencies(
const std::vector<SUnit> &SUnits,
145 unsigned InsertPosIndex,
151 unsigned InsertPosIndex)
override;
154 void FinishBlock()
override;
158 using RenameOrderType = std::map<const TargetRegisterClass *, unsigned>;
166 void GetPassthruRegs(
MachineInstr &
MI, std::set<unsigned> &PassthruRegs);
168 void HandleLastUse(
unsigned Reg,
unsigned KillIdx,
const char *tag,
169 const char *header =
nullptr,
170 const char *footer =
nullptr);
173 std::set<unsigned> &PassthruRegs);
176 bool FindSuitableFreeRegisters(
unsigned AntiDepGroupIndex,
177 RenameOrderType& RenameOrder,
178 std::map<unsigned, unsigned> &RenameMap);
183 #endif // LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
This is an optimization pass for GlobalISel generic memory operations.
std::multimap< unsigned, RegisterReference > & GetRegRefs()
Return the RegRefs map.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand * Operand
The registers operand.
unsigned const TargetRegisterInfo * TRI
Contains all the state necessary for anti-dep breaking.
TargetInstrInfo - Interface to description of machine instruction set.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
Representation of each machine instruction.
std::vector< unsigned > & GetKillIndices()
Return the kill indices.
std::vector< unsigned > & GetDefIndices()
Return the define indices.
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
const TargetRegisterClass * RC
The register class.
unsigned const MachineRegisterInfo * MRI
Information about a register reference within a liverange.
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector