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19 #define DEBUG_TYPE "csky-asmbackend"
23 std::unique_ptr<MCObjectTargetWriter>
38 {
"fixup_csky_pcrel_uimm16_scale4", 0, 32,
42 {
"fixup_csky_pcrel_uimm8_scale4", 0, 32,
51 {
"fixup_csky_got_imm18_scale4", 0, 32, 0}},
57 {
"fixup_csky_plt_imm18_scale4", 0, 32, 0}},
61 {
"fixup_csky_pcrel_uimm7_scale4", 0, 16,
65 {
"fixup_csky_doffset_imm18", 0, 18, 0}},
67 {
"fixup_csky_doffset_imm18_scale2", 0, 18, 0}},
69 {
"fixup_csky_doffset_imm18_scale4", 0, 18, 0}}};
72 "Not all fixup kinds added to Infos array");
88 switch (
Fixup.getTargetKind()) {
104 return Value & 0xffffffff;
111 return (
Value >> 1) & 0xffff;
118 return (
Value >> 2) & 0xffff;
125 return (
Value >> 1) & 0x3ffffff;
132 return (
Value >> 1) & 0x3ffff;
139 unsigned IMM4L = (
Value >> 2) & 0xf;
140 unsigned IMM4H = (
Value >> 6) & 0xf;
142 Value = (IMM4H << 21) | (IMM4L << 4);
151 return (
Value >> 1) & 0x3ff;
158 if ((
Value & 0xff) <= 0b111111100) {
159 unsigned IMM5L = (
Value >> 2) & 0x1f;
160 unsigned IMM2H = (
Value >> 7) & 0
x3;
162 Value = (1 << 12) | (IMM2H << 8) | IMM5L;
164 unsigned IMM5L = (!
Value >> 2) & 0x1f;
165 unsigned IMM2H = (!
Value >> 7) & 0
x3;
167 Value = (IMM2H << 8) | IMM5L;
170 return Value & 0xffff;
178 const bool WasForced)
const {
183 if (!Resolved && !WasForced)
186 int64_t Offset = int64_t(
Value);
187 switch (
Fixup.getTargetKind()) {
191 return !isShiftedInt<10, 1>(Offset);
193 return !isShiftedInt<16, 1>(Offset);
195 return !isShiftedInt<26, 1>(Offset);
197 return !isShiftedUInt<8, 2>(Offset);
219 unsigned Offset =
Fixup.getOffset();
220 unsigned NumBytes =
alignTo(
Info.TargetSize +
Info.TargetOffset, 8) / 8;
222 assert(Offset + NumBytes <=
Data.size() &&
"Invalid fixup offset!");
229 if (IsLittleEndian && IsInstFixup && (NumBytes == 4)) {
230 Data[Offset + 0] |= uint8_t((
Value >> 16) & 0xff);
231 Data[Offset + 1] |= uint8_t((
Value >> 24) & 0xff);
232 Data[Offset + 2] |= uint8_t(
Value & 0xff);
233 Data[Offset + 3] |= uint8_t((
Value >> 8) & 0xff);
235 for (
unsigned I = 0;
I != NumBytes;
I++) {
236 unsigned Idx = IsLittleEndian ?
I : (NumBytes - 1 -
I);
237 Data[Offset + Idx] |= uint8_t((
Value >> (
I * 8)) & 0xff);
268 switch (
Fixup.getTargetKind()) {
334 opcode = Inst.
getOpcode() == CSKY::JBT16 ? CSKY::JBT32 : CSKY::JBF32;
336 opcode = Inst.
getOpcode() == CSKY::JBT16 ? CSKY::JBT_E : CSKY::JBF_E;
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Context object for machine code objects.
Target - Wrapper for Target specific information.
@ fixup_csky_pcrel_imm10_scale2
@ fixup_csky_pcrel_uimm7_scale4
@ fixup_csky_doffset_imm18
Instances of this class represent a single low-level machine instruction.
@ fixup_csky_got_imm18_scale4
unsigned int getNumFixupKinds() const override
Get the number of target specific fixup kinds.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ fixup_csky_pcrel_uimm8_scale4
const support::endianness Endian
void setOpcode(unsigned Op)
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
@ FK_Data_4
A four-byte fixup.
Generic interface to target specific assembler backends.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
@ fixup_csky_doffset_imm18_scale4
@ fixup_csky_doffset_imm18_scale2
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
const FeatureBitset & getFeatureBits() const
MCAsmBackend * createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
Analysis containing CSE Info
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
@ fixup_csky_pcrel_imm26_scale2
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
void addOperand(const MCOperand Op)
@ fixup_csky_pcrel_imm16_scale2
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
Target independent information on a fixup kind.
void reportError(SMLoc L, const Twine &Msg)
@ fixup_csky_pcrel_uimm16_scale4
@ FK_Data_1
A one-byte fixup.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
@ fixup_csky_plt_imm18_scale4
PowerPC TLS Dynamic Call Fixup
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_csky_pcrel_imm18_scale2
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
unsigned const MachineRegisterInfo * MRI
std::unique_ptr< MCObjectTargetWriter > createCSKYELFObjectWriter()
Encapsulates the layout of an assembly file at a particular point in time.
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getOpcode() const
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_Data_8
A eight-byte fixup.
const MCOperand & getOperand(unsigned i) const
This represents an "assembler immediate".
@ FK_Data_2
A two-byte fixup.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.