LLVM  15.0.0git
MachineInstrBundle.cpp
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1 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/SmallSet.h"
11 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/InitializePasses.h"
19 #include "llvm/Pass.h"
20 #include "llvm/PassRegistry.h"
21 #include <utility>
22 using namespace llvm;
23 
24 namespace {
25  class UnpackMachineBundles : public MachineFunctionPass {
26  public:
27  static char ID; // Pass identification
28  UnpackMachineBundles(
29  std::function<bool(const MachineFunction &)> Ftor = nullptr)
30  : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
32  }
33 
34  bool runOnMachineFunction(MachineFunction &MF) override;
35 
36  private:
37  std::function<bool(const MachineFunction &)> PredicateFtor;
38  };
39 } // end anonymous namespace
40 
43 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
44  "Unpack machine instruction bundles", false, false)
45 
46 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
47  if (PredicateFtor && !PredicateFtor(MF))
48  return false;
49 
50  bool Changed = false;
51  for (MachineBasicBlock &MBB : MF) {
53  MIE = MBB.instr_end(); MII != MIE; ) {
54  MachineInstr *MI = &*MII;
55 
56  // Remove BUNDLE instruction and the InsideBundle flags from bundled
57  // instructions.
58  if (MI->isBundle()) {
59  while (++MII != MIE && MII->isBundledWithPred()) {
60  MII->unbundleFromPred();
61  for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
62  MachineOperand &MO = MII->getOperand(i);
63  if (MO.isReg() && MO.isInternalRead())
64  MO.setIsInternalRead(false);
65  }
66  }
67  MI->eraseFromParent();
68 
69  Changed = true;
70  continue;
71  }
72 
73  ++MII;
74  }
75  }
76 
77  return Changed;
78 }
79 
82  std::function<bool(const MachineFunction &)> Ftor) {
83  return new UnpackMachineBundles(std::move(Ftor));
84 }
85 
86 namespace {
87  class FinalizeMachineBundles : public MachineFunctionPass {
88  public:
89  static char ID; // Pass identification
90  FinalizeMachineBundles() : MachineFunctionPass(ID) {
92  }
93 
94  bool runOnMachineFunction(MachineFunction &MF) override;
95  };
96 } // end anonymous namespace
97 
100 INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
101  "Finalize machine instruction bundles", false, false)
102 
103 bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
104  return llvm::finalizeBundles(MF);
105 }
106 
107 /// Return the first found DebugLoc that has a DILocation, given a range of
108 /// instructions. The search range is from FirstMI to LastMI (exclusive). If no
109 /// DILocation is found, then an empty location is returned.
112  for (auto MII = FirstMI; MII != LastMI; ++MII)
113  if (MII->getDebugLoc())
114  return MII->getDebugLoc();
115  return DebugLoc();
116 }
117 
118 /// finalizeBundle - Finalize a machine instruction bundle which includes
119 /// a sequence of instructions starting from FirstMI to LastMI (exclusive).
120 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
121 /// IsInternalRead markers to MachineOperands which are defined inside the
122 /// bundle, and it copies externally visible defs and uses to the BUNDLE
123 /// instruction.
127  assert(FirstMI != LastMI && "Empty bundle?");
128  MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
129 
130  MachineFunction &MF = *MBB.getParent();
133 
134  MachineInstrBuilder MIB =
135  BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));
136  Bundle.prepend(MIB);
137 
138  SmallVector<Register, 32> LocalDefs;
139  SmallSet<Register, 32> LocalDefSet;
140  SmallSet<Register, 8> DeadDefSet;
141  SmallSet<Register, 16> KilledDefSet;
142  SmallVector<Register, 8> ExternUses;
143  SmallSet<Register, 8> ExternUseSet;
144  SmallSet<Register, 8> KilledUseSet;
145  SmallSet<Register, 8> UndefUseSet;
147  for (auto MII = FirstMI; MII != LastMI; ++MII) {
148  // Debug instructions have no effects to track.
149  if (MII->isDebugInstr())
150  continue;
151 
152  for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
153  MachineOperand &MO = MII->getOperand(i);
154  if (!MO.isReg())
155  continue;
156  if (MO.isDef()) {
157  Defs.push_back(&MO);
158  continue;
159  }
160 
161  Register Reg = MO.getReg();
162  if (!Reg)
163  continue;
164 
165  if (LocalDefSet.count(Reg)) {
166  MO.setIsInternalRead();
167  if (MO.isKill())
168  // Internal def is now killed.
169  KilledDefSet.insert(Reg);
170  } else {
171  if (ExternUseSet.insert(Reg).second) {
172  ExternUses.push_back(Reg);
173  if (MO.isUndef())
174  UndefUseSet.insert(Reg);
175  }
176  if (MO.isKill())
177  // External def is now killed.
178  KilledUseSet.insert(Reg);
179  }
180  }
181 
182  for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
183  MachineOperand &MO = *Defs[i];
184  Register Reg = MO.getReg();
185  if (!Reg)
186  continue;
187 
188  if (LocalDefSet.insert(Reg).second) {
189  LocalDefs.push_back(Reg);
190  if (MO.isDead()) {
191  DeadDefSet.insert(Reg);
192  }
193  } else {
194  // Re-defined inside the bundle, it's no longer killed.
195  KilledDefSet.erase(Reg);
196  if (!MO.isDead())
197  // Previously defined but dead.
198  DeadDefSet.erase(Reg);
199  }
200 
201  if (!MO.isDead() && Register::isPhysicalRegister(Reg)) {
202  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
203  unsigned SubReg = *SubRegs;
204  if (LocalDefSet.insert(SubReg).second)
205  LocalDefs.push_back(SubReg);
206  }
207  }
208  }
209 
210  Defs.clear();
211  }
212 
214  for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
215  Register Reg = LocalDefs[i];
216  if (Added.insert(Reg).second) {
217  // If it's not live beyond end of the bundle, mark it dead.
218  bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
219  MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
220  getImplRegState(true));
221  }
222  }
223 
224  for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
225  Register Reg = ExternUses[i];
226  bool isKill = KilledUseSet.count(Reg);
227  bool isUndef = UndefUseSet.count(Reg);
229  getImplRegState(true));
230  }
231 
232  // Set FrameSetup/FrameDestroy for the bundle. If any of the instructions got
233  // the property, then also set it on the bundle.
234  for (auto MII = FirstMI; MII != LastMI; ++MII) {
235  if (MII->getFlag(MachineInstr::FrameSetup))
237  if (MII->getFlag(MachineInstr::FrameDestroy))
239  }
240 }
241 
242 /// finalizeBundle - Same functionality as the previous finalizeBundle except
243 /// the last instruction in the bundle is not provided as an input. This is
244 /// used in cases where bundles are pre-determined by marking instructions
245 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
246 /// points to the end of the bundle.
251  MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
252  while (LastMI != E && LastMI->isInsideBundle())
253  ++LastMI;
254  finalizeBundle(MBB, FirstMI, LastMI);
255  return LastMI;
256 }
257 
258 /// finalizeBundles - Finalize instruction bundles in the specified
259 /// MachineFunction. Return true if any bundles are finalized.
261  bool Changed = false;
262  for (MachineBasicBlock &MBB : MF) {
265  if (MII == MIE)
266  continue;
267  assert(!MII->isInsideBundle() &&
268  "First instr cannot be inside bundle before finalization!");
269 
270  for (++MII; MII != MIE; ) {
271  if (!MII->isInsideBundle())
272  ++MII;
273  else {
274  MII = finalizeBundle(MBB, std::prev(MII));
275  Changed = true;
276  }
277  }
278  }
279 
280  return Changed;
281 }
282 
285  SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) {
286  VirtRegInfo RI = {false, false, false};
287  for (MIBundleOperands O(MI); O.isValid(); ++O) {
288  MachineOperand &MO = *O;
289  if (!MO.isReg() || MO.getReg() != Reg)
290  continue;
291 
292  // Remember each (MI, OpNo) that refers to Reg.
293  if (Ops)
294  Ops->push_back(std::make_pair(MO.getParent(), O.getOperandNo()));
295 
296  // Both defs and uses can read virtual registers.
297  if (MO.readsReg()) {
298  RI.Reads = true;
299  if (MO.isDef())
300  RI.Tied = true;
301  }
302 
303  // Only defs can write.
304  if (MO.isDef())
305  RI.Writes = true;
306  else if (!RI.Tied &&
307  MO.getParent()->isRegTiedToDefOperand(O.getOperandNo()))
308  RI.Tied = true;
309  }
310  return RI;
311 }
312 
314  const TargetRegisterInfo *TRI) {
315  bool AllDefsDead = true;
316  PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
317 
318  assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!");
319  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
320  const MachineOperand &MO = *O;
321 
322  if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
323  PRI.Clobbered = true;
324  continue;
325  }
326 
327  if (!MO.isReg())
328  continue;
329 
330  Register MOReg = MO.getReg();
331  if (!MOReg || !Register::isPhysicalRegister(MOReg))
332  continue;
333 
334  if (!TRI->regsOverlap(MOReg, Reg))
335  continue;
336 
337  bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
338  if (MO.readsReg()) {
339  PRI.Read = true;
340  if (Covered) {
341  PRI.FullyRead = true;
342  if (MO.isKill())
343  PRI.Killed = true;
344  }
345  } else if (MO.isDef()) {
346  PRI.Defined = true;
347  if (Covered)
348  PRI.FullyDefined = true;
349  if (!MO.isDead())
350  AllDefsDead = false;
351  }
352  }
353 
354  if (AllDefsDead) {
355  if (PRI.FullyDefined || PRI.Clobbered)
356  PRI.DeadDef = true;
357  else if (PRI.Defined)
358  PRI.PartialDeadDef = true;
359  }
360 
361  return PRI;
362 }
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:527
llvm::VirtRegInfo::Tied
bool Tied
Tied - Uses and defs must use the same register.
Definition: MachineInstrBundle.h:229
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::PhysRegInfo::FullyRead
bool FullyRead
Reg or a super-register is read. The full register is read.
Definition: MachineInstrBundle.h:262
llvm::VirtRegInfo::Reads
bool Reads
Reads - One of the operands read the virtual register.
Definition: MachineInstrBundle.h:221
llvm::finalizeBundles
bool finalizeBundles(MachineFunction &MF)
finalizeBundles - Finalize instruction bundles in the specified MachineFunction.
Definition: MachineInstrBundle.cpp:260
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::PhysRegInfo::DeadDef
bool DeadDef
Either:
Definition: MachineInstrBundle.h:268
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::UnpackMachineBundlesID
char & UnpackMachineBundlesID
UnpackMachineBundles - This pass unpack machine instruction bundles.
Definition: MachineInstrBundle.cpp:42
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::PhysRegInfo::FullyDefined
bool FullyDefined
Reg or a super-register is defined.
Definition: MachineInstrBundle.h:256
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:511
PassRegistry.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AnalyzePhysRegInBundle
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
Definition: MachineInstrBundle.cpp:313
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1535
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::PhysRegInfo::Killed
bool Killed
There is a use operand of reg or a super-register with kill flag set.
Definition: MachineInstrBundle.h:275
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:909
llvm::PhysRegInfo::Clobbered
bool Clobbered
There is a regmask operand indicating Reg is clobbered.
Definition: MachineInstrBundle.h:249
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::finalizeBundle
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Definition: MachineInstrBundle.cpp:124
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::initializeUnpackMachineBundlesPass
void initializeUnpackMachineBundlesPass(PassRegistry &)
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::PhysRegInfo::Read
bool Read
Reg or one of its aliases is read.
Definition: MachineInstrBundle.h:260
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::VirtRegInfo::Writes
bool Writes
Writes - One of the operands writes the virtual register.
Definition: MachineInstrBundle.h:224
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
MachineInstrBundle.h
llvm::MIBundleOperands
MIBundleOperands - Iterate over all operands in a bundle of machine instructions.
Definition: MachineInstrBundle.h:166
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
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bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:419
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
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Definition: MachineInstrBuilder.h:69
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VirtRegInfo AnalyzeVirtRegInBundle(MachineInstr &MI, Register Reg, SmallVectorImpl< std::pair< MachineInstr *, unsigned >> *Ops=nullptr)
AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses a virtual register.
Definition: MachineInstrBundle.cpp:283
llvm::FinalizeMachineBundlesID
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier,...
Definition: MachineInstrBundle.cpp:99
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compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
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constexpr double e
Definition: MathExtras.h:57
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bool isDead() const
Definition: MachineOperand.h:384
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1675
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Information about how a physical register Reg is used by a set of operands.
Definition: MachineInstrBundle.h:246
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const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
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isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:344
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Definition: MemDepPrinter.cpp:82
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const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:262
llvm::SmallSet::erase
bool erase(const T &V)
Definition: SmallSet.h:209
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:264
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Definition: MachineFunction.h:257
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:110
llvm::PhysRegInfo::Defined
bool Defined
Reg or one of its aliases is defined.
Definition: MachineInstrBundle.h:253
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Helper class for constructing bundles of MachineInstrs.
Definition: MachineInstrBuilder.h:544
TargetSubtargetInfo.h
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bool isDef() const
Definition: MachineOperand.h:374
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std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
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Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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Definition: AArch64SLSHardening.cpp:74
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Insert MI into MBB by prepending it to the instructions in the bundle.
Definition: MachineInstrBuilder.h:611
std
Definition: BitVector.h:851
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bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:574
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bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
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ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
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Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:237
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void clear()
Definition: SmallVector.h:591
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MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:597
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unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
SmallVector.h
MachineInstrBuilder.h
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MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
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bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
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bool isInternalRead() const
Definition: MachineOperand.h:430
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This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
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void initializeFinalizeMachineBundlesPass(PassRegistry &)
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FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
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A debug info location.
Definition: DebugLoc.h:33
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VirtRegInfo - Information about a virtual register used by a set of operands.
Definition: MachineInstrBundle.h:218
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:505
InitializePasses.h
TargetRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles", "Unpack machine instruction bundles", false, false) bool UnpackMachineBundles
Definition: MachineInstrBundle.cpp:43
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::PhysRegInfo::PartialDeadDef
bool PartialDeadDef
Reg is Defined and all defs of reg or an overlapping register are dead.
Definition: MachineInstrBundle.h:272