LLVM  14.0.0git
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
18 #include "llvm/CodeGen/Register.h"
20 #include "llvm/IR/DataLayout.h"
22 #include <algorithm>
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "dwarfdebug"
27 
29  if (Value < 32)
30  emitOp(dwarf::DW_OP_lit0 + Value);
32  // Only do this for 64-bit values as the DWARF expression stack uses
33  // target-address-size values.
34  emitOp(dwarf::DW_OP_lit0);
35  emitOp(dwarf::DW_OP_not);
36  } else {
37  emitOp(dwarf::DW_OP_constu);
39  }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
45  "location description already locked down");
47  if (DwarfReg < 32) {
48  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49  } else {
50  emitOp(dwarf::DW_OP_regx, Comment);
51  emitUnsigned(DwarfReg);
52  }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57  assert(!isRegisterLocation() && "location description already locked down");
58  if (DwarfReg < 32) {
59  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60  } else {
61  emitOp(dwarf::DW_OP_bregx);
62  emitUnsigned(DwarfReg);
63  }
65 }
66 
68  emitOp(dwarf::DW_OP_fbreg);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73  if (!SizeInBits)
74  return;
75 
76  const unsigned SizeOfByte = 8;
77  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78  emitOp(dwarf::DW_OP_bit_piece);
79  emitUnsigned(SizeInBits);
81  } else {
82  emitOp(dwarf::DW_OP_piece);
83  unsigned ByteSize = SizeInBits / SizeOfByte;
84  emitUnsigned(ByteSize);
85  }
86  this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90  emitConstu(ShiftBy);
91  emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
96  emitOp(dwarf::DW_OP_and);
97 }
98 
100  llvm::Register MachineReg,
101  unsigned MaxSize) {
102  if (!llvm::Register::isPhysicalRegister(MachineReg)) {
103  if (isFrameRegister(TRI, MachineReg)) {
104  DwarfRegs.push_back(Register::createRegister(-1, nullptr));
105  return true;
106  }
107  return false;
108  }
109 
110  int Reg = TRI.getDwarfRegNum(MachineReg, false);
111 
112  // If this is a valid register number, emit it.
113  if (Reg >= 0) {
114  DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
115  return true;
116  }
117 
118  // Walk up the super-register chain until we find a valid number.
119  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
120  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
121  Reg = TRI.getDwarfRegNum(*SR, false);
122  if (Reg >= 0) {
123  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
124  unsigned Size = TRI.getSubRegIdxSize(Idx);
125  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
126  DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
127  // Use a DW_OP_bit_piece to describe the sub-register.
128  setSubRegisterPiece(Size, RegOffset);
129  return true;
130  }
131  }
132 
133  // Otherwise, attempt to find a covering set of sub-register numbers.
134  // For example, Q0 on ARM is a composition of D0+D1.
135  unsigned CurPos = 0;
136  // The size of the register in bits.
137  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
138  unsigned RegSize = TRI.getRegSizeInBits(*RC);
139  // Keep track of the bits in the register we already emitted, so we
140  // can avoid emitting redundant aliasing subregs. Because this is
141  // just doing a greedy scan of all subregisters, it is possible that
142  // this doesn't find a combination of subregisters that fully cover
143  // the register (even though one may exist).
144  SmallBitVector Coverage(RegSize, false);
145  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
146  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
147  unsigned Size = TRI.getSubRegIdxSize(Idx);
148  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
149  Reg = TRI.getDwarfRegNum(*SR, false);
150  if (Reg < 0)
151  continue;
152 
153  // Used to build the intersection between the bits we already
154  // emitted and the bits covered by this subregister.
155  SmallBitVector CurSubReg(RegSize, false);
156  CurSubReg.set(Offset, Offset + Size);
157 
158  // If this sub-register has a DWARF number and we haven't covered
159  // its range, and its range covers the value, emit a DWARF piece for it.
160  if (Offset < MaxSize && CurSubReg.test(Coverage)) {
161  // Emit a piece for any gap in the coverage.
162  if (Offset > CurPos)
164  -1, Offset - CurPos, "no DWARF register encoding"));
165  if (Offset == 0 && Size >= MaxSize)
166  DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
167  else
169  Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
170  }
171  // Mark it as emitted.
172  Coverage.set(Offset, Offset + Size);
173  CurPos = Offset + Size;
174  }
175  // Failed to find any DWARF encoding.
176  if (CurPos == 0)
177  return false;
178  // Found a partial or complete DWARF encoding.
179  if (CurPos < RegSize)
181  -1, RegSize - CurPos, "no DWARF register encoding"));
182  return true;
183 }
184 
186  if (DwarfVersion >= 4)
187  emitOp(dwarf::DW_OP_stack_value);
188 }
189 
193  emitOp(dwarf::DW_OP_consts);
194  emitSigned(Value);
195 }
196 
200  emitConstu(Value);
201 }
202 
206 
207  unsigned Size = Value.getBitWidth();
208  const uint64_t *Data = Value.getRawData();
209 
210  // Chop it up into 64-bit pieces, because that's the maximum that
211  // addUnsignedConstant takes.
212  unsigned Offset = 0;
213  while (Offset < Size) {
215  if (Offset == 0 && Size <= 64)
216  break;
217  addStackValue();
219  Offset += 64;
220  }
221 }
222 
223 void DwarfExpression::addConstantFP(const APFloat &APF, const AsmPrinter &AP) {
225  APInt API = APF.bitcastToAPInt();
226  int NumBytes = API.getBitWidth() / 8;
227  if (NumBytes == 4 /*float*/ || NumBytes == 8 /*double*/) {
228  // FIXME: Add support for `long double`.
229  emitOp(dwarf::DW_OP_implicit_value);
230  emitUnsigned(NumBytes /*Size of the block in bytes*/);
231 
232  // The loop below is emitting the value starting at least significant byte,
233  // so we need to perform a byte-swap to get the byte order correct in case
234  // of a big-endian target.
235  if (AP.getDataLayout().isBigEndian())
236  API = API.byteSwap();
237 
238  for (int i = 0; i < NumBytes; ++i) {
239  emitData1(API.getZExtValue() & 0xFF);
240  API = API.lshr(8);
241  }
242 
243  return;
244  }
245  LLVM_DEBUG(
246  dbgs() << "Skipped DW_OP_implicit_value creation for ConstantFP of size: "
247  << API.getBitWidth() << " bits\n");
248 }
249 
251  DIExpressionCursor &ExprCursor,
252  llvm::Register MachineReg,
253  unsigned FragmentOffsetInBits) {
254  auto Fragment = ExprCursor.getFragmentInfo();
255  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
257  return false;
258  }
259 
260  bool HasComplexExpression = false;
261  auto Op = ExprCursor.peek();
262  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
263  HasComplexExpression = true;
264 
265  // If the register can only be described by a complex expression (i.e.,
266  // multiple subregisters) it doesn't safely compose with another complex
267  // expression. For example, it is not possible to apply a DW_OP_deref
268  // operation to multiple DW_OP_pieces, since composite location descriptions
269  // do not push anything on the DWARF stack.
270  //
271  // DW_OP_entry_value operations can only hold a DWARF expression or a
272  // register location description, so we can't emit a single entry value
273  // covering a composite location description. In the future we may want to
274  // emit entry value operations for each register location in the composite
275  // location, but until that is supported do not emit anything.
276  if ((HasComplexExpression || IsEmittingEntryValue) && DwarfRegs.size() > 1) {
279  DwarfRegs.clear();
281  return false;
282  }
283 
284  // Handle simple register locations. If we are supposed to emit
285  // a call site parameter expression and if that expression is just a register
286  // location, emit it with addBReg and offset 0, because we should emit a DWARF
287  // expression representing a value, rather than a location.
288  if ((!isParameterValue() && !isMemoryLocation() && !HasComplexExpression) ||
289  isEntryValue()) {
290  for (auto &Reg : DwarfRegs) {
291  if (Reg.DwarfRegNo >= 0)
292  addReg(Reg.DwarfRegNo, Reg.Comment);
293  addOpPiece(Reg.SubRegSize);
294  }
295 
296  if (isEntryValue()) {
298 
299  if (!isIndirect() && !isParameterValue() && !HasComplexExpression &&
300  DwarfVersion >= 4)
301  emitOp(dwarf::DW_OP_stack_value);
302  }
303 
304  DwarfRegs.clear();
305  // If we need to mask out a subregister, do it now, unless the next
306  // operation would emit an OpPiece anyway.
307  auto NextOp = ExprCursor.peek();
308  if (SubRegisterSizeInBits && NextOp &&
309  (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment))
310  maskSubRegister();
311  return true;
312  }
313 
314  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
315  if (DwarfVersion < 4)
316  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
317  return Op.getOp() == dwarf::DW_OP_stack_value;
318  })) {
319  DwarfRegs.clear();
321  return false;
322  }
323 
324  assert(DwarfRegs.size() == 1);
325  auto Reg = DwarfRegs[0];
326  bool FBReg = isFrameRegister(TRI, MachineReg);
327  int SignedOffset = 0;
328  assert(!Reg.isSubRegister() && "full register expected");
329 
330  // Pattern-match combinations for which more efficient representations exist.
331  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
332  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
333  uint64_t Offset = Op->getArg(0);
334  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
335  if (Offset <= IntMax) {
336  SignedOffset = Offset;
337  ExprCursor.take();
338  }
339  }
340 
341  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
342  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
343  // If Reg is a subregister we need to mask it out before subtracting.
344  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
345  uint64_t Offset = Op->getArg(0);
346  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
347  auto N = ExprCursor.peekNext();
348  if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
349  SignedOffset = Offset;
350  ExprCursor.consume(2);
351  } else if (N && N->getOp() == dwarf::DW_OP_minus &&
352  !SubRegisterSizeInBits && Offset <= IntMax + 1) {
353  SignedOffset = -static_cast<int64_t>(Offset);
354  ExprCursor.consume(2);
355  }
356  }
357 
358  if (FBReg)
359  addFBReg(SignedOffset);
360  else
361  addBReg(Reg.DwarfRegNo, SignedOffset);
362  DwarfRegs.clear();
363 
364  // If we need to mask out a subregister, do it now, unless the next
365  // operation would emit an OpPiece anyway.
366  auto NextOp = ExprCursor.peek();
367  if (SubRegisterSizeInBits && NextOp &&
368  (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment))
369  maskSubRegister();
370 
371  return true;
372 }
373 
376  if (Loc.isIndirect())
378 }
379 
381  const DIExpression *DIExpr) {
382  if (Loc.isIndirect())
384 
385  if (DIExpr->isEntryValue())
386  setEntryValueFlags(Loc);
387 }
388 
390  DIExpressionCursor &ExprCursor) {
391  auto Op = ExprCursor.take();
392  (void)Op;
393  assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
394  assert(!IsEmittingEntryValue && "Already emitting entry value?");
395  assert(Op->getArg(0) == 1 &&
396  "Can currently only emit entry values covering a single operation");
397 
400  IsEmittingEntryValue = true;
402 }
403 
405  assert(IsEmittingEntryValue && "Entry value not open?");
407 
408  emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
409 
410  // Emit the entry value's size operand.
411  unsigned Size = getTemporaryBufferSize();
413 
414  // Emit the entry value's DWARF block operand.
416 
419  IsEmittingEntryValue = false;
420 }
421 
423  assert(IsEmittingEntryValue && "Entry value not open?");
425 
426  // The temporary buffer can't be emptied, so for now just assert that nothing
427  // has been emitted to it.
429  "Began emitting entry value block before cancelling entry value");
430 
432  IsEmittingEntryValue = false;
433 }
434 
435 unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
436  dwarf::TypeKind Encoding) {
437  // Reuse the base_type if we already have one in this CU otherwise we
438  // create a new one.
439  unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
440  for (; I != E; ++I)
441  if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
442  CU.ExprRefedBaseTypes[I].Encoding == Encoding)
443  break;
444 
445  if (I == E)
446  CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
447  return I;
448 }
449 
450 /// Assuming a well-formed expression, match "DW_OP_deref*
451 /// DW_OP_LLVM_fragment?".
452 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
453  while (ExprCursor) {
454  auto Op = ExprCursor.take();
455  switch (Op->getOp()) {
456  case dwarf::DW_OP_deref:
458  break;
459  default:
460  return false;
461  }
462  }
463  return true;
464 }
465 
467  unsigned FragmentOffsetInBits) {
468  addExpression(std::move(ExprCursor),
469  [](unsigned Idx, DIExpressionCursor &Cursor) -> bool {
470  llvm_unreachable("unhandled opcode found in expression");
471  });
472 }
473 
475  DIExpressionCursor &&ExprCursor,
476  llvm::function_ref<bool(unsigned, DIExpressionCursor &)> InsertArg) {
477  // Entry values can currently only cover the initial register location,
478  // and not any other parts of the following DWARF expression.
479  assert(!IsEmittingEntryValue && "Can't emit entry value around expression");
480 
482 
483  while (ExprCursor) {
484  auto Op = ExprCursor.take();
485  uint64_t OpNum = Op->getOp();
486 
487  if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
488  emitOp(OpNum);
489  continue;
490  } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
491  addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
492  continue;
493  }
494 
495  switch (OpNum) {
497  if (!InsertArg(Op->getArg(0), ExprCursor)) {
499  return;
500  }
501  break;
503  unsigned SizeInBits = Op->getArg(1);
504  unsigned FragmentOffset = Op->getArg(0);
505  // The fragment offset must have already been adjusted by emitting an
506  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
507  // location.
508  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
509  assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
510 
511  // If addMachineReg already emitted DW_OP_piece operations to represent
512  // a super-register by splicing together sub-registers, subtract the size
513  // of the pieces that was already emitted.
514  SizeInBits -= OffsetInBits - FragmentOffset;
515 
516  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
517  // sub-register that is smaller than the current fragment's size, use it.
519  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
520 
521  // Emit a DW_OP_stack_value for implicit location descriptions.
522  if (isImplicitLocation())
523  addStackValue();
524 
525  // Emit the DW_OP_piece.
526  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
527  setSubRegisterPiece(0, 0);
528  // Reset the location description kind.
530  return;
531  }
532  case dwarf::DW_OP_plus_uconst:
534  emitOp(dwarf::DW_OP_plus_uconst);
535  emitUnsigned(Op->getArg(0));
536  break;
537  case dwarf::DW_OP_plus:
538  case dwarf::DW_OP_minus:
539  case dwarf::DW_OP_mul:
540  case dwarf::DW_OP_div:
541  case dwarf::DW_OP_mod:
542  case dwarf::DW_OP_or:
543  case dwarf::DW_OP_and:
544  case dwarf::DW_OP_xor:
545  case dwarf::DW_OP_shl:
546  case dwarf::DW_OP_shr:
547  case dwarf::DW_OP_shra:
548  case dwarf::DW_OP_lit0:
549  case dwarf::DW_OP_not:
550  case dwarf::DW_OP_dup:
551  case dwarf::DW_OP_push_object_address:
552  case dwarf::DW_OP_over:
553  emitOp(OpNum);
554  break;
555  case dwarf::DW_OP_deref:
557  if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
558  // Turning this into a memory location description makes the deref
559  // implicit.
561  else
562  emitOp(dwarf::DW_OP_deref);
563  break;
564  case dwarf::DW_OP_constu:
566  emitConstu(Op->getArg(0));
567  break;
568  case dwarf::DW_OP_consts:
570  emitOp(dwarf::DW_OP_consts);
571  emitSigned(Op->getArg(0));
572  break;
574  unsigned BitSize = Op->getArg(0);
575  dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
576  if (DwarfVersion >= 5 && CU.getDwarfDebug().useOpConvert()) {
577  emitOp(dwarf::DW_OP_convert);
578  // If targeting a location-list; simply emit the index into the raw
579  // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
580  // fitted with means to extract it later.
581  // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
582  // (containing the index and a resolve mechanism during emit) into the
583  // DIE value list.
584  emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
585  } else {
586  if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
587  if (Encoding == dwarf::DW_ATE_signed)
588  emitLegacySExt(PrevConvertOp->getArg(0));
589  else if (Encoding == dwarf::DW_ATE_unsigned)
590  emitLegacyZExt(PrevConvertOp->getArg(0));
591  PrevConvertOp = None;
592  } else {
593  PrevConvertOp = Op;
594  }
595  }
596  break;
597  }
598  case dwarf::DW_OP_stack_value:
600  break;
601  case dwarf::DW_OP_swap:
603  emitOp(dwarf::DW_OP_swap);
604  break;
605  case dwarf::DW_OP_xderef:
607  emitOp(dwarf::DW_OP_xderef);
608  break;
609  case dwarf::DW_OP_deref_size:
610  emitOp(dwarf::DW_OP_deref_size);
611  emitData1(Op->getArg(0));
612  break;
614  TagOffset = Op->getArg(0);
615  break;
616  case dwarf::DW_OP_regx:
617  emitOp(dwarf::DW_OP_regx);
618  emitUnsigned(Op->getArg(0));
619  break;
620  case dwarf::DW_OP_bregx:
621  emitOp(dwarf::DW_OP_bregx);
622  emitUnsigned(Op->getArg(0));
623  emitSigned(Op->getArg(1));
624  break;
625  default:
626  llvm_unreachable("unhandled opcode found in expression");
627  }
628  }
629 
631  // Turn this into an implicit location description.
632  addStackValue();
633 }
634 
635 /// add masking operations to stencil out a subregister.
637  assert(SubRegisterSizeInBits && "no subregister was registered");
638  if (SubRegisterOffsetInBits > 0)
640  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
641  addAnd(Mask);
642 }
643 
645  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
646  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
647  if (SubRegisterSizeInBits == 0)
648  return;
649  // Don't emit a DW_OP_piece for a subregister at offset 0.
650  if (SubRegisterOffsetInBits == 0)
651  return;
653 }
654 
656  if (!Expr || !Expr->isFragment())
657  return;
658 
659  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
660  assert(FragmentOffset >= OffsetInBits &&
661  "overlapping or duplicate fragments");
662  if (FragmentOffset > OffsetInBits)
663  addOpPiece(FragmentOffset - OffsetInBits);
664  OffsetInBits = FragmentOffset;
665 }
666 
667 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
668  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
669  emitOp(dwarf::DW_OP_dup);
670  emitOp(dwarf::DW_OP_constu);
671  emitUnsigned(FromBits - 1);
672  emitOp(dwarf::DW_OP_shr);
673  emitOp(dwarf::DW_OP_lit0);
674  emitOp(dwarf::DW_OP_not);
675  emitOp(dwarf::DW_OP_mul);
676  emitOp(dwarf::DW_OP_constu);
677  emitUnsigned(FromBits);
678  emitOp(dwarf::DW_OP_shl);
679  emitOp(dwarf::DW_OP_or);
680 }
681 
682 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
683  // (X & (1 << FromBits - 1))
684  emitOp(dwarf::DW_OP_constu);
685  emitUnsigned((1ULL << FromBits) - 1);
686  emitOp(dwarf::DW_OP_and);
687 }
688 
690  emitOp(dwarf::DW_OP_WASM_location);
691  emitUnsigned(Index == 4/*TI_LOCAL_INDIRECT*/ ? 0/*TI_LOCAL*/ : Index);
693  if (Index == 4 /*TI_LOCAL_INDIRECT*/) {
696  } else {
699  }
700 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:365
llvm::DwarfExpression::SubRegisterSizeInBits
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
Definition: DwarfExpression.h:140
llvm::MachineLocation
Definition: MachineLocation.h:22
llvm::DwarfExpression::addFBReg
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
Definition: DwarfExpression.cpp:67
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::DwarfExpression::addUnsignedConstant
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
Definition: DwarfExpression.cpp:197
llvm::DwarfExpression::emitConstu
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
Definition: DwarfExpression.cpp:28
llvm::DwarfExpression::Memory
@ Memory
Definition: DwarfExpression.h:144
llvm::APInt::byteSwap
APInt byteSwap() const
Definition: APInt.cpp:690
llvm::DwarfExpression::addShr
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
Definition: DwarfExpression.cpp:89
llvm::DwarfExpression::enableTemporaryBuffer
virtual void enableTemporaryBuffer()=0
Start emitting data to the temporary buffer.
llvm::DwarfExpression::emitSigned
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
ErrorHandling.h
llvm::MCRegisterInfo::getDwarfRegNum
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Definition: MCRegisterInfo.cpp:68
llvm::dwarf::DW_OP_LLVM_tag_offset
@ DW_OP_LLVM_tag_offset
Only used in LLVM metadata.
Definition: Dwarf.h:144
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::DwarfExpression::TagOffset
Optional< uint8_t > TagOffset
Definition: DwarfExpression.h:173
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1403
llvm::DIExpression::ExprOperand
A lightweight wrapper around an expression operand.
Definition: DebugInfoMetadata.h:2643
llvm::DwarfExpression::DwarfRegs
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
Definition: DwarfExpression.h:134
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::DIExpressionCursor::getFragmentInfo
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
Definition: DwarfExpression.h:91
llvm::DwarfExpression::DwarfVersion
unsigned DwarfVersion
Definition: DwarfExpression.h:153
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2586
llvm::APInt::lshr
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:808
llvm::SmallBitVector::test
bool test(unsigned Idx) const
Definition: SmallBitVector.h:465
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::DwarfExpression::setLocation
void setLocation(const MachineLocation &Loc, const DIExpression *DIExpr)
Set the location (Loc) and DIExpression (DIExpr) to describe.
Definition: DwarfExpression.cpp:380
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::DwarfExpression::finalizeEntryValue
void finalizeEntryValue()
Finalize an entry value by emitting its size operand, and committing the DWARF block which has been e...
Definition: DwarfExpression.cpp:404
llvm::DwarfExpression::LocationKind
unsigned LocationKind
Definition: DwarfExpression.h:150
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::DwarfExpression::isMemoryLocation
bool isMemoryLocation() const
Definition: DwarfExpression.h:161
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::DwarfExpression::Implicit
@ Implicit
Definition: DwarfExpression.h:144
llvm::DwarfExpression::isImplicitLocation
bool isImplicitLocation() const
Definition: DwarfExpression.h:165
llvm::DwarfExpression::commitTemporaryBuffer
virtual void commitTemporaryBuffer()=0
Commit the data stored in the temporary buffer to the main output.
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
DwarfExpression.h
llvm::DwarfExpression::setSubRegisterPiece
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister.
Definition: DwarfExpression.h:178
llvm::DwarfExpression::isFrameRegister
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, llvm::Register MachineReg)=0
Return whether the given machine register is the frame register in the current function.
llvm::DwarfExpression::emitData1
virtual void emitData1(uint8_t Value)=0
llvm::DwarfExpression::setEntryValueFlags
void setEntryValueFlags(const MachineLocation &Loc)
Lock this down to become an entry value location.
Definition: DwarfExpression.cpp:374
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::DIExpression::ExprOperand::getArg
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Definition: DebugInfoMetadata.h:2658
llvm::DwarfExpression::getOrCreateBaseType
unsigned getOrCreateBaseType(unsigned BitSize, dwarf::TypeKind Encoding)
Return the index of a base type with the given properties and create one if necessary.
Definition: DwarfExpression.cpp:435
llvm::DwarfExpression::addConstantFP
void addConstantFP(const APFloat &Value, const AsmPrinter &AP)
Emit an floating point constant.
Definition: DwarfExpression.cpp:223
llvm::DwarfExpression::emitLegacySExt
void emitLegacySExt(unsigned FromBits)
Definition: DwarfExpression.cpp:667
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::DwarfExpression::finalize
void finalize()
This needs to be called last to commit any pending changes.
Definition: DwarfExpression.cpp:644
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::DwarfExpression::OffsetInBits
uint64_t OffsetInBits
Current Fragment Offset in Bits.
Definition: DwarfExpression.h:137
isMemoryLocation
static bool isMemoryLocation(DIExpressionCursor ExprCursor)
Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
Definition: DwarfExpression.cpp:452
llvm::DIExpressionCursor::consume
void consume(unsigned N)
Consume N operations.
Definition: DwarfExpression.h:63
llvm::MCRegisterInfo::getSubRegIndex
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
Definition: MCRegisterInfo.cpp:44
llvm::DwarfExpression::setMemoryLocationKind
void setMemoryLocationKind()
Lock this down to become a memory location description.
Definition: DwarfExpression.h:307
llvm::DwarfExpression::addMachineRegExpression
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, llvm::Register MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
Definition: DwarfExpression.cpp:250
llvm::DwarfExpression::addWasmLocation
void addWasmLocation(unsigned Index, uint64_t Offset)
Emit location information expressed via WebAssembly location + offset The Index is an identifier for ...
Definition: DwarfExpression.cpp:689
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1453
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::DwarfExpression::cancelEntryValue
void cancelEntryValue()
Cancel the emission of an entry value.
Definition: DwarfExpression.cpp:422
llvm::None
const NoneType None
Definition: None.h:23
llvm::DwarfExpression::SavedLocationKind
unsigned SavedLocationKind
Definition: DwarfExpression.h:151
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:168
llvm::DwarfExpression::Register
@ Register
Definition: DwarfExpression.h:144
llvm::DwarfExpression::LocationFlags
unsigned LocationFlags
Definition: DwarfExpression.h:152
llvm::DwarfExpression::emitBaseTypeRef
virtual void emitBaseTypeRef(uint64_t Idx)=0
llvm::DataLayout::isBigEndian
bool isBigEndian() const
Definition: DataLayout.h:243
llvm::APFloat
Definition: APFloat.h:701
llvm::dwarf::DW_OP_LLVM_entry_value
@ DW_OP_LLVM_entry_value
Only used in LLVM metadata.
Definition: Dwarf.h:145
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::DwarfExpression::emitUnsigned
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
uint64_t
llvm::DwarfExpression::maskSubRegister
void maskSubRegister()
Add masking operations to stencil out a subregister.
Definition: DwarfExpression.cpp:636
llvm::DwarfExpression::disableTemporaryBuffer
virtual void disableTemporaryBuffer()=0
Disable emission to the temporary buffer.
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::DwarfExpression::isIndirect
bool isIndirect() const
Definition: DwarfExpression.h:169
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::DwarfExpression::beginEntryValueExpression
void beginEntryValueExpression(DIExpressionCursor &ExprCursor)
Begin emission of an entry value dwarf operation.
Definition: DwarfExpression.cpp:389
llvm::DwarfExpression::EntryValue
@ EntryValue
Definition: DwarfExpression.h:148
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.h:2904
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::DwarfExpression::addBReg
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
Definition: DwarfExpression.cpp:55
llvm::DwarfExpression::addSignedConstant
void addSignedConstant(int64_t Value)
Emit a signed constant.
Definition: DwarfExpression.cpp:190
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::DwarfExpression::isUnknownLocation
bool isUnknownLocation() const
Definition: DwarfExpression.h:159
llvm::dwarf::DW_OP_LLVM_arg
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
Definition: Dwarf.h:147
llvm::dwarf::DW_OP_LLVM_fragment
@ DW_OP_LLVM_fragment
Only used in LLVM metadata.
Definition: Dwarf.h:142
llvm::DwarfExpression::isEntryValue
bool isEntryValue() const
Definition: DwarfExpression.h:167
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
DataLayout.h
Dwarf.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::DwarfExpression::addMachineReg
bool addMachineReg(const TargetRegisterInfo &TRI, llvm::Register MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
Definition: DwarfExpression.cpp:99
DwarfCompileUnit.h
llvm::MachineLocation::isIndirect
bool isIndirect() const
Definition: MachineLocation.h:45
llvm::DIExpressionCursor::peekNext
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
Definition: DwarfExpression.h:73
llvm::DwarfExpression::Register::createRegister
static Register createRegister(int RegNo, const char *Comment)
Create a full register, no extra DW_OP_piece operators necessary.
Definition: DwarfExpression.h:115
llvm::DIExpressionCursor::peek
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
Definition: DwarfExpression.h:66
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::DIExpression::getFragmentInfo
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
Definition: DebugInfoMetadata.cpp:1219
llvm::dwarf::TypeKind
TypeKind
Definition: Dwarf.h:150
llvm::DwarfExpression::IsEmittingEntryValue
bool IsEmittingEntryValue
Whether we are currently emitting an entry value operation.
Definition: DwarfExpression.h:129
llvm::DwarfExpression::isRegisterLocation
bool isRegisterLocation() const
Definition: DwarfExpression.h:163
llvm::DIExpression::isFragment
bool isFragment() const
Return whether this is a piece of an aggregate variable.
Definition: DebugInfoMetadata.h:2765
llvm::DwarfExpression::addFragmentOffset
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
Definition: DwarfExpression.cpp:655
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::DwarfExpression::emitOp
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::dwarf::DW_OP_LLVM_convert
@ DW_OP_LLVM_convert
Only used in LLVM metadata.
Definition: Dwarf.h:143
llvm::DwarfExpression::Register::createSubRegister
static Register createSubRegister(int RegNo, unsigned SizeInBits, const char *Comment)
Create a subregister that needs a DW_OP_piece operator with SizeInBits.
Definition: DwarfExpression.h:120
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::DwarfExpression::addAnd
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
Definition: DwarfExpression.cpp:94
llvm::DIExpressionCursor
Holds a DIExpression and keeps track of how many operands have been consumed so far.
Definition: DwarfExpression.h:37
llvm::DwarfExpression::addExpression
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
Definition: DwarfExpression.cpp:466
SmallBitVector.h
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::DwarfExpression::emitLegacyZExt
void emitLegacyZExt(unsigned FromBits)
Definition: DwarfExpression.cpp:682
llvm::DwarfExpression::Unknown
@ Unknown
Definition: DwarfExpression.h:144
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:228
llvm::MCRegisterInfo::getSubRegIdxOffset
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:62
Register.h
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
CU
Definition: AArch64AsmBackend.cpp:501
llvm::DwarfExpression::isParameterValue
bool isParameterValue()
Definition: DwarfExpression.h:171
llvm::DwarfExpression::Indirect
@ Indirect
Definition: DwarfExpression.h:148
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::DwarfExpression::addOpPiece
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
Definition: DwarfExpression.cpp:72
llvm::DwarfExpression::addStackValue
void addStackValue()
Emit a DW_OP_stack_value, if supported.
Definition: DwarfExpression.cpp:185
llvm::DwarfExpression::addReg
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
Definition: DwarfExpression.cpp:42
llvm::DwarfExpression::getTemporaryBufferSize
virtual unsigned getTemporaryBufferSize()=0
Return the emitted size, in number of bytes, for the data stored in the temporary buffer.
llvm::DIExpressionCursor::take
Optional< DIExpression::ExprOperand > take()
Consume one operation.
Definition: DwarfExpression.h:56
llvm::DwarfExpression::SubRegisterOffsetInBits
unsigned SubRegisterOffsetInBits
Definition: DwarfExpression.h:141
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56