LLVM 19.0.0git
MachineInstr.cpp
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1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
37#include "llvm/IR/Constants.h"
39#include "llvm/IR/DebugLoc.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/InlineAsm.h"
42#include "llvm/IR/LLVMContext.h"
43#include "llvm/IR/Metadata.h"
44#include "llvm/IR/Module.h"
46#include "llvm/IR/Operator.h"
47#include "llvm/MC/MCInstrDesc.h"
51#include "llvm/Support/Debug.h"
56#include <algorithm>
57#include <cassert>
58#include <cstdint>
59#include <cstring>
60#include <utility>
61
62using namespace llvm;
63
65 if (const MachineBasicBlock *MBB = MI.getParent())
66 if (const MachineFunction *MF = MBB->getParent())
67 return MF;
68 return nullptr;
69}
70
71// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
72// it.
74 const TargetRegisterInfo *&TRI,
76 const TargetIntrinsicInfo *&IntrinsicInfo,
77 const TargetInstrInfo *&TII) {
78
79 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
80 TRI = MF->getSubtarget().getRegisterInfo();
81 MRI = &MF->getRegInfo();
82 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83 TII = MF->getSubtarget().getInstrInfo();
84 }
85}
86
88 for (MCPhysReg ImpDef : MCID->implicit_defs())
89 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true));
90 for (MCPhysReg ImpUse : MCID->implicit_uses())
91 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true));
92}
93
94/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
95/// implicit operands. It reserves space for the number of operands specified by
96/// the MCInstrDesc.
97MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
98 DebugLoc DL, bool NoImp)
99 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
100 DbgLoc(std::move(DL)), DebugInstrNum(0) {
101 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
102
103 // Reserve space for the expected number of operands.
104 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
105 MCID->implicit_uses().size()) {
106 CapOperands = OperandCapacity::get(NumOps);
107 Operands = MF.allocateOperandArray(CapOperands);
108 }
109
110 if (!NoImp)
112}
113
114/// MachineInstr ctor - Copies MachineInstr arg exactly.
115/// Does not copy the number from debug instruction numbering, to preserve
116/// uniqueness.
117MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
118 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
119 Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0) {
120 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
121
122 CapOperands = OperandCapacity::get(MI.getNumOperands());
123 Operands = MF.allocateOperandArray(CapOperands);
124
125 // Copy operands.
126 for (const MachineOperand &MO : MI.operands())
127 addOperand(MF, MO);
128
129 // Replicate ties between the operands, which addOperand was not
130 // able to do reliably.
131 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
132 MachineOperand &NewMO = getOperand(i);
133 const MachineOperand &OrigMO = MI.getOperand(i);
134 NewMO.TiedTo = OrigMO.TiedTo;
135 }
136
137 // Copy all the sensible flags.
138 setFlags(MI.Flags);
139}
140
142 if (getParent())
143 getMF()->handleChangeDesc(*this, TID);
144 MCID = &TID;
145}
146
148 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
149}
150
151/// getRegInfo - If this instruction is embedded into a MachineFunction,
152/// return the MachineRegisterInfo object for the current function, otherwise
153/// return null.
154MachineRegisterInfo *MachineInstr::getRegInfo() {
156 return &MBB->getParent()->getRegInfo();
157 return nullptr;
158}
159
160const MachineRegisterInfo *MachineInstr::getRegInfo() const {
161 if (const MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164}
165
166void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
167 for (MachineOperand &MO : operands())
168 if (MO.isReg())
169 MRI.removeRegOperandFromUseList(&MO);
170}
171
172void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
173 for (MachineOperand &MO : operands())
174 if (MO.isReg())
175 MRI.addRegOperandToUseList(&MO);
176}
177
180 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
182 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
183 addOperand(*MF, Op);
184}
185
186/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
187/// ranges. If MRI is non-null also update use-def chains.
189 unsigned NumOps, MachineRegisterInfo *MRI) {
190 if (MRI)
191 return MRI->moveOperands(Dst, Src, NumOps);
192 // MachineOperand is a trivially copyable type so we can just use memmove.
193 assert(Dst && Src && "Unknown operands");
194 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
195}
196
197/// addOperand - Add the specified operand to the instruction. If it is an
198/// implicit operand, it is added to the end of the operand list. If it is
199/// an explicit operand it is added at the end of the explicit operand list
200/// (before the first implicit operand).
202 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
203 "Cannot add more operands.");
204 assert(MCID && "Cannot add operands before providing an instr descriptor");
205
206 // Check if we're adding one of our existing operands.
207 if (&Op >= Operands && &Op < Operands + NumOperands) {
208 // This is unusual: MI->addOperand(MI->getOperand(i)).
209 // If adding Op requires reallocating or moving existing operands around,
210 // the Op reference could go stale. Support it by copying Op.
211 MachineOperand CopyOp(Op);
212 return addOperand(MF, CopyOp);
213 }
214
215 // Find the insert location for the new operand. Implicit registers go at
216 // the end, everything else goes before the implicit regs.
217 //
218 // FIXME: Allow mixed explicit and implicit operands on inline asm.
219 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
220 // implicit-defs, but they must not be moved around. See the FIXME in
221 // InstrEmitter.cpp.
222 unsigned OpNo = getNumOperands();
223 bool isImpReg = Op.isReg() && Op.isImplicit();
224 if (!isImpReg && !isInlineAsm()) {
225 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
226 --OpNo;
227 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
228 }
229 }
230
231 // OpNo now points as the desired insertion point. Unless this is a variadic
232 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
233 // RegMask operands go between the explicit and implicit operands.
234 MachineRegisterInfo *MRI = getRegInfo();
235
236 // Determine if the Operands array needs to be reallocated.
237 // Save the old capacity and operand array.
238 OperandCapacity OldCap = CapOperands;
239 MachineOperand *OldOperands = Operands;
240 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
241 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
242 Operands = MF.allocateOperandArray(CapOperands);
243 // Move the operands before the insertion point.
244 if (OpNo)
245 moveOperands(Operands, OldOperands, OpNo, MRI);
246 }
247
248 // Move the operands following the insertion point.
249 if (OpNo != NumOperands)
250 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
251 MRI);
252 ++NumOperands;
253
254 // Deallocate the old operand array.
255 if (OldOperands != Operands && OldOperands)
256 MF.deallocateOperandArray(OldCap, OldOperands);
257
258 // Copy Op into place. It still needs to be inserted into the MRI use lists.
259 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
260 NewMO->ParentMI = this;
261
262 // When adding a register operand, tell MRI about it.
263 if (NewMO->isReg()) {
264 // Ensure isOnRegUseList() returns false, regardless of Op's status.
265 NewMO->Contents.Reg.Prev = nullptr;
266 // Ignore existing ties. This is not a property that can be copied.
267 NewMO->TiedTo = 0;
268 // Add the new operand to MRI, but only for instructions in an MBB.
269 if (MRI)
270 MRI->addRegOperandToUseList(NewMO);
271 // The MCID operand information isn't accurate until we start adding
272 // explicit operands. The implicit operands are added first, then the
273 // explicits are inserted before them.
274 if (!isImpReg) {
275 // Tie uses to defs as indicated in MCInstrDesc.
276 if (NewMO->isUse()) {
277 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
278 if (DefIdx != -1)
279 tieOperands(DefIdx, OpNo);
280 }
281 // If the register operand is flagged as early, mark the operand as such.
282 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
283 NewMO->setIsEarlyClobber(true);
284 }
285 // Ensure debug instructions set debug flag on register uses.
286 if (NewMO->isUse() && isDebugInstr())
287 NewMO->setIsDebug();
288 }
289}
290
291void MachineInstr::removeOperand(unsigned OpNo) {
292 assert(OpNo < getNumOperands() && "Invalid operand number");
293 untieRegOperand(OpNo);
294
295#ifndef NDEBUG
296 // Moving tied operands would break the ties.
297 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
298 if (Operands[i].isReg())
299 assert(!Operands[i].isTied() && "Cannot move tied operands");
300#endif
301
302 MachineRegisterInfo *MRI = getRegInfo();
303 if (MRI && Operands[OpNo].isReg())
304 MRI->removeRegOperandFromUseList(Operands + OpNo);
305
306 // Don't call the MachineOperand destructor. A lot of this code depends on
307 // MachineOperand having a trivial destructor anyway, and adding a call here
308 // wouldn't make it 'destructor-correct'.
309
310 if (unsigned N = NumOperands - 1 - OpNo)
311 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
312 --NumOperands;
313}
314
315void MachineInstr::setExtraInfo(MachineFunction &MF,
317 MCSymbol *PreInstrSymbol,
318 MCSymbol *PostInstrSymbol,
319 MDNode *HeapAllocMarker, MDNode *PCSections,
320 uint32_t CFIType) {
321 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
322 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
323 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
324 bool HasPCSections = PCSections != nullptr;
325 bool HasCFIType = CFIType != 0;
326 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
327 HasHeapAllocMarker + HasPCSections + HasCFIType;
328
329 // Drop all extra info if there is none.
330 if (NumPointers <= 0) {
331 Info.clear();
332 return;
333 }
334
335 // If more than one pointer, then store out of line. Store heap alloc markers
336 // out of line because PointerSumType cannot hold more than 4 tag types with
337 // 32-bit pointers.
338 // FIXME: Maybe we should make the symbols in the extra info mutable?
339 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
340 HasCFIType) {
341 Info.set<EIIK_OutOfLine>(
342 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
343 HeapAllocMarker, PCSections, CFIType));
344 return;
345 }
346
347 // Otherwise store the single pointer inline.
348 if (HasPreInstrSymbol)
349 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
350 else if (HasPostInstrSymbol)
351 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
352 else
353 Info.set<EIIK_MMO>(MMOs[0]);
354}
355
357 if (memoperands_empty())
358 return;
359
360 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
362}
363
366 if (MMOs.empty()) {
367 dropMemRefs(MF);
368 return;
369 }
370
371 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
373}
374
376 MachineMemOperand *MO) {
379 MMOs.push_back(MO);
380 setMemRefs(MF, MMOs);
381}
382
384 if (this == &MI)
385 // Nothing to do for a self-clone!
386 return;
387
388 assert(&MF == MI.getMF() &&
389 "Invalid machine functions when cloning memory refrences!");
390 // See if we can just steal the extra info already allocated for the
391 // instruction. We can do this whenever the pre- and post-instruction symbols
392 // are the same (including null).
393 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
394 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
395 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
396 getPCSections() == MI.getPCSections()) {
397 Info = MI.Info;
398 return;
399 }
400
401 // Otherwise, fall back on a copy-based clone.
402 setMemRefs(MF, MI.memoperands());
403}
404
405/// Check to see if the MMOs pointed to by the two MemRefs arrays are
406/// identical.
409 if (LHS.size() != RHS.size())
410 return false;
411
412 auto LHSPointees = make_pointee_range(LHS);
413 auto RHSPointees = make_pointee_range(RHS);
414 return std::equal(LHSPointees.begin(), LHSPointees.end(),
415 RHSPointees.begin());
416}
417
420 // Try handling easy numbers of MIs with simpler mechanisms.
421 if (MIs.empty()) {
422 dropMemRefs(MF);
423 return;
424 }
425 if (MIs.size() == 1) {
426 cloneMemRefs(MF, *MIs[0]);
427 return;
428 }
429 // Because an empty memoperands list provides *no* information and must be
430 // handled conservatively (assuming the instruction can do anything), the only
431 // way to merge with it is to drop all other memoperands.
432 if (MIs[0]->memoperands_empty()) {
433 dropMemRefs(MF);
434 return;
435 }
436
437 // Handle the general case.
439 // Start with the first instruction.
440 assert(&MF == MIs[0]->getMF() &&
441 "Invalid machine functions when cloning memory references!");
442 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
443 // Now walk all the other instructions and accumulate any different MMOs.
444 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
445 assert(&MF == MI.getMF() &&
446 "Invalid machine functions when cloning memory references!");
447
448 // Skip MIs with identical operands to the first. This is a somewhat
449 // arbitrary hack but will catch common cases without being quadratic.
450 // TODO: We could fully implement merge semantics here if needed.
451 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
452 continue;
453
454 // Because an empty memoperands list provides *no* information and must be
455 // handled conservatively (assuming the instruction can do anything), the
456 // only way to merge with it is to drop all other memoperands.
457 if (MI.memoperands_empty()) {
458 dropMemRefs(MF);
459 return;
460 }
461
462 // Otherwise accumulate these into our temporary buffer of the merged state.
463 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
464 }
465
466 setMemRefs(MF, MergedMMOs);
467}
468
470 // Do nothing if old and new symbols are the same.
471 if (Symbol == getPreInstrSymbol())
472 return;
473
474 // If there was only one symbol and we're removing it, just clear info.
475 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
476 Info.clear();
477 return;
478 }
479
480 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
482}
483
485 // Do nothing if old and new symbols are the same.
486 if (Symbol == getPostInstrSymbol())
487 return;
488
489 // If there was only one symbol and we're removing it, just clear info.
490 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
491 Info.clear();
492 return;
493 }
494
495 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
497}
498
500 // Do nothing if old and new symbols are the same.
501 if (Marker == getHeapAllocMarker())
502 return;
503
504 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
505 Marker, getPCSections(), getCFIType());
506}
507
509 // Do nothing if old and new symbols are the same.
510 if (PCSections == getPCSections())
511 return;
512
513 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
514 getHeapAllocMarker(), PCSections, getCFIType());
515}
516
518 // Do nothing if old and new types are the same.
519 if (Type == getCFIType())
520 return;
521
522 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
524}
525
527 const MachineInstr &MI) {
528 if (this == &MI)
529 // Nothing to do for a self-clone!
530 return;
531
532 assert(&MF == MI.getMF() &&
533 "Invalid machine functions when cloning instruction symbols!");
534
535 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
536 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
537 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
538 setPCSections(MF, MI.getPCSections());
539}
540
542 // For now, the just return the union of the flags. If the flags get more
543 // complicated over time, we might need more logic here.
544 return getFlags() | Other.getFlags();
545}
546
548 uint32_t MIFlags = 0;
549 // Copy the wrapping flags.
550 if (const OverflowingBinaryOperator *OB =
551 dyn_cast<OverflowingBinaryOperator>(&I)) {
552 if (OB->hasNoSignedWrap())
554 if (OB->hasNoUnsignedWrap())
556 }
557
558 // Copy the nonneg flag.
559 if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(&I)) {
560 if (PNI->hasNonNeg())
562 // Copy the disjoint flag.
563 } else if (const PossiblyDisjointInst *PD =
564 dyn_cast<PossiblyDisjointInst>(&I)) {
565 if (PD->isDisjoint())
567 }
568
569 // Copy the exact flag.
570 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
571 if (PE->isExact())
573
574 // Copy the fast-math flags.
575 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
576 const FastMathFlags Flags = FP->getFastMathFlags();
577 if (Flags.noNaNs())
579 if (Flags.noInfs())
581 if (Flags.noSignedZeros())
583 if (Flags.allowReciprocal())
585 if (Flags.allowContract())
587 if (Flags.approxFunc())
589 if (Flags.allowReassoc())
591 }
592
593 if (I.getMetadata(LLVMContext::MD_unpredictable))
595
596 return MIFlags;
597}
598
601}
602
603bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
604 assert(!isBundledWithPred() && "Must be called on bundle header");
606 if (MII->getDesc().getFlags() & Mask) {
607 if (Type == AnyInBundle)
608 return true;
609 } else {
610 if (Type == AllInBundle && !MII->isBundle())
611 return false;
612 }
613 // This was the last instruction in the bundle.
614 if (!MII->isBundledWithSucc())
615 return Type == AllInBundle;
616 }
617}
618
620 MICheckType Check) const {
621 // If opcodes or number of operands are not the same then the two
622 // instructions are obviously not identical.
623 if (Other.getOpcode() != getOpcode() ||
624 Other.getNumOperands() != getNumOperands())
625 return false;
626
627 if (isBundle()) {
628 // We have passed the test above that both instructions have the same
629 // opcode, so we know that both instructions are bundles here. Let's compare
630 // MIs inside the bundle.
631 assert(Other.isBundle() && "Expected that both instructions are bundles.");
634 // Loop until we analysed the last intruction inside at least one of the
635 // bundles.
636 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
637 ++I1;
638 ++I2;
639 if (!I1->isIdenticalTo(*I2, Check))
640 return false;
641 }
642 // If we've reached the end of just one of the two bundles, but not both,
643 // the instructions are not identical.
644 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
645 return false;
646 }
647
648 // Check operands to make sure they match.
649 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
650 const MachineOperand &MO = getOperand(i);
651 const MachineOperand &OMO = Other.getOperand(i);
652 if (!MO.isReg()) {
653 if (!MO.isIdenticalTo(OMO))
654 return false;
655 continue;
656 }
657
658 // Clients may or may not want to ignore defs when testing for equality.
659 // For example, machine CSE pass only cares about finding common
660 // subexpressions, so it's safe to ignore virtual register defs.
661 if (MO.isDef()) {
662 if (Check == IgnoreDefs)
663 continue;
664 else if (Check == IgnoreVRegDefs) {
665 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
666 if (!MO.isIdenticalTo(OMO))
667 return false;
668 } else {
669 if (!MO.isIdenticalTo(OMO))
670 return false;
671 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
672 return false;
673 }
674 } else {
675 if (!MO.isIdenticalTo(OMO))
676 return false;
677 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
678 return false;
679 }
680 }
681 // If DebugLoc does not match then two debug instructions are not identical.
682 if (isDebugInstr())
683 if (getDebugLoc() && Other.getDebugLoc() &&
684 getDebugLoc() != Other.getDebugLoc())
685 return false;
686 // If pre- or post-instruction symbols do not match then the two instructions
687 // are not identical.
688 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
689 getPostInstrSymbol() != Other.getPostInstrSymbol())
690 return false;
691 // Call instructions with different CFI types are not identical.
692 if (isCall() && getCFIType() != Other.getCFIType())
693 return false;
694
695 return true;
696}
697
699 if (!isDebugValueLike() || !Other.isDebugValueLike())
700 return false;
701 if (getDebugLoc() != Other.getDebugLoc())
702 return false;
703 if (getDebugVariable() != Other.getDebugVariable())
704 return false;
705 if (getNumDebugOperands() != Other.getNumDebugOperands())
706 return false;
707 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
708 if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx)))
709 return false;
712 Other.getDebugExpression(), Other.isIndirectDebugValue()))
713 return false;
714 return true;
715}
716
718 return getParent()->getParent();
719}
720
722 assert(getParent() && "Not embedded in a basic block!");
723 return getParent()->remove(this);
724}
725
727 assert(getParent() && "Not embedded in a basic block!");
728 return getParent()->remove_instr(this);
729}
730
732 assert(getParent() && "Not embedded in a basic block!");
733 getParent()->erase(this);
734}
735
737 assert(getParent() && "Not embedded in a basic block!");
738 getParent()->erase_instr(this);
739}
740
742 if (!isCall(Type))
743 return false;
744 switch (getOpcode()) {
745 case TargetOpcode::PATCHPOINT:
746 case TargetOpcode::STACKMAP:
747 case TargetOpcode::STATEPOINT:
748 case TargetOpcode::FENTRY_CALL:
749 return false;
750 }
751 return true;
752}
753
755 if (isBundle())
758}
759
761 unsigned NumOperands = MCID->getNumOperands();
762 if (!MCID->isVariadic())
763 return NumOperands;
764
765 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
766 const MachineOperand &MO = getOperand(I);
767 // The operands must always be in the following order:
768 // - explicit reg defs,
769 // - other explicit operands (reg uses, immediates, etc.),
770 // - implicit reg defs
771 // - implicit reg uses
772 if (MO.isReg() && MO.isImplicit())
773 break;
774 ++NumOperands;
775 }
776 return NumOperands;
777}
778
780 unsigned NumDefs = MCID->getNumDefs();
781 if (!MCID->isVariadic())
782 return NumDefs;
783
784 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
785 const MachineOperand &MO = getOperand(I);
786 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
787 break;
788 ++NumDefs;
789 }
790 return NumDefs;
791}
792
794 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
797 --Pred;
798 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
799 Pred->setFlag(BundledSucc);
800}
801
803 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
806 ++Succ;
807 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
808 Succ->setFlag(BundledPred);
809}
810
812 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
815 --Pred;
816 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
817 Pred->clearFlag(BundledSucc);
818}
819
821 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
824 ++Succ;
825 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
826 Succ->clearFlag(BundledPred);
827}
828
830 if (isInlineAsm()) {
831 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
832 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
833 return true;
834 }
835 return false;
836}
837
839 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
840 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
841 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
842}
843
845 unsigned *GroupNo) const {
846 assert(isInlineAsm() && "Expected an inline asm instruction");
847 assert(OpIdx < getNumOperands() && "OpIdx out of range");
848
849 // Ignore queries about the initial operands.
851 return -1;
852
853 unsigned Group = 0;
854 unsigned NumOps;
855 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
856 i += NumOps) {
857 const MachineOperand &FlagMO = getOperand(i);
858 // If we reach the implicit register operands, stop looking.
859 if (!FlagMO.isImm())
860 return -1;
861 const InlineAsm::Flag F(FlagMO.getImm());
862 NumOps = 1 + F.getNumOperandRegisters();
863 if (i + NumOps > OpIdx) {
864 if (GroupNo)
865 *GroupNo = Group;
866 return i;
867 }
868 ++Group;
869 }
870 return -1;
871}
872
874 assert(isDebugLabel() && "not a DBG_LABEL");
875 return cast<DILabel>(getOperand(0).getMetadata());
876}
877
879 assert((isDebugValueLike()) && "not a DBG_VALUE*");
880 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
881 return getOperand(VariableOp);
882}
883
885 assert((isDebugValueLike()) && "not a DBG_VALUE*");
886 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
887 return getOperand(VariableOp);
888}
889
891 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
892}
893
895 assert((isDebugValueLike()) && "not a DBG_VALUE*");
896 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
897 return getOperand(ExpressionOp);
898}
899
901 assert((isDebugValueLike()) && "not a DBG_VALUE*");
902 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
903 return getOperand(ExpressionOp);
904}
905
907 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
908}
909
912}
913
916 const TargetInstrInfo *TII,
917 const TargetRegisterInfo *TRI) const {
918 assert(getParent() && "Can't have an MBB reference here!");
919 assert(getMF() && "Can't have an MF reference here!");
920 const MachineFunction &MF = *getMF();
921
922 // Most opcodes have fixed constraints in their MCInstrDesc.
923 if (!isInlineAsm())
924 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
925
926 if (!getOperand(OpIdx).isReg())
927 return nullptr;
928
929 // For tied uses on inline asm, get the constraint from the def.
930 unsigned DefIdx;
931 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
932 OpIdx = DefIdx;
933
934 // Inline asm stores register class constraints in the flag word.
935 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
936 if (FlagIdx < 0)
937 return nullptr;
938
939 const InlineAsm::Flag F(getOperand(FlagIdx).getImm());
940 unsigned RCID;
941 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
942 F.hasRegClassConstraint(RCID))
943 return TRI->getRegClass(RCID);
944
945 // Assume that all registers in a memory operand are pointers.
946 if (F.isMemKind())
947 return TRI->getPointerRegClass(MF);
948
949 return nullptr;
950}
951
953 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
954 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
955 // Check every operands inside the bundle if we have
956 // been asked to.
957 if (ExploreBundle)
958 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
959 ++OpndIt)
960 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
961 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
962 else
963 // Otherwise, just check the current operands.
964 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
965 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
966 return CurRC;
967}
968
969const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
970 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
971 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
972 assert(CurRC && "Invalid initial register class");
973 // Check if Reg is constrained by some of its use/def from MI.
974 const MachineOperand &MO = getOperand(OpIdx);
975 if (!MO.isReg() || MO.getReg() != Reg)
976 return CurRC;
977 // If yes, accumulate the constraints through the operand.
978 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
979}
980
982 unsigned OpIdx, const TargetRegisterClass *CurRC,
983 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
984 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
985 const MachineOperand &MO = getOperand(OpIdx);
986 assert(MO.isReg() &&
987 "Cannot get register constraints for non-register operand");
988 assert(CurRC && "Invalid initial register class");
989 if (unsigned SubIdx = MO.getSubReg()) {
990 if (OpRC)
991 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
992 else
993 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
994 } else if (OpRC)
995 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
996 return CurRC;
997}
998
999/// Return the number of instructions inside the MI bundle, not counting the
1000/// header instruction.
1003 unsigned Size = 0;
1004 while (I->isBundledWithSucc()) {
1005 ++Size;
1006 ++I;
1007 }
1008 return Size;
1009}
1010
1011/// Returns true if the MachineInstr has an implicit-use operand of exactly
1012/// the given register (not considering sub/super-registers).
1014 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1015 const MachineOperand &MO = getOperand(i);
1016 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1017 return true;
1018 }
1019 return false;
1020}
1021
1022/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1023/// the specific register or -1 if it is not found. It further tightens
1024/// the search criteria to a use that kills the register if isKill is true.
1026 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1027 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1028 const MachineOperand &MO = getOperand(i);
1029 if (!MO.isReg() || !MO.isUse())
1030 continue;
1031 Register MOReg = MO.getReg();
1032 if (!MOReg)
1033 continue;
1034 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1035 if (!isKill || MO.isKill())
1036 return i;
1037 }
1038 return -1;
1039}
1040
1041/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1042/// indicating if this instruction reads or writes Reg. This also considers
1043/// partial defines.
1044std::pair<bool,bool>
1046 SmallVectorImpl<unsigned> *Ops) const {
1047 bool PartDef = false; // Partial redefine.
1048 bool FullDef = false; // Full define.
1049 bool Use = false;
1050
1051 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1052 const MachineOperand &MO = getOperand(i);
1053 if (!MO.isReg() || MO.getReg() != Reg)
1054 continue;
1055 if (Ops)
1056 Ops->push_back(i);
1057 if (MO.isUse())
1058 Use |= !MO.isUndef();
1059 else if (MO.getSubReg() && !MO.isUndef())
1060 // A partial def undef doesn't count as reading the register.
1061 PartDef = true;
1062 else
1063 FullDef = true;
1064 }
1065 // A partial redefine uses Reg unless there is also a full define.
1066 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1067}
1068
1069/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1070/// the specified register or -1 if it is not found. If isDead is true, defs
1071/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1072/// also checks if there is a def of a super-register.
1073int
1075 const TargetRegisterInfo *TRI) const {
1076 bool isPhys = Reg.isPhysical();
1077 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1078 const MachineOperand &MO = getOperand(i);
1079 // Accept regmask operands when Overlap is set.
1080 // Ignore them when looking for a specific def operand (Overlap == false).
1081 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1082 return i;
1083 if (!MO.isReg() || !MO.isDef())
1084 continue;
1085 Register MOReg = MO.getReg();
1086 bool Found = (MOReg == Reg);
1087 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1088 if (Overlap)
1089 Found = TRI->regsOverlap(MOReg, Reg);
1090 else
1091 Found = TRI->isSubRegister(MOReg, Reg);
1092 }
1093 if (Found && (!isDead || MO.isDead()))
1094 return i;
1095 }
1096 return -1;
1097}
1098
1099/// findFirstPredOperandIdx() - Find the index of the first operand in the
1100/// operand list that is used to represent the predicate. It returns -1 if
1101/// none is found.
1103 // Don't call MCID.findFirstPredOperandIdx() because this variant
1104 // is sometimes called on an instruction that's not yet complete, and
1105 // so the number of operands is less than the MCID indicates. In
1106 // particular, the PTX target does this.
1107 const MCInstrDesc &MCID = getDesc();
1108 if (MCID.isPredicable()) {
1109 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1110 if (MCID.operands()[i].isPredicate())
1111 return i;
1112 }
1113
1114 return -1;
1115}
1116
1117// MachineOperand::TiedTo is 4 bits wide.
1118const unsigned TiedMax = 15;
1119
1120/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1121///
1122/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1123/// field. TiedTo can have these values:
1124///
1125/// 0: Operand is not tied to anything.
1126/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1127/// TiedMax: Tied to an operand >= TiedMax-1.
1128///
1129/// The tied def must be one of the first TiedMax operands on a normal
1130/// instruction. INLINEASM instructions allow more tied defs.
1131///
1132void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1133 MachineOperand &DefMO = getOperand(DefIdx);
1134 MachineOperand &UseMO = getOperand(UseIdx);
1135 assert(DefMO.isDef() && "DefIdx must be a def operand");
1136 assert(UseMO.isUse() && "UseIdx must be a use operand");
1137 assert(!DefMO.isTied() && "Def is already tied to another use");
1138 assert(!UseMO.isTied() && "Use is already tied to another def");
1139
1140 if (DefIdx < TiedMax)
1141 UseMO.TiedTo = DefIdx + 1;
1142 else {
1143 // Inline asm can use the group descriptors to find tied operands,
1144 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1145 // but on normal instruction, the tied def must be within the first TiedMax
1146 // operands.
1147 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1148 "DefIdx out of range");
1149 UseMO.TiedTo = TiedMax;
1150 }
1151
1152 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1153 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1154}
1155
1156/// Given the index of a tied register operand, find the operand it is tied to.
1157/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1158/// which must exist.
1159unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1160 const MachineOperand &MO = getOperand(OpIdx);
1161 assert(MO.isTied() && "Operand isn't tied");
1162
1163 // Normally TiedTo is in range.
1164 if (MO.TiedTo < TiedMax)
1165 return MO.TiedTo - 1;
1166
1167 // Uses on normal instructions can be out of range.
1168 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1169 // Normal tied defs must be in the 0..TiedMax-1 range.
1170 if (MO.isUse())
1171 return TiedMax - 1;
1172 // MO is a def. Search for the tied use.
1173 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1174 const MachineOperand &UseMO = getOperand(i);
1175 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1176 return i;
1177 }
1178 llvm_unreachable("Can't find tied use");
1179 }
1180
1181 if (getOpcode() == TargetOpcode::STATEPOINT) {
1182 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1183 // on registers.
1184 StatepointOpers SO(this);
1185 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1186 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1187 unsigned NumDefs = getNumDefs();
1188 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1189 while (!getOperand(CurUseIdx).isReg())
1190 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1191 if (OpIdx == CurDefIdx)
1192 return CurUseIdx;
1193 if (OpIdx == CurUseIdx)
1194 return CurDefIdx;
1195 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1196 }
1197 llvm_unreachable("Can't find tied use");
1198 }
1199
1200 // Now deal with inline asm by parsing the operand group descriptor flags.
1201 // Find the beginning of each operand group.
1202 SmallVector<unsigned, 8> GroupIdx;
1203 unsigned OpIdxGroup = ~0u;
1204 unsigned NumOps;
1205 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1206 i += NumOps) {
1207 const MachineOperand &FlagMO = getOperand(i);
1208 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1209 unsigned CurGroup = GroupIdx.size();
1210 GroupIdx.push_back(i);
1211 const InlineAsm::Flag F(FlagMO.getImm());
1212 NumOps = 1 + F.getNumOperandRegisters();
1213 // OpIdx belongs to this operand group.
1214 if (OpIdx > i && OpIdx < i + NumOps)
1215 OpIdxGroup = CurGroup;
1216 unsigned TiedGroup;
1217 if (!F.isUseOperandTiedToDef(TiedGroup))
1218 continue;
1219 // Operands in this group are tied to operands in TiedGroup which must be
1220 // earlier. Find the number of operands between the two groups.
1221 unsigned Delta = i - GroupIdx[TiedGroup];
1222
1223 // OpIdx is a use tied to TiedGroup.
1224 if (OpIdxGroup == CurGroup)
1225 return OpIdx - Delta;
1226
1227 // OpIdx is a def tied to this use group.
1228 if (OpIdxGroup == TiedGroup)
1229 return OpIdx + Delta;
1230 }
1231 llvm_unreachable("Invalid tied operand on inline asm");
1232}
1233
1234/// clearKillInfo - Clears kill flags on all operands.
1235///
1237 for (MachineOperand &MO : operands()) {
1238 if (MO.isReg() && MO.isUse())
1239 MO.setIsKill(false);
1240 }
1241}
1242
1244 unsigned SubIdx,
1245 const TargetRegisterInfo &RegInfo) {
1246 if (ToReg.isPhysical()) {
1247 if (SubIdx)
1248 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1249 for (MachineOperand &MO : operands()) {
1250 if (!MO.isReg() || MO.getReg() != FromReg)
1251 continue;
1252 MO.substPhysReg(ToReg, RegInfo);
1253 }
1254 } else {
1255 for (MachineOperand &MO : operands()) {
1256 if (!MO.isReg() || MO.getReg() != FromReg)
1257 continue;
1258 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1259 }
1260 }
1261}
1262
1263/// isSafeToMove - Return true if it is safe to move this instruction. If
1264/// SawStore is set to true, it means that there is a store (or call) between
1265/// the instruction's location and its intended destination.
1266bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1267 // Ignore stuff that we obviously can't move.
1268 //
1269 // Treat volatile loads as stores. This is not strictly necessary for
1270 // volatiles, but it is required for atomic loads. It is not allowed to move
1271 // a load across an atomic load with Ordering > Monotonic.
1272 if (mayStore() || isCall() || isPHI() ||
1273 (mayLoad() && hasOrderedMemoryRef())) {
1274 SawStore = true;
1275 return false;
1276 }
1277
1278 if (isPosition() || isDebugInstr() || isTerminator() ||
1281 return false;
1282
1283 // See if this instruction does a load. If so, we have to guarantee that the
1284 // loaded value doesn't change between the load and the its intended
1285 // destination. The check for isInvariantLoad gives the target the chance to
1286 // classify the load as always returning a constant, e.g. a constant pool
1287 // load.
1289 // Otherwise, this is a real load. If there is a store between the load and
1290 // end of block, we can't move it.
1291 return !SawStore;
1292
1293 return true;
1294}
1295
1297 bool UseTBAA, const MachineMemOperand *MMOa,
1298 const MachineMemOperand *MMOb) {
1299 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1300 // operates with MachineMemOperand offset with some important assumptions:
1301 // - LLVM fundamentally assumes flat address spaces.
1302 // - MachineOperand offset can *only* result from legalization and cannot
1303 // affect queries other than the trivial case of overlap checking.
1304 // - These offsets never wrap and never step outside of allocated objects.
1305 // - There should never be any negative offsets here.
1306 //
1307 // FIXME: Modify API to hide this math from "user"
1308 // Even before we go to AA we can reason locally about some memory objects. It
1309 // can save compile time, and possibly catch some corner cases not currently
1310 // covered.
1311
1312 int64_t OffsetA = MMOa->getOffset();
1313 int64_t OffsetB = MMOb->getOffset();
1314 int64_t MinOffset = std::min(OffsetA, OffsetB);
1315
1316 LocationSize WidthA = MMOa->getSize();
1317 LocationSize WidthB = MMOb->getSize();
1318 bool KnownWidthA = WidthA.hasValue();
1319 bool KnownWidthB = WidthB.hasValue();
1320 bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
1321
1322 const Value *ValA = MMOa->getValue();
1323 const Value *ValB = MMOb->getValue();
1324 bool SameVal = (ValA && ValB && (ValA == ValB));
1325 if (!SameVal) {
1326 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1327 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1328 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1329 return false;
1330 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1331 return false;
1332 if (PSVa && PSVb && (PSVa == PSVb))
1333 SameVal = true;
1334 }
1335
1336 if (SameVal && BothMMONonScalable) {
1337 if (!KnownWidthA || !KnownWidthB)
1338 return true;
1339 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1340 int64_t LowWidth = (MinOffset == OffsetA)
1341 ? WidthA.getValue().getKnownMinValue()
1342 : WidthB.getValue().getKnownMinValue();
1343 return (MinOffset + LowWidth > MaxOffset);
1344 }
1345
1346 if (!AA)
1347 return true;
1348
1349 if (!ValA || !ValB)
1350 return true;
1351
1352 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1353 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1354
1355 // If Scalable Location Size has non-zero offset, Width + Offset does not work
1356 // at the moment
1357 if ((WidthA.isScalable() && OffsetA > 0) ||
1358 (WidthB.isScalable() && OffsetB > 0))
1359 return true;
1360
1361 int64_t OverlapA =
1362 KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1364 int64_t OverlapB =
1365 KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1367
1368 LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1369 ? WidthA
1370 : LocationSize::precise(OverlapA);
1371 LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1372 ? WidthB
1373 : LocationSize::precise(OverlapB);
1374
1375 return !AA->isNoAlias(
1376 MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1377 MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1378}
1379
1381 bool UseTBAA) const {
1382 const MachineFunction *MF = getMF();
1384 const MachineFrameInfo &MFI = MF->getFrameInfo();
1385
1386 // Exclude call instruction which may alter the memory but can not be handled
1387 // by this function.
1388 if (isCall() || Other.isCall())
1389 return true;
1390
1391 // If neither instruction stores to memory, they can't alias in any
1392 // meaningful way, even if they read from the same address.
1393 if (!mayStore() && !Other.mayStore())
1394 return false;
1395
1396 // Both instructions must be memory operations to be able to alias.
1397 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1398 return false;
1399
1400 // Let the target decide if memory accesses cannot possibly overlap.
1402 return false;
1403
1404 // Memory operations without memory operands may access anything. Be
1405 // conservative and assume `MayAlias`.
1406 if (memoperands_empty() || Other.memoperands_empty())
1407 return true;
1408
1409 // Skip if there are too many memory operands.
1410 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1411 if (NumChecks > TII->getMemOperandAACheckLimit())
1412 return true;
1413
1414 // Check each pair of memory operands from both instructions, which can't
1415 // alias only if all pairs won't alias.
1416 for (auto *MMOa : memoperands())
1417 for (auto *MMOb : Other.memoperands())
1418 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1419 return true;
1420
1421 return false;
1422}
1423
1424/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1425/// or volatile memory reference, or if the information describing the memory
1426/// reference is not available. Return false if it is known to have no ordered
1427/// memory references.
1429 // An instruction known never to access memory won't have a volatile access.
1430 if (!mayStore() &&
1431 !mayLoad() &&
1432 !isCall() &&
1434 return false;
1435
1436 // Otherwise, if the instruction has no memory reference information,
1437 // conservatively assume it wasn't preserved.
1438 if (memoperands_empty())
1439 return true;
1440
1441 // Check if any of our memory operands are ordered.
1442 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1443 return !MMO->isUnordered();
1444 });
1445}
1446
1447/// isDereferenceableInvariantLoad - Return true if this instruction will never
1448/// trap and is loading from a location whose value is invariant across a run of
1449/// this function.
1451 // If the instruction doesn't load at all, it isn't an invariant load.
1452 if (!mayLoad())
1453 return false;
1454
1455 // If the instruction has lost its memoperands, conservatively assume that
1456 // it may not be an invariant load.
1457 if (memoperands_empty())
1458 return false;
1459
1460 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1461
1462 for (MachineMemOperand *MMO : memoperands()) {
1463 if (!MMO->isUnordered())
1464 // If the memory operand has ordering side effects, we can't move the
1465 // instruction. Such an instruction is technically an invariant load,
1466 // but the caller code would need updated to expect that.
1467 return false;
1468 if (MMO->isStore()) return false;
1469 if (MMO->isInvariant() && MMO->isDereferenceable())
1470 continue;
1471
1472 // A load from a constant PseudoSourceValue is invariant.
1473 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1474 if (PSV->isConstant(&MFI))
1475 continue;
1476 }
1477
1478 // Otherwise assume conservatively.
1479 return false;
1480 }
1481
1482 // Everything checks out.
1483 return true;
1484}
1485
1486/// isConstantValuePHI - If the specified instruction is a PHI that always
1487/// merges together the same virtual register, return the register, otherwise
1488/// return 0.
1490 if (!isPHI())
1491 return 0;
1492 assert(getNumOperands() >= 3 &&
1493 "It's illegal to have a PHI without source operands");
1494
1495 Register Reg = getOperand(1).getReg();
1496 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1497 if (getOperand(i).getReg() != Reg)
1498 return 0;
1499 return Reg;
1500}
1501
1504 return true;
1505 if (isInlineAsm()) {
1506 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1507 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1508 return true;
1509 }
1510
1511 return false;
1512}
1513
1515 return mayStore() || isCall() ||
1517}
1518
1519/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1520///
1522 for (const MachineOperand &MO : operands()) {
1523 if (!MO.isReg() || MO.isUse())
1524 continue;
1525 if (!MO.isDead())
1526 return false;
1527 }
1528 return true;
1529}
1530
1532 for (const MachineOperand &MO : implicit_operands()) {
1533 if (!MO.isReg() || MO.isUse())
1534 continue;
1535 if (!MO.isDead())
1536 return false;
1537 }
1538 return true;
1539}
1540
1541/// copyImplicitOps - Copy implicit register operands from specified
1542/// instruction to this instruction.
1544 const MachineInstr &MI) {
1545 for (const MachineOperand &MO :
1546 llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1547 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1548 addOperand(MF, MO);
1549}
1550
1552 const MCInstrDesc &MCID = getDesc();
1553 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1554 return true;
1555 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1556 const auto &Operand = getOperand(I);
1557 if (!Operand.isReg() || Operand.isDef())
1558 // Ignore the defined registers as MCID marks only the uses as tied.
1559 continue;
1560 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1561 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1562 if (ExpectedTiedIdx != TiedIdx)
1563 return true;
1564 }
1565 return false;
1566}
1567
1569 const MachineRegisterInfo &MRI) const {
1570 const MachineOperand &Op = getOperand(OpIdx);
1571 if (!Op.isReg())
1572 return LLT{};
1573
1574 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1575 return MRI.getType(Op.getReg());
1576
1577 auto &OpInfo = getDesc().operands()[OpIdx];
1578 if (!OpInfo.isGenericType())
1579 return MRI.getType(Op.getReg());
1580
1581 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1582 return LLT{};
1583
1584 LLT TypeToPrint = MRI.getType(Op.getReg());
1585 // Don't mark the type index printed if it wasn't actually printed: maybe
1586 // another operand with the same type index has an actual type attached:
1587 if (TypeToPrint.isValid())
1588 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1589 return TypeToPrint;
1590}
1591
1592#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1594 dbgs() << " ";
1595 print(dbgs());
1596}
1597
1598LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1599 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1600 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1601 if (Depth >= MaxDepth)
1602 return;
1603 if (!AlreadySeenInstrs.insert(this).second)
1604 return;
1605 // PadToColumn always inserts at least one space.
1606 // Don't mess up the alignment if we don't want any space.
1607 if (Depth)
1608 fdbgs().PadToColumn(Depth * 2);
1609 print(fdbgs());
1610 for (const MachineOperand &MO : operands()) {
1611 if (!MO.isReg() || MO.isDef())
1612 continue;
1613 Register Reg = MO.getReg();
1614 if (Reg.isPhysical())
1615 continue;
1616 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1617 if (NewMI == nullptr)
1618 continue;
1619 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1620 }
1621}
1622
1624 unsigned MaxDepth) const {
1625 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1626 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1627}
1628#endif
1629
1630void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1631 bool SkipDebugLoc, bool AddNewLine,
1632 const TargetInstrInfo *TII) const {
1633 const Module *M = nullptr;
1634 const Function *F = nullptr;
1635 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1636 F = &MF->getFunction();
1637 M = F->getParent();
1638 if (!TII)
1639 TII = MF->getSubtarget().getInstrInfo();
1640 }
1641
1642 ModuleSlotTracker MST(M);
1643 if (F)
1644 MST.incorporateFunction(*F);
1645 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1646}
1647
1649 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1650 bool AddNewLine, const TargetInstrInfo *TII) const {
1651 // We can be a bit tidier if we know the MachineFunction.
1652 const TargetRegisterInfo *TRI = nullptr;
1653 const MachineRegisterInfo *MRI = nullptr;
1654 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1655 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1656
1657 if (isCFIInstruction())
1658 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1659
1660 SmallBitVector PrintedTypes(8);
1661 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1662 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1663 if (!ShouldPrintRegisterTies)
1664 return 0U;
1665 const MachineOperand &MO = getOperand(OpIdx);
1666 if (MO.isReg() && MO.isTied() && !MO.isDef())
1667 return findTiedOperandIdx(OpIdx);
1668 return 0U;
1669 };
1670 unsigned StartOp = 0;
1671 unsigned e = getNumOperands();
1672
1673 // Print explicitly defined operands on the left of an assignment syntax.
1674 while (StartOp < e) {
1675 const MachineOperand &MO = getOperand(StartOp);
1676 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1677 break;
1678
1679 if (StartOp != 0)
1680 OS << ", ";
1681
1682 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1683 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1684 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1685 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1686 ++StartOp;
1687 }
1688
1689 if (StartOp != 0)
1690 OS << " = ";
1691
1693 OS << "frame-setup ";
1695 OS << "frame-destroy ";
1697 OS << "nnan ";
1699 OS << "ninf ";
1701 OS << "nsz ";
1703 OS << "arcp ";
1705 OS << "contract ";
1707 OS << "afn ";
1709 OS << "reassoc ";
1711 OS << "nuw ";
1713 OS << "nsw ";
1715 OS << "exact ";
1717 OS << "nofpexcept ";
1719 OS << "nomerge ";
1721 OS << "nneg ";
1723 OS << "disjoint ";
1724
1725 // Print the opcode name.
1726 if (TII)
1727 OS << TII->getName(getOpcode());
1728 else
1729 OS << "UNKNOWN";
1730
1731 if (SkipOpers)
1732 return;
1733
1734 // Print the rest of the operands.
1735 bool FirstOp = true;
1736 unsigned AsmDescOp = ~0u;
1737 unsigned AsmOpCount = 0;
1738
1740 // Print asm string.
1741 OS << " ";
1742 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1743 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1744 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1745 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1746 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1747 IntrinsicInfo);
1748
1749 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1750 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1751 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1752 OS << " [sideeffect]";
1753 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1754 OS << " [mayload]";
1755 if (ExtraInfo & InlineAsm::Extra_MayStore)
1756 OS << " [maystore]";
1757 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1758 OS << " [isconvergent]";
1759 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1760 OS << " [alignstack]";
1762 OS << " [attdialect]";
1764 OS << " [inteldialect]";
1765
1766 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1767 FirstOp = false;
1768 }
1769
1770 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1771 const MachineOperand &MO = getOperand(i);
1772
1773 if (FirstOp) FirstOp = false; else OS << ",";
1774 OS << " ";
1775
1776 if (isDebugValueLike() && MO.isMetadata()) {
1777 // Pretty print DBG_VALUE* instructions.
1778 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1779 if (DIV && !DIV->getName().empty())
1780 OS << "!\"" << DIV->getName() << '\"';
1781 else {
1782 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1783 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1784 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1785 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1786 }
1787 } else if (isDebugLabel() && MO.isMetadata()) {
1788 // Pretty print DBG_LABEL instructions.
1789 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1790 if (DIL && !DIL->getName().empty())
1791 OS << "\"" << DIL->getName() << '\"';
1792 else {
1793 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1794 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1795 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1796 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1797 }
1798 } else if (i == AsmDescOp && MO.isImm()) {
1799 // Pretty print the inline asm operand descriptor.
1800 OS << '$' << AsmOpCount++;
1801 unsigned Flag = MO.getImm();
1802 const InlineAsm::Flag F(Flag);
1803 OS << ":[";
1804 OS << F.getKindName();
1805
1806 unsigned RCID;
1807 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
1808 if (TRI) {
1809 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1810 } else
1811 OS << ":RC" << RCID;
1812 }
1813
1814 if (F.isMemKind()) {
1815 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1816 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1817 }
1818
1819 unsigned TiedTo;
1820 if (F.isUseOperandTiedToDef(TiedTo))
1821 OS << " tiedto:$" << TiedTo;
1822
1823 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
1824 F.isRegUseKind()) &&
1825 F.getRegMayBeFolded()) {
1826 OS << " foldable";
1827 }
1828
1829 OS << ']';
1830
1831 // Compute the index of the next operand descriptor.
1832 AsmDescOp += 1 + F.getNumOperandRegisters();
1833 } else {
1834 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1835 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1836 if (MO.isImm() && isOperandSubregIdx(i))
1838 else
1839 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1840 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1841 }
1842 }
1843
1844 // Print any optional symbols attached to this instruction as-if they were
1845 // operands.
1846 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1847 if (!FirstOp) {
1848 FirstOp = false;
1849 OS << ',';
1850 }
1851 OS << " pre-instr-symbol ";
1852 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1853 }
1854 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1855 if (!FirstOp) {
1856 FirstOp = false;
1857 OS << ',';
1858 }
1859 OS << " post-instr-symbol ";
1860 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1861 }
1862 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1863 if (!FirstOp) {
1864 FirstOp = false;
1865 OS << ',';
1866 }
1867 OS << " heap-alloc-marker ";
1868 HeapAllocMarker->printAsOperand(OS, MST);
1869 }
1870 if (MDNode *PCSections = getPCSections()) {
1871 if (!FirstOp) {
1872 FirstOp = false;
1873 OS << ',';
1874 }
1875 OS << " pcsections ";
1876 PCSections->printAsOperand(OS, MST);
1877 }
1878 if (uint32_t CFIType = getCFIType()) {
1879 if (!FirstOp)
1880 OS << ',';
1881 OS << " cfi-type " << CFIType;
1882 }
1883
1884 if (DebugInstrNum) {
1885 if (!FirstOp)
1886 OS << ",";
1887 OS << " debug-instr-number " << DebugInstrNum;
1888 }
1889
1890 if (!SkipDebugLoc) {
1891 if (const DebugLoc &DL = getDebugLoc()) {
1892 if (!FirstOp)
1893 OS << ',';
1894 OS << " debug-location ";
1895 DL->printAsOperand(OS, MST);
1896 }
1897 }
1898
1899 if (!memoperands_empty()) {
1901 const LLVMContext *Context = nullptr;
1902 std::unique_ptr<LLVMContext> CtxPtr;
1903 const MachineFrameInfo *MFI = nullptr;
1904 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1905 MFI = &MF->getFrameInfo();
1906 Context = &MF->getFunction().getContext();
1907 } else {
1908 CtxPtr = std::make_unique<LLVMContext>();
1909 Context = CtxPtr.get();
1910 }
1911
1912 OS << " :: ";
1913 bool NeedComma = false;
1914 for (const MachineMemOperand *Op : memoperands()) {
1915 if (NeedComma)
1916 OS << ", ";
1917 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1918 NeedComma = true;
1919 }
1920 }
1921
1922 if (SkipDebugLoc)
1923 return;
1924
1925 bool HaveSemi = false;
1926
1927 // Print debug location information.
1928 if (const DebugLoc &DL = getDebugLoc()) {
1929 if (!HaveSemi) {
1930 OS << ';';
1931 HaveSemi = true;
1932 }
1933 OS << ' ';
1934 DL.print(OS);
1935 }
1936
1937 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
1938 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
1939 (isDebugValueList() && getNumOperands() >= 2) ||
1940 (isDebugRef() && getNumOperands() >= 3)) {
1941 if (getDebugVariableOp().isMetadata()) {
1942 if (!HaveSemi) {
1943 OS << ";";
1944 HaveSemi = true;
1945 }
1946 auto *DV = getDebugVariable();
1947 OS << " line no:" << DV->getLine();
1949 OS << " indirect";
1950 }
1951 }
1952 // TODO: DBG_LABEL
1953
1954 if (AddNewLine)
1955 OS << '\n';
1956}
1957
1959 const TargetRegisterInfo *RegInfo,
1960 bool AddIfNotFound) {
1961 bool isPhysReg = IncomingReg.isPhysical();
1962 bool hasAliases = isPhysReg &&
1963 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1964 bool Found = false;
1966 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1967 MachineOperand &MO = getOperand(i);
1968 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1969 continue;
1970
1971 // DEBUG_VALUE nodes do not contribute to code generation and should
1972 // always be ignored. Failure to do so may result in trying to modify
1973 // KILL flags on DEBUG_VALUE nodes.
1974 if (MO.isDebug())
1975 continue;
1976
1977 Register Reg = MO.getReg();
1978 if (!Reg)
1979 continue;
1980
1981 if (Reg == IncomingReg) {
1982 if (!Found) {
1983 if (MO.isKill())
1984 // The register is already marked kill.
1985 return true;
1986 if (isPhysReg && isRegTiedToDefOperand(i))
1987 // Two-address uses of physregs must not be marked kill.
1988 return true;
1989 MO.setIsKill();
1990 Found = true;
1991 }
1992 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
1993 // A super-register kill already exists.
1994 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1995 return true;
1996 if (RegInfo->isSubRegister(IncomingReg, Reg))
1997 DeadOps.push_back(i);
1998 }
1999 }
2000
2001 // Trim unneeded kill operands.
2002 while (!DeadOps.empty()) {
2003 unsigned OpIdx = DeadOps.back();
2004 if (getOperand(OpIdx).isImplicit() &&
2005 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2006 removeOperand(OpIdx);
2007 else
2008 getOperand(OpIdx).setIsKill(false);
2009 DeadOps.pop_back();
2010 }
2011
2012 // If not found, this means an alias of one of the operands is killed. Add a
2013 // new implicit operand if required.
2014 if (!Found && AddIfNotFound) {
2016 false /*IsDef*/,
2017 true /*IsImp*/,
2018 true /*IsKill*/));
2019 return true;
2020 }
2021 return Found;
2022}
2023
2025 const TargetRegisterInfo *RegInfo) {
2026 if (!Reg.isPhysical())
2027 RegInfo = nullptr;
2028 for (MachineOperand &MO : operands()) {
2029 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2030 continue;
2031 Register OpReg = MO.getReg();
2032 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
2033 MO.setIsKill(false);
2034 }
2035}
2036
2038 const TargetRegisterInfo *RegInfo,
2039 bool AddIfNotFound) {
2040 bool isPhysReg = Reg.isPhysical();
2041 bool hasAliases = isPhysReg &&
2042 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2043 bool Found = false;
2045 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2046 MachineOperand &MO = getOperand(i);
2047 if (!MO.isReg() || !MO.isDef())
2048 continue;
2049 Register MOReg = MO.getReg();
2050 if (!MOReg)
2051 continue;
2052
2053 if (MOReg == Reg) {
2054 MO.setIsDead();
2055 Found = true;
2056 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2057 // There exists a super-register that's marked dead.
2058 if (RegInfo->isSuperRegister(Reg, MOReg))
2059 return true;
2060 if (RegInfo->isSubRegister(Reg, MOReg))
2061 DeadOps.push_back(i);
2062 }
2063 }
2064
2065 // Trim unneeded dead operands.
2066 while (!DeadOps.empty()) {
2067 unsigned OpIdx = DeadOps.back();
2068 if (getOperand(OpIdx).isImplicit() &&
2069 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2070 removeOperand(OpIdx);
2071 else
2072 getOperand(OpIdx).setIsDead(false);
2073 DeadOps.pop_back();
2074 }
2075
2076 // If not found, this means an alias of one of the operands is dead. Add a
2077 // new implicit operand if required.
2078 if (Found || !AddIfNotFound)
2079 return Found;
2080
2082 true /*IsDef*/,
2083 true /*IsImp*/,
2084 false /*IsKill*/,
2085 true /*IsDead*/));
2086 return true;
2087}
2088
2090 for (MachineOperand &MO : operands()) {
2091 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2092 continue;
2093 MO.setIsDead(false);
2094 }
2095}
2096
2098 for (MachineOperand &MO : operands()) {
2099 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2100 continue;
2101 MO.setIsUndef(IsUndef);
2102 }
2103}
2104
2106 const TargetRegisterInfo *RegInfo) {
2107 if (Reg.isPhysical()) {
2108 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2109 if (MO)
2110 return;
2111 } else {
2112 for (const MachineOperand &MO : operands()) {
2113 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2114 MO.getSubReg() == 0)
2115 return;
2116 }
2117 }
2119 true /*IsDef*/,
2120 true /*IsImp*/));
2121}
2122
2124 const TargetRegisterInfo &TRI) {
2125 bool HasRegMask = false;
2126 for (MachineOperand &MO : operands()) {
2127 if (MO.isRegMask()) {
2128 HasRegMask = true;
2129 continue;
2130 }
2131 if (!MO.isReg() || !MO.isDef()) continue;
2132 Register Reg = MO.getReg();
2133 if (!Reg.isPhysical())
2134 continue;
2135 // If there are no uses, including partial uses, the def is dead.
2136 if (llvm::none_of(UsedRegs,
2137 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2138 MO.setIsDead();
2139 }
2140
2141 // This is a call with a register mask operand.
2142 // Mask clobbers are always dead, so add defs for the non-dead defines.
2143 if (HasRegMask)
2144 for (const Register &UsedReg : UsedRegs)
2145 addRegisterDefined(UsedReg, &TRI);
2146}
2147
2148unsigned
2150 // Build up a buffer of hash code components.
2151 SmallVector<size_t, 16> HashComponents;
2152 HashComponents.reserve(MI->getNumOperands() + 1);
2153 HashComponents.push_back(MI->getOpcode());
2154 for (const MachineOperand &MO : MI->operands()) {
2155 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2156 continue; // Skip virtual register defs.
2157
2158 HashComponents.push_back(hash_value(MO));
2159 }
2160 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2161}
2162
2164 // Find the source location cookie.
2165 uint64_t LocCookie = 0;
2166 const MDNode *LocMD = nullptr;
2167 for (unsigned i = getNumOperands(); i != 0; --i) {
2168 if (getOperand(i-1).isMetadata() &&
2169 (LocMD = getOperand(i-1).getMetadata()) &&
2170 LocMD->getNumOperands() != 0) {
2171 if (const ConstantInt *CI =
2172 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2173 LocCookie = CI->getZExtValue();
2174 break;
2175 }
2176 }
2177 }
2178
2179 if (const MachineBasicBlock *MBB = getParent())
2180 if (const MachineFunction *MF = MBB->getParent())
2181 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2182 report_fatal_error(Msg);
2183}
2184
2186 const MCInstrDesc &MCID, bool IsIndirect,
2187 Register Reg, const MDNode *Variable,
2188 const MDNode *Expr) {
2189 assert(isa<DILocalVariable>(Variable) && "not a variable");
2190 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2191 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2192 "Expected inlined-at fields to agree");
2193 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2194 if (IsIndirect)
2195 MIB.addImm(0U);
2196 else
2197 MIB.addReg(0U);
2198 return MIB.addMetadata(Variable).addMetadata(Expr);
2199}
2200
2202 const MCInstrDesc &MCID, bool IsIndirect,
2203 ArrayRef<MachineOperand> DebugOps,
2204 const MDNode *Variable, const MDNode *Expr) {
2205 assert(isa<DILocalVariable>(Variable) && "not a variable");
2206 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2207 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2208 "Expected inlined-at fields to agree");
2209 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2210 assert(DebugOps.size() == 1 &&
2211 "DBG_VALUE must contain exactly one debug operand");
2212 MachineOperand DebugOp = DebugOps[0];
2213 if (DebugOp.isReg())
2214 return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,
2215 Expr);
2216
2217 auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);
2218 if (IsIndirect)
2219 MIB.addImm(0U);
2220 else
2221 MIB.addReg(0U);
2222 return MIB.addMetadata(Variable).addMetadata(Expr);
2223 }
2224
2225 auto MIB = BuildMI(MF, DL, MCID);
2226 MIB.addMetadata(Variable).addMetadata(Expr);
2227 for (const MachineOperand &DebugOp : DebugOps)
2228 if (DebugOp.isReg())
2229 MIB.addReg(DebugOp.getReg());
2230 else
2231 MIB.add(DebugOp);
2232 return MIB;
2233}
2234
2237 const DebugLoc &DL, const MCInstrDesc &MCID,
2238 bool IsIndirect, Register Reg,
2239 const MDNode *Variable, const MDNode *Expr) {
2240 MachineFunction &MF = *BB.getParent();
2241 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2242 BB.insert(I, MI);
2243 return MachineInstrBuilder(MF, MI);
2244}
2245
2248 const DebugLoc &DL, const MCInstrDesc &MCID,
2249 bool IsIndirect,
2250 ArrayRef<MachineOperand> DebugOps,
2251 const MDNode *Variable, const MDNode *Expr) {
2252 MachineFunction &MF = *BB.getParent();
2253 MachineInstr *MI =
2254 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2255 BB.insert(I, MI);
2256 return MachineInstrBuilder(MF, *MI);
2257}
2258
2259/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2260/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2261static const DIExpression *
2263 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2264 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2265 "Expected inlined-at fields to agree");
2266
2267 const DIExpression *Expr = MI.getDebugExpression();
2268 if (MI.isIndirectDebugValue()) {
2269 assert(MI.getDebugOffset().getImm() == 0 &&
2270 "DBG_VALUE with nonzero offset");
2272 } else if (MI.isDebugValueList()) {
2273 // We will replace the spilled register with a frame index, so
2274 // immediately deref all references to the spilled register.
2275 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2276 for (const MachineOperand *Op : SpilledOperands) {
2277 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2278 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2279 }
2280 }
2281 return Expr;
2282}
2284 Register SpillReg) {
2285 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2287 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2288 SpillOperands.push_back(&Op);
2289 return computeExprForSpill(MI, SpillOperands);
2290}
2291
2294 const MachineInstr &Orig,
2295 int FrameIndex, Register SpillReg) {
2296 assert(!Orig.isDebugRef() &&
2297 "DBG_INSTR_REF should not reference a virtual register.");
2298 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2299 MachineInstrBuilder NewMI =
2300 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2301 // Non-Variadic Operands: Location, Offset, Variable, Expression
2302 // Variadic Operands: Variable, Expression, Locations...
2303 if (Orig.isNonListDebugValue())
2304 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2305 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2306 if (Orig.isDebugValueList()) {
2307 for (const MachineOperand &Op : Orig.debug_operands())
2308 if (Op.isReg() && Op.getReg() == SpillReg)
2309 NewMI.addFrameIndex(FrameIndex);
2310 else
2311 NewMI.add(MachineOperand(Op));
2312 }
2313 return NewMI;
2314}
2317 const MachineInstr &Orig, int FrameIndex,
2318 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2319 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2320 MachineInstrBuilder NewMI =
2321 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2322 // Non-Variadic Operands: Location, Offset, Variable, Expression
2323 // Variadic Operands: Variable, Expression, Locations...
2324 if (Orig.isNonListDebugValue())
2325 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2326 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2327 if (Orig.isDebugValueList()) {
2328 for (const MachineOperand &Op : Orig.debug_operands())
2329 if (is_contained(SpilledOperands, &Op))
2330 NewMI.addFrameIndex(FrameIndex);
2331 else
2332 NewMI.add(MachineOperand(Op));
2333 }
2334 return NewMI;
2335}
2336
2338 Register Reg) {
2339 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2340 if (Orig.isNonListDebugValue())
2342 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2343 Op.ChangeToFrameIndex(FrameIndex);
2344 Orig.getDebugExpressionOp().setMetadata(Expr);
2345}
2346
2349 MachineInstr &MI = *this;
2350 if (!MI.getOperand(0).isReg())
2351 return;
2352
2354 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2355 DI != DE; ++DI) {
2356 if (!DI->isDebugValue())
2357 return;
2358 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2359 DbgValues.push_back(&*DI);
2360 }
2361}
2362
2364 // Collect matching debug values.
2366
2367 if (!getOperand(0).isReg())
2368 return;
2369
2370 Register DefReg = getOperand(0).getReg();
2371 auto *MRI = getRegInfo();
2372 for (auto &MO : MRI->use_operands(DefReg)) {
2373 auto *DI = MO.getParent();
2374 if (!DI->isDebugValue())
2375 continue;
2376 if (DI->hasDebugOperandForReg(DefReg)) {
2377 DbgValues.push_back(DI);
2378 }
2379 }
2380
2381 // Propagate Reg to debug value instructions.
2382 for (auto *DBI : DbgValues)
2383 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2384 Op.setReg(Reg);
2385}
2386
2388
2390 const MachineFrameInfo &MFI) {
2391 uint64_t Size = 0;
2392 for (const auto *A : Accesses) {
2393 if (MFI.isSpillSlotObjectIndex(
2394 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2395 ->getFrameIndex())) {
2396 LocationSize S = A->getSize();
2397 if (!S.hasValue())
2399 Size += S.getValue();
2400 }
2401 }
2402 return Size;
2403}
2404
2405std::optional<LocationSize>
2407 int FI;
2408 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2409 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2410 if (MFI.isSpillSlotObjectIndex(FI))
2411 return (*memoperands_begin())->getSize();
2412 }
2413 return std::nullopt;
2414}
2415
2416std::optional<LocationSize>
2418 MMOList Accesses;
2419 if (TII->hasStoreToStackSlot(*this, Accesses))
2420 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2421 return std::nullopt;
2422}
2423
2424std::optional<LocationSize>
2426 int FI;
2427 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2428 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2429 if (MFI.isSpillSlotObjectIndex(FI))
2430 return (*memoperands_begin())->getSize();
2431 }
2432 return std::nullopt;
2433}
2434
2435std::optional<LocationSize>
2437 MMOList Accesses;
2438 if (TII->hasLoadFromStackSlot(*this, Accesses))
2439 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2440 return std::nullopt;
2441}
2442
2444 if (DebugInstrNum == 0)
2445 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2446 return DebugInstrNum;
2447}
2448
2450 if (DebugInstrNum == 0)
2451 DebugInstrNum = MF.getNewDebugInstrNum();
2452 return DebugInstrNum;
2453}
2454
2455std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2456 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2457 getRegInfo()->getType(getOperand(1).getReg()));
2458}
2459
2460std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2461 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2462 getRegInfo()->getType(getOperand(1).getReg()),
2463 getRegInfo()->getType(getOperand(2).getReg()));
2464}
2465
2466std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2467 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2468 getRegInfo()->getType(getOperand(1).getReg()),
2469 getRegInfo()->getType(getOperand(2).getReg()),
2470 getRegInfo()->getType(getOperand(3).getReg()));
2471}
2472
2473std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2474 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2475 getRegInfo()->getType(getOperand(1).getReg()),
2476 getRegInfo()->getType(getOperand(2).getReg()),
2477 getRegInfo()->getType(getOperand(3).getReg()),
2478 getRegInfo()->getType(getOperand(4).getReg()));
2479}
2480
2481std::tuple<Register, LLT, Register, LLT>
2483 Register Reg0 = getOperand(0).getReg();
2484 Register Reg1 = getOperand(1).getReg();
2485 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2486 getRegInfo()->getType(Reg1));
2487}
2488
2489std::tuple<Register, LLT, Register, LLT, Register, LLT>
2491 Register Reg0 = getOperand(0).getReg();
2492 Register Reg1 = getOperand(1).getReg();
2493 Register Reg2 = getOperand(2).getReg();
2494 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2495 getRegInfo()->getType(Reg1), Reg2,
2496 getRegInfo()->getType(Reg2));
2497}
2498
2499std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2501 Register Reg0 = getOperand(0).getReg();
2502 Register Reg1 = getOperand(1).getReg();
2503 Register Reg2 = getOperand(2).getReg();
2504 Register Reg3 = getOperand(3).getReg();
2505 return std::tuple(
2506 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2507 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));
2508}
2509
2511 LLT>
2513 Register Reg0 = getOperand(0).getReg();
2514 Register Reg1 = getOperand(1).getReg();
2515 Register Reg2 = getOperand(2).getReg();
2516 Register Reg3 = getOperand(3).getReg();
2517 Register Reg4 = getOperand(4).getReg();
2518 return std::tuple(
2519 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2520 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),
2521 Reg4, getRegInfo()->getType(Reg4));
2522}
2523
2526 assert(InsertBefore != nullptr && "invalid iterator");
2527 assert(InsertBefore->getParent() == this &&
2528 "iterator points to operand of other inst");
2529 if (Ops.empty())
2530 return;
2531
2532 // Do one pass to untie operands.
2534 for (const MachineOperand &MO : operands()) {
2535 if (MO.isReg() && MO.isTied()) {
2536 unsigned OpNo = getOperandNo(&MO);
2537 unsigned TiedTo = findTiedOperandIdx(OpNo);
2538 TiedOpIndices[OpNo] = TiedTo;
2539 untieRegOperand(OpNo);
2540 }
2541 }
2542
2543 unsigned OpIdx = getOperandNo(InsertBefore);
2544 unsigned NumOperands = getNumOperands();
2545 unsigned OpsToMove = NumOperands - OpIdx;
2546
2548 MovingOps.reserve(OpsToMove);
2549
2550 for (unsigned I = 0; I < OpsToMove; ++I) {
2551 MovingOps.emplace_back(getOperand(OpIdx));
2552 removeOperand(OpIdx);
2553 }
2554 for (const MachineOperand &MO : Ops)
2555 addOperand(MO);
2556 for (const MachineOperand &OpMoved : MovingOps)
2557 addOperand(OpMoved);
2558
2559 // Re-tie operands.
2560 for (auto [Tie1, Tie2] : TiedOpIndices) {
2561 if (Tie1 >= OpIdx)
2562 Tie1 += Ops.size();
2563 if (Tie2 >= OpIdx)
2564 Tie2 += Ops.size();
2565 tieOperands(Tie1, Tie2);
2566 }
2567}
2568
2569bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
2570 assert(OpId && "expected non-zero operand id");
2571 assert(isInlineAsm() && "should only be used on inline asm");
2572
2573 if (!getOperand(OpId).isReg())
2574 return false;
2575
2576 const MachineOperand &MD = getOperand(OpId - 1);
2577 if (!MD.isImm())
2578 return false;
2579
2580 InlineAsm::Flag F(MD.getImm());
2581 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
2582 return F.getRegMayBeFolded();
2583 return false;
2584}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:529
This file contains the declarations for the subclasses of Constant, which represent the different fla...
uint64_t Size
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
const unsigned TiedMax
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
This file contains the declarations for metadata subclasses.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
Value * RHS
Value * LHS
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
DWARF expression.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
A debug info location.
Definition: DebugLoc.h:33
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:200
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:350
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
static StringRef getMemConstraintName(ConstraintCode C)
Definition: InlineAsm.h:467
constexpr bool isValid() const
Definition: LowLevelType.h:145
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
bool hasValue() const
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
bool isScalable() const
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:338
unsigned short Opcode
Definition: MCInstrDesc.h:205
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:261
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1428
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1434
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Instructions::iterator instr_iterator
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:587
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isPosition() const
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:942
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:684
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:329
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:842
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:865
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:392
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:854
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:918
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:379
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:552
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:549
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:789
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:784
bool isDebugRef() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:752
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:454
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:832
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:795
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:401
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:633
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:662
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:777
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:759
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:475
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:798
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:480
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:565
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:676
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:458
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:822
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:374
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:810
void unbundleFromSucc()
Break bundle below this instruction.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:615
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
bool isKill() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:886
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5165
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:896
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:295
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:75
An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...
Definition: InstrTypes.h:516
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:150
Instruction that can have a nneg flag (only zext).
Definition: InstrTypes.h:931
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
SmallBitVector & set()
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void reserve(size_type N)
Definition: SmallVector.h:676
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:171
MI-level Statepoint operands.
Definition: StackMaps.h:158
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
LLVM Value Representation.
Definition: Value.h:74
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:173
constexpr double e
Definition: MathExtras.h:31
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1745
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
@ Other
Any other memory.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1888
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:491
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
#define N
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
static unsigned getHashValue(const MachineInstr *const &MI)