LLVM 18.0.0git
MachineInstr.cpp
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1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
37#include "llvm/IR/Constants.h"
39#include "llvm/IR/DebugLoc.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/InlineAsm.h"
42#include "llvm/IR/LLVMContext.h"
43#include "llvm/IR/Metadata.h"
44#include "llvm/IR/Module.h"
46#include "llvm/IR/Operator.h"
47#include "llvm/MC/MCInstrDesc.h"
51#include "llvm/Support/Debug.h"
56#include <algorithm>
57#include <cassert>
58#include <cstdint>
59#include <cstring>
60#include <utility>
61
62using namespace llvm;
63
65 if (const MachineBasicBlock *MBB = MI.getParent())
66 if (const MachineFunction *MF = MBB->getParent())
67 return MF;
68 return nullptr;
69}
70
71// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
72// it.
74 const TargetRegisterInfo *&TRI,
76 const TargetIntrinsicInfo *&IntrinsicInfo,
77 const TargetInstrInfo *&TII) {
78
79 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
80 TRI = MF->getSubtarget().getRegisterInfo();
81 MRI = &MF->getRegInfo();
82 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83 TII = MF->getSubtarget().getInstrInfo();
84 }
85}
86
88 for (MCPhysReg ImpDef : MCID->implicit_defs())
89 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true));
90 for (MCPhysReg ImpUse : MCID->implicit_uses())
91 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true));
92}
93
94/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
95/// implicit operands. It reserves space for the number of operands specified by
96/// the MCInstrDesc.
97MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
98 DebugLoc DL, bool NoImp)
99 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
100 DbgLoc(std::move(DL)), DebugInstrNum(0) {
101 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
102
103 // Reserve space for the expected number of operands.
104 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
105 MCID->implicit_uses().size()) {
106 CapOperands = OperandCapacity::get(NumOps);
107 Operands = MF.allocateOperandArray(CapOperands);
108 }
109
110 if (!NoImp)
112}
113
114/// MachineInstr ctor - Copies MachineInstr arg exactly.
115/// Does not copy the number from debug instruction numbering, to preserve
116/// uniqueness.
117MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
118 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
119 Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0) {
120 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
121
122 CapOperands = OperandCapacity::get(MI.getNumOperands());
123 Operands = MF.allocateOperandArray(CapOperands);
124
125 // Copy operands.
126 for (const MachineOperand &MO : MI.operands())
127 addOperand(MF, MO);
128
129 // Replicate ties between the operands, which addOperand was not
130 // able to do reliably.
131 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
132 MachineOperand &NewMO = getOperand(i);
133 const MachineOperand &OrigMO = MI.getOperand(i);
134 NewMO.TiedTo = OrigMO.TiedTo;
135 }
136
137 // Copy all the sensible flags.
138 setFlags(MI.Flags);
139}
140
142 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
143}
144
145/// getRegInfo - If this instruction is embedded into a MachineFunction,
146/// return the MachineRegisterInfo object for the current function, otherwise
147/// return null.
148MachineRegisterInfo *MachineInstr::getRegInfo() {
150 return &MBB->getParent()->getRegInfo();
151 return nullptr;
152}
153
154const MachineRegisterInfo *MachineInstr::getRegInfo() const {
155 if (const MachineBasicBlock *MBB = getParent())
156 return &MBB->getParent()->getRegInfo();
157 return nullptr;
158}
159
160void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
161 for (MachineOperand &MO : operands())
162 if (MO.isReg())
163 MRI.removeRegOperandFromUseList(&MO);
164}
165
166void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
167 for (MachineOperand &MO : operands())
168 if (MO.isReg())
169 MRI.addRegOperandToUseList(&MO);
170}
171
174 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
176 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
177 addOperand(*MF, Op);
178}
179
180/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
181/// ranges. If MRI is non-null also update use-def chains.
183 unsigned NumOps, MachineRegisterInfo *MRI) {
184 if (MRI)
185 return MRI->moveOperands(Dst, Src, NumOps);
186 // MachineOperand is a trivially copyable type so we can just use memmove.
187 assert(Dst && Src && "Unknown operands");
188 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
189}
190
191/// addOperand - Add the specified operand to the instruction. If it is an
192/// implicit operand, it is added to the end of the operand list. If it is
193/// an explicit operand it is added at the end of the explicit operand list
194/// (before the first implicit operand).
196 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
197 "Cannot add more operands.");
198 assert(MCID && "Cannot add operands before providing an instr descriptor");
199
200 // Check if we're adding one of our existing operands.
201 if (&Op >= Operands && &Op < Operands + NumOperands) {
202 // This is unusual: MI->addOperand(MI->getOperand(i)).
203 // If adding Op requires reallocating or moving existing operands around,
204 // the Op reference could go stale. Support it by copying Op.
205 MachineOperand CopyOp(Op);
206 return addOperand(MF, CopyOp);
207 }
208
209 // Find the insert location for the new operand. Implicit registers go at
210 // the end, everything else goes before the implicit regs.
211 //
212 // FIXME: Allow mixed explicit and implicit operands on inline asm.
213 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
214 // implicit-defs, but they must not be moved around. See the FIXME in
215 // InstrEmitter.cpp.
216 unsigned OpNo = getNumOperands();
217 bool isImpReg = Op.isReg() && Op.isImplicit();
218 if (!isImpReg && !isInlineAsm()) {
219 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
220 --OpNo;
221 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
222 }
223 }
224
225 // OpNo now points as the desired insertion point. Unless this is a variadic
226 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
227 // RegMask operands go between the explicit and implicit operands.
228 assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||
229 Op.isValidExcessOperand()) &&
230 "Trying to add an operand to a machine instr that is already done!");
231
232 MachineRegisterInfo *MRI = getRegInfo();
233
234 // Determine if the Operands array needs to be reallocated.
235 // Save the old capacity and operand array.
236 OperandCapacity OldCap = CapOperands;
237 MachineOperand *OldOperands = Operands;
238 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
239 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
240 Operands = MF.allocateOperandArray(CapOperands);
241 // Move the operands before the insertion point.
242 if (OpNo)
243 moveOperands(Operands, OldOperands, OpNo, MRI);
244 }
245
246 // Move the operands following the insertion point.
247 if (OpNo != NumOperands)
248 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
249 MRI);
250 ++NumOperands;
251
252 // Deallocate the old operand array.
253 if (OldOperands != Operands && OldOperands)
254 MF.deallocateOperandArray(OldCap, OldOperands);
255
256 // Copy Op into place. It still needs to be inserted into the MRI use lists.
257 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
258 NewMO->ParentMI = this;
259
260 // When adding a register operand, tell MRI about it.
261 if (NewMO->isReg()) {
262 // Ensure isOnRegUseList() returns false, regardless of Op's status.
263 NewMO->Contents.Reg.Prev = nullptr;
264 // Ignore existing ties. This is not a property that can be copied.
265 NewMO->TiedTo = 0;
266 // Add the new operand to MRI, but only for instructions in an MBB.
267 if (MRI)
268 MRI->addRegOperandToUseList(NewMO);
269 // The MCID operand information isn't accurate until we start adding
270 // explicit operands. The implicit operands are added first, then the
271 // explicits are inserted before them.
272 if (!isImpReg) {
273 // Tie uses to defs as indicated in MCInstrDesc.
274 if (NewMO->isUse()) {
275 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
276 if (DefIdx != -1)
277 tieOperands(DefIdx, OpNo);
278 }
279 // If the register operand is flagged as early, mark the operand as such.
280 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
281 NewMO->setIsEarlyClobber(true);
282 }
283 // Ensure debug instructions set debug flag on register uses.
284 if (NewMO->isUse() && isDebugInstr())
285 NewMO->setIsDebug();
286 }
287}
288
289void MachineInstr::removeOperand(unsigned OpNo) {
290 assert(OpNo < getNumOperands() && "Invalid operand number");
291 untieRegOperand(OpNo);
292
293#ifndef NDEBUG
294 // Moving tied operands would break the ties.
295 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
296 if (Operands[i].isReg())
297 assert(!Operands[i].isTied() && "Cannot move tied operands");
298#endif
299
300 MachineRegisterInfo *MRI = getRegInfo();
301 if (MRI && Operands[OpNo].isReg())
302 MRI->removeRegOperandFromUseList(Operands + OpNo);
303
304 // Don't call the MachineOperand destructor. A lot of this code depends on
305 // MachineOperand having a trivial destructor anyway, and adding a call here
306 // wouldn't make it 'destructor-correct'.
307
308 if (unsigned N = NumOperands - 1 - OpNo)
309 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
310 --NumOperands;
311}
312
313void MachineInstr::setExtraInfo(MachineFunction &MF,
315 MCSymbol *PreInstrSymbol,
316 MCSymbol *PostInstrSymbol,
317 MDNode *HeapAllocMarker, MDNode *PCSections,
318 uint32_t CFIType) {
319 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
320 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
321 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
322 bool HasPCSections = PCSections != nullptr;
323 bool HasCFIType = CFIType != 0;
324 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
325 HasHeapAllocMarker + HasPCSections + HasCFIType;
326
327 // Drop all extra info if there is none.
328 if (NumPointers <= 0) {
329 Info.clear();
330 return;
331 }
332
333 // If more than one pointer, then store out of line. Store heap alloc markers
334 // out of line because PointerSumType cannot hold more than 4 tag types with
335 // 32-bit pointers.
336 // FIXME: Maybe we should make the symbols in the extra info mutable?
337 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
338 HasCFIType) {
339 Info.set<EIIK_OutOfLine>(
340 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
341 HeapAllocMarker, PCSections, CFIType));
342 return;
343 }
344
345 // Otherwise store the single pointer inline.
346 if (HasPreInstrSymbol)
347 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
348 else if (HasPostInstrSymbol)
349 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
350 else
351 Info.set<EIIK_MMO>(MMOs[0]);
352}
353
355 if (memoperands_empty())
356 return;
357
358 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
360}
361
364 if (MMOs.empty()) {
365 dropMemRefs(MF);
366 return;
367 }
368
369 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
371}
372
374 MachineMemOperand *MO) {
377 MMOs.push_back(MO);
378 setMemRefs(MF, MMOs);
379}
380
382 if (this == &MI)
383 // Nothing to do for a self-clone!
384 return;
385
386 assert(&MF == MI.getMF() &&
387 "Invalid machine functions when cloning memory refrences!");
388 // See if we can just steal the extra info already allocated for the
389 // instruction. We can do this whenever the pre- and post-instruction symbols
390 // are the same (including null).
391 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
392 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
393 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
394 getPCSections() == MI.getPCSections()) {
395 Info = MI.Info;
396 return;
397 }
398
399 // Otherwise, fall back on a copy-based clone.
400 setMemRefs(MF, MI.memoperands());
401}
402
403/// Check to see if the MMOs pointed to by the two MemRefs arrays are
404/// identical.
407 if (LHS.size() != RHS.size())
408 return false;
409
410 auto LHSPointees = make_pointee_range(LHS);
411 auto RHSPointees = make_pointee_range(RHS);
412 return std::equal(LHSPointees.begin(), LHSPointees.end(),
413 RHSPointees.begin());
414}
415
418 // Try handling easy numbers of MIs with simpler mechanisms.
419 if (MIs.empty()) {
420 dropMemRefs(MF);
421 return;
422 }
423 if (MIs.size() == 1) {
424 cloneMemRefs(MF, *MIs[0]);
425 return;
426 }
427 // Because an empty memoperands list provides *no* information and must be
428 // handled conservatively (assuming the instruction can do anything), the only
429 // way to merge with it is to drop all other memoperands.
430 if (MIs[0]->memoperands_empty()) {
431 dropMemRefs(MF);
432 return;
433 }
434
435 // Handle the general case.
437 // Start with the first instruction.
438 assert(&MF == MIs[0]->getMF() &&
439 "Invalid machine functions when cloning memory references!");
440 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
441 // Now walk all the other instructions and accumulate any different MMOs.
442 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
443 assert(&MF == MI.getMF() &&
444 "Invalid machine functions when cloning memory references!");
445
446 // Skip MIs with identical operands to the first. This is a somewhat
447 // arbitrary hack but will catch common cases without being quadratic.
448 // TODO: We could fully implement merge semantics here if needed.
449 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
450 continue;
451
452 // Because an empty memoperands list provides *no* information and must be
453 // handled conservatively (assuming the instruction can do anything), the
454 // only way to merge with it is to drop all other memoperands.
455 if (MI.memoperands_empty()) {
456 dropMemRefs(MF);
457 return;
458 }
459
460 // Otherwise accumulate these into our temporary buffer of the merged state.
461 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
462 }
463
464 setMemRefs(MF, MergedMMOs);
465}
466
468 // Do nothing if old and new symbols are the same.
469 if (Symbol == getPreInstrSymbol())
470 return;
471
472 // If there was only one symbol and we're removing it, just clear info.
473 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
474 Info.clear();
475 return;
476 }
477
478 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
480}
481
483 // Do nothing if old and new symbols are the same.
484 if (Symbol == getPostInstrSymbol())
485 return;
486
487 // If there was only one symbol and we're removing it, just clear info.
488 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
489 Info.clear();
490 return;
491 }
492
493 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
495}
496
498 // Do nothing if old and new symbols are the same.
499 if (Marker == getHeapAllocMarker())
500 return;
501
502 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
503 Marker, getPCSections(), getCFIType());
504}
505
507 // Do nothing if old and new symbols are the same.
508 if (PCSections == getPCSections())
509 return;
510
511 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
512 getHeapAllocMarker(), PCSections, getCFIType());
513}
514
516 // Do nothing if old and new types are the same.
517 if (Type == getCFIType())
518 return;
519
520 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
522}
523
525 const MachineInstr &MI) {
526 if (this == &MI)
527 // Nothing to do for a self-clone!
528 return;
529
530 assert(&MF == MI.getMF() &&
531 "Invalid machine functions when cloning instruction symbols!");
532
533 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
534 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
535 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
536 setPCSections(MF, MI.getPCSections());
537}
538
540 // For now, the just return the union of the flags. If the flags get more
541 // complicated over time, we might need more logic here.
542 return getFlags() | Other.getFlags();
543}
544
546 uint32_t MIFlags = 0;
547 // Copy the wrapping flags.
548 if (const OverflowingBinaryOperator *OB =
549 dyn_cast<OverflowingBinaryOperator>(&I)) {
550 if (OB->hasNoSignedWrap())
552 if (OB->hasNoUnsignedWrap())
554 }
555
556 // Copy the exact flag.
557 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
558 if (PE->isExact())
560
561 // Copy the fast-math flags.
562 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
563 const FastMathFlags Flags = FP->getFastMathFlags();
564 if (Flags.noNaNs())
566 if (Flags.noInfs())
568 if (Flags.noSignedZeros())
570 if (Flags.allowReciprocal())
572 if (Flags.allowContract())
574 if (Flags.approxFunc())
576 if (Flags.allowReassoc())
578 }
579
580 if (I.getMetadata(LLVMContext::MD_unpredictable))
582
583 return MIFlags;
584}
585
588}
589
590bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
591 assert(!isBundledWithPred() && "Must be called on bundle header");
593 if (MII->getDesc().getFlags() & Mask) {
594 if (Type == AnyInBundle)
595 return true;
596 } else {
597 if (Type == AllInBundle && !MII->isBundle())
598 return false;
599 }
600 // This was the last instruction in the bundle.
601 if (!MII->isBundledWithSucc())
602 return Type == AllInBundle;
603 }
604}
605
607 MICheckType Check) const {
608 // If opcodes or number of operands are not the same then the two
609 // instructions are obviously not identical.
610 if (Other.getOpcode() != getOpcode() ||
611 Other.getNumOperands() != getNumOperands())
612 return false;
613
614 if (isBundle()) {
615 // We have passed the test above that both instructions have the same
616 // opcode, so we know that both instructions are bundles here. Let's compare
617 // MIs inside the bundle.
618 assert(Other.isBundle() && "Expected that both instructions are bundles.");
621 // Loop until we analysed the last intruction inside at least one of the
622 // bundles.
623 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
624 ++I1;
625 ++I2;
626 if (!I1->isIdenticalTo(*I2, Check))
627 return false;
628 }
629 // If we've reached the end of just one of the two bundles, but not both,
630 // the instructions are not identical.
631 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
632 return false;
633 }
634
635 // Check operands to make sure they match.
636 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
637 const MachineOperand &MO = getOperand(i);
638 const MachineOperand &OMO = Other.getOperand(i);
639 if (!MO.isReg()) {
640 if (!MO.isIdenticalTo(OMO))
641 return false;
642 continue;
643 }
644
645 // Clients may or may not want to ignore defs when testing for equality.
646 // For example, machine CSE pass only cares about finding common
647 // subexpressions, so it's safe to ignore virtual register defs.
648 if (MO.isDef()) {
649 if (Check == IgnoreDefs)
650 continue;
651 else if (Check == IgnoreVRegDefs) {
652 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
653 if (!MO.isIdenticalTo(OMO))
654 return false;
655 } else {
656 if (!MO.isIdenticalTo(OMO))
657 return false;
658 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
659 return false;
660 }
661 } else {
662 if (!MO.isIdenticalTo(OMO))
663 return false;
664 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
665 return false;
666 }
667 }
668 // If DebugLoc does not match then two debug instructions are not identical.
669 if (isDebugInstr())
670 if (getDebugLoc() && Other.getDebugLoc() &&
671 getDebugLoc() != Other.getDebugLoc())
672 return false;
673 // If pre- or post-instruction symbols do not match then the two instructions
674 // are not identical.
675 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
676 getPostInstrSymbol() != Other.getPostInstrSymbol())
677 return false;
678 // Call instructions with different CFI types are not identical.
679 if (isCall() && getCFIType() != Other.getCFIType())
680 return false;
681
682 return true;
683}
684
686 if (!isDebugValueLike() || !Other.isDebugValueLike())
687 return false;
688 if (getDebugLoc() != Other.getDebugLoc())
689 return false;
690 if (getDebugVariable() != Other.getDebugVariable())
691 return false;
692 if (getNumDebugOperands() != Other.getNumDebugOperands())
693 return false;
694 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
695 if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx)))
696 return false;
699 Other.getDebugExpression(), Other.isIndirectDebugValue()))
700 return false;
701 return true;
702}
703
705 return getParent()->getParent();
706}
707
709 assert(getParent() && "Not embedded in a basic block!");
710 return getParent()->remove(this);
711}
712
714 assert(getParent() && "Not embedded in a basic block!");
715 return getParent()->remove_instr(this);
716}
717
719 assert(getParent() && "Not embedded in a basic block!");
720 getParent()->erase(this);
721}
722
724 assert(getParent() && "Not embedded in a basic block!");
725 getParent()->erase_instr(this);
726}
727
729 if (!isCall(Type))
730 return false;
731 switch (getOpcode()) {
732 case TargetOpcode::PATCHPOINT:
733 case TargetOpcode::STACKMAP:
734 case TargetOpcode::STATEPOINT:
735 case TargetOpcode::FENTRY_CALL:
736 return false;
737 }
738 return true;
739}
740
742 if (isBundle())
745}
746
748 unsigned NumOperands = MCID->getNumOperands();
749 if (!MCID->isVariadic())
750 return NumOperands;
751
752 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
753 const MachineOperand &MO = getOperand(I);
754 // The operands must always be in the following order:
755 // - explicit reg defs,
756 // - other explicit operands (reg uses, immediates, etc.),
757 // - implicit reg defs
758 // - implicit reg uses
759 if (MO.isReg() && MO.isImplicit())
760 break;
761 ++NumOperands;
762 }
763 return NumOperands;
764}
765
767 unsigned NumDefs = MCID->getNumDefs();
768 if (!MCID->isVariadic())
769 return NumDefs;
770
771 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
772 const MachineOperand &MO = getOperand(I);
773 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
774 break;
775 ++NumDefs;
776 }
777 return NumDefs;
778}
779
781 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
784 --Pred;
785 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
786 Pred->setFlag(BundledSucc);
787}
788
790 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
793 ++Succ;
794 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
795 Succ->setFlag(BundledPred);
796}
797
799 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
802 --Pred;
803 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
804 Pred->clearFlag(BundledSucc);
805}
806
808 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
811 ++Succ;
812 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
813 Succ->clearFlag(BundledPred);
814}
815
817 if (isInlineAsm()) {
818 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
819 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
820 return true;
821 }
822 return false;
823}
824
826 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
827 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
828 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
829}
830
832 unsigned *GroupNo) const {
833 assert(isInlineAsm() && "Expected an inline asm instruction");
834 assert(OpIdx < getNumOperands() && "OpIdx out of range");
835
836 // Ignore queries about the initial operands.
838 return -1;
839
840 unsigned Group = 0;
841 unsigned NumOps;
842 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
843 i += NumOps) {
844 const MachineOperand &FlagMO = getOperand(i);
845 // If we reach the implicit register operands, stop looking.
846 if (!FlagMO.isImm())
847 return -1;
848 const InlineAsm::Flag F(FlagMO.getImm());
849 NumOps = 1 + F.getNumOperandRegisters();
850 if (i + NumOps > OpIdx) {
851 if (GroupNo)
852 *GroupNo = Group;
853 return i;
854 }
855 ++Group;
856 }
857 return -1;
858}
859
861 assert(isDebugLabel() && "not a DBG_LABEL");
862 return cast<DILabel>(getOperand(0).getMetadata());
863}
864
866 assert((isDebugValueLike()) && "not a DBG_VALUE*");
867 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
868 return getOperand(VariableOp);
869}
870
872 assert((isDebugValueLike()) && "not a DBG_VALUE*");
873 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
874 return getOperand(VariableOp);
875}
876
878 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
879}
880
882 assert((isDebugValueLike()) && "not a DBG_VALUE*");
883 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
884 return getOperand(ExpressionOp);
885}
886
888 assert((isDebugValueLike()) && "not a DBG_VALUE*");
889 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
890 return getOperand(ExpressionOp);
891}
892
894 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
895}
896
899}
900
903 const TargetInstrInfo *TII,
904 const TargetRegisterInfo *TRI) const {
905 assert(getParent() && "Can't have an MBB reference here!");
906 assert(getMF() && "Can't have an MF reference here!");
907 const MachineFunction &MF = *getMF();
908
909 // Most opcodes have fixed constraints in their MCInstrDesc.
910 if (!isInlineAsm())
911 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
912
913 if (!getOperand(OpIdx).isReg())
914 return nullptr;
915
916 // For tied uses on inline asm, get the constraint from the def.
917 unsigned DefIdx;
918 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
919 OpIdx = DefIdx;
920
921 // Inline asm stores register class constraints in the flag word.
922 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
923 if (FlagIdx < 0)
924 return nullptr;
925
926 const InlineAsm::Flag F(getOperand(FlagIdx).getImm());
927 unsigned RCID;
928 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
929 F.hasRegClassConstraint(RCID))
930 return TRI->getRegClass(RCID);
931
932 // Assume that all registers in a memory operand are pointers.
933 if (F.isMemKind())
934 return TRI->getPointerRegClass(MF);
935
936 return nullptr;
937}
938
940 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
941 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
942 // Check every operands inside the bundle if we have
943 // been asked to.
944 if (ExploreBundle)
945 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
946 ++OpndIt)
947 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
948 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
949 else
950 // Otherwise, just check the current operands.
951 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
952 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
953 return CurRC;
954}
955
956const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
957 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
958 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
959 assert(CurRC && "Invalid initial register class");
960 // Check if Reg is constrained by some of its use/def from MI.
961 const MachineOperand &MO = getOperand(OpIdx);
962 if (!MO.isReg() || MO.getReg() != Reg)
963 return CurRC;
964 // If yes, accumulate the constraints through the operand.
965 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
966}
967
969 unsigned OpIdx, const TargetRegisterClass *CurRC,
970 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
971 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
972 const MachineOperand &MO = getOperand(OpIdx);
973 assert(MO.isReg() &&
974 "Cannot get register constraints for non-register operand");
975 assert(CurRC && "Invalid initial register class");
976 if (unsigned SubIdx = MO.getSubReg()) {
977 if (OpRC)
978 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
979 else
980 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
981 } else if (OpRC)
982 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
983 return CurRC;
984}
985
986/// Return the number of instructions inside the MI bundle, not counting the
987/// header instruction.
990 unsigned Size = 0;
991 while (I->isBundledWithSucc()) {
992 ++Size;
993 ++I;
994 }
995 return Size;
996}
997
998/// Returns true if the MachineInstr has an implicit-use operand of exactly
999/// the given register (not considering sub/super-registers).
1001 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1002 const MachineOperand &MO = getOperand(i);
1003 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1004 return true;
1005 }
1006 return false;
1007}
1008
1009/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1010/// the specific register or -1 if it is not found. It further tightens
1011/// the search criteria to a use that kills the register if isKill is true.
1013 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1014 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1015 const MachineOperand &MO = getOperand(i);
1016 if (!MO.isReg() || !MO.isUse())
1017 continue;
1018 Register MOReg = MO.getReg();
1019 if (!MOReg)
1020 continue;
1021 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1022 if (!isKill || MO.isKill())
1023 return i;
1024 }
1025 return -1;
1026}
1027
1028/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1029/// indicating if this instruction reads or writes Reg. This also considers
1030/// partial defines.
1031std::pair<bool,bool>
1033 SmallVectorImpl<unsigned> *Ops) const {
1034 bool PartDef = false; // Partial redefine.
1035 bool FullDef = false; // Full define.
1036 bool Use = false;
1037
1038 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1039 const MachineOperand &MO = getOperand(i);
1040 if (!MO.isReg() || MO.getReg() != Reg)
1041 continue;
1042 if (Ops)
1043 Ops->push_back(i);
1044 if (MO.isUse())
1045 Use |= !MO.isUndef();
1046 else if (MO.getSubReg() && !MO.isUndef())
1047 // A partial def undef doesn't count as reading the register.
1048 PartDef = true;
1049 else
1050 FullDef = true;
1051 }
1052 // A partial redefine uses Reg unless there is also a full define.
1053 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1054}
1055
1056/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1057/// the specified register or -1 if it is not found. If isDead is true, defs
1058/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1059/// also checks if there is a def of a super-register.
1060int
1062 const TargetRegisterInfo *TRI) const {
1063 bool isPhys = Reg.isPhysical();
1064 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1065 const MachineOperand &MO = getOperand(i);
1066 // Accept regmask operands when Overlap is set.
1067 // Ignore them when looking for a specific def operand (Overlap == false).
1068 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1069 return i;
1070 if (!MO.isReg() || !MO.isDef())
1071 continue;
1072 Register MOReg = MO.getReg();
1073 bool Found = (MOReg == Reg);
1074 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1075 if (Overlap)
1076 Found = TRI->regsOverlap(MOReg, Reg);
1077 else
1078 Found = TRI->isSubRegister(MOReg, Reg);
1079 }
1080 if (Found && (!isDead || MO.isDead()))
1081 return i;
1082 }
1083 return -1;
1084}
1085
1086/// findFirstPredOperandIdx() - Find the index of the first operand in the
1087/// operand list that is used to represent the predicate. It returns -1 if
1088/// none is found.
1090 // Don't call MCID.findFirstPredOperandIdx() because this variant
1091 // is sometimes called on an instruction that's not yet complete, and
1092 // so the number of operands is less than the MCID indicates. In
1093 // particular, the PTX target does this.
1094 const MCInstrDesc &MCID = getDesc();
1095 if (MCID.isPredicable()) {
1096 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1097 if (MCID.operands()[i].isPredicate())
1098 return i;
1099 }
1100
1101 return -1;
1102}
1103
1104// MachineOperand::TiedTo is 4 bits wide.
1105const unsigned TiedMax = 15;
1106
1107/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1108///
1109/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1110/// field. TiedTo can have these values:
1111///
1112/// 0: Operand is not tied to anything.
1113/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1114/// TiedMax: Tied to an operand >= TiedMax-1.
1115///
1116/// The tied def must be one of the first TiedMax operands on a normal
1117/// instruction. INLINEASM instructions allow more tied defs.
1118///
1119void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1120 MachineOperand &DefMO = getOperand(DefIdx);
1121 MachineOperand &UseMO = getOperand(UseIdx);
1122 assert(DefMO.isDef() && "DefIdx must be a def operand");
1123 assert(UseMO.isUse() && "UseIdx must be a use operand");
1124 assert(!DefMO.isTied() && "Def is already tied to another use");
1125 assert(!UseMO.isTied() && "Use is already tied to another def");
1126
1127 if (DefIdx < TiedMax)
1128 UseMO.TiedTo = DefIdx + 1;
1129 else {
1130 // Inline asm can use the group descriptors to find tied operands,
1131 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1132 // but on normal instruction, the tied def must be within the first TiedMax
1133 // operands.
1134 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1135 "DefIdx out of range");
1136 UseMO.TiedTo = TiedMax;
1137 }
1138
1139 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1140 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1141}
1142
1143/// Given the index of a tied register operand, find the operand it is tied to.
1144/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1145/// which must exist.
1146unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1147 const MachineOperand &MO = getOperand(OpIdx);
1148 assert(MO.isTied() && "Operand isn't tied");
1149
1150 // Normally TiedTo is in range.
1151 if (MO.TiedTo < TiedMax)
1152 return MO.TiedTo - 1;
1153
1154 // Uses on normal instructions can be out of range.
1155 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1156 // Normal tied defs must be in the 0..TiedMax-1 range.
1157 if (MO.isUse())
1158 return TiedMax - 1;
1159 // MO is a def. Search for the tied use.
1160 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1161 const MachineOperand &UseMO = getOperand(i);
1162 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1163 return i;
1164 }
1165 llvm_unreachable("Can't find tied use");
1166 }
1167
1168 if (getOpcode() == TargetOpcode::STATEPOINT) {
1169 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1170 // on registers.
1171 StatepointOpers SO(this);
1172 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1173 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1174 unsigned NumDefs = getNumDefs();
1175 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1176 while (!getOperand(CurUseIdx).isReg())
1177 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1178 if (OpIdx == CurDefIdx)
1179 return CurUseIdx;
1180 if (OpIdx == CurUseIdx)
1181 return CurDefIdx;
1182 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1183 }
1184 llvm_unreachable("Can't find tied use");
1185 }
1186
1187 // Now deal with inline asm by parsing the operand group descriptor flags.
1188 // Find the beginning of each operand group.
1189 SmallVector<unsigned, 8> GroupIdx;
1190 unsigned OpIdxGroup = ~0u;
1191 unsigned NumOps;
1192 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1193 i += NumOps) {
1194 const MachineOperand &FlagMO = getOperand(i);
1195 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1196 unsigned CurGroup = GroupIdx.size();
1197 GroupIdx.push_back(i);
1198 const InlineAsm::Flag F(FlagMO.getImm());
1199 NumOps = 1 + F.getNumOperandRegisters();
1200 // OpIdx belongs to this operand group.
1201 if (OpIdx > i && OpIdx < i + NumOps)
1202 OpIdxGroup = CurGroup;
1203 unsigned TiedGroup;
1204 if (!F.isUseOperandTiedToDef(TiedGroup))
1205 continue;
1206 // Operands in this group are tied to operands in TiedGroup which must be
1207 // earlier. Find the number of operands between the two groups.
1208 unsigned Delta = i - GroupIdx[TiedGroup];
1209
1210 // OpIdx is a use tied to TiedGroup.
1211 if (OpIdxGroup == CurGroup)
1212 return OpIdx - Delta;
1213
1214 // OpIdx is a def tied to this use group.
1215 if (OpIdxGroup == TiedGroup)
1216 return OpIdx + Delta;
1217 }
1218 llvm_unreachable("Invalid tied operand on inline asm");
1219}
1220
1221/// clearKillInfo - Clears kill flags on all operands.
1222///
1224 for (MachineOperand &MO : operands()) {
1225 if (MO.isReg() && MO.isUse())
1226 MO.setIsKill(false);
1227 }
1228}
1229
1231 unsigned SubIdx,
1232 const TargetRegisterInfo &RegInfo) {
1233 if (ToReg.isPhysical()) {
1234 if (SubIdx)
1235 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1236 for (MachineOperand &MO : operands()) {
1237 if (!MO.isReg() || MO.getReg() != FromReg)
1238 continue;
1239 MO.substPhysReg(ToReg, RegInfo);
1240 }
1241 } else {
1242 for (MachineOperand &MO : operands()) {
1243 if (!MO.isReg() || MO.getReg() != FromReg)
1244 continue;
1245 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1246 }
1247 }
1248}
1249
1250/// isSafeToMove - Return true if it is safe to move this instruction. If
1251/// SawStore is set to true, it means that there is a store (or call) between
1252/// the instruction's location and its intended destination.
1253bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1254 // Ignore stuff that we obviously can't move.
1255 //
1256 // Treat volatile loads as stores. This is not strictly necessary for
1257 // volatiles, but it is required for atomic loads. It is not allowed to move
1258 // a load across an atomic load with Ordering > Monotonic.
1259 if (mayStore() || isCall() || isPHI() ||
1260 (mayLoad() && hasOrderedMemoryRef())) {
1261 SawStore = true;
1262 return false;
1263 }
1264
1265 if (isPosition() || isDebugInstr() || isTerminator() ||
1268 return false;
1269
1270 // See if this instruction does a load. If so, we have to guarantee that the
1271 // loaded value doesn't change between the load and the its intended
1272 // destination. The check for isInvariantLoad gives the target the chance to
1273 // classify the load as always returning a constant, e.g. a constant pool
1274 // load.
1276 // Otherwise, this is a real load. If there is a store between the load and
1277 // end of block, we can't move it.
1278 return !SawStore;
1279
1280 return true;
1281}
1282
1284 bool UseTBAA, const MachineMemOperand *MMOa,
1285 const MachineMemOperand *MMOb) {
1286 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1287 // operates with MachineMemOperand offset with some important assumptions:
1288 // - LLVM fundamentally assumes flat address spaces.
1289 // - MachineOperand offset can *only* result from legalization and cannot
1290 // affect queries other than the trivial case of overlap checking.
1291 // - These offsets never wrap and never step outside of allocated objects.
1292 // - There should never be any negative offsets here.
1293 //
1294 // FIXME: Modify API to hide this math from "user"
1295 // Even before we go to AA we can reason locally about some memory objects. It
1296 // can save compile time, and possibly catch some corner cases not currently
1297 // covered.
1298
1299 int64_t OffsetA = MMOa->getOffset();
1300 int64_t OffsetB = MMOb->getOffset();
1301 int64_t MinOffset = std::min(OffsetA, OffsetB);
1302
1303 uint64_t WidthA = MMOa->getSize();
1304 uint64_t WidthB = MMOb->getSize();
1305 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1306 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1307
1308 const Value *ValA = MMOa->getValue();
1309 const Value *ValB = MMOb->getValue();
1310 bool SameVal = (ValA && ValB && (ValA == ValB));
1311 if (!SameVal) {
1312 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1313 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1314 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1315 return false;
1316 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1317 return false;
1318 if (PSVa && PSVb && (PSVa == PSVb))
1319 SameVal = true;
1320 }
1321
1322 if (SameVal) {
1323 if (!KnownWidthA || !KnownWidthB)
1324 return true;
1325 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1326 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1327 return (MinOffset + LowWidth > MaxOffset);
1328 }
1329
1330 if (!AA)
1331 return true;
1332
1333 if (!ValA || !ValB)
1334 return true;
1335
1336 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1337 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1338
1339 int64_t OverlapA =
1340 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1341 int64_t OverlapB =
1342 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1343
1344 return !AA->isNoAlias(
1345 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1346 MemoryLocation(ValB, OverlapB,
1347 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1348}
1349
1351 bool UseTBAA) const {
1352 const MachineFunction *MF = getMF();
1354 const MachineFrameInfo &MFI = MF->getFrameInfo();
1355
1356 // Exclude call instruction which may alter the memory but can not be handled
1357 // by this function.
1358 if (isCall() || Other.isCall())
1359 return true;
1360
1361 // If neither instruction stores to memory, they can't alias in any
1362 // meaningful way, even if they read from the same address.
1363 if (!mayStore() && !Other.mayStore())
1364 return false;
1365
1366 // Both instructions must be memory operations to be able to alias.
1367 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1368 return false;
1369
1370 // Let the target decide if memory accesses cannot possibly overlap.
1372 return false;
1373
1374 // Memory operations without memory operands may access anything. Be
1375 // conservative and assume `MayAlias`.
1376 if (memoperands_empty() || Other.memoperands_empty())
1377 return true;
1378
1379 // Skip if there are too many memory operands.
1380 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1381 if (NumChecks > TII->getMemOperandAACheckLimit())
1382 return true;
1383
1384 // Check each pair of memory operands from both instructions, which can't
1385 // alias only if all pairs won't alias.
1386 for (auto *MMOa : memoperands())
1387 for (auto *MMOb : Other.memoperands())
1388 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1389 return true;
1390
1391 return false;
1392}
1393
1394/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1395/// or volatile memory reference, or if the information describing the memory
1396/// reference is not available. Return false if it is known to have no ordered
1397/// memory references.
1399 // An instruction known never to access memory won't have a volatile access.
1400 if (!mayStore() &&
1401 !mayLoad() &&
1402 !isCall() &&
1404 return false;
1405
1406 // Otherwise, if the instruction has no memory reference information,
1407 // conservatively assume it wasn't preserved.
1408 if (memoperands_empty())
1409 return true;
1410
1411 // Check if any of our memory operands are ordered.
1412 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1413 return !MMO->isUnordered();
1414 });
1415}
1416
1417/// isDereferenceableInvariantLoad - Return true if this instruction will never
1418/// trap and is loading from a location whose value is invariant across a run of
1419/// this function.
1421 // If the instruction doesn't load at all, it isn't an invariant load.
1422 if (!mayLoad())
1423 return false;
1424
1425 // If the instruction has lost its memoperands, conservatively assume that
1426 // it may not be an invariant load.
1427 if (memoperands_empty())
1428 return false;
1429
1430 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1431
1432 for (MachineMemOperand *MMO : memoperands()) {
1433 if (!MMO->isUnordered())
1434 // If the memory operand has ordering side effects, we can't move the
1435 // instruction. Such an instruction is technically an invariant load,
1436 // but the caller code would need updated to expect that.
1437 return false;
1438 if (MMO->isStore()) return false;
1439 if (MMO->isInvariant() && MMO->isDereferenceable())
1440 continue;
1441
1442 // A load from a constant PseudoSourceValue is invariant.
1443 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1444 if (PSV->isConstant(&MFI))
1445 continue;
1446 }
1447
1448 // Otherwise assume conservatively.
1449 return false;
1450 }
1451
1452 // Everything checks out.
1453 return true;
1454}
1455
1456/// isConstantValuePHI - If the specified instruction is a PHI that always
1457/// merges together the same virtual register, return the register, otherwise
1458/// return 0.
1460 if (!isPHI())
1461 return 0;
1462 assert(getNumOperands() >= 3 &&
1463 "It's illegal to have a PHI without source operands");
1464
1465 Register Reg = getOperand(1).getReg();
1466 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1467 if (getOperand(i).getReg() != Reg)
1468 return 0;
1469 return Reg;
1470}
1471
1474 return true;
1475 if (isInlineAsm()) {
1476 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1477 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1478 return true;
1479 }
1480
1481 return false;
1482}
1483
1485 return mayStore() || isCall() ||
1487}
1488
1489/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1490///
1492 for (const MachineOperand &MO : operands()) {
1493 if (!MO.isReg() || MO.isUse())
1494 continue;
1495 if (!MO.isDead())
1496 return false;
1497 }
1498 return true;
1499}
1500
1502 for (const MachineOperand &MO : implicit_operands()) {
1503 if (!MO.isReg() || MO.isUse())
1504 continue;
1505 if (!MO.isDead())
1506 return false;
1507 }
1508 return true;
1509}
1510
1511/// copyImplicitOps - Copy implicit register operands from specified
1512/// instruction to this instruction.
1514 const MachineInstr &MI) {
1515 for (const MachineOperand &MO :
1516 llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1517 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1518 addOperand(MF, MO);
1519}
1520
1522 const MCInstrDesc &MCID = getDesc();
1523 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1524 return true;
1525 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1526 const auto &Operand = getOperand(I);
1527 if (!Operand.isReg() || Operand.isDef())
1528 // Ignore the defined registers as MCID marks only the uses as tied.
1529 continue;
1530 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1531 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1532 if (ExpectedTiedIdx != TiedIdx)
1533 return true;
1534 }
1535 return false;
1536}
1537
1539 const MachineRegisterInfo &MRI) const {
1540 const MachineOperand &Op = getOperand(OpIdx);
1541 if (!Op.isReg())
1542 return LLT{};
1543
1544 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1545 return MRI.getType(Op.getReg());
1546
1547 auto &OpInfo = getDesc().operands()[OpIdx];
1548 if (!OpInfo.isGenericType())
1549 return MRI.getType(Op.getReg());
1550
1551 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1552 return LLT{};
1553
1554 LLT TypeToPrint = MRI.getType(Op.getReg());
1555 // Don't mark the type index printed if it wasn't actually printed: maybe
1556 // another operand with the same type index has an actual type attached:
1557 if (TypeToPrint.isValid())
1558 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1559 return TypeToPrint;
1560}
1561
1562#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1564 dbgs() << " ";
1565 print(dbgs());
1566}
1567
1568LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1569 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1570 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1571 if (Depth >= MaxDepth)
1572 return;
1573 if (!AlreadySeenInstrs.insert(this).second)
1574 return;
1575 // PadToColumn always inserts at least one space.
1576 // Don't mess up the alignment if we don't want any space.
1577 if (Depth)
1578 fdbgs().PadToColumn(Depth * 2);
1579 print(fdbgs());
1580 for (const MachineOperand &MO : operands()) {
1581 if (!MO.isReg() || MO.isDef())
1582 continue;
1583 Register Reg = MO.getReg();
1584 if (Reg.isPhysical())
1585 continue;
1586 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1587 if (NewMI == nullptr)
1588 continue;
1589 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1590 }
1591}
1592
1594 unsigned MaxDepth) const {
1595 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1596 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1597}
1598#endif
1599
1600void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1601 bool SkipDebugLoc, bool AddNewLine,
1602 const TargetInstrInfo *TII) const {
1603 const Module *M = nullptr;
1604 const Function *F = nullptr;
1605 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1606 F = &MF->getFunction();
1607 M = F->getParent();
1608 if (!TII)
1609 TII = MF->getSubtarget().getInstrInfo();
1610 }
1611
1612 ModuleSlotTracker MST(M);
1613 if (F)
1614 MST.incorporateFunction(*F);
1615 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1616}
1617
1619 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1620 bool AddNewLine, const TargetInstrInfo *TII) const {
1621 // We can be a bit tidier if we know the MachineFunction.
1622 const TargetRegisterInfo *TRI = nullptr;
1623 const MachineRegisterInfo *MRI = nullptr;
1624 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1625 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1626
1627 if (isCFIInstruction())
1628 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1629
1630 SmallBitVector PrintedTypes(8);
1631 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1632 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1633 if (!ShouldPrintRegisterTies)
1634 return 0U;
1635 const MachineOperand &MO = getOperand(OpIdx);
1636 if (MO.isReg() && MO.isTied() && !MO.isDef())
1637 return findTiedOperandIdx(OpIdx);
1638 return 0U;
1639 };
1640 unsigned StartOp = 0;
1641 unsigned e = getNumOperands();
1642
1643 // Print explicitly defined operands on the left of an assignment syntax.
1644 while (StartOp < e) {
1645 const MachineOperand &MO = getOperand(StartOp);
1646 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1647 break;
1648
1649 if (StartOp != 0)
1650 OS << ", ";
1651
1652 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1653 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1654 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1655 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1656 ++StartOp;
1657 }
1658
1659 if (StartOp != 0)
1660 OS << " = ";
1661
1663 OS << "frame-setup ";
1665 OS << "frame-destroy ";
1667 OS << "nnan ";
1669 OS << "ninf ";
1671 OS << "nsz ";
1673 OS << "arcp ";
1675 OS << "contract ";
1677 OS << "afn ";
1679 OS << "reassoc ";
1681 OS << "nuw ";
1683 OS << "nsw ";
1685 OS << "exact ";
1687 OS << "nofpexcept ";
1689 OS << "nomerge ";
1690
1691 // Print the opcode name.
1692 if (TII)
1693 OS << TII->getName(getOpcode());
1694 else
1695 OS << "UNKNOWN";
1696
1697 if (SkipOpers)
1698 return;
1699
1700 // Print the rest of the operands.
1701 bool FirstOp = true;
1702 unsigned AsmDescOp = ~0u;
1703 unsigned AsmOpCount = 0;
1704
1706 // Print asm string.
1707 OS << " ";
1708 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1709 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1710 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1711 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1712 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1713 IntrinsicInfo);
1714
1715 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1716 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1717 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1718 OS << " [sideeffect]";
1719 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1720 OS << " [mayload]";
1721 if (ExtraInfo & InlineAsm::Extra_MayStore)
1722 OS << " [maystore]";
1723 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1724 OS << " [isconvergent]";
1725 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1726 OS << " [alignstack]";
1728 OS << " [attdialect]";
1730 OS << " [inteldialect]";
1731
1732 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1733 FirstOp = false;
1734 }
1735
1736 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1737 const MachineOperand &MO = getOperand(i);
1738
1739 if (FirstOp) FirstOp = false; else OS << ",";
1740 OS << " ";
1741
1742 if (isDebugValueLike() && MO.isMetadata()) {
1743 // Pretty print DBG_VALUE* instructions.
1744 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1745 if (DIV && !DIV->getName().empty())
1746 OS << "!\"" << DIV->getName() << '\"';
1747 else {
1748 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1749 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1750 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1751 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1752 }
1753 } else if (isDebugLabel() && MO.isMetadata()) {
1754 // Pretty print DBG_LABEL instructions.
1755 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1756 if (DIL && !DIL->getName().empty())
1757 OS << "\"" << DIL->getName() << '\"';
1758 else {
1759 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1760 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1761 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1762 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1763 }
1764 } else if (i == AsmDescOp && MO.isImm()) {
1765 // Pretty print the inline asm operand descriptor.
1766 OS << '$' << AsmOpCount++;
1767 unsigned Flag = MO.getImm();
1768 const InlineAsm::Flag F(Flag);
1769 OS << ":[";
1770 OS << F.getKindName();
1771
1772 unsigned RCID;
1773 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
1774 if (TRI) {
1775 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1776 } else
1777 OS << ":RC" << RCID;
1778 }
1779
1780 if (F.isMemKind()) {
1781 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1782 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1783 }
1784
1785 unsigned TiedTo;
1786 if (F.isUseOperandTiedToDef(TiedTo))
1787 OS << " tiedto:$" << TiedTo;
1788
1789 OS << ']';
1790
1791 // Compute the index of the next operand descriptor.
1792 AsmDescOp += 1 + F.getNumOperandRegisters();
1793 } else {
1794 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1795 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1796 if (MO.isImm() && isOperandSubregIdx(i))
1798 else
1799 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1800 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1801 }
1802 }
1803
1804 // Print any optional symbols attached to this instruction as-if they were
1805 // operands.
1806 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1807 if (!FirstOp) {
1808 FirstOp = false;
1809 OS << ',';
1810 }
1811 OS << " pre-instr-symbol ";
1812 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1813 }
1814 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1815 if (!FirstOp) {
1816 FirstOp = false;
1817 OS << ',';
1818 }
1819 OS << " post-instr-symbol ";
1820 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1821 }
1822 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1823 if (!FirstOp) {
1824 FirstOp = false;
1825 OS << ',';
1826 }
1827 OS << " heap-alloc-marker ";
1828 HeapAllocMarker->printAsOperand(OS, MST);
1829 }
1830 if (MDNode *PCSections = getPCSections()) {
1831 if (!FirstOp) {
1832 FirstOp = false;
1833 OS << ',';
1834 }
1835 OS << " pcsections ";
1836 PCSections->printAsOperand(OS, MST);
1837 }
1838 if (uint32_t CFIType = getCFIType()) {
1839 if (!FirstOp)
1840 OS << ',';
1841 OS << " cfi-type " << CFIType;
1842 }
1843
1844 if (DebugInstrNum) {
1845 if (!FirstOp)
1846 OS << ",";
1847 OS << " debug-instr-number " << DebugInstrNum;
1848 }
1849
1850 if (!SkipDebugLoc) {
1851 if (const DebugLoc &DL = getDebugLoc()) {
1852 if (!FirstOp)
1853 OS << ',';
1854 OS << " debug-location ";
1855 DL->printAsOperand(OS, MST);
1856 }
1857 }
1858
1859 if (!memoperands_empty()) {
1861 const LLVMContext *Context = nullptr;
1862 std::unique_ptr<LLVMContext> CtxPtr;
1863 const MachineFrameInfo *MFI = nullptr;
1864 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1865 MFI = &MF->getFrameInfo();
1866 Context = &MF->getFunction().getContext();
1867 } else {
1868 CtxPtr = std::make_unique<LLVMContext>();
1869 Context = CtxPtr.get();
1870 }
1871
1872 OS << " :: ";
1873 bool NeedComma = false;
1874 for (const MachineMemOperand *Op : memoperands()) {
1875 if (NeedComma)
1876 OS << ", ";
1877 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1878 NeedComma = true;
1879 }
1880 }
1881
1882 if (SkipDebugLoc)
1883 return;
1884
1885 bool HaveSemi = false;
1886
1887 // Print debug location information.
1888 if (const DebugLoc &DL = getDebugLoc()) {
1889 if (!HaveSemi) {
1890 OS << ';';
1891 HaveSemi = true;
1892 }
1893 OS << ' ';
1894 DL.print(OS);
1895 }
1896
1897 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
1898 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
1899 (isDebugValueList() && getNumOperands() >= 2) ||
1900 (isDebugRef() && getNumOperands() >= 3)) {
1901 if (getDebugVariableOp().isMetadata()) {
1902 if (!HaveSemi) {
1903 OS << ";";
1904 HaveSemi = true;
1905 }
1906 auto *DV = getDebugVariable();
1907 OS << " line no:" << DV->getLine();
1909 OS << " indirect";
1910 }
1911 }
1912 // TODO: DBG_LABEL
1913
1914 if (AddNewLine)
1915 OS << '\n';
1916}
1917
1919 const TargetRegisterInfo *RegInfo,
1920 bool AddIfNotFound) {
1921 bool isPhysReg = IncomingReg.isPhysical();
1922 bool hasAliases = isPhysReg &&
1923 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1924 bool Found = false;
1926 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1927 MachineOperand &MO = getOperand(i);
1928 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1929 continue;
1930
1931 // DEBUG_VALUE nodes do not contribute to code generation and should
1932 // always be ignored. Failure to do so may result in trying to modify
1933 // KILL flags on DEBUG_VALUE nodes.
1934 if (MO.isDebug())
1935 continue;
1936
1937 Register Reg = MO.getReg();
1938 if (!Reg)
1939 continue;
1940
1941 if (Reg == IncomingReg) {
1942 if (!Found) {
1943 if (MO.isKill())
1944 // The register is already marked kill.
1945 return true;
1946 if (isPhysReg && isRegTiedToDefOperand(i))
1947 // Two-address uses of physregs must not be marked kill.
1948 return true;
1949 MO.setIsKill();
1950 Found = true;
1951 }
1952 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
1953 // A super-register kill already exists.
1954 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1955 return true;
1956 if (RegInfo->isSubRegister(IncomingReg, Reg))
1957 DeadOps.push_back(i);
1958 }
1959 }
1960
1961 // Trim unneeded kill operands.
1962 while (!DeadOps.empty()) {
1963 unsigned OpIdx = DeadOps.back();
1964 if (getOperand(OpIdx).isImplicit() &&
1965 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1966 removeOperand(OpIdx);
1967 else
1968 getOperand(OpIdx).setIsKill(false);
1969 DeadOps.pop_back();
1970 }
1971
1972 // If not found, this means an alias of one of the operands is killed. Add a
1973 // new implicit operand if required.
1974 if (!Found && AddIfNotFound) {
1976 false /*IsDef*/,
1977 true /*IsImp*/,
1978 true /*IsKill*/));
1979 return true;
1980 }
1981 return Found;
1982}
1983
1985 const TargetRegisterInfo *RegInfo) {
1986 if (!Reg.isPhysical())
1987 RegInfo = nullptr;
1988 for (MachineOperand &MO : operands()) {
1989 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1990 continue;
1991 Register OpReg = MO.getReg();
1992 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1993 MO.setIsKill(false);
1994 }
1995}
1996
1998 const TargetRegisterInfo *RegInfo,
1999 bool AddIfNotFound) {
2000 bool isPhysReg = Reg.isPhysical();
2001 bool hasAliases = isPhysReg &&
2002 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2003 bool Found = false;
2005 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2006 MachineOperand &MO = getOperand(i);
2007 if (!MO.isReg() || !MO.isDef())
2008 continue;
2009 Register MOReg = MO.getReg();
2010 if (!MOReg)
2011 continue;
2012
2013 if (MOReg == Reg) {
2014 MO.setIsDead();
2015 Found = true;
2016 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2017 // There exists a super-register that's marked dead.
2018 if (RegInfo->isSuperRegister(Reg, MOReg))
2019 return true;
2020 if (RegInfo->isSubRegister(Reg, MOReg))
2021 DeadOps.push_back(i);
2022 }
2023 }
2024
2025 // Trim unneeded dead operands.
2026 while (!DeadOps.empty()) {
2027 unsigned OpIdx = DeadOps.back();
2028 if (getOperand(OpIdx).isImplicit() &&
2029 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2030 removeOperand(OpIdx);
2031 else
2032 getOperand(OpIdx).setIsDead(false);
2033 DeadOps.pop_back();
2034 }
2035
2036 // If not found, this means an alias of one of the operands is dead. Add a
2037 // new implicit operand if required.
2038 if (Found || !AddIfNotFound)
2039 return Found;
2040
2042 true /*IsDef*/,
2043 true /*IsImp*/,
2044 false /*IsKill*/,
2045 true /*IsDead*/));
2046 return true;
2047}
2048
2050 for (MachineOperand &MO : operands()) {
2051 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2052 continue;
2053 MO.setIsDead(false);
2054 }
2055}
2056
2058 for (MachineOperand &MO : operands()) {
2059 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2060 continue;
2061 MO.setIsUndef(IsUndef);
2062 }
2063}
2064
2066 const TargetRegisterInfo *RegInfo) {
2067 if (Reg.isPhysical()) {
2068 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2069 if (MO)
2070 return;
2071 } else {
2072 for (const MachineOperand &MO : operands()) {
2073 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2074 MO.getSubReg() == 0)
2075 return;
2076 }
2077 }
2079 true /*IsDef*/,
2080 true /*IsImp*/));
2081}
2082
2084 const TargetRegisterInfo &TRI) {
2085 bool HasRegMask = false;
2086 for (MachineOperand &MO : operands()) {
2087 if (MO.isRegMask()) {
2088 HasRegMask = true;
2089 continue;
2090 }
2091 if (!MO.isReg() || !MO.isDef()) continue;
2092 Register Reg = MO.getReg();
2093 if (!Reg.isPhysical())
2094 continue;
2095 // If there are no uses, including partial uses, the def is dead.
2096 if (llvm::none_of(UsedRegs,
2097 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2098 MO.setIsDead();
2099 }
2100
2101 // This is a call with a register mask operand.
2102 // Mask clobbers are always dead, so add defs for the non-dead defines.
2103 if (HasRegMask)
2104 for (const Register &UsedReg : UsedRegs)
2105 addRegisterDefined(UsedReg, &TRI);
2106}
2107
2108unsigned
2110 // Build up a buffer of hash code components.
2111 SmallVector<size_t, 16> HashComponents;
2112 HashComponents.reserve(MI->getNumOperands() + 1);
2113 HashComponents.push_back(MI->getOpcode());
2114 for (const MachineOperand &MO : MI->operands()) {
2115 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2116 continue; // Skip virtual register defs.
2117
2118 HashComponents.push_back(hash_value(MO));
2119 }
2120 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2121}
2122
2124 // Find the source location cookie.
2125 uint64_t LocCookie = 0;
2126 const MDNode *LocMD = nullptr;
2127 for (unsigned i = getNumOperands(); i != 0; --i) {
2128 if (getOperand(i-1).isMetadata() &&
2129 (LocMD = getOperand(i-1).getMetadata()) &&
2130 LocMD->getNumOperands() != 0) {
2131 if (const ConstantInt *CI =
2132 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2133 LocCookie = CI->getZExtValue();
2134 break;
2135 }
2136 }
2137 }
2138
2139 if (const MachineBasicBlock *MBB = getParent())
2140 if (const MachineFunction *MF = MBB->getParent())
2141 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2142 report_fatal_error(Msg);
2143}
2144
2146 const MCInstrDesc &MCID, bool IsIndirect,
2147 Register Reg, const MDNode *Variable,
2148 const MDNode *Expr) {
2149 assert(isa<DILocalVariable>(Variable) && "not a variable");
2150 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2151 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2152 "Expected inlined-at fields to agree");
2153 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2154 if (IsIndirect)
2155 MIB.addImm(0U);
2156 else
2157 MIB.addReg(0U);
2158 return MIB.addMetadata(Variable).addMetadata(Expr);
2159}
2160
2162 const MCInstrDesc &MCID, bool IsIndirect,
2163 ArrayRef<MachineOperand> DebugOps,
2164 const MDNode *Variable, const MDNode *Expr) {
2165 assert(isa<DILocalVariable>(Variable) && "not a variable");
2166 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2167 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2168 "Expected inlined-at fields to agree");
2169 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2170 assert(DebugOps.size() == 1 &&
2171 "DBG_VALUE must contain exactly one debug operand");
2172 MachineOperand DebugOp = DebugOps[0];
2173 if (DebugOp.isReg())
2174 return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,
2175 Expr);
2176
2177 auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);
2178 if (IsIndirect)
2179 MIB.addImm(0U);
2180 else
2181 MIB.addReg(0U);
2182 return MIB.addMetadata(Variable).addMetadata(Expr);
2183 }
2184
2185 auto MIB = BuildMI(MF, DL, MCID);
2186 MIB.addMetadata(Variable).addMetadata(Expr);
2187 for (const MachineOperand &DebugOp : DebugOps)
2188 if (DebugOp.isReg())
2189 MIB.addReg(DebugOp.getReg());
2190 else
2191 MIB.add(DebugOp);
2192 return MIB;
2193}
2194
2197 const DebugLoc &DL, const MCInstrDesc &MCID,
2198 bool IsIndirect, Register Reg,
2199 const MDNode *Variable, const MDNode *Expr) {
2200 MachineFunction &MF = *BB.getParent();
2201 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2202 BB.insert(I, MI);
2203 return MachineInstrBuilder(MF, MI);
2204}
2205
2208 const DebugLoc &DL, const MCInstrDesc &MCID,
2209 bool IsIndirect,
2210 ArrayRef<MachineOperand> DebugOps,
2211 const MDNode *Variable, const MDNode *Expr) {
2212 MachineFunction &MF = *BB.getParent();
2213 MachineInstr *MI =
2214 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2215 BB.insert(I, MI);
2216 return MachineInstrBuilder(MF, *MI);
2217}
2218
2219/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2220/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2221static const DIExpression *
2223 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2224 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2225 "Expected inlined-at fields to agree");
2226
2227 const DIExpression *Expr = MI.getDebugExpression();
2228 if (MI.isIndirectDebugValue()) {
2229 assert(MI.getDebugOffset().getImm() == 0 &&
2230 "DBG_VALUE with nonzero offset");
2232 } else if (MI.isDebugValueList()) {
2233 // We will replace the spilled register with a frame index, so
2234 // immediately deref all references to the spilled register.
2235 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2236 for (const MachineOperand *Op : SpilledOperands) {
2237 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2238 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2239 }
2240 }
2241 return Expr;
2242}
2244 Register SpillReg) {
2245 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2247 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2248 SpillOperands.push_back(&Op);
2249 return computeExprForSpill(MI, SpillOperands);
2250}
2251
2254 const MachineInstr &Orig,
2255 int FrameIndex, Register SpillReg) {
2256 assert(!Orig.isDebugRef() &&
2257 "DBG_INSTR_REF should not reference a virtual register.");
2258 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2259 MachineInstrBuilder NewMI =
2260 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2261 // Non-Variadic Operands: Location, Offset, Variable, Expression
2262 // Variadic Operands: Variable, Expression, Locations...
2263 if (Orig.isNonListDebugValue())
2264 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2265 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2266 if (Orig.isDebugValueList()) {
2267 for (const MachineOperand &Op : Orig.debug_operands())
2268 if (Op.isReg() && Op.getReg() == SpillReg)
2269 NewMI.addFrameIndex(FrameIndex);
2270 else
2271 NewMI.add(MachineOperand(Op));
2272 }
2273 return NewMI;
2274}
2277 const MachineInstr &Orig, int FrameIndex,
2278 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2279 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2280 MachineInstrBuilder NewMI =
2281 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2282 // Non-Variadic Operands: Location, Offset, Variable, Expression
2283 // Variadic Operands: Variable, Expression, Locations...
2284 if (Orig.isNonListDebugValue())
2285 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2286 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2287 if (Orig.isDebugValueList()) {
2288 for (const MachineOperand &Op : Orig.debug_operands())
2289 if (is_contained(SpilledOperands, &Op))
2290 NewMI.addFrameIndex(FrameIndex);
2291 else
2292 NewMI.add(MachineOperand(Op));
2293 }
2294 return NewMI;
2295}
2296
2298 Register Reg) {
2299 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2300 if (Orig.isNonListDebugValue())
2302 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2303 Op.ChangeToFrameIndex(FrameIndex);
2304 Orig.getDebugExpressionOp().setMetadata(Expr);
2305}
2306
2309 MachineInstr &MI = *this;
2310 if (!MI.getOperand(0).isReg())
2311 return;
2312
2314 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2315 DI != DE; ++DI) {
2316 if (!DI->isDebugValue())
2317 return;
2318 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2319 DbgValues.push_back(&*DI);
2320 }
2321}
2322
2324 // Collect matching debug values.
2326
2327 if (!getOperand(0).isReg())
2328 return;
2329
2330 Register DefReg = getOperand(0).getReg();
2331 auto *MRI = getRegInfo();
2332 for (auto &MO : MRI->use_operands(DefReg)) {
2333 auto *DI = MO.getParent();
2334 if (!DI->isDebugValue())
2335 continue;
2336 if (DI->hasDebugOperandForReg(DefReg)) {
2337 DbgValues.push_back(DI);
2338 }
2339 }
2340
2341 // Propagate Reg to debug value instructions.
2342 for (auto *DBI : DbgValues)
2343 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2344 Op.setReg(Reg);
2345}
2346
2348
2349static unsigned getSpillSlotSize(const MMOList &Accesses,
2350 const MachineFrameInfo &MFI) {
2351 unsigned Size = 0;
2352 for (const auto *A : Accesses)
2353 if (MFI.isSpillSlotObjectIndex(
2354 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2355 ->getFrameIndex()))
2356 Size += A->getSize();
2357 return Size;
2358}
2359
2360std::optional<unsigned>
2362 int FI;
2363 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2364 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2365 if (MFI.isSpillSlotObjectIndex(FI))
2366 return (*memoperands_begin())->getSize();
2367 }
2368 return std::nullopt;
2369}
2370
2371std::optional<unsigned>
2373 MMOList Accesses;
2374 if (TII->hasStoreToStackSlot(*this, Accesses))
2375 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2376 return std::nullopt;
2377}
2378
2379std::optional<unsigned>
2381 int FI;
2382 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2383 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2384 if (MFI.isSpillSlotObjectIndex(FI))
2385 return (*memoperands_begin())->getSize();
2386 }
2387 return std::nullopt;
2388}
2389
2390std::optional<unsigned>
2392 MMOList Accesses;
2393 if (TII->hasLoadFromStackSlot(*this, Accesses))
2394 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2395 return std::nullopt;
2396}
2397
2399 if (DebugInstrNum == 0)
2400 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2401 return DebugInstrNum;
2402}
2403
2405 if (DebugInstrNum == 0)
2406 DebugInstrNum = MF.getNewDebugInstrNum();
2407 return DebugInstrNum;
2408}
2409
2410std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2411 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2412 getRegInfo()->getType(getOperand(1).getReg()));
2413}
2414
2415std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2416 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2417 getRegInfo()->getType(getOperand(1).getReg()),
2418 getRegInfo()->getType(getOperand(2).getReg()));
2419}
2420
2421std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2422 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2423 getRegInfo()->getType(getOperand(1).getReg()),
2424 getRegInfo()->getType(getOperand(2).getReg()),
2425 getRegInfo()->getType(getOperand(3).getReg()));
2426}
2427
2428std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2429 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2430 getRegInfo()->getType(getOperand(1).getReg()),
2431 getRegInfo()->getType(getOperand(2).getReg()),
2432 getRegInfo()->getType(getOperand(3).getReg()),
2433 getRegInfo()->getType(getOperand(4).getReg()));
2434}
2435
2436std::tuple<Register, LLT, Register, LLT>
2438 Register Reg0 = getOperand(0).getReg();
2439 Register Reg1 = getOperand(1).getReg();
2440 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2441 getRegInfo()->getType(Reg1));
2442}
2443
2444std::tuple<Register, LLT, Register, LLT, Register, LLT>
2446 Register Reg0 = getOperand(0).getReg();
2447 Register Reg1 = getOperand(1).getReg();
2448 Register Reg2 = getOperand(2).getReg();
2449 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2450 getRegInfo()->getType(Reg1), Reg2,
2451 getRegInfo()->getType(Reg2));
2452}
2453
2454std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2456 Register Reg0 = getOperand(0).getReg();
2457 Register Reg1 = getOperand(1).getReg();
2458 Register Reg2 = getOperand(2).getReg();
2459 Register Reg3 = getOperand(3).getReg();
2460 return std::tuple(
2461 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2462 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));
2463}
2464
2466 LLT>
2468 Register Reg0 = getOperand(0).getReg();
2469 Register Reg1 = getOperand(1).getReg();
2470 Register Reg2 = getOperand(2).getReg();
2471 Register Reg3 = getOperand(3).getReg();
2472 Register Reg4 = getOperand(4).getReg();
2473 return std::tuple(
2474 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2475 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),
2476 Reg4, getRegInfo()->getType(Reg4));
2477}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
This file contains the declarations for the subclasses of Constant, which represent the different fla...
uint64_t Size
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
const unsigned TiedMax
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
This file contains the declarations for metadata subclasses.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
Value * RHS
Value * LHS
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
DWARF expression.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
A debug info location.
Definition: DebugLoc.h:33
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:170
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
static StringRef getMemConstraintName(ConstraintCode C)
Definition: InlineAsm.h:437
constexpr bool isValid() const
Definition: LowLevelType.h:137
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:338
unsigned short Opcode
Definition: MCInstrDesc.h:205
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:261
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:950
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1303
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1309
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:584
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isPosition() const
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:939
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:681
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:326
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:839
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:862
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:389
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:851
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:915
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:376
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:549
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:546
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:786
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:781
bool isDebugRef() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:451
std::optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
std::tuple< LLT, LLT > getFirst2LLTs() const
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:829
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:540
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:792
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:398
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:630
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:659
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:774
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
std::optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
std::optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:756
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
std::optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:383
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:472
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:795
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:477
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:562
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:673
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:455
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:819
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:371
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:807
void unbundleFromSucc()
Break bundle below this instruction.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:612
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
bool isKill() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:883
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
uint64_t getSize() const
Return the size in bytes of the memory reference.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4883
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:873
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:262
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:75
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:129
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
SmallBitVector & set()
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:345
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:366
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:451
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void reserve(size_type N)
Definition: SmallVector.h:667
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:171
MI-level Statepoint operands.
Definition: StackMaps.h:158
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
LLVM Value Representation.
Definition: Value.h:74
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Iterator for intrusive lists based on ilist_node.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:173
constexpr double e
Definition: MathExtras.h:31
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:330
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1741
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
@ Other
Any other memory.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1854
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1884
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:491
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
#define N
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
static unsigned getHashValue(const MachineInstr *const &MI)