LLVM  14.0.0git
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Analysis/Loads.h"
37 #include "llvm/CodeGen/StackMaps.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/InstrTypes.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Module.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/Value.h"
57 #include "llvm/MC/MCInstrDesc.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/Compiler.h"
63 #include "llvm/Support/Debug.h"
71 #include <algorithm>
72 #include <cassert>
73 #include <cstddef>
74 #include <cstdint>
75 #include <cstring>
76 #include <iterator>
77 #include <utility>
78 
79 using namespace llvm;
80 
82  if (const MachineBasicBlock *MBB = MI.getParent())
83  if (const MachineFunction *MF = MBB->getParent())
84  return MF;
85  return nullptr;
86 }
87 
88 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 // it.
90 static void tryToGetTargetInfo(const MachineInstr &MI,
91  const TargetRegisterInfo *&TRI,
92  const MachineRegisterInfo *&MRI,
93  const TargetIntrinsicInfo *&IntrinsicInfo,
94  const TargetInstrInfo *&TII) {
95 
96  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97  TRI = MF->getSubtarget().getRegisterInfo();
98  MRI = &MF->getRegInfo();
99  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100  TII = MF->getSubtarget().getInstrInfo();
101  }
102 }
103 
105  if (MCID->ImplicitDefs)
106  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107  ++ImpDefs)
108  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109  if (MCID->ImplicitUses)
110  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111  ++ImpUses)
112  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 }
114 
115 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116 /// implicit operands. It reserves space for the number of operands specified by
117 /// the MCInstrDesc.
118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119  DebugLoc dl, bool NoImp)
120  : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
122 
123  // Reserve space for the expected number of operands.
124  if (unsigned NumOps = MCID->getNumOperands() +
125  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126  CapOperands = OperandCapacity::get(NumOps);
127  Operands = MF.allocateOperandArray(CapOperands);
128  }
129 
130  if (!NoImp)
132 }
133 
134 /// MachineInstr ctor - Copies MachineInstr arg exactly.
135 /// Does not copy the number from debug instruction numbering, to preserve
136 /// uniqueness.
137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138  : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139  DebugInstrNum(0) {
140  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
141 
142  CapOperands = OperandCapacity::get(MI.getNumOperands());
143  Operands = MF.allocateOperandArray(CapOperands);
144 
145  // Copy operands.
146  for (const MachineOperand &MO : MI.operands())
147  addOperand(MF, MO);
148 
149  // Copy all the sensible flags.
150  setFlags(MI.Flags);
151 }
152 
154  MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155 }
156 
157 /// getRegInfo - If this instruction is embedded into a MachineFunction,
158 /// return the MachineRegisterInfo object for the current function, otherwise
159 /// return null.
160 MachineRegisterInfo *MachineInstr::getRegInfo() {
162  return &MBB->getParent()->getRegInfo();
163  return nullptr;
164 }
165 
166 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167 /// this instruction from their respective use lists. This requires that the
168 /// operands already be on their use lists.
169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170  for (MachineOperand &MO : operands())
171  if (MO.isReg())
173 }
174 
175 /// AddRegOperandsToUseLists - Add all of the register operands in
176 /// this instruction from their respective use lists. This requires that the
177 /// operands not be on their use lists yet.
178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179  for (MachineOperand &MO : operands())
180  if (MO.isReg())
182 }
183 
186  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
187  MachineFunction *MF = MBB->getParent();
188  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
189  addOperand(*MF, Op);
190 }
191 
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193 /// ranges. If MRI is non-null also update use-def chains.
195  unsigned NumOps, MachineRegisterInfo *MRI) {
196  if (MRI)
197  return MRI->moveOperands(Dst, Src, NumOps);
198  // MachineOperand is a trivially copyable type so we can just use memmove.
199  assert(Dst && Src && "Unknown operands");
200  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201 }
202 
203 /// addOperand - Add the specified operand to the instruction. If it is an
204 /// implicit operand, it is added to the end of the operand list. If it is
205 /// an explicit operand it is added at the end of the explicit operand list
206 /// (before the first implicit operand).
208  assert(MCID && "Cannot add operands before providing an instr descriptor");
209 
210  // Check if we're adding one of our existing operands.
211  if (&Op >= Operands && &Op < Operands + NumOperands) {
212  // This is unusual: MI->addOperand(MI->getOperand(i)).
213  // If adding Op requires reallocating or moving existing operands around,
214  // the Op reference could go stale. Support it by copying Op.
215  MachineOperand CopyOp(Op);
216  return addOperand(MF, CopyOp);
217  }
218 
219  // Find the insert location for the new operand. Implicit registers go at
220  // the end, everything else goes before the implicit regs.
221  //
222  // FIXME: Allow mixed explicit and implicit operands on inline asm.
223  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224  // implicit-defs, but they must not be moved around. See the FIXME in
225  // InstrEmitter.cpp.
226  unsigned OpNo = getNumOperands();
227  bool isImpReg = Op.isReg() && Op.isImplicit();
228  if (!isImpReg && !isInlineAsm()) {
229  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230  --OpNo;
231  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
232  }
233  }
234 
235 #ifndef NDEBUG
236  bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237  Op.getType() == MachineOperand::MO_MCSymbol;
238  // OpNo now points as the desired insertion point. Unless this is a variadic
239  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240  // RegMask operands go between the explicit and implicit operands.
241  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
242  OpNo < MCID->getNumOperands() || isDebugOp) &&
243  "Trying to add an operand to a machine instr that is already done!");
244 #endif
245 
246  MachineRegisterInfo *MRI = getRegInfo();
247 
248  // Determine if the Operands array needs to be reallocated.
249  // Save the old capacity and operand array.
250  OperandCapacity OldCap = CapOperands;
251  MachineOperand *OldOperands = Operands;
252  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254  Operands = MF.allocateOperandArray(CapOperands);
255  // Move the operands before the insertion point.
256  if (OpNo)
257  moveOperands(Operands, OldOperands, OpNo, MRI);
258  }
259 
260  // Move the operands following the insertion point.
261  if (OpNo != NumOperands)
262  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263  MRI);
264  ++NumOperands;
265 
266  // Deallocate the old operand array.
267  if (OldOperands != Operands && OldOperands)
268  MF.deallocateOperandArray(OldCap, OldOperands);
269 
270  // Copy Op into place. It still needs to be inserted into the MRI use lists.
271  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272  NewMO->ParentMI = this;
273 
274  // When adding a register operand, tell MRI about it.
275  if (NewMO->isReg()) {
276  // Ensure isOnRegUseList() returns false, regardless of Op's status.
277  NewMO->Contents.Reg.Prev = nullptr;
278  // Ignore existing ties. This is not a property that can be copied.
279  NewMO->TiedTo = 0;
280  // Add the new operand to MRI, but only for instructions in an MBB.
281  if (MRI)
282  MRI->addRegOperandToUseList(NewMO);
283  // The MCID operand information isn't accurate until we start adding
284  // explicit operands. The implicit operands are added first, then the
285  // explicits are inserted before them.
286  if (!isImpReg) {
287  // Tie uses to defs as indicated in MCInstrDesc.
288  if (NewMO->isUse()) {
289  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290  if (DefIdx != -1)
291  tieOperands(DefIdx, OpNo);
292  }
293  // If the register operand is flagged as early, mark the operand as such.
294  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295  NewMO->setIsEarlyClobber(true);
296  }
297  // Ensure debug instructions set debug flag on register uses.
298  if (NewMO->isUse() && isDebugInstr())
299  NewMO->setIsDebug();
300  }
301 }
302 
303 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
304 /// fewer operand than it started with.
305 ///
306 void MachineInstr::RemoveOperand(unsigned OpNo) {
307  assert(OpNo < getNumOperands() && "Invalid operand number");
308  untieRegOperand(OpNo);
309 
310 #ifndef NDEBUG
311  // Moving tied operands would break the ties.
312  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
313  if (Operands[i].isReg())
314  assert(!Operands[i].isTied() && "Cannot move tied operands");
315 #endif
316 
317  MachineRegisterInfo *MRI = getRegInfo();
318  if (MRI && Operands[OpNo].isReg())
319  MRI->removeRegOperandFromUseList(Operands + OpNo);
320 
321  // Don't call the MachineOperand destructor. A lot of this code depends on
322  // MachineOperand having a trivial destructor anyway, and adding a call here
323  // wouldn't make it 'destructor-correct'.
324 
325  if (unsigned N = NumOperands - 1 - OpNo)
326  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
327  --NumOperands;
328 }
329 
330 void MachineInstr::setExtraInfo(MachineFunction &MF,
332  MCSymbol *PreInstrSymbol,
333  MCSymbol *PostInstrSymbol,
334  MDNode *HeapAllocMarker) {
335  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
336  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
337  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
338  int NumPointers =
339  MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
340 
341  // Drop all extra info if there is none.
342  if (NumPointers <= 0) {
343  Info.clear();
344  return;
345  }
346 
347  // If more than one pointer, then store out of line. Store heap alloc markers
348  // out of line because PointerSumType cannot hold more than 4 tag types with
349  // 32-bit pointers.
350  // FIXME: Maybe we should make the symbols in the extra info mutable?
351  else if (NumPointers > 1 || HasHeapAllocMarker) {
352  Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
353  MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
354  return;
355  }
356 
357  // Otherwise store the single pointer inline.
358  if (HasPreInstrSymbol)
359  Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
360  else if (HasPostInstrSymbol)
361  Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
362  else
363  Info.set<EIIK_MMO>(MMOs[0]);
364 }
365 
367  if (memoperands_empty())
368  return;
369 
370  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
372 }
373 
376  if (MMOs.empty()) {
377  dropMemRefs(MF);
378  return;
379  }
380 
381  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
383 }
384 
386  MachineMemOperand *MO) {
389  MMOs.push_back(MO);
390  setMemRefs(MF, MMOs);
391 }
392 
394  if (this == &MI)
395  // Nothing to do for a self-clone!
396  return;
397 
398  assert(&MF == MI.getMF() &&
399  "Invalid machine functions when cloning memory refrences!");
400  // See if we can just steal the extra info already allocated for the
401  // instruction. We can do this whenever the pre- and post-instruction symbols
402  // are the same (including null).
403  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
404  getPostInstrSymbol() == MI.getPostInstrSymbol() &&
405  getHeapAllocMarker() == MI.getHeapAllocMarker()) {
406  Info = MI.Info;
407  return;
408  }
409 
410  // Otherwise, fall back on a copy-based clone.
411  setMemRefs(MF, MI.memoperands());
412 }
413 
414 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
415 /// identical.
418  if (LHS.size() != RHS.size())
419  return false;
420 
421  auto LHSPointees = make_pointee_range(LHS);
422  auto RHSPointees = make_pointee_range(RHS);
423  return std::equal(LHSPointees.begin(), LHSPointees.end(),
424  RHSPointees.begin());
425 }
426 
429  // Try handling easy numbers of MIs with simpler mechanisms.
430  if (MIs.empty()) {
431  dropMemRefs(MF);
432  return;
433  }
434  if (MIs.size() == 1) {
435  cloneMemRefs(MF, *MIs[0]);
436  return;
437  }
438  // Because an empty memoperands list provides *no* information and must be
439  // handled conservatively (assuming the instruction can do anything), the only
440  // way to merge with it is to drop all other memoperands.
441  if (MIs[0]->memoperands_empty()) {
442  dropMemRefs(MF);
443  return;
444  }
445 
446  // Handle the general case.
448  // Start with the first instruction.
449  assert(&MF == MIs[0]->getMF() &&
450  "Invalid machine functions when cloning memory references!");
451  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
452  // Now walk all the other instructions and accumulate any different MMOs.
453  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
454  assert(&MF == MI.getMF() &&
455  "Invalid machine functions when cloning memory references!");
456 
457  // Skip MIs with identical operands to the first. This is a somewhat
458  // arbitrary hack but will catch common cases without being quadratic.
459  // TODO: We could fully implement merge semantics here if needed.
460  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
461  continue;
462 
463  // Because an empty memoperands list provides *no* information and must be
464  // handled conservatively (assuming the instruction can do anything), the
465  // only way to merge with it is to drop all other memoperands.
466  if (MI.memoperands_empty()) {
467  dropMemRefs(MF);
468  return;
469  }
470 
471  // Otherwise accumulate these into our temporary buffer of the merged state.
472  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
473  }
474 
475  setMemRefs(MF, MergedMMOs);
476 }
477 
479  // Do nothing if old and new symbols are the same.
480  if (Symbol == getPreInstrSymbol())
481  return;
482 
483  // If there was only one symbol and we're removing it, just clear info.
484  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
485  Info.clear();
486  return;
487  }
488 
489  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
491 }
492 
494  // Do nothing if old and new symbols are the same.
495  if (Symbol == getPostInstrSymbol())
496  return;
497 
498  // If there was only one symbol and we're removing it, just clear info.
499  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
500  Info.clear();
501  return;
502  }
503 
504  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
506 }
507 
509  // Do nothing if old and new symbols are the same.
510  if (Marker == getHeapAllocMarker())
511  return;
512 
513  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
514  Marker);
515 }
516 
518  const MachineInstr &MI) {
519  if (this == &MI)
520  // Nothing to do for a self-clone!
521  return;
522 
523  assert(&MF == MI.getMF() &&
524  "Invalid machine functions when cloning instruction symbols!");
525 
526  setPreInstrSymbol(MF, MI.getPreInstrSymbol());
527  setPostInstrSymbol(MF, MI.getPostInstrSymbol());
528  setHeapAllocMarker(MF, MI.getHeapAllocMarker());
529 }
530 
532  // For now, the just return the union of the flags. If the flags get more
533  // complicated over time, we might need more logic here.
534  return getFlags() | Other.getFlags();
535 }
536 
538  uint16_t MIFlags = 0;
539  // Copy the wrapping flags.
540  if (const OverflowingBinaryOperator *OB =
541  dyn_cast<OverflowingBinaryOperator>(&I)) {
542  if (OB->hasNoSignedWrap())
543  MIFlags |= MachineInstr::MIFlag::NoSWrap;
544  if (OB->hasNoUnsignedWrap())
545  MIFlags |= MachineInstr::MIFlag::NoUWrap;
546  }
547 
548  // Copy the exact flag.
549  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
550  if (PE->isExact())
551  MIFlags |= MachineInstr::MIFlag::IsExact;
552 
553  // Copy the fast-math flags.
554  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
555  const FastMathFlags Flags = FP->getFastMathFlags();
556  if (Flags.noNaNs())
557  MIFlags |= MachineInstr::MIFlag::FmNoNans;
558  if (Flags.noInfs())
559  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
560  if (Flags.noSignedZeros())
561  MIFlags |= MachineInstr::MIFlag::FmNsz;
562  if (Flags.allowReciprocal())
563  MIFlags |= MachineInstr::MIFlag::FmArcp;
564  if (Flags.allowContract())
565  MIFlags |= MachineInstr::MIFlag::FmContract;
566  if (Flags.approxFunc())
567  MIFlags |= MachineInstr::MIFlag::FmAfn;
568  if (Flags.allowReassoc())
569  MIFlags |= MachineInstr::MIFlag::FmReassoc;
570  }
571 
572  return MIFlags;
573 }
574 
576  Flags = copyFlagsFromInstruction(I);
577 }
578 
579 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
580  assert(!isBundledWithPred() && "Must be called on bundle header");
582  if (MII->getDesc().getFlags() & Mask) {
583  if (Type == AnyInBundle)
584  return true;
585  } else {
586  if (Type == AllInBundle && !MII->isBundle())
587  return false;
588  }
589  // This was the last instruction in the bundle.
590  if (!MII->isBundledWithSucc())
591  return Type == AllInBundle;
592  }
593 }
594 
596  MICheckType Check) const {
597  // If opcodes or number of operands are not the same then the two
598  // instructions are obviously not identical.
599  if (Other.getOpcode() != getOpcode() ||
600  Other.getNumOperands() != getNumOperands())
601  return false;
602 
603  if (isBundle()) {
604  // We have passed the test above that both instructions have the same
605  // opcode, so we know that both instructions are bundles here. Let's compare
606  // MIs inside the bundle.
607  assert(Other.isBundle() && "Expected that both instructions are bundles.");
610  // Loop until we analysed the last intruction inside at least one of the
611  // bundles.
612  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
613  ++I1;
614  ++I2;
615  if (!I1->isIdenticalTo(*I2, Check))
616  return false;
617  }
618  // If we've reached the end of just one of the two bundles, but not both,
619  // the instructions are not identical.
620  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
621  return false;
622  }
623 
624  // Check operands to make sure they match.
625  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
626  const MachineOperand &MO = getOperand(i);
627  const MachineOperand &OMO = Other.getOperand(i);
628  if (!MO.isReg()) {
629  if (!MO.isIdenticalTo(OMO))
630  return false;
631  continue;
632  }
633 
634  // Clients may or may not want to ignore defs when testing for equality.
635  // For example, machine CSE pass only cares about finding common
636  // subexpressions, so it's safe to ignore virtual register defs.
637  if (MO.isDef()) {
638  if (Check == IgnoreDefs)
639  continue;
640  else if (Check == IgnoreVRegDefs) {
641  if (!Register::isVirtualRegister(MO.getReg()) ||
643  if (!MO.isIdenticalTo(OMO))
644  return false;
645  } else {
646  if (!MO.isIdenticalTo(OMO))
647  return false;
648  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
649  return false;
650  }
651  } else {
652  if (!MO.isIdenticalTo(OMO))
653  return false;
654  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
655  return false;
656  }
657  }
658  // If DebugLoc does not match then two debug instructions are not identical.
659  if (isDebugInstr())
660  if (getDebugLoc() && Other.getDebugLoc() &&
661  getDebugLoc() != Other.getDebugLoc())
662  return false;
663  return true;
664 }
665 
667  return getParent()->getParent();
668 }
669 
671  assert(getParent() && "Not embedded in a basic block!");
672  return getParent()->remove(this);
673 }
674 
676  assert(getParent() && "Not embedded in a basic block!");
677  return getParent()->remove_instr(this);
678 }
679 
681  assert(getParent() && "Not embedded in a basic block!");
682  getParent()->erase(this);
683 }
684 
686  assert(getParent() && "Not embedded in a basic block!");
688  MachineFunction *MF = MBB->getParent();
689  assert(MF && "Not embedded in a function!");
690 
691  MachineInstr *MI = (MachineInstr *)this;
693 
694  for (const MachineOperand &MO : MI->operands()) {
695  if (!MO.isReg() || !MO.isDef())
696  continue;
697  Register Reg = MO.getReg();
698  if (!Reg.isVirtual())
699  continue;
701  }
702  MI->eraseFromParent();
703 }
704 
706  assert(getParent() && "Not embedded in a basic block!");
707  getParent()->erase_instr(this);
708 }
709 
711  if (!isCall(Type))
712  return false;
713  switch (getOpcode()) {
714  case TargetOpcode::PATCHPOINT:
715  case TargetOpcode::STACKMAP:
716  case TargetOpcode::STATEPOINT:
717  case TargetOpcode::FENTRY_CALL:
718  return false;
719  }
720  return true;
721 }
722 
724  if (isBundle())
727 }
728 
730  unsigned NumOperands = MCID->getNumOperands();
731  if (!MCID->isVariadic())
732  return NumOperands;
733 
734  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
735  const MachineOperand &MO = getOperand(I);
736  // The operands must always be in the following order:
737  // - explicit reg defs,
738  // - other explicit operands (reg uses, immediates, etc.),
739  // - implicit reg defs
740  // - implicit reg uses
741  if (MO.isReg() && MO.isImplicit())
742  break;
743  ++NumOperands;
744  }
745  return NumOperands;
746 }
747 
749  unsigned NumDefs = MCID->getNumDefs();
750  if (!MCID->isVariadic())
751  return NumDefs;
752 
753  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
754  const MachineOperand &MO = getOperand(I);
755  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
756  break;
757  ++NumDefs;
758  }
759  return NumDefs;
760 }
761 
763  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
766  --Pred;
767  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
768  Pred->setFlag(BundledSucc);
769 }
770 
772  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
775  ++Succ;
776  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
777  Succ->setFlag(BundledPred);
778 }
779 
781  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
784  --Pred;
785  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
786  Pred->clearFlag(BundledSucc);
787 }
788 
790  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
793  ++Succ;
794  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
795  Succ->clearFlag(BundledPred);
796 }
797 
799  if (isInlineAsm()) {
800  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
801  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
802  return true;
803  }
804  return false;
805 }
806 
808  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
809  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
810  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
811 }
812 
814  unsigned *GroupNo) const {
815  assert(isInlineAsm() && "Expected an inline asm instruction");
816  assert(OpIdx < getNumOperands() && "OpIdx out of range");
817 
818  // Ignore queries about the initial operands.
819  if (OpIdx < InlineAsm::MIOp_FirstOperand)
820  return -1;
821 
822  unsigned Group = 0;
823  unsigned NumOps;
824  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
825  i += NumOps) {
826  const MachineOperand &FlagMO = getOperand(i);
827  // If we reach the implicit register operands, stop looking.
828  if (!FlagMO.isImm())
829  return -1;
830  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
831  if (i + NumOps > OpIdx) {
832  if (GroupNo)
833  *GroupNo = Group;
834  return i;
835  }
836  ++Group;
837  }
838  return -1;
839 }
840 
842  assert(isDebugLabel() && "not a DBG_LABEL");
843  return cast<DILabel>(getOperand(0).getMetadata());
844 }
845 
847  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
848  unsigned VariableOp = isDebugValueList() ? 0 : 2;
849  return getOperand(VariableOp);
850 }
851 
853  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
854  unsigned VariableOp = isDebugValueList() ? 0 : 2;
855  return getOperand(VariableOp);
856 }
857 
859  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
860 }
861 
863  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
864  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
865  return getOperand(ExpressionOp);
866 }
867 
869  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
870  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
871  return getOperand(ExpressionOp);
872 }
873 
875  return cast<DIExpression>(getDebugExpressionOp().getMetadata());
876 }
877 
880 }
881 
882 const TargetRegisterClass*
884  const TargetInstrInfo *TII,
885  const TargetRegisterInfo *TRI) const {
886  assert(getParent() && "Can't have an MBB reference here!");
887  assert(getMF() && "Can't have an MF reference here!");
888  const MachineFunction &MF = *getMF();
889 
890  // Most opcodes have fixed constraints in their MCInstrDesc.
891  if (!isInlineAsm())
892  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
893 
894  if (!getOperand(OpIdx).isReg())
895  return nullptr;
896 
897  // For tied uses on inline asm, get the constraint from the def.
898  unsigned DefIdx;
899  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
900  OpIdx = DefIdx;
901 
902  // Inline asm stores register class constraints in the flag word.
903  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
904  if (FlagIdx < 0)
905  return nullptr;
906 
907  unsigned Flag = getOperand(FlagIdx).getImm();
908  unsigned RCID;
913  return TRI->getRegClass(RCID);
914 
915  // Assume that all registers in a memory operand are pointers.
917  return TRI->getPointerRegClass(MF);
918 
919  return nullptr;
920 }
921 
923  Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
924  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
925  // Check every operands inside the bundle if we have
926  // been asked to.
927  if (ExploreBundle)
928  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
929  ++OpndIt)
930  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
931  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
932  else
933  // Otherwise, just check the current operands.
934  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
935  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
936  return CurRC;
937 }
938 
939 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
940  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
941  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
942  assert(CurRC && "Invalid initial register class");
943  // Check if Reg is constrained by some of its use/def from MI.
944  const MachineOperand &MO = getOperand(OpIdx);
945  if (!MO.isReg() || MO.getReg() != Reg)
946  return CurRC;
947  // If yes, accumulate the constraints through the operand.
948  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
949 }
950 
952  unsigned OpIdx, const TargetRegisterClass *CurRC,
953  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
954  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
955  const MachineOperand &MO = getOperand(OpIdx);
956  assert(MO.isReg() &&
957  "Cannot get register constraints for non-register operand");
958  assert(CurRC && "Invalid initial register class");
959  if (unsigned SubIdx = MO.getSubReg()) {
960  if (OpRC)
961  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
962  else
963  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
964  } else if (OpRC)
965  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
966  return CurRC;
967 }
968 
969 /// Return the number of instructions inside the MI bundle, not counting the
970 /// header instruction.
971 unsigned MachineInstr::getBundleSize() const {
973  unsigned Size = 0;
974  while (I->isBundledWithSucc()) {
975  ++Size;
976  ++I;
977  }
978  return Size;
979 }
980 
981 /// Returns true if the MachineInstr has an implicit-use operand of exactly
982 /// the given register (not considering sub/super-registers).
984  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
985  const MachineOperand &MO = getOperand(i);
986  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
987  return true;
988  }
989  return false;
990 }
991 
992 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
993 /// the specific register or -1 if it is not found. It further tightens
994 /// the search criteria to a use that kills the register if isKill is true.
996  Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
997  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
998  const MachineOperand &MO = getOperand(i);
999  if (!MO.isReg() || !MO.isUse())
1000  continue;
1001  Register MOReg = MO.getReg();
1002  if (!MOReg)
1003  continue;
1004  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1005  if (!isKill || MO.isKill())
1006  return i;
1007  }
1008  return -1;
1009 }
1010 
1011 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1012 /// indicating if this instruction reads or writes Reg. This also considers
1013 /// partial defines.
1014 std::pair<bool,bool>
1016  SmallVectorImpl<unsigned> *Ops) const {
1017  bool PartDef = false; // Partial redefine.
1018  bool FullDef = false; // Full define.
1019  bool Use = false;
1020 
1021  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1022  const MachineOperand &MO = getOperand(i);
1023  if (!MO.isReg() || MO.getReg() != Reg)
1024  continue;
1025  if (Ops)
1026  Ops->push_back(i);
1027  if (MO.isUse())
1028  Use |= !MO.isUndef();
1029  else if (MO.getSubReg() && !MO.isUndef())
1030  // A partial def undef doesn't count as reading the register.
1031  PartDef = true;
1032  else
1033  FullDef = true;
1034  }
1035  // A partial redefine uses Reg unless there is also a full define.
1036  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1037 }
1038 
1039 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1040 /// the specified register or -1 if it is not found. If isDead is true, defs
1041 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1042 /// also checks if there is a def of a super-register.
1043 int
1045  const TargetRegisterInfo *TRI) const {
1046  bool isPhys = Register::isPhysicalRegister(Reg);
1047  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1048  const MachineOperand &MO = getOperand(i);
1049  // Accept regmask operands when Overlap is set.
1050  // Ignore them when looking for a specific def operand (Overlap == false).
1051  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1052  return i;
1053  if (!MO.isReg() || !MO.isDef())
1054  continue;
1055  Register MOReg = MO.getReg();
1056  bool Found = (MOReg == Reg);
1057  if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1058  if (Overlap)
1059  Found = TRI->regsOverlap(MOReg, Reg);
1060  else
1061  Found = TRI->isSubRegister(MOReg, Reg);
1062  }
1063  if (Found && (!isDead || MO.isDead()))
1064  return i;
1065  }
1066  return -1;
1067 }
1068 
1069 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1070 /// operand list that is used to represent the predicate. It returns -1 if
1071 /// none is found.
1073  // Don't call MCID.findFirstPredOperandIdx() because this variant
1074  // is sometimes called on an instruction that's not yet complete, and
1075  // so the number of operands is less than the MCID indicates. In
1076  // particular, the PTX target does this.
1077  const MCInstrDesc &MCID = getDesc();
1078  if (MCID.isPredicable()) {
1079  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1080  if (MCID.OpInfo[i].isPredicate())
1081  return i;
1082  }
1083 
1084  return -1;
1085 }
1086 
1087 // MachineOperand::TiedTo is 4 bits wide.
1088 const unsigned TiedMax = 15;
1089 
1090 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1091 ///
1092 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1093 /// field. TiedTo can have these values:
1094 ///
1095 /// 0: Operand is not tied to anything.
1096 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1097 /// TiedMax: Tied to an operand >= TiedMax-1.
1098 ///
1099 /// The tied def must be one of the first TiedMax operands on a normal
1100 /// instruction. INLINEASM instructions allow more tied defs.
1101 ///
1102 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1103  MachineOperand &DefMO = getOperand(DefIdx);
1104  MachineOperand &UseMO = getOperand(UseIdx);
1105  assert(DefMO.isDef() && "DefIdx must be a def operand");
1106  assert(UseMO.isUse() && "UseIdx must be a use operand");
1107  assert(!DefMO.isTied() && "Def is already tied to another use");
1108  assert(!UseMO.isTied() && "Use is already tied to another def");
1109 
1110  if (DefIdx < TiedMax)
1111  UseMO.TiedTo = DefIdx + 1;
1112  else {
1113  // Inline asm can use the group descriptors to find tied operands,
1114  // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1115  // but on normal instruction, the tied def must be within the first TiedMax
1116  // operands.
1117  assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1118  "DefIdx out of range");
1119  UseMO.TiedTo = TiedMax;
1120  }
1121 
1122  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1123  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1124 }
1125 
1126 /// Given the index of a tied register operand, find the operand it is tied to.
1127 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1128 /// which must exist.
1129 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1130  const MachineOperand &MO = getOperand(OpIdx);
1131  assert(MO.isTied() && "Operand isn't tied");
1132 
1133  // Normally TiedTo is in range.
1134  if (MO.TiedTo < TiedMax)
1135  return MO.TiedTo - 1;
1136 
1137  // Uses on normal instructions can be out of range.
1138  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1139  // Normal tied defs must be in the 0..TiedMax-1 range.
1140  if (MO.isUse())
1141  return TiedMax - 1;
1142  // MO is a def. Search for the tied use.
1143  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1144  const MachineOperand &UseMO = getOperand(i);
1145  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1146  return i;
1147  }
1148  llvm_unreachable("Can't find tied use");
1149  }
1150 
1151  if (getOpcode() == TargetOpcode::STATEPOINT) {
1152  // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1153  // on registers.
1154  StatepointOpers SO(this);
1155  unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1156  assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1157  unsigned NumDefs = getNumDefs();
1158  for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1159  while (!getOperand(CurUseIdx).isReg())
1160  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1161  if (OpIdx == CurDefIdx)
1162  return CurUseIdx;
1163  if (OpIdx == CurUseIdx)
1164  return CurDefIdx;
1165  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1166  }
1167  llvm_unreachable("Can't find tied use");
1168  }
1169 
1170  // Now deal with inline asm by parsing the operand group descriptor flags.
1171  // Find the beginning of each operand group.
1172  SmallVector<unsigned, 8> GroupIdx;
1173  unsigned OpIdxGroup = ~0u;
1174  unsigned NumOps;
1175  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1176  i += NumOps) {
1177  const MachineOperand &FlagMO = getOperand(i);
1178  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1179  unsigned CurGroup = GroupIdx.size();
1180  GroupIdx.push_back(i);
1181  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1182  // OpIdx belongs to this operand group.
1183  if (OpIdx > i && OpIdx < i + NumOps)
1184  OpIdxGroup = CurGroup;
1185  unsigned TiedGroup;
1186  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1187  continue;
1188  // Operands in this group are tied to operands in TiedGroup which must be
1189  // earlier. Find the number of operands between the two groups.
1190  unsigned Delta = i - GroupIdx[TiedGroup];
1191 
1192  // OpIdx is a use tied to TiedGroup.
1193  if (OpIdxGroup == CurGroup)
1194  return OpIdx - Delta;
1195 
1196  // OpIdx is a def tied to this use group.
1197  if (OpIdxGroup == TiedGroup)
1198  return OpIdx + Delta;
1199  }
1200  llvm_unreachable("Invalid tied operand on inline asm");
1201 }
1202 
1203 /// clearKillInfo - Clears kill flags on all operands.
1204 ///
1206  for (MachineOperand &MO : operands()) {
1207  if (MO.isReg() && MO.isUse())
1208  MO.setIsKill(false);
1209  }
1210 }
1211 
1213  unsigned SubIdx,
1214  const TargetRegisterInfo &RegInfo) {
1215  if (Register::isPhysicalRegister(ToReg)) {
1216  if (SubIdx)
1217  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1218  for (MachineOperand &MO : operands()) {
1219  if (!MO.isReg() || MO.getReg() != FromReg)
1220  continue;
1221  MO.substPhysReg(ToReg, RegInfo);
1222  }
1223  } else {
1224  for (MachineOperand &MO : operands()) {
1225  if (!MO.isReg() || MO.getReg() != FromReg)
1226  continue;
1227  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1228  }
1229  }
1230 }
1231 
1232 /// isSafeToMove - Return true if it is safe to move this instruction. If
1233 /// SawStore is set to true, it means that there is a store (or call) between
1234 /// the instruction's location and its intended destination.
1235 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1236  // Ignore stuff that we obviously can't move.
1237  //
1238  // Treat volatile loads as stores. This is not strictly necessary for
1239  // volatiles, but it is required for atomic loads. It is not allowed to move
1240  // a load across an atomic load with Ordering > Monotonic.
1241  if (mayStore() || isCall() || isPHI() ||
1242  (mayLoad() && hasOrderedMemoryRef())) {
1243  SawStore = true;
1244  return false;
1245  }
1246 
1247  if (isPosition() || isDebugInstr() || isTerminator() ||
1249  return false;
1250 
1251  // See if this instruction does a load. If so, we have to guarantee that the
1252  // loaded value doesn't change between the load and the its intended
1253  // destination. The check for isInvariantLoad gives the target the chance to
1254  // classify the load as always returning a constant, e.g. a constant pool
1255  // load.
1257  // Otherwise, this is a real load. If there is a store between the load and
1258  // end of block, we can't move it.
1259  return !SawStore;
1260 
1261  return true;
1262 }
1263 
1265  bool UseTBAA, const MachineMemOperand *MMOa,
1266  const MachineMemOperand *MMOb) {
1267  // The following interface to AA is fashioned after DAGCombiner::isAlias and
1268  // operates with MachineMemOperand offset with some important assumptions:
1269  // - LLVM fundamentally assumes flat address spaces.
1270  // - MachineOperand offset can *only* result from legalization and cannot
1271  // affect queries other than the trivial case of overlap checking.
1272  // - These offsets never wrap and never step outside of allocated objects.
1273  // - There should never be any negative offsets here.
1274  //
1275  // FIXME: Modify API to hide this math from "user"
1276  // Even before we go to AA we can reason locally about some memory objects. It
1277  // can save compile time, and possibly catch some corner cases not currently
1278  // covered.
1279 
1280  int64_t OffsetA = MMOa->getOffset();
1281  int64_t OffsetB = MMOb->getOffset();
1282  int64_t MinOffset = std::min(OffsetA, OffsetB);
1283 
1284  uint64_t WidthA = MMOa->getSize();
1285  uint64_t WidthB = MMOb->getSize();
1286  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1287  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1288 
1289  const Value *ValA = MMOa->getValue();
1290  const Value *ValB = MMOb->getValue();
1291  bool SameVal = (ValA && ValB && (ValA == ValB));
1292  if (!SameVal) {
1293  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1294  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1295  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1296  return false;
1297  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1298  return false;
1299  if (PSVa && PSVb && (PSVa == PSVb))
1300  SameVal = true;
1301  }
1302 
1303  if (SameVal) {
1304  if (!KnownWidthA || !KnownWidthB)
1305  return true;
1306  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1307  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1308  return (MinOffset + LowWidth > MaxOffset);
1309  }
1310 
1311  if (!AA)
1312  return true;
1313 
1314  if (!ValA || !ValB)
1315  return true;
1316 
1317  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1318  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1319 
1320  int64_t OverlapA =
1321  KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1322  int64_t OverlapB =
1323  KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1324 
1325  return !AA->isNoAlias(
1326  MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1327  MemoryLocation(ValB, OverlapB,
1328  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1329 }
1330 
1332  bool UseTBAA) const {
1333  const MachineFunction *MF = getMF();
1334  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1335  const MachineFrameInfo &MFI = MF->getFrameInfo();
1336 
1337  // Exclude call instruction which may alter the memory but can not be handled
1338  // by this function.
1339  if (isCall() || Other.isCall())
1340  return true;
1341 
1342  // If neither instruction stores to memory, they can't alias in any
1343  // meaningful way, even if they read from the same address.
1344  if (!mayStore() && !Other.mayStore())
1345  return false;
1346 
1347  // Both instructions must be memory operations to be able to alias.
1348  if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1349  return false;
1350 
1351  // Let the target decide if memory accesses cannot possibly overlap.
1353  return false;
1354 
1355  // Memory operations without memory operands may access anything. Be
1356  // conservative and assume `MayAlias`.
1357  if (memoperands_empty() || Other.memoperands_empty())
1358  return true;
1359 
1360  // Skip if there are too many memory operands.
1361  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1362  if (NumChecks > TII->getMemOperandAACheckLimit())
1363  return true;
1364 
1365  // Check each pair of memory operands from both instructions, which can't
1366  // alias only if all pairs won't alias.
1367  for (auto *MMOa : memoperands())
1368  for (auto *MMOb : Other.memoperands())
1369  if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1370  return true;
1371 
1372  return false;
1373 }
1374 
1375 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1376 /// or volatile memory reference, or if the information describing the memory
1377 /// reference is not available. Return false if it is known to have no ordered
1378 /// memory references.
1380  // An instruction known never to access memory won't have a volatile access.
1381  if (!mayStore() &&
1382  !mayLoad() &&
1383  !isCall() &&
1385  return false;
1386 
1387  // Otherwise, if the instruction has no memory reference information,
1388  // conservatively assume it wasn't preserved.
1389  if (memoperands_empty())
1390  return true;
1391 
1392  // Check if any of our memory operands are ordered.
1393  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1394  return !MMO->isUnordered();
1395  });
1396 }
1397 
1398 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1399 /// trap and is loading from a location whose value is invariant across a run of
1400 /// this function.
1402  // If the instruction doesn't load at all, it isn't an invariant load.
1403  if (!mayLoad())
1404  return false;
1405 
1406  // If the instruction has lost its memoperands, conservatively assume that
1407  // it may not be an invariant load.
1408  if (memoperands_empty())
1409  return false;
1410 
1411  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1412 
1413  for (MachineMemOperand *MMO : memoperands()) {
1414  if (!MMO->isUnordered())
1415  // If the memory operand has ordering side effects, we can't move the
1416  // instruction. Such an instruction is technically an invariant load,
1417  // but the caller code would need updated to expect that.
1418  return false;
1419  if (MMO->isStore()) return false;
1420  if (MMO->isInvariant() && MMO->isDereferenceable())
1421  continue;
1422 
1423  // A load from a constant PseudoSourceValue is invariant.
1424  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1425  if (PSV->isConstant(&MFI))
1426  continue;
1427 
1428  if (const Value *V = MMO->getValue()) {
1429  // If we have an AliasAnalysis, ask it whether the memory is constant.
1430  if (AA &&
1432  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1433  continue;
1434  }
1435 
1436  // Otherwise assume conservatively.
1437  return false;
1438  }
1439 
1440  // Everything checks out.
1441  return true;
1442 }
1443 
1444 /// isConstantValuePHI - If the specified instruction is a PHI that always
1445 /// merges together the same virtual register, return the register, otherwise
1446 /// return 0.
1448  if (!isPHI())
1449  return 0;
1450  assert(getNumOperands() >= 3 &&
1451  "It's illegal to have a PHI without source operands");
1452 
1453  Register Reg = getOperand(1).getReg();
1454  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1455  if (getOperand(i).getReg() != Reg)
1456  return 0;
1457  return Reg;
1458 }
1459 
1462  return true;
1463  if (isInlineAsm()) {
1464  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1465  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1466  return true;
1467  }
1468 
1469  return false;
1470 }
1471 
1473  return mayStore() || isCall() ||
1475 }
1476 
1477 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1478 ///
1480  for (const MachineOperand &MO : operands()) {
1481  if (!MO.isReg() || MO.isUse())
1482  continue;
1483  if (!MO.isDead())
1484  return false;
1485  }
1486  return true;
1487 }
1488 
1489 /// copyImplicitOps - Copy implicit register operands from specified
1490 /// instruction to this instruction.
1492  const MachineInstr &MI) {
1493  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1494  i != e; ++i) {
1495  const MachineOperand &MO = MI.getOperand(i);
1496  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1497  addOperand(MF, MO);
1498  }
1499 }
1500 
1502  const MCInstrDesc &MCID = getDesc();
1503  if (MCID.Opcode == TargetOpcode::STATEPOINT)
1504  return true;
1505  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1506  const auto &Operand = getOperand(I);
1507  if (!Operand.isReg() || Operand.isDef())
1508  // Ignore the defined registers as MCID marks only the uses as tied.
1509  continue;
1510  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1511  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1512  if (ExpectedTiedIdx != TiedIdx)
1513  return true;
1514  }
1515  return false;
1516 }
1517 
1518 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1519  const MachineRegisterInfo &MRI) const {
1520  const MachineOperand &Op = getOperand(OpIdx);
1521  if (!Op.isReg())
1522  return LLT{};
1523 
1524  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1525  return MRI.getType(Op.getReg());
1526 
1527  auto &OpInfo = getDesc().OpInfo[OpIdx];
1528  if (!OpInfo.isGenericType())
1529  return MRI.getType(Op.getReg());
1530 
1531  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1532  return LLT{};
1533 
1534  LLT TypeToPrint = MRI.getType(Op.getReg());
1535  // Don't mark the type index printed if it wasn't actually printed: maybe
1536  // another operand with the same type index has an actual type attached:
1537  if (TypeToPrint.isValid())
1538  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1539  return TypeToPrint;
1540 }
1541 
1542 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1544  dbgs() << " ";
1545  print(dbgs());
1546 }
1547 
1548 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1549  const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1550  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1551  if (Depth >= MaxDepth)
1552  return;
1553  if (!AlreadySeenInstrs.insert(this).second)
1554  return;
1555  // PadToColumn always inserts at least one space.
1556  // Don't mess up the alignment if we don't want any space.
1557  if (Depth)
1558  fdbgs().PadToColumn(Depth * 2);
1559  print(fdbgs());
1560  for (const MachineOperand &MO : operands()) {
1561  if (!MO.isReg() || MO.isDef())
1562  continue;
1563  Register Reg = MO.getReg();
1564  if (Reg.isPhysical())
1565  continue;
1566  const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1567  if (NewMI == nullptr)
1568  continue;
1569  NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1570  }
1571 }
1572 
1574  unsigned MaxDepth) const {
1575  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1576  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1577 }
1578 #endif
1579 
1580 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1581  bool SkipDebugLoc, bool AddNewLine,
1582  const TargetInstrInfo *TII) const {
1583  const Module *M = nullptr;
1584  const Function *F = nullptr;
1585  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1586  F = &MF->getFunction();
1587  M = F->getParent();
1588  if (!TII)
1589  TII = MF->getSubtarget().getInstrInfo();
1590  }
1591 
1592  ModuleSlotTracker MST(M);
1593  if (F)
1594  MST.incorporateFunction(*F);
1595  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1596 }
1597 
1599  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1600  bool AddNewLine, const TargetInstrInfo *TII) const {
1601  // We can be a bit tidier if we know the MachineFunction.
1602  const TargetRegisterInfo *TRI = nullptr;
1603  const MachineRegisterInfo *MRI = nullptr;
1604  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1605  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1606 
1607  if (isCFIInstruction())
1608  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1609 
1610  SmallBitVector PrintedTypes(8);
1611  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1612  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1613  if (!ShouldPrintRegisterTies)
1614  return 0U;
1615  const MachineOperand &MO = getOperand(OpIdx);
1616  if (MO.isReg() && MO.isTied() && !MO.isDef())
1617  return findTiedOperandIdx(OpIdx);
1618  return 0U;
1619  };
1620  unsigned StartOp = 0;
1621  unsigned e = getNumOperands();
1622 
1623  // Print explicitly defined operands on the left of an assignment syntax.
1624  while (StartOp < e) {
1625  const MachineOperand &MO = getOperand(StartOp);
1626  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1627  break;
1628 
1629  if (StartOp != 0)
1630  OS << ", ";
1631 
1632  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1633  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1634  MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1635  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1636  ++StartOp;
1637  }
1638 
1639  if (StartOp != 0)
1640  OS << " = ";
1641 
1643  OS << "frame-setup ";
1645  OS << "frame-destroy ";
1647  OS << "nnan ";
1649  OS << "ninf ";
1651  OS << "nsz ";
1653  OS << "arcp ";
1655  OS << "contract ";
1657  OS << "afn ";
1659  OS << "reassoc ";
1661  OS << "nuw ";
1663  OS << "nsw ";
1665  OS << "exact ";
1667  OS << "nofpexcept ";
1669  OS << "nomerge ";
1670 
1671  // Print the opcode name.
1672  if (TII)
1673  OS << TII->getName(getOpcode());
1674  else
1675  OS << "UNKNOWN";
1676 
1677  if (SkipOpers)
1678  return;
1679 
1680  // Print the rest of the operands.
1681  bool FirstOp = true;
1682  unsigned AsmDescOp = ~0u;
1683  unsigned AsmOpCount = 0;
1684 
1686  // Print asm string.
1687  OS << " ";
1688  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1689  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1690  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1691  getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1692  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1693  IntrinsicInfo);
1694 
1695  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1696  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1697  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1698  OS << " [sideeffect]";
1699  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1700  OS << " [mayload]";
1701  if (ExtraInfo & InlineAsm::Extra_MayStore)
1702  OS << " [maystore]";
1703  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1704  OS << " [isconvergent]";
1705  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1706  OS << " [alignstack]";
1708  OS << " [attdialect]";
1710  OS << " [inteldialect]";
1711 
1712  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1713  FirstOp = false;
1714  }
1715 
1716  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1717  const MachineOperand &MO = getOperand(i);
1718 
1719  if (FirstOp) FirstOp = false; else OS << ",";
1720  OS << " ";
1721 
1722  if (isDebugValue() && MO.isMetadata()) {
1723  // Pretty print DBG_VALUE* instructions.
1724  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1725  if (DIV && !DIV->getName().empty())
1726  OS << "!\"" << DIV->getName() << '\"';
1727  else {
1728  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1729  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1730  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1731  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1732  }
1733  } else if (isDebugLabel() && MO.isMetadata()) {
1734  // Pretty print DBG_LABEL instructions.
1735  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1736  if (DIL && !DIL->getName().empty())
1737  OS << "\"" << DIL->getName() << '\"';
1738  else {
1739  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1740  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1741  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1742  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1743  }
1744  } else if (i == AsmDescOp && MO.isImm()) {
1745  // Pretty print the inline asm operand descriptor.
1746  OS << '$' << AsmOpCount++;
1747  unsigned Flag = MO.getImm();
1748  OS << ":[";
1750 
1751  unsigned RCID = 0;
1754  if (TRI) {
1755  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1756  } else
1757  OS << ":RC" << RCID;
1758  }
1759 
1760  if (InlineAsm::isMemKind(Flag)) {
1761  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1762  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1763  }
1764 
1765  unsigned TiedTo = 0;
1767  OS << " tiedto:$" << TiedTo;
1768 
1769  OS << ']';
1770 
1771  // Compute the index of the next operand descriptor.
1772  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1773  } else {
1774  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1775  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1776  if (MO.isImm() && isOperandSubregIdx(i))
1778  else
1779  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1780  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1781  }
1782  }
1783 
1784  // Print any optional symbols attached to this instruction as-if they were
1785  // operands.
1786  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1787  if (!FirstOp) {
1788  FirstOp = false;
1789  OS << ',';
1790  }
1791  OS << " pre-instr-symbol ";
1792  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1793  }
1794  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1795  if (!FirstOp) {
1796  FirstOp = false;
1797  OS << ',';
1798  }
1799  OS << " post-instr-symbol ";
1800  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1801  }
1802  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1803  if (!FirstOp) {
1804  FirstOp = false;
1805  OS << ',';
1806  }
1807  OS << " heap-alloc-marker ";
1808  HeapAllocMarker->printAsOperand(OS, MST);
1809  }
1810 
1811  if (DebugInstrNum) {
1812  if (!FirstOp)
1813  OS << ",";
1814  OS << " debug-instr-number " << DebugInstrNum;
1815  }
1816 
1817  if (!SkipDebugLoc) {
1818  if (const DebugLoc &DL = getDebugLoc()) {
1819  if (!FirstOp)
1820  OS << ',';
1821  OS << " debug-location ";
1822  DL->printAsOperand(OS, MST);
1823  }
1824  }
1825 
1826  if (!memoperands_empty()) {
1828  const LLVMContext *Context = nullptr;
1829  std::unique_ptr<LLVMContext> CtxPtr;
1830  const MachineFrameInfo *MFI = nullptr;
1831  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1832  MFI = &MF->getFrameInfo();
1833  Context = &MF->getFunction().getContext();
1834  } else {
1835  CtxPtr = std::make_unique<LLVMContext>();
1836  Context = CtxPtr.get();
1837  }
1838 
1839  OS << " :: ";
1840  bool NeedComma = false;
1841  for (const MachineMemOperand *Op : memoperands()) {
1842  if (NeedComma)
1843  OS << ", ";
1844  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1845  NeedComma = true;
1846  }
1847  }
1848 
1849  if (SkipDebugLoc)
1850  return;
1851 
1852  bool HaveSemi = false;
1853 
1854  // Print debug location information.
1855  if (const DebugLoc &DL = getDebugLoc()) {
1856  if (!HaveSemi) {
1857  OS << ';';
1858  HaveSemi = true;
1859  }
1860  OS << ' ';
1861  DL.print(OS);
1862  }
1863 
1864  // Print extra comments for DEBUG_VALUE.
1865  if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1866  if (!HaveSemi) {
1867  OS << ";";
1868  HaveSemi = true;
1869  }
1870  auto *DV = getDebugVariable();
1871  OS << " line no:" << DV->getLine();
1872  if (isIndirectDebugValue())
1873  OS << " indirect";
1874  }
1875  // TODO: DBG_LABEL
1876 
1877  if (AddNewLine)
1878  OS << '\n';
1879 }
1880 
1882  const TargetRegisterInfo *RegInfo,
1883  bool AddIfNotFound) {
1884  bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1885  bool hasAliases = isPhysReg &&
1886  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1887  bool Found = false;
1888  SmallVector<unsigned,4> DeadOps;
1889  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1890  MachineOperand &MO = getOperand(i);
1891  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1892  continue;
1893 
1894  // DEBUG_VALUE nodes do not contribute to code generation and should
1895  // always be ignored. Failure to do so may result in trying to modify
1896  // KILL flags on DEBUG_VALUE nodes.
1897  if (MO.isDebug())
1898  continue;
1899 
1900  Register Reg = MO.getReg();
1901  if (!Reg)
1902  continue;
1903 
1904  if (Reg == IncomingReg) {
1905  if (!Found) {
1906  if (MO.isKill())
1907  // The register is already marked kill.
1908  return true;
1909  if (isPhysReg && isRegTiedToDefOperand(i))
1910  // Two-address uses of physregs must not be marked kill.
1911  return true;
1912  MO.setIsKill();
1913  Found = true;
1914  }
1915  } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1916  // A super-register kill already exists.
1917  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1918  return true;
1919  if (RegInfo->isSubRegister(IncomingReg, Reg))
1920  DeadOps.push_back(i);
1921  }
1922  }
1923 
1924  // Trim unneeded kill operands.
1925  while (!DeadOps.empty()) {
1926  unsigned OpIdx = DeadOps.back();
1927  if (getOperand(OpIdx).isImplicit() &&
1928  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1929  RemoveOperand(OpIdx);
1930  else
1931  getOperand(OpIdx).setIsKill(false);
1932  DeadOps.pop_back();
1933  }
1934 
1935  // If not found, this means an alias of one of the operands is killed. Add a
1936  // new implicit operand if required.
1937  if (!Found && AddIfNotFound) {
1939  false /*IsDef*/,
1940  true /*IsImp*/,
1941  true /*IsKill*/));
1942  return true;
1943  }
1944  return Found;
1945 }
1946 
1948  const TargetRegisterInfo *RegInfo) {
1950  RegInfo = nullptr;
1951  for (MachineOperand &MO : operands()) {
1952  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1953  continue;
1954  Register OpReg = MO.getReg();
1955  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1956  MO.setIsKill(false);
1957  }
1958 }
1959 
1961  const TargetRegisterInfo *RegInfo,
1962  bool AddIfNotFound) {
1963  bool isPhysReg = Register::isPhysicalRegister(Reg);
1964  bool hasAliases = isPhysReg &&
1965  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1966  bool Found = false;
1967  SmallVector<unsigned,4> DeadOps;
1968  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1969  MachineOperand &MO = getOperand(i);
1970  if (!MO.isReg() || !MO.isDef())
1971  continue;
1972  Register MOReg = MO.getReg();
1973  if (!MOReg)
1974  continue;
1975 
1976  if (MOReg == Reg) {
1977  MO.setIsDead();
1978  Found = true;
1979  } else if (hasAliases && MO.isDead() &&
1981  // There exists a super-register that's marked dead.
1982  if (RegInfo->isSuperRegister(Reg, MOReg))
1983  return true;
1984  if (RegInfo->isSubRegister(Reg, MOReg))
1985  DeadOps.push_back(i);
1986  }
1987  }
1988 
1989  // Trim unneeded dead operands.
1990  while (!DeadOps.empty()) {
1991  unsigned OpIdx = DeadOps.back();
1992  if (getOperand(OpIdx).isImplicit() &&
1993  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1994  RemoveOperand(OpIdx);
1995  else
1996  getOperand(OpIdx).setIsDead(false);
1997  DeadOps.pop_back();
1998  }
1999 
2000  // If not found, this means an alias of one of the operands is dead. Add a
2001  // new implicit operand if required.
2002  if (Found || !AddIfNotFound)
2003  return Found;
2004 
2006  true /*IsDef*/,
2007  true /*IsImp*/,
2008  false /*IsKill*/,
2009  true /*IsDead*/));
2010  return true;
2011 }
2012 
2014  for (MachineOperand &MO : operands()) {
2015  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2016  continue;
2017  MO.setIsDead(false);
2018  }
2019 }
2020 
2022  for (MachineOperand &MO : operands()) {
2023  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2024  continue;
2025  MO.setIsUndef(IsUndef);
2026  }
2027 }
2028 
2030  const TargetRegisterInfo *RegInfo) {
2032  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2033  if (MO)
2034  return;
2035  } else {
2036  for (const MachineOperand &MO : operands()) {
2037  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2038  MO.getSubReg() == 0)
2039  return;
2040  }
2041  }
2043  true /*IsDef*/,
2044  true /*IsImp*/));
2045 }
2046 
2048  const TargetRegisterInfo &TRI) {
2049  bool HasRegMask = false;
2050  for (MachineOperand &MO : operands()) {
2051  if (MO.isRegMask()) {
2052  HasRegMask = true;
2053  continue;
2054  }
2055  if (!MO.isReg() || !MO.isDef()) continue;
2056  Register Reg = MO.getReg();
2057  if (!Reg.isPhysical())
2058  continue;
2059  // If there are no uses, including partial uses, the def is dead.
2060  if (llvm::none_of(UsedRegs,
2061  [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2062  MO.setIsDead();
2063  }
2064 
2065  // This is a call with a register mask operand.
2066  // Mask clobbers are always dead, so add defs for the non-dead defines.
2067  if (HasRegMask)
2068  for (const Register &UsedReg : UsedRegs)
2069  addRegisterDefined(UsedReg, &TRI);
2070 }
2071 
2072 unsigned
2074  // Build up a buffer of hash code components.
2075  SmallVector<size_t, 16> HashComponents;
2076  HashComponents.reserve(MI->getNumOperands() + 1);
2077  HashComponents.push_back(MI->getOpcode());
2078  for (const MachineOperand &MO : MI->operands()) {
2079  if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2080  continue; // Skip virtual register defs.
2081 
2082  HashComponents.push_back(hash_value(MO));
2083  }
2084  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2085 }
2086 
2088  // Find the source location cookie.
2089  uint64_t LocCookie = 0;
2090  const MDNode *LocMD = nullptr;
2091  for (unsigned i = getNumOperands(); i != 0; --i) {
2092  if (getOperand(i-1).isMetadata() &&
2093  (LocMD = getOperand(i-1).getMetadata()) &&
2094  LocMD->getNumOperands() != 0) {
2095  if (const ConstantInt *CI =
2096  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2097  LocCookie = CI->getZExtValue();
2098  break;
2099  }
2100  }
2101  }
2102 
2103  if (const MachineBasicBlock *MBB = getParent())
2104  if (const MachineFunction *MF = MBB->getParent())
2105  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2106  report_fatal_error(Msg);
2107 }
2108 
2110  const MCInstrDesc &MCID, bool IsIndirect,
2111  Register Reg, const MDNode *Variable,
2112  const MDNode *Expr) {
2113  assert(isa<DILocalVariable>(Variable) && "not a variable");
2114  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2115  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2116  "Expected inlined-at fields to agree");
2117  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2118  if (IsIndirect)
2119  MIB.addImm(0U);
2120  else
2121  MIB.addReg(0U);
2122  return MIB.addMetadata(Variable).addMetadata(Expr);
2123 }
2124 
2126  const MCInstrDesc &MCID, bool IsIndirect,
2127  const MachineOperand &MO,
2128  const MDNode *Variable, const MDNode *Expr) {
2129  assert(isa<DILocalVariable>(Variable) && "not a variable");
2130  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2131  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2132  "Expected inlined-at fields to agree");
2133  if (MO.isReg())
2134  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2135 
2136  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2137  if (IsIndirect)
2138  MIB.addImm(0U);
2139  else
2140  MIB.addReg(0U);
2141  return MIB.addMetadata(Variable).addMetadata(Expr);
2142 }
2143 
2145  const MCInstrDesc &MCID, bool IsIndirect,
2147  const MDNode *Variable, const MDNode *Expr) {
2148  assert(isa<DILocalVariable>(Variable) && "not a variable");
2149  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2150  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2151  "Expected inlined-at fields to agree");
2152  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2153  return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2154 
2155  auto MIB = BuildMI(MF, DL, MCID);
2156  MIB.addMetadata(Variable).addMetadata(Expr);
2157  for (const MachineOperand &MO : MOs)
2158  if (MO.isReg())
2159  MIB.addReg(MO.getReg());
2160  else
2161  MIB.add(MO);
2162  return MIB;
2163 }
2164 
2167  const DebugLoc &DL, const MCInstrDesc &MCID,
2168  bool IsIndirect, Register Reg,
2169  const MDNode *Variable, const MDNode *Expr) {
2170  MachineFunction &MF = *BB.getParent();
2171  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2172  BB.insert(I, MI);
2173  return MachineInstrBuilder(MF, MI);
2174 }
2175 
2178  const DebugLoc &DL, const MCInstrDesc &MCID,
2179  bool IsIndirect, MachineOperand &MO,
2180  const MDNode *Variable, const MDNode *Expr) {
2181  MachineFunction &MF = *BB.getParent();
2182  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2183  BB.insert(I, MI);
2184  return MachineInstrBuilder(MF, *MI);
2185 }
2186 
2189  const DebugLoc &DL, const MCInstrDesc &MCID,
2190  bool IsIndirect, ArrayRef<MachineOperand> MOs,
2191  const MDNode *Variable, const MDNode *Expr) {
2192  MachineFunction &MF = *BB.getParent();
2193  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2194  BB.insert(I, MI);
2195  return MachineInstrBuilder(MF, *MI);
2196 }
2197 
2198 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2199 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2200 static const DIExpression *
2202  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2203  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2204  "Expected inlined-at fields to agree");
2205 
2206  const DIExpression *Expr = MI.getDebugExpression();
2207  if (MI.isIndirectDebugValue()) {
2208  assert(MI.getDebugOffset().getImm() == 0 &&
2209  "DBG_VALUE with nonzero offset");
2211  } else if (MI.isDebugValueList()) {
2212  // We will replace the spilled register with a frame index, so
2213  // immediately deref all references to the spilled register.
2214  std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2215  for (const MachineOperand *Op : SpilledOperands) {
2216  unsigned OpIdx = MI.getDebugOperandIndex(Op);
2217  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2218  }
2219  }
2220  return Expr;
2221 }
2223  Register SpillReg) {
2224  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2226  for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2227  SpillOperands.push_back(&Op);
2228  return computeExprForSpill(MI, SpillOperands);
2229 }
2230 
2233  const MachineInstr &Orig,
2234  int FrameIndex, Register SpillReg) {
2235  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2236  MachineInstrBuilder NewMI =
2237  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2238  // Non-Variadic Operands: Location, Offset, Variable, Expression
2239  // Variadic Operands: Variable, Expression, Locations...
2240  if (Orig.isNonListDebugValue())
2241  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2242  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2243  if (Orig.isDebugValueList()) {
2244  for (const MachineOperand &Op : Orig.debug_operands())
2245  if (Op.isReg() && Op.getReg() == SpillReg)
2246  NewMI.addFrameIndex(FrameIndex);
2247  else
2248  NewMI.add(MachineOperand(Op));
2249  }
2250  return NewMI;
2251 }
2254  const MachineInstr &Orig, int FrameIndex,
2255  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2256  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2257  MachineInstrBuilder NewMI =
2258  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2259  // Non-Variadic Operands: Location, Offset, Variable, Expression
2260  // Variadic Operands: Variable, Expression, Locations...
2261  if (Orig.isNonListDebugValue())
2262  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2263  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2264  if (Orig.isDebugValueList()) {
2265  for (const MachineOperand &Op : Orig.debug_operands())
2266  if (is_contained(SpilledOperands, &Op))
2267  NewMI.addFrameIndex(FrameIndex);
2268  else
2269  NewMI.add(MachineOperand(Op));
2270  }
2271  return NewMI;
2272 }
2273 
2275  Register Reg) {
2276  const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2277  if (Orig.isNonListDebugValue())
2278  Orig.getDebugOffset().ChangeToImmediate(0U);
2280  Op.ChangeToFrameIndex(FrameIndex);
2281  Orig.getDebugExpressionOp().setMetadata(Expr);
2282 }
2283 
2285  SmallVectorImpl<MachineInstr *> &DbgValues) {
2286  MachineInstr &MI = *this;
2287  if (!MI.getOperand(0).isReg())
2288  return;
2289 
2290  MachineBasicBlock::iterator DI = MI; ++DI;
2291  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2292  DI != DE; ++DI) {
2293  if (!DI->isDebugValue())
2294  return;
2295  if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2296  DbgValues.push_back(&*DI);
2297  }
2298 }
2299 
2301  // Collect matching debug values.
2303 
2304  if (!getOperand(0).isReg())
2305  return;
2306 
2307  Register DefReg = getOperand(0).getReg();
2308  auto *MRI = getRegInfo();
2309  for (auto &MO : MRI->use_operands(DefReg)) {
2310  auto *DI = MO.getParent();
2311  if (!DI->isDebugValue())
2312  continue;
2313  if (DI->hasDebugOperandForReg(DefReg)) {
2314  DbgValues.push_back(DI);
2315  }
2316  }
2317 
2318  // Propagate Reg to debug value instructions.
2319  for (auto *DBI : DbgValues)
2320  for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2321  Op.setReg(Reg);
2322 }
2323 
2325 
2326 static unsigned getSpillSlotSize(const MMOList &Accesses,
2327  const MachineFrameInfo &MFI) {
2328  unsigned Size = 0;
2329  for (auto A : Accesses)
2330  if (MFI.isSpillSlotObjectIndex(
2331  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2332  ->getFrameIndex()))
2333  Size += A->getSize();
2334  return Size;
2335 }
2336 
2339  int FI;
2340  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2341  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2342  if (MFI.isSpillSlotObjectIndex(FI))
2343  return (*memoperands_begin())->getSize();
2344  }
2345  return None;
2346 }
2347 
2350  MMOList Accesses;
2351  if (TII->hasStoreToStackSlot(*this, Accesses))
2352  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2353  return None;
2354 }
2355 
2358  int FI;
2359  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2360  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2361  if (MFI.isSpillSlotObjectIndex(FI))
2362  return (*memoperands_begin())->getSize();
2363  }
2364  return None;
2365 }
2366 
2369  MMOList Accesses;
2370  if (TII->hasLoadFromStackSlot(*this, Accesses))
2371  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2372  return None;
2373 }
2374 
2376  if (DebugInstrNum == 0)
2377  DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2378  return DebugInstrNum;
2379 }
2380 
2382  if (DebugInstrNum == 0)
2383  DebugInstrNum = MF.getNewDebugInstrNum();
2384  return DebugInstrNum;
2385 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1296
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1216
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:771
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:862
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
CmpMode::FP
@ FP
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:365
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2013
llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
Definition: MachineRegisterInfo.cpp:532
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2047
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2375
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1960
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:170
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:506
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1565
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2073
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
Metadata.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:235
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1235
Loads.h
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:640
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1028
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:729
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:708
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:741
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:537
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:390
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:306
llvm::InlineAsm::AD_ATT
@ AD_ATT
Definition: InlineAsm.h:34
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:675
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1235
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:731
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1142
InlineAsm.h
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:227
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:233
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::AAResults::isNoAlias
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Definition: AliasAnalysis.h:562
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:762
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1203
MachineBasicBlock.h
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2029
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1479
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1447
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:684
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:345
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MachineFunction::getNewDebugInstrNum
unsigned getNewDebugInstrNum()
Definition: MachineFunction.h:1219
Module.h
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:343
TargetInstrInfo.h
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:98
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4783
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:983
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:469
llvm::FastMathFlags::noSignedZeros
bool noSignedZeros() const
Definition: Operator.h:209
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:666
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
llvm::Optional< unsigned >
llvm::SmallPtrSet< const MachineInstr *, 16 >
Operator.h
Hashing.h
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:797
hasIdenticalMMOs
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
Definition: MachineInstr.cpp:416
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:856
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2586
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:161
llvm::FastMathFlags::noNaNs
bool noNaNs() const
Definition: Operator.h:207
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4821
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:258
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:304
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:225
llvm::PossiblyExactOperator
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:121
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:329
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:385
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:841
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1379
MachineRegisterInfo.h
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1558
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:567
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:238
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:582
llvm::MDNode::getNumOperands
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1143
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1304
AliasAnalysis.h
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1129
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:521
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:325
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:539
CommandLine.h
FormattedStream.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:153
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1312
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
getSpillSlotSize
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
Definition: MachineInstr.cpp:2326
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
llvm::FastMathFlags::approxFunc
bool approxFunc() const
Definition: Operator.h:212
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:508
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:930
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:204
Constants.h
llvm::AAResults
Definition: AliasAnalysis.h:508
SmallString.h
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3097
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1491
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:648
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:374
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:211
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
Intrinsics.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2231
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2349
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1205
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:562
InstrTypes.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1140
llvm::fdbgs
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
Definition: FormattedStream.cpp:152
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:427
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1331
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
MCSymbol.h
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:224
llvm::FastMathFlags::allowReassoc
bool allowReassoc() const
Flag queries.
Definition: Operator.h:206
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:670
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:789
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1222
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:104
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition: MachineInstr.cpp:81
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1881
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:90
llvm::FastMathFlags::allowReciprocal
bool allowReciprocal() const
Definition: Operator.h:210
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:346
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1212
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:723
MachineInstrBundle.h
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:971
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:197
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:214
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:798
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:478
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:595
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:776
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:104
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1472
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1573
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:92
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1210
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:328
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:280
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:767
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:759
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:646
llvm::MDNode::getOperand
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1137
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:575
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:108
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:581
llvm::MachineFunction::deallocateOperandArray
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
Definition: MachineFunction.h:974
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:242
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1518
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:423
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:226
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:556
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::FastMathFlags::noInfs
bool noInfs() const
Definition: Operator.h:208
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:35
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2087
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:874
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:726
uint64_t
llvm::MachineFunction::createMIExtraInfo
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
Definition: MachineFunction.cpp:508
TiedMax
const unsigned TiedMax
Definition: MachineInstr.cpp:1088
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2274
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1898
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:846
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:393
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:100
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MemoryLocation.h
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:219
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2021
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::InlineAsm::MIOp_AsmString
@ MIOp_AsmString
Definition: InlineAsm.h:218
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:279
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
MCRegisterInfo.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:768
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::make_pointee_range
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:330
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2284
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:339
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:780
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1947
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2794
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FPMathOperator
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:250
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1609
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1015
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:646
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.h:2904
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:715
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:220
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:332
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:345
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1255
MachineModuleInfo.h
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:807
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1401
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:528
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:588
llvm::DebugLoc::hasTrivialDestructor
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1144
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1543
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:705
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:858
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:106
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:813
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition: MachineInstr.cpp:90
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1558
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1261
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:234
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1826
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:523
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:753
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2368
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:511
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:796
Compiler.h
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1072
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:110
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1580
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:847
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1219
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:729
llvm::OverflowingBinaryOperator
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:67
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:409
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1208
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:228
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:883
MemOperandsHaveAlias
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
Definition: MachineInstr.cpp:1264
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1199
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:875
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
FoldingSet.h
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:951
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
std
Definition: BitVector.h:838
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:531
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:354
uint16_t
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:349
moveOperands
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
Definition: MachineInstr.cpp:194
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:517
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1460
llvm::Module::getContext
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:261
Casting.h
llvm::MachineFunction::allocateOperandArray
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
Definition: MachineFunction.h:967
Function.h
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:878
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:256
StackMaps.h
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:710
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:96
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:686
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:397
llvm::AAResults::pointsToConstantMemory
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Definition: AliasAnalysis.cpp:163
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:720
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1287
llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:685
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
computeExprForSpill
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
Definition: MachineInstr.cpp:2201
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1220
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:656
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:217
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1044
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:339
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:102
RegisterBank.h
TargetIntrinsicInfo.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
SmallBitVector.h
N
#define N
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:401
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::hash_combine_range
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:483
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:223
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:366
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:94
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:690
ModuleSlotTracker.h
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1501
llvm::SmallVectorImpl< unsigned >
llvm::MachineBasicBlock::erase_instr
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.h:901
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
DerivedTypes.h
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2357
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:922
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1143
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3185
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1259
LLVMContext.h
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:361
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:333
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FastMathFlags::allowContract
bool allowContract() const
Definition: Operator.h:211
raw_ostream.h
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1102
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1038
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:624
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1213
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1458
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
Value.h
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:174
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:765
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:995
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1309
TargetRegisterInfo.h
Debug.h
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:227
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:493
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:559
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:209
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2338
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:748
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:335
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1184
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:287
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:205
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2300
llvm::LLT
Definition: LowLevelTypeImpl.h:40