LLVM  14.0.0git
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Analysis/Loads.h"
37 #include "llvm/CodeGen/StackMaps.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/InstrTypes.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Module.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/Value.h"
57 #include "llvm/MC/MCInstrDesc.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/Compiler.h"
63 #include "llvm/Support/Debug.h"
71 #include <algorithm>
72 #include <cassert>
73 #include <cstddef>
74 #include <cstdint>
75 #include <cstring>
76 #include <iterator>
77 #include <utility>
78 
79 using namespace llvm;
80 
82  if (const MachineBasicBlock *MBB = MI.getParent())
83  if (const MachineFunction *MF = MBB->getParent())
84  return MF;
85  return nullptr;
86 }
87 
88 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 // it.
90 static void tryToGetTargetInfo(const MachineInstr &MI,
91  const TargetRegisterInfo *&TRI,
92  const MachineRegisterInfo *&MRI,
93  const TargetIntrinsicInfo *&IntrinsicInfo,
94  const TargetInstrInfo *&TII) {
95 
96  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97  TRI = MF->getSubtarget().getRegisterInfo();
98  MRI = &MF->getRegInfo();
99  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100  TII = MF->getSubtarget().getInstrInfo();
101  }
102 }
103 
105  if (MCID->ImplicitDefs)
106  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107  ++ImpDefs)
108  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109  if (MCID->ImplicitUses)
110  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111  ++ImpUses)
112  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 }
114 
115 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116 /// implicit operands. It reserves space for the number of operands specified by
117 /// the MCInstrDesc.
118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
119  DebugLoc DL, bool NoImp)
120  : MCID(&TID), DbgLoc(std::move(DL)), DebugInstrNum(0) {
121  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
122 
123  // Reserve space for the expected number of operands.
124  if (unsigned NumOps = MCID->getNumOperands() +
125  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126  CapOperands = OperandCapacity::get(NumOps);
127  Operands = MF.allocateOperandArray(CapOperands);
128  }
129 
130  if (!NoImp)
132 }
133 
134 /// MachineInstr ctor - Copies MachineInstr arg exactly.
135 /// Does not copy the number from debug instruction numbering, to preserve
136 /// uniqueness.
137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138  : MCID(&MI.getDesc()), Info(MI.Info), DbgLoc(MI.getDebugLoc()),
139  DebugInstrNum(0) {
140  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
141 
142  CapOperands = OperandCapacity::get(MI.getNumOperands());
143  Operands = MF.allocateOperandArray(CapOperands);
144 
145  // Copy operands.
146  for (const MachineOperand &MO : MI.operands())
147  addOperand(MF, MO);
148 
149  // Copy all the sensible flags.
150  setFlags(MI.Flags);
151 }
152 
154  MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155 }
156 
157 /// getRegInfo - If this instruction is embedded into a MachineFunction,
158 /// return the MachineRegisterInfo object for the current function, otherwise
159 /// return null.
160 MachineRegisterInfo *MachineInstr::getRegInfo() {
162  return &MBB->getParent()->getRegInfo();
163  return nullptr;
164 }
165 
166 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167 /// this instruction from their respective use lists. This requires that the
168 /// operands already be on their use lists.
169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170  for (MachineOperand &MO : operands())
171  if (MO.isReg())
173 }
174 
175 /// AddRegOperandsToUseLists - Add all of the register operands in
176 /// this instruction from their respective use lists. This requires that the
177 /// operands not be on their use lists yet.
178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179  for (MachineOperand &MO : operands())
180  if (MO.isReg())
182 }
183 
186  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
187  MachineFunction *MF = MBB->getParent();
188  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
189  addOperand(*MF, Op);
190 }
191 
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193 /// ranges. If MRI is non-null also update use-def chains.
195  unsigned NumOps, MachineRegisterInfo *MRI) {
196  if (MRI)
197  return MRI->moveOperands(Dst, Src, NumOps);
198  // MachineOperand is a trivially copyable type so we can just use memmove.
199  assert(Dst && Src && "Unknown operands");
200  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201 }
202 
203 /// addOperand - Add the specified operand to the instruction. If it is an
204 /// implicit operand, it is added to the end of the operand list. If it is
205 /// an explicit operand it is added at the end of the explicit operand list
206 /// (before the first implicit operand).
208  assert(MCID && "Cannot add operands before providing an instr descriptor");
209 
210  // Check if we're adding one of our existing operands.
211  if (&Op >= Operands && &Op < Operands + NumOperands) {
212  // This is unusual: MI->addOperand(MI->getOperand(i)).
213  // If adding Op requires reallocating or moving existing operands around,
214  // the Op reference could go stale. Support it by copying Op.
215  MachineOperand CopyOp(Op);
216  return addOperand(MF, CopyOp);
217  }
218 
219  // Find the insert location for the new operand. Implicit registers go at
220  // the end, everything else goes before the implicit regs.
221  //
222  // FIXME: Allow mixed explicit and implicit operands on inline asm.
223  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224  // implicit-defs, but they must not be moved around. See the FIXME in
225  // InstrEmitter.cpp.
226  unsigned OpNo = getNumOperands();
227  bool isImpReg = Op.isReg() && Op.isImplicit();
228  if (!isImpReg && !isInlineAsm()) {
229  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230  --OpNo;
231  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
232  }
233  }
234 
235 #ifndef NDEBUG
236  bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237  Op.getType() == MachineOperand::MO_MCSymbol;
238  // OpNo now points as the desired insertion point. Unless this is a variadic
239  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240  // RegMask operands go between the explicit and implicit operands.
241  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
242  OpNo < MCID->getNumOperands() || isDebugOp) &&
243  "Trying to add an operand to a machine instr that is already done!");
244 #endif
245 
246  MachineRegisterInfo *MRI = getRegInfo();
247 
248  // Determine if the Operands array needs to be reallocated.
249  // Save the old capacity and operand array.
250  OperandCapacity OldCap = CapOperands;
251  MachineOperand *OldOperands = Operands;
252  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254  Operands = MF.allocateOperandArray(CapOperands);
255  // Move the operands before the insertion point.
256  if (OpNo)
257  moveOperands(Operands, OldOperands, OpNo, MRI);
258  }
259 
260  // Move the operands following the insertion point.
261  if (OpNo != NumOperands)
262  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263  MRI);
264  ++NumOperands;
265 
266  // Deallocate the old operand array.
267  if (OldOperands != Operands && OldOperands)
268  MF.deallocateOperandArray(OldCap, OldOperands);
269 
270  // Copy Op into place. It still needs to be inserted into the MRI use lists.
271  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272  NewMO->ParentMI = this;
273 
274  // When adding a register operand, tell MRI about it.
275  if (NewMO->isReg()) {
276  // Ensure isOnRegUseList() returns false, regardless of Op's status.
277  NewMO->Contents.Reg.Prev = nullptr;
278  // Ignore existing ties. This is not a property that can be copied.
279  NewMO->TiedTo = 0;
280  // Add the new operand to MRI, but only for instructions in an MBB.
281  if (MRI)
282  MRI->addRegOperandToUseList(NewMO);
283  // The MCID operand information isn't accurate until we start adding
284  // explicit operands. The implicit operands are added first, then the
285  // explicits are inserted before them.
286  if (!isImpReg) {
287  // Tie uses to defs as indicated in MCInstrDesc.
288  if (NewMO->isUse()) {
289  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290  if (DefIdx != -1)
291  tieOperands(DefIdx, OpNo);
292  }
293  // If the register operand is flagged as early, mark the operand as such.
294  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295  NewMO->setIsEarlyClobber(true);
296  }
297  // Ensure debug instructions set debug flag on register uses.
298  if (NewMO->isUse() && isDebugInstr())
299  NewMO->setIsDebug();
300  }
301 }
302 
303 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
304 /// fewer operand than it started with.
305 ///
306 void MachineInstr::RemoveOperand(unsigned OpNo) {
307  assert(OpNo < getNumOperands() && "Invalid operand number");
308  untieRegOperand(OpNo);
309 
310 #ifndef NDEBUG
311  // Moving tied operands would break the ties.
312  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
313  if (Operands[i].isReg())
314  assert(!Operands[i].isTied() && "Cannot move tied operands");
315 #endif
316 
317  MachineRegisterInfo *MRI = getRegInfo();
318  if (MRI && Operands[OpNo].isReg())
319  MRI->removeRegOperandFromUseList(Operands + OpNo);
320 
321  // Don't call the MachineOperand destructor. A lot of this code depends on
322  // MachineOperand having a trivial destructor anyway, and adding a call here
323  // wouldn't make it 'destructor-correct'.
324 
325  if (unsigned N = NumOperands - 1 - OpNo)
326  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
327  --NumOperands;
328 }
329 
330 void MachineInstr::setExtraInfo(MachineFunction &MF,
332  MCSymbol *PreInstrSymbol,
333  MCSymbol *PostInstrSymbol,
334  MDNode *HeapAllocMarker) {
335  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
336  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
337  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
338  int NumPointers =
339  MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
340 
341  // Drop all extra info if there is none.
342  if (NumPointers <= 0) {
343  Info.clear();
344  return;
345  }
346 
347  // If more than one pointer, then store out of line. Store heap alloc markers
348  // out of line because PointerSumType cannot hold more than 4 tag types with
349  // 32-bit pointers.
350  // FIXME: Maybe we should make the symbols in the extra info mutable?
351  else if (NumPointers > 1 || HasHeapAllocMarker) {
352  Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
353  MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
354  return;
355  }
356 
357  // Otherwise store the single pointer inline.
358  if (HasPreInstrSymbol)
359  Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
360  else if (HasPostInstrSymbol)
361  Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
362  else
363  Info.set<EIIK_MMO>(MMOs[0]);
364 }
365 
367  if (memoperands_empty())
368  return;
369 
370  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
372 }
373 
376  if (MMOs.empty()) {
377  dropMemRefs(MF);
378  return;
379  }
380 
381  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
383 }
384 
386  MachineMemOperand *MO) {
389  MMOs.push_back(MO);
390  setMemRefs(MF, MMOs);
391 }
392 
394  if (this == &MI)
395  // Nothing to do for a self-clone!
396  return;
397 
398  assert(&MF == MI.getMF() &&
399  "Invalid machine functions when cloning memory refrences!");
400  // See if we can just steal the extra info already allocated for the
401  // instruction. We can do this whenever the pre- and post-instruction symbols
402  // are the same (including null).
403  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
404  getPostInstrSymbol() == MI.getPostInstrSymbol() &&
405  getHeapAllocMarker() == MI.getHeapAllocMarker()) {
406  Info = MI.Info;
407  return;
408  }
409 
410  // Otherwise, fall back on a copy-based clone.
411  setMemRefs(MF, MI.memoperands());
412 }
413 
414 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
415 /// identical.
418  if (LHS.size() != RHS.size())
419  return false;
420 
421  auto LHSPointees = make_pointee_range(LHS);
422  auto RHSPointees = make_pointee_range(RHS);
423  return std::equal(LHSPointees.begin(), LHSPointees.end(),
424  RHSPointees.begin());
425 }
426 
429  // Try handling easy numbers of MIs with simpler mechanisms.
430  if (MIs.empty()) {
431  dropMemRefs(MF);
432  return;
433  }
434  if (MIs.size() == 1) {
435  cloneMemRefs(MF, *MIs[0]);
436  return;
437  }
438  // Because an empty memoperands list provides *no* information and must be
439  // handled conservatively (assuming the instruction can do anything), the only
440  // way to merge with it is to drop all other memoperands.
441  if (MIs[0]->memoperands_empty()) {
442  dropMemRefs(MF);
443  return;
444  }
445 
446  // Handle the general case.
448  // Start with the first instruction.
449  assert(&MF == MIs[0]->getMF() &&
450  "Invalid machine functions when cloning memory references!");
451  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
452  // Now walk all the other instructions and accumulate any different MMOs.
453  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
454  assert(&MF == MI.getMF() &&
455  "Invalid machine functions when cloning memory references!");
456 
457  // Skip MIs with identical operands to the first. This is a somewhat
458  // arbitrary hack but will catch common cases without being quadratic.
459  // TODO: We could fully implement merge semantics here if needed.
460  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
461  continue;
462 
463  // Because an empty memoperands list provides *no* information and must be
464  // handled conservatively (assuming the instruction can do anything), the
465  // only way to merge with it is to drop all other memoperands.
466  if (MI.memoperands_empty()) {
467  dropMemRefs(MF);
468  return;
469  }
470 
471  // Otherwise accumulate these into our temporary buffer of the merged state.
472  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
473  }
474 
475  setMemRefs(MF, MergedMMOs);
476 }
477 
479  // Do nothing if old and new symbols are the same.
480  if (Symbol == getPreInstrSymbol())
481  return;
482 
483  // If there was only one symbol and we're removing it, just clear info.
484  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
485  Info.clear();
486  return;
487  }
488 
489  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
491 }
492 
494  // Do nothing if old and new symbols are the same.
495  if (Symbol == getPostInstrSymbol())
496  return;
497 
498  // If there was only one symbol and we're removing it, just clear info.
499  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
500  Info.clear();
501  return;
502  }
503 
504  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
506 }
507 
509  // Do nothing if old and new symbols are the same.
510  if (Marker == getHeapAllocMarker())
511  return;
512 
513  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
514  Marker);
515 }
516 
518  const MachineInstr &MI) {
519  if (this == &MI)
520  // Nothing to do for a self-clone!
521  return;
522 
523  assert(&MF == MI.getMF() &&
524  "Invalid machine functions when cloning instruction symbols!");
525 
526  setPreInstrSymbol(MF, MI.getPreInstrSymbol());
527  setPostInstrSymbol(MF, MI.getPostInstrSymbol());
528  setHeapAllocMarker(MF, MI.getHeapAllocMarker());
529 }
530 
532  // For now, the just return the union of the flags. If the flags get more
533  // complicated over time, we might need more logic here.
534  return getFlags() | Other.getFlags();
535 }
536 
538  uint16_t MIFlags = 0;
539  // Copy the wrapping flags.
540  if (const OverflowingBinaryOperator *OB =
541  dyn_cast<OverflowingBinaryOperator>(&I)) {
542  if (OB->hasNoSignedWrap())
543  MIFlags |= MachineInstr::MIFlag::NoSWrap;
544  if (OB->hasNoUnsignedWrap())
545  MIFlags |= MachineInstr::MIFlag::NoUWrap;
546  }
547 
548  // Copy the exact flag.
549  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
550  if (PE->isExact())
551  MIFlags |= MachineInstr::MIFlag::IsExact;
552 
553  // Copy the fast-math flags.
554  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
555  const FastMathFlags Flags = FP->getFastMathFlags();
556  if (Flags.noNaNs())
557  MIFlags |= MachineInstr::MIFlag::FmNoNans;
558  if (Flags.noInfs())
559  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
560  if (Flags.noSignedZeros())
561  MIFlags |= MachineInstr::MIFlag::FmNsz;
562  if (Flags.allowReciprocal())
563  MIFlags |= MachineInstr::MIFlag::FmArcp;
564  if (Flags.allowContract())
565  MIFlags |= MachineInstr::MIFlag::FmContract;
566  if (Flags.approxFunc())
567  MIFlags |= MachineInstr::MIFlag::FmAfn;
568  if (Flags.allowReassoc())
569  MIFlags |= MachineInstr::MIFlag::FmReassoc;
570  }
571 
572  return MIFlags;
573 }
574 
576  Flags = copyFlagsFromInstruction(I);
577 }
578 
579 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
580  assert(!isBundledWithPred() && "Must be called on bundle header");
582  if (MII->getDesc().getFlags() & Mask) {
583  if (Type == AnyInBundle)
584  return true;
585  } else {
586  if (Type == AllInBundle && !MII->isBundle())
587  return false;
588  }
589  // This was the last instruction in the bundle.
590  if (!MII->isBundledWithSucc())
591  return Type == AllInBundle;
592  }
593 }
594 
596  MICheckType Check) const {
597  // If opcodes or number of operands are not the same then the two
598  // instructions are obviously not identical.
599  if (Other.getOpcode() != getOpcode() ||
600  Other.getNumOperands() != getNumOperands())
601  return false;
602 
603  if (isBundle()) {
604  // We have passed the test above that both instructions have the same
605  // opcode, so we know that both instructions are bundles here. Let's compare
606  // MIs inside the bundle.
607  assert(Other.isBundle() && "Expected that both instructions are bundles.");
610  // Loop until we analysed the last intruction inside at least one of the
611  // bundles.
612  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
613  ++I1;
614  ++I2;
615  if (!I1->isIdenticalTo(*I2, Check))
616  return false;
617  }
618  // If we've reached the end of just one of the two bundles, but not both,
619  // the instructions are not identical.
620  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
621  return false;
622  }
623 
624  // Check operands to make sure they match.
625  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
626  const MachineOperand &MO = getOperand(i);
627  const MachineOperand &OMO = Other.getOperand(i);
628  if (!MO.isReg()) {
629  if (!MO.isIdenticalTo(OMO))
630  return false;
631  continue;
632  }
633 
634  // Clients may or may not want to ignore defs when testing for equality.
635  // For example, machine CSE pass only cares about finding common
636  // subexpressions, so it's safe to ignore virtual register defs.
637  if (MO.isDef()) {
638  if (Check == IgnoreDefs)
639  continue;
640  else if (Check == IgnoreVRegDefs) {
641  if (!Register::isVirtualRegister(MO.getReg()) ||
643  if (!MO.isIdenticalTo(OMO))
644  return false;
645  } else {
646  if (!MO.isIdenticalTo(OMO))
647  return false;
648  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
649  return false;
650  }
651  } else {
652  if (!MO.isIdenticalTo(OMO))
653  return false;
654  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
655  return false;
656  }
657  }
658  // If DebugLoc does not match then two debug instructions are not identical.
659  if (isDebugInstr())
660  if (getDebugLoc() && Other.getDebugLoc() &&
661  getDebugLoc() != Other.getDebugLoc())
662  return false;
663  return true;
664 }
665 
667  return getParent()->getParent();
668 }
669 
671  assert(getParent() && "Not embedded in a basic block!");
672  return getParent()->remove(this);
673 }
674 
676  assert(getParent() && "Not embedded in a basic block!");
677  return getParent()->remove_instr(this);
678 }
679 
681  assert(getParent() && "Not embedded in a basic block!");
682  getParent()->erase(this);
683 }
684 
686  assert(getParent() && "Not embedded in a basic block!");
687  getParent()->erase_instr(this);
688 }
689 
691  if (!isCall(Type))
692  return false;
693  switch (getOpcode()) {
694  case TargetOpcode::PATCHPOINT:
695  case TargetOpcode::STACKMAP:
696  case TargetOpcode::STATEPOINT:
697  case TargetOpcode::FENTRY_CALL:
698  return false;
699  }
700  return true;
701 }
702 
704  if (isBundle())
707 }
708 
710  unsigned NumOperands = MCID->getNumOperands();
711  if (!MCID->isVariadic())
712  return NumOperands;
713 
714  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
715  const MachineOperand &MO = getOperand(I);
716  // The operands must always be in the following order:
717  // - explicit reg defs,
718  // - other explicit operands (reg uses, immediates, etc.),
719  // - implicit reg defs
720  // - implicit reg uses
721  if (MO.isReg() && MO.isImplicit())
722  break;
723  ++NumOperands;
724  }
725  return NumOperands;
726 }
727 
729  unsigned NumDefs = MCID->getNumDefs();
730  if (!MCID->isVariadic())
731  return NumDefs;
732 
733  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
734  const MachineOperand &MO = getOperand(I);
735  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
736  break;
737  ++NumDefs;
738  }
739  return NumDefs;
740 }
741 
743  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
746  --Pred;
747  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
748  Pred->setFlag(BundledSucc);
749 }
750 
752  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
755  ++Succ;
756  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
757  Succ->setFlag(BundledPred);
758 }
759 
761  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
764  --Pred;
765  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
766  Pred->clearFlag(BundledSucc);
767 }
768 
770  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
773  ++Succ;
774  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
775  Succ->clearFlag(BundledPred);
776 }
777 
779  if (isInlineAsm()) {
780  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
781  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
782  return true;
783  }
784  return false;
785 }
786 
788  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
789  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
790  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
791 }
792 
794  unsigned *GroupNo) const {
795  assert(isInlineAsm() && "Expected an inline asm instruction");
796  assert(OpIdx < getNumOperands() && "OpIdx out of range");
797 
798  // Ignore queries about the initial operands.
799  if (OpIdx < InlineAsm::MIOp_FirstOperand)
800  return -1;
801 
802  unsigned Group = 0;
803  unsigned NumOps;
804  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
805  i += NumOps) {
806  const MachineOperand &FlagMO = getOperand(i);
807  // If we reach the implicit register operands, stop looking.
808  if (!FlagMO.isImm())
809  return -1;
810  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
811  if (i + NumOps > OpIdx) {
812  if (GroupNo)
813  *GroupNo = Group;
814  return i;
815  }
816  ++Group;
817  }
818  return -1;
819 }
820 
822  assert(isDebugLabel() && "not a DBG_LABEL");
823  return cast<DILabel>(getOperand(0).getMetadata());
824 }
825 
827  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
828  unsigned VariableOp = isDebugValueList() ? 0 : 2;
829  return getOperand(VariableOp);
830 }
831 
833  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
834  unsigned VariableOp = isDebugValueList() ? 0 : 2;
835  return getOperand(VariableOp);
836 }
837 
839  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
840 }
841 
843  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
844  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
845  return getOperand(ExpressionOp);
846 }
847 
849  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
850  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
851  return getOperand(ExpressionOp);
852 }
853 
855  return cast<DIExpression>(getDebugExpressionOp().getMetadata());
856 }
857 
860 }
861 
862 const TargetRegisterClass*
864  const TargetInstrInfo *TII,
865  const TargetRegisterInfo *TRI) const {
866  assert(getParent() && "Can't have an MBB reference here!");
867  assert(getMF() && "Can't have an MF reference here!");
868  const MachineFunction &MF = *getMF();
869 
870  // Most opcodes have fixed constraints in their MCInstrDesc.
871  if (!isInlineAsm())
872  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
873 
874  if (!getOperand(OpIdx).isReg())
875  return nullptr;
876 
877  // For tied uses on inline asm, get the constraint from the def.
878  unsigned DefIdx;
879  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
880  OpIdx = DefIdx;
881 
882  // Inline asm stores register class constraints in the flag word.
883  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
884  if (FlagIdx < 0)
885  return nullptr;
886 
887  unsigned Flag = getOperand(FlagIdx).getImm();
888  unsigned RCID;
893  return TRI->getRegClass(RCID);
894 
895  // Assume that all registers in a memory operand are pointers.
897  return TRI->getPointerRegClass(MF);
898 
899  return nullptr;
900 }
901 
903  Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
904  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
905  // Check every operands inside the bundle if we have
906  // been asked to.
907  if (ExploreBundle)
908  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
909  ++OpndIt)
910  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
911  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
912  else
913  // Otherwise, just check the current operands.
914  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
915  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
916  return CurRC;
917 }
918 
919 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
920  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
921  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
922  assert(CurRC && "Invalid initial register class");
923  // Check if Reg is constrained by some of its use/def from MI.
924  const MachineOperand &MO = getOperand(OpIdx);
925  if (!MO.isReg() || MO.getReg() != Reg)
926  return CurRC;
927  // If yes, accumulate the constraints through the operand.
928  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
929 }
930 
932  unsigned OpIdx, const TargetRegisterClass *CurRC,
933  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
934  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
935  const MachineOperand &MO = getOperand(OpIdx);
936  assert(MO.isReg() &&
937  "Cannot get register constraints for non-register operand");
938  assert(CurRC && "Invalid initial register class");
939  if (unsigned SubIdx = MO.getSubReg()) {
940  if (OpRC)
941  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
942  else
943  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
944  } else if (OpRC)
945  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
946  return CurRC;
947 }
948 
949 /// Return the number of instructions inside the MI bundle, not counting the
950 /// header instruction.
951 unsigned MachineInstr::getBundleSize() const {
953  unsigned Size = 0;
954  while (I->isBundledWithSucc()) {
955  ++Size;
956  ++I;
957  }
958  return Size;
959 }
960 
961 /// Returns true if the MachineInstr has an implicit-use operand of exactly
962 /// the given register (not considering sub/super-registers).
964  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
965  const MachineOperand &MO = getOperand(i);
966  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
967  return true;
968  }
969  return false;
970 }
971 
972 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
973 /// the specific register or -1 if it is not found. It further tightens
974 /// the search criteria to a use that kills the register if isKill is true.
976  Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
977  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
978  const MachineOperand &MO = getOperand(i);
979  if (!MO.isReg() || !MO.isUse())
980  continue;
981  Register MOReg = MO.getReg();
982  if (!MOReg)
983  continue;
984  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
985  if (!isKill || MO.isKill())
986  return i;
987  }
988  return -1;
989 }
990 
991 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
992 /// indicating if this instruction reads or writes Reg. This also considers
993 /// partial defines.
994 std::pair<bool,bool>
996  SmallVectorImpl<unsigned> *Ops) const {
997  bool PartDef = false; // Partial redefine.
998  bool FullDef = false; // Full define.
999  bool Use = false;
1000 
1001  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1002  const MachineOperand &MO = getOperand(i);
1003  if (!MO.isReg() || MO.getReg() != Reg)
1004  continue;
1005  if (Ops)
1006  Ops->push_back(i);
1007  if (MO.isUse())
1008  Use |= !MO.isUndef();
1009  else if (MO.getSubReg() && !MO.isUndef())
1010  // A partial def undef doesn't count as reading the register.
1011  PartDef = true;
1012  else
1013  FullDef = true;
1014  }
1015  // A partial redefine uses Reg unless there is also a full define.
1016  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1017 }
1018 
1019 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1020 /// the specified register or -1 if it is not found. If isDead is true, defs
1021 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1022 /// also checks if there is a def of a super-register.
1023 int
1025  const TargetRegisterInfo *TRI) const {
1026  bool isPhys = Register::isPhysicalRegister(Reg);
1027  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1028  const MachineOperand &MO = getOperand(i);
1029  // Accept regmask operands when Overlap is set.
1030  // Ignore them when looking for a specific def operand (Overlap == false).
1031  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1032  return i;
1033  if (!MO.isReg() || !MO.isDef())
1034  continue;
1035  Register MOReg = MO.getReg();
1036  bool Found = (MOReg == Reg);
1037  if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1038  if (Overlap)
1039  Found = TRI->regsOverlap(MOReg, Reg);
1040  else
1041  Found = TRI->isSubRegister(MOReg, Reg);
1042  }
1043  if (Found && (!isDead || MO.isDead()))
1044  return i;
1045  }
1046  return -1;
1047 }
1048 
1049 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1050 /// operand list that is used to represent the predicate. It returns -1 if
1051 /// none is found.
1053  // Don't call MCID.findFirstPredOperandIdx() because this variant
1054  // is sometimes called on an instruction that's not yet complete, and
1055  // so the number of operands is less than the MCID indicates. In
1056  // particular, the PTX target does this.
1057  const MCInstrDesc &MCID = getDesc();
1058  if (MCID.isPredicable()) {
1059  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1060  if (MCID.OpInfo[i].isPredicate())
1061  return i;
1062  }
1063 
1064  return -1;
1065 }
1066 
1067 // MachineOperand::TiedTo is 4 bits wide.
1068 const unsigned TiedMax = 15;
1069 
1070 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1071 ///
1072 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1073 /// field. TiedTo can have these values:
1074 ///
1075 /// 0: Operand is not tied to anything.
1076 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1077 /// TiedMax: Tied to an operand >= TiedMax-1.
1078 ///
1079 /// The tied def must be one of the first TiedMax operands on a normal
1080 /// instruction. INLINEASM instructions allow more tied defs.
1081 ///
1082 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1083  MachineOperand &DefMO = getOperand(DefIdx);
1084  MachineOperand &UseMO = getOperand(UseIdx);
1085  assert(DefMO.isDef() && "DefIdx must be a def operand");
1086  assert(UseMO.isUse() && "UseIdx must be a use operand");
1087  assert(!DefMO.isTied() && "Def is already tied to another use");
1088  assert(!UseMO.isTied() && "Use is already tied to another def");
1089 
1090  if (DefIdx < TiedMax)
1091  UseMO.TiedTo = DefIdx + 1;
1092  else {
1093  // Inline asm can use the group descriptors to find tied operands,
1094  // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1095  // but on normal instruction, the tied def must be within the first TiedMax
1096  // operands.
1097  assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1098  "DefIdx out of range");
1099  UseMO.TiedTo = TiedMax;
1100  }
1101 
1102  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1103  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1104 }
1105 
1106 /// Given the index of a tied register operand, find the operand it is tied to.
1107 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1108 /// which must exist.
1109 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1110  const MachineOperand &MO = getOperand(OpIdx);
1111  assert(MO.isTied() && "Operand isn't tied");
1112 
1113  // Normally TiedTo is in range.
1114  if (MO.TiedTo < TiedMax)
1115  return MO.TiedTo - 1;
1116 
1117  // Uses on normal instructions can be out of range.
1118  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1119  // Normal tied defs must be in the 0..TiedMax-1 range.
1120  if (MO.isUse())
1121  return TiedMax - 1;
1122  // MO is a def. Search for the tied use.
1123  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1124  const MachineOperand &UseMO = getOperand(i);
1125  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1126  return i;
1127  }
1128  llvm_unreachable("Can't find tied use");
1129  }
1130 
1131  if (getOpcode() == TargetOpcode::STATEPOINT) {
1132  // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1133  // on registers.
1134  StatepointOpers SO(this);
1135  unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1136  assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1137  unsigned NumDefs = getNumDefs();
1138  for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1139  while (!getOperand(CurUseIdx).isReg())
1140  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1141  if (OpIdx == CurDefIdx)
1142  return CurUseIdx;
1143  if (OpIdx == CurUseIdx)
1144  return CurDefIdx;
1145  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1146  }
1147  llvm_unreachable("Can't find tied use");
1148  }
1149 
1150  // Now deal with inline asm by parsing the operand group descriptor flags.
1151  // Find the beginning of each operand group.
1152  SmallVector<unsigned, 8> GroupIdx;
1153  unsigned OpIdxGroup = ~0u;
1154  unsigned NumOps;
1155  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1156  i += NumOps) {
1157  const MachineOperand &FlagMO = getOperand(i);
1158  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1159  unsigned CurGroup = GroupIdx.size();
1160  GroupIdx.push_back(i);
1161  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1162  // OpIdx belongs to this operand group.
1163  if (OpIdx > i && OpIdx < i + NumOps)
1164  OpIdxGroup = CurGroup;
1165  unsigned TiedGroup;
1166  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1167  continue;
1168  // Operands in this group are tied to operands in TiedGroup which must be
1169  // earlier. Find the number of operands between the two groups.
1170  unsigned Delta = i - GroupIdx[TiedGroup];
1171 
1172  // OpIdx is a use tied to TiedGroup.
1173  if (OpIdxGroup == CurGroup)
1174  return OpIdx - Delta;
1175 
1176  // OpIdx is a def tied to this use group.
1177  if (OpIdxGroup == TiedGroup)
1178  return OpIdx + Delta;
1179  }
1180  llvm_unreachable("Invalid tied operand on inline asm");
1181 }
1182 
1183 /// clearKillInfo - Clears kill flags on all operands.
1184 ///
1186  for (MachineOperand &MO : operands()) {
1187  if (MO.isReg() && MO.isUse())
1188  MO.setIsKill(false);
1189  }
1190 }
1191 
1193  unsigned SubIdx,
1194  const TargetRegisterInfo &RegInfo) {
1195  if (Register::isPhysicalRegister(ToReg)) {
1196  if (SubIdx)
1197  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1198  for (MachineOperand &MO : operands()) {
1199  if (!MO.isReg() || MO.getReg() != FromReg)
1200  continue;
1201  MO.substPhysReg(ToReg, RegInfo);
1202  }
1203  } else {
1204  for (MachineOperand &MO : operands()) {
1205  if (!MO.isReg() || MO.getReg() != FromReg)
1206  continue;
1207  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1208  }
1209  }
1210 }
1211 
1212 /// isSafeToMove - Return true if it is safe to move this instruction. If
1213 /// SawStore is set to true, it means that there is a store (or call) between
1214 /// the instruction's location and its intended destination.
1215 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1216  // Ignore stuff that we obviously can't move.
1217  //
1218  // Treat volatile loads as stores. This is not strictly necessary for
1219  // volatiles, but it is required for atomic loads. It is not allowed to move
1220  // a load across an atomic load with Ordering > Monotonic.
1221  if (mayStore() || isCall() || isPHI() ||
1222  (mayLoad() && hasOrderedMemoryRef())) {
1223  SawStore = true;
1224  return false;
1225  }
1226 
1227  if (isPosition() || isDebugInstr() || isTerminator() ||
1229  return false;
1230 
1231  // See if this instruction does a load. If so, we have to guarantee that the
1232  // loaded value doesn't change between the load and the its intended
1233  // destination. The check for isInvariantLoad gives the target the chance to
1234  // classify the load as always returning a constant, e.g. a constant pool
1235  // load.
1237  // Otherwise, this is a real load. If there is a store between the load and
1238  // end of block, we can't move it.
1239  return !SawStore;
1240 
1241  return true;
1242 }
1243 
1245  bool UseTBAA, const MachineMemOperand *MMOa,
1246  const MachineMemOperand *MMOb) {
1247  // The following interface to AA is fashioned after DAGCombiner::isAlias and
1248  // operates with MachineMemOperand offset with some important assumptions:
1249  // - LLVM fundamentally assumes flat address spaces.
1250  // - MachineOperand offset can *only* result from legalization and cannot
1251  // affect queries other than the trivial case of overlap checking.
1252  // - These offsets never wrap and never step outside of allocated objects.
1253  // - There should never be any negative offsets here.
1254  //
1255  // FIXME: Modify API to hide this math from "user"
1256  // Even before we go to AA we can reason locally about some memory objects. It
1257  // can save compile time, and possibly catch some corner cases not currently
1258  // covered.
1259 
1260  int64_t OffsetA = MMOa->getOffset();
1261  int64_t OffsetB = MMOb->getOffset();
1262  int64_t MinOffset = std::min(OffsetA, OffsetB);
1263 
1264  uint64_t WidthA = MMOa->getSize();
1265  uint64_t WidthB = MMOb->getSize();
1266  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1267  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1268 
1269  const Value *ValA = MMOa->getValue();
1270  const Value *ValB = MMOb->getValue();
1271  bool SameVal = (ValA && ValB && (ValA == ValB));
1272  if (!SameVal) {
1273  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1274  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1275  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1276  return false;
1277  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1278  return false;
1279  if (PSVa && PSVb && (PSVa == PSVb))
1280  SameVal = true;
1281  }
1282 
1283  if (SameVal) {
1284  if (!KnownWidthA || !KnownWidthB)
1285  return true;
1286  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1287  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1288  return (MinOffset + LowWidth > MaxOffset);
1289  }
1290 
1291  if (!AA)
1292  return true;
1293 
1294  if (!ValA || !ValB)
1295  return true;
1296 
1297  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1298  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1299 
1300  int64_t OverlapA =
1301  KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1302  int64_t OverlapB =
1303  KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1304 
1305  return !AA->isNoAlias(
1306  MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1307  MemoryLocation(ValB, OverlapB,
1308  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1309 }
1310 
1312  bool UseTBAA) const {
1313  const MachineFunction *MF = getMF();
1314  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1315  const MachineFrameInfo &MFI = MF->getFrameInfo();
1316 
1317  // Exclude call instruction which may alter the memory but can not be handled
1318  // by this function.
1319  if (isCall() || Other.isCall())
1320  return true;
1321 
1322  // If neither instruction stores to memory, they can't alias in any
1323  // meaningful way, even if they read from the same address.
1324  if (!mayStore() && !Other.mayStore())
1325  return false;
1326 
1327  // Both instructions must be memory operations to be able to alias.
1328  if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1329  return false;
1330 
1331  // Let the target decide if memory accesses cannot possibly overlap.
1333  return false;
1334 
1335  // Memory operations without memory operands may access anything. Be
1336  // conservative and assume `MayAlias`.
1337  if (memoperands_empty() || Other.memoperands_empty())
1338  return true;
1339 
1340  // Skip if there are too many memory operands.
1341  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1342  if (NumChecks > TII->getMemOperandAACheckLimit())
1343  return true;
1344 
1345  // Check each pair of memory operands from both instructions, which can't
1346  // alias only if all pairs won't alias.
1347  for (auto *MMOa : memoperands())
1348  for (auto *MMOb : Other.memoperands())
1349  if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1350  return true;
1351 
1352  return false;
1353 }
1354 
1355 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1356 /// or volatile memory reference, or if the information describing the memory
1357 /// reference is not available. Return false if it is known to have no ordered
1358 /// memory references.
1360  // An instruction known never to access memory won't have a volatile access.
1361  if (!mayStore() &&
1362  !mayLoad() &&
1363  !isCall() &&
1365  return false;
1366 
1367  // Otherwise, if the instruction has no memory reference information,
1368  // conservatively assume it wasn't preserved.
1369  if (memoperands_empty())
1370  return true;
1371 
1372  // Check if any of our memory operands are ordered.
1373  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1374  return !MMO->isUnordered();
1375  });
1376 }
1377 
1378 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1379 /// trap and is loading from a location whose value is invariant across a run of
1380 /// this function.
1382  // If the instruction doesn't load at all, it isn't an invariant load.
1383  if (!mayLoad())
1384  return false;
1385 
1386  // If the instruction has lost its memoperands, conservatively assume that
1387  // it may not be an invariant load.
1388  if (memoperands_empty())
1389  return false;
1390 
1391  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1392 
1393  for (MachineMemOperand *MMO : memoperands()) {
1394  if (!MMO->isUnordered())
1395  // If the memory operand has ordering side effects, we can't move the
1396  // instruction. Such an instruction is technically an invariant load,
1397  // but the caller code would need updated to expect that.
1398  return false;
1399  if (MMO->isStore()) return false;
1400  if (MMO->isInvariant() && MMO->isDereferenceable())
1401  continue;
1402 
1403  // A load from a constant PseudoSourceValue is invariant.
1404  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1405  if (PSV->isConstant(&MFI))
1406  continue;
1407 
1408  if (const Value *V = MMO->getValue()) {
1409  // If we have an AliasAnalysis, ask it whether the memory is constant.
1410  if (AA &&
1412  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1413  continue;
1414  }
1415 
1416  // Otherwise assume conservatively.
1417  return false;
1418  }
1419 
1420  // Everything checks out.
1421  return true;
1422 }
1423 
1424 /// isConstantValuePHI - If the specified instruction is a PHI that always
1425 /// merges together the same virtual register, return the register, otherwise
1426 /// return 0.
1428  if (!isPHI())
1429  return 0;
1430  assert(getNumOperands() >= 3 &&
1431  "It's illegal to have a PHI without source operands");
1432 
1433  Register Reg = getOperand(1).getReg();
1434  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1435  if (getOperand(i).getReg() != Reg)
1436  return 0;
1437  return Reg;
1438 }
1439 
1442  return true;
1443  if (isInlineAsm()) {
1444  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1445  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1446  return true;
1447  }
1448 
1449  return false;
1450 }
1451 
1453  return mayStore() || isCall() ||
1455 }
1456 
1457 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1458 ///
1460  for (const MachineOperand &MO : operands()) {
1461  if (!MO.isReg() || MO.isUse())
1462  continue;
1463  if (!MO.isDead())
1464  return false;
1465  }
1466  return true;
1467 }
1468 
1469 /// copyImplicitOps - Copy implicit register operands from specified
1470 /// instruction to this instruction.
1472  const MachineInstr &MI) {
1473  for (const MachineOperand &MO :
1474  llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1475  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1476  addOperand(MF, MO);
1477 }
1478 
1480  const MCInstrDesc &MCID = getDesc();
1481  if (MCID.Opcode == TargetOpcode::STATEPOINT)
1482  return true;
1483  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1484  const auto &Operand = getOperand(I);
1485  if (!Operand.isReg() || Operand.isDef())
1486  // Ignore the defined registers as MCID marks only the uses as tied.
1487  continue;
1488  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1489  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1490  if (ExpectedTiedIdx != TiedIdx)
1491  return true;
1492  }
1493  return false;
1494 }
1495 
1496 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1497  const MachineRegisterInfo &MRI) const {
1498  const MachineOperand &Op = getOperand(OpIdx);
1499  if (!Op.isReg())
1500  return LLT{};
1501 
1502  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1503  return MRI.getType(Op.getReg());
1504 
1505  auto &OpInfo = getDesc().OpInfo[OpIdx];
1506  if (!OpInfo.isGenericType())
1507  return MRI.getType(Op.getReg());
1508 
1509  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1510  return LLT{};
1511 
1512  LLT TypeToPrint = MRI.getType(Op.getReg());
1513  // Don't mark the type index printed if it wasn't actually printed: maybe
1514  // another operand with the same type index has an actual type attached:
1515  if (TypeToPrint.isValid())
1516  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1517  return TypeToPrint;
1518 }
1519 
1520 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1522  dbgs() << " ";
1523  print(dbgs());
1524 }
1525 
1526 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1527  const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1528  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1529  if (Depth >= MaxDepth)
1530  return;
1531  if (!AlreadySeenInstrs.insert(this).second)
1532  return;
1533  // PadToColumn always inserts at least one space.
1534  // Don't mess up the alignment if we don't want any space.
1535  if (Depth)
1536  fdbgs().PadToColumn(Depth * 2);
1537  print(fdbgs());
1538  for (const MachineOperand &MO : operands()) {
1539  if (!MO.isReg() || MO.isDef())
1540  continue;
1541  Register Reg = MO.getReg();
1542  if (Reg.isPhysical())
1543  continue;
1544  const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1545  if (NewMI == nullptr)
1546  continue;
1547  NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1548  }
1549 }
1550 
1552  unsigned MaxDepth) const {
1553  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1554  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1555 }
1556 #endif
1557 
1558 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1559  bool SkipDebugLoc, bool AddNewLine,
1560  const TargetInstrInfo *TII) const {
1561  const Module *M = nullptr;
1562  const Function *F = nullptr;
1563  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1564  F = &MF->getFunction();
1565  M = F->getParent();
1566  if (!TII)
1567  TII = MF->getSubtarget().getInstrInfo();
1568  }
1569 
1570  ModuleSlotTracker MST(M);
1571  if (F)
1572  MST.incorporateFunction(*F);
1573  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1574 }
1575 
1577  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1578  bool AddNewLine, const TargetInstrInfo *TII) const {
1579  // We can be a bit tidier if we know the MachineFunction.
1580  const TargetRegisterInfo *TRI = nullptr;
1581  const MachineRegisterInfo *MRI = nullptr;
1582  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1583  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1584 
1585  if (isCFIInstruction())
1586  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1587 
1588  SmallBitVector PrintedTypes(8);
1589  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1590  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1591  if (!ShouldPrintRegisterTies)
1592  return 0U;
1593  const MachineOperand &MO = getOperand(OpIdx);
1594  if (MO.isReg() && MO.isTied() && !MO.isDef())
1595  return findTiedOperandIdx(OpIdx);
1596  return 0U;
1597  };
1598  unsigned StartOp = 0;
1599  unsigned e = getNumOperands();
1600 
1601  // Print explicitly defined operands on the left of an assignment syntax.
1602  while (StartOp < e) {
1603  const MachineOperand &MO = getOperand(StartOp);
1604  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1605  break;
1606 
1607  if (StartOp != 0)
1608  OS << ", ";
1609 
1610  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1611  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1612  MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1613  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1614  ++StartOp;
1615  }
1616 
1617  if (StartOp != 0)
1618  OS << " = ";
1619 
1621  OS << "frame-setup ";
1623  OS << "frame-destroy ";
1625  OS << "nnan ";
1627  OS << "ninf ";
1629  OS << "nsz ";
1631  OS << "arcp ";
1633  OS << "contract ";
1635  OS << "afn ";
1637  OS << "reassoc ";
1639  OS << "nuw ";
1641  OS << "nsw ";
1643  OS << "exact ";
1645  OS << "nofpexcept ";
1647  OS << "nomerge ";
1648 
1649  // Print the opcode name.
1650  if (TII)
1651  OS << TII->getName(getOpcode());
1652  else
1653  OS << "UNKNOWN";
1654 
1655  if (SkipOpers)
1656  return;
1657 
1658  // Print the rest of the operands.
1659  bool FirstOp = true;
1660  unsigned AsmDescOp = ~0u;
1661  unsigned AsmOpCount = 0;
1662 
1664  // Print asm string.
1665  OS << " ";
1666  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1667  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1668  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1669  getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1670  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1671  IntrinsicInfo);
1672 
1673  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1674  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1675  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1676  OS << " [sideeffect]";
1677  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1678  OS << " [mayload]";
1679  if (ExtraInfo & InlineAsm::Extra_MayStore)
1680  OS << " [maystore]";
1681  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1682  OS << " [isconvergent]";
1683  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1684  OS << " [alignstack]";
1686  OS << " [attdialect]";
1688  OS << " [inteldialect]";
1689 
1690  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1691  FirstOp = false;
1692  }
1693 
1694  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1695  const MachineOperand &MO = getOperand(i);
1696 
1697  if (FirstOp) FirstOp = false; else OS << ",";
1698  OS << " ";
1699 
1700  if (isDebugValue() && MO.isMetadata()) {
1701  // Pretty print DBG_VALUE* instructions.
1702  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1703  if (DIV && !DIV->getName().empty())
1704  OS << "!\"" << DIV->getName() << '\"';
1705  else {
1706  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1707  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1708  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1709  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1710  }
1711  } else if (isDebugLabel() && MO.isMetadata()) {
1712  // Pretty print DBG_LABEL instructions.
1713  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1714  if (DIL && !DIL->getName().empty())
1715  OS << "\"" << DIL->getName() << '\"';
1716  else {
1717  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1718  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1719  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1720  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1721  }
1722  } else if (i == AsmDescOp && MO.isImm()) {
1723  // Pretty print the inline asm operand descriptor.
1724  OS << '$' << AsmOpCount++;
1725  unsigned Flag = MO.getImm();
1726  OS << ":[";
1728 
1729  unsigned RCID = 0;
1732  if (TRI) {
1733  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1734  } else
1735  OS << ":RC" << RCID;
1736  }
1737 
1738  if (InlineAsm::isMemKind(Flag)) {
1739  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1740  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1741  }
1742 
1743  unsigned TiedTo = 0;
1745  OS << " tiedto:$" << TiedTo;
1746 
1747  OS << ']';
1748 
1749  // Compute the index of the next operand descriptor.
1750  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1751  } else {
1752  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1753  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1754  if (MO.isImm() && isOperandSubregIdx(i))
1756  else
1757  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1758  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1759  }
1760  }
1761 
1762  // Print any optional symbols attached to this instruction as-if they were
1763  // operands.
1764  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1765  if (!FirstOp) {
1766  FirstOp = false;
1767  OS << ',';
1768  }
1769  OS << " pre-instr-symbol ";
1770  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1771  }
1772  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1773  if (!FirstOp) {
1774  FirstOp = false;
1775  OS << ',';
1776  }
1777  OS << " post-instr-symbol ";
1778  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1779  }
1780  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1781  if (!FirstOp) {
1782  FirstOp = false;
1783  OS << ',';
1784  }
1785  OS << " heap-alloc-marker ";
1786  HeapAllocMarker->printAsOperand(OS, MST);
1787  }
1788 
1789  if (DebugInstrNum) {
1790  if (!FirstOp)
1791  OS << ",";
1792  OS << " debug-instr-number " << DebugInstrNum;
1793  }
1794 
1795  if (!SkipDebugLoc) {
1796  if (const DebugLoc &DL = getDebugLoc()) {
1797  if (!FirstOp)
1798  OS << ',';
1799  OS << " debug-location ";
1800  DL->printAsOperand(OS, MST);
1801  }
1802  }
1803 
1804  if (!memoperands_empty()) {
1806  const LLVMContext *Context = nullptr;
1807  std::unique_ptr<LLVMContext> CtxPtr;
1808  const MachineFrameInfo *MFI = nullptr;
1809  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1810  MFI = &MF->getFrameInfo();
1811  Context = &MF->getFunction().getContext();
1812  } else {
1813  CtxPtr = std::make_unique<LLVMContext>();
1814  Context = CtxPtr.get();
1815  }
1816 
1817  OS << " :: ";
1818  bool NeedComma = false;
1819  for (const MachineMemOperand *Op : memoperands()) {
1820  if (NeedComma)
1821  OS << ", ";
1822  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1823  NeedComma = true;
1824  }
1825  }
1826 
1827  if (SkipDebugLoc)
1828  return;
1829 
1830  bool HaveSemi = false;
1831 
1832  // Print debug location information.
1833  if (const DebugLoc &DL = getDebugLoc()) {
1834  if (!HaveSemi) {
1835  OS << ';';
1836  HaveSemi = true;
1837  }
1838  OS << ' ';
1839  DL.print(OS);
1840  }
1841 
1842  // Print extra comments for DEBUG_VALUE.
1843  if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1844  if (!HaveSemi) {
1845  OS << ";";
1846  HaveSemi = true;
1847  }
1848  auto *DV = getDebugVariable();
1849  OS << " line no:" << DV->getLine();
1850  if (isIndirectDebugValue())
1851  OS << " indirect";
1852  }
1853  // TODO: DBG_LABEL
1854 
1855  if (AddNewLine)
1856  OS << '\n';
1857 }
1858 
1860  const TargetRegisterInfo *RegInfo,
1861  bool AddIfNotFound) {
1862  bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1863  bool hasAliases = isPhysReg &&
1864  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1865  bool Found = false;
1866  SmallVector<unsigned,4> DeadOps;
1867  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1868  MachineOperand &MO = getOperand(i);
1869  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1870  continue;
1871 
1872  // DEBUG_VALUE nodes do not contribute to code generation and should
1873  // always be ignored. Failure to do so may result in trying to modify
1874  // KILL flags on DEBUG_VALUE nodes.
1875  if (MO.isDebug())
1876  continue;
1877 
1878  Register Reg = MO.getReg();
1879  if (!Reg)
1880  continue;
1881 
1882  if (Reg == IncomingReg) {
1883  if (!Found) {
1884  if (MO.isKill())
1885  // The register is already marked kill.
1886  return true;
1887  if (isPhysReg && isRegTiedToDefOperand(i))
1888  // Two-address uses of physregs must not be marked kill.
1889  return true;
1890  MO.setIsKill();
1891  Found = true;
1892  }
1893  } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1894  // A super-register kill already exists.
1895  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1896  return true;
1897  if (RegInfo->isSubRegister(IncomingReg, Reg))
1898  DeadOps.push_back(i);
1899  }
1900  }
1901 
1902  // Trim unneeded kill operands.
1903  while (!DeadOps.empty()) {
1904  unsigned OpIdx = DeadOps.back();
1905  if (getOperand(OpIdx).isImplicit() &&
1906  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1907  RemoveOperand(OpIdx);
1908  else
1909  getOperand(OpIdx).setIsKill(false);
1910  DeadOps.pop_back();
1911  }
1912 
1913  // If not found, this means an alias of one of the operands is killed. Add a
1914  // new implicit operand if required.
1915  if (!Found && AddIfNotFound) {
1917  false /*IsDef*/,
1918  true /*IsImp*/,
1919  true /*IsKill*/));
1920  return true;
1921  }
1922  return Found;
1923 }
1924 
1926  const TargetRegisterInfo *RegInfo) {
1928  RegInfo = nullptr;
1929  for (MachineOperand &MO : operands()) {
1930  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1931  continue;
1932  Register OpReg = MO.getReg();
1933  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1934  MO.setIsKill(false);
1935  }
1936 }
1937 
1939  const TargetRegisterInfo *RegInfo,
1940  bool AddIfNotFound) {
1941  bool isPhysReg = Register::isPhysicalRegister(Reg);
1942  bool hasAliases = isPhysReg &&
1943  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1944  bool Found = false;
1945  SmallVector<unsigned,4> DeadOps;
1946  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1947  MachineOperand &MO = getOperand(i);
1948  if (!MO.isReg() || !MO.isDef())
1949  continue;
1950  Register MOReg = MO.getReg();
1951  if (!MOReg)
1952  continue;
1953 
1954  if (MOReg == Reg) {
1955  MO.setIsDead();
1956  Found = true;
1957  } else if (hasAliases && MO.isDead() &&
1959  // There exists a super-register that's marked dead.
1960  if (RegInfo->isSuperRegister(Reg, MOReg))
1961  return true;
1962  if (RegInfo->isSubRegister(Reg, MOReg))
1963  DeadOps.push_back(i);
1964  }
1965  }
1966 
1967  // Trim unneeded dead operands.
1968  while (!DeadOps.empty()) {
1969  unsigned OpIdx = DeadOps.back();
1970  if (getOperand(OpIdx).isImplicit() &&
1971  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1972  RemoveOperand(OpIdx);
1973  else
1974  getOperand(OpIdx).setIsDead(false);
1975  DeadOps.pop_back();
1976  }
1977 
1978  // If not found, this means an alias of one of the operands is dead. Add a
1979  // new implicit operand if required.
1980  if (Found || !AddIfNotFound)
1981  return Found;
1982 
1984  true /*IsDef*/,
1985  true /*IsImp*/,
1986  false /*IsKill*/,
1987  true /*IsDead*/));
1988  return true;
1989 }
1990 
1992  for (MachineOperand &MO : operands()) {
1993  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1994  continue;
1995  MO.setIsDead(false);
1996  }
1997 }
1998 
2000  for (MachineOperand &MO : operands()) {
2001  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2002  continue;
2003  MO.setIsUndef(IsUndef);
2004  }
2005 }
2006 
2008  const TargetRegisterInfo *RegInfo) {
2010  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2011  if (MO)
2012  return;
2013  } else {
2014  for (const MachineOperand &MO : operands()) {
2015  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2016  MO.getSubReg() == 0)
2017  return;
2018  }
2019  }
2021  true /*IsDef*/,
2022  true /*IsImp*/));
2023 }
2024 
2026  const TargetRegisterInfo &TRI) {
2027  bool HasRegMask = false;
2028  for (MachineOperand &MO : operands()) {
2029  if (MO.isRegMask()) {
2030  HasRegMask = true;
2031  continue;
2032  }
2033  if (!MO.isReg() || !MO.isDef()) continue;
2034  Register Reg = MO.getReg();
2035  if (!Reg.isPhysical())
2036  continue;
2037  // If there are no uses, including partial uses, the def is dead.
2038  if (llvm::none_of(UsedRegs,
2039  [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2040  MO.setIsDead();
2041  }
2042 
2043  // This is a call with a register mask operand.
2044  // Mask clobbers are always dead, so add defs for the non-dead defines.
2045  if (HasRegMask)
2046  for (const Register &UsedReg : UsedRegs)
2047  addRegisterDefined(UsedReg, &TRI);
2048 }
2049 
2050 unsigned
2052  // Build up a buffer of hash code components.
2053  SmallVector<size_t, 16> HashComponents;
2054  HashComponents.reserve(MI->getNumOperands() + 1);
2055  HashComponents.push_back(MI->getOpcode());
2056  for (const MachineOperand &MO : MI->operands()) {
2057  if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2058  continue; // Skip virtual register defs.
2059 
2060  HashComponents.push_back(hash_value(MO));
2061  }
2062  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2063 }
2064 
2066  // Find the source location cookie.
2067  uint64_t LocCookie = 0;
2068  const MDNode *LocMD = nullptr;
2069  for (unsigned i = getNumOperands(); i != 0; --i) {
2070  if (getOperand(i-1).isMetadata() &&
2071  (LocMD = getOperand(i-1).getMetadata()) &&
2072  LocMD->getNumOperands() != 0) {
2073  if (const ConstantInt *CI =
2074  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2075  LocCookie = CI->getZExtValue();
2076  break;
2077  }
2078  }
2079  }
2080 
2081  if (const MachineBasicBlock *MBB = getParent())
2082  if (const MachineFunction *MF = MBB->getParent())
2083  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2084  report_fatal_error(Msg);
2085 }
2086 
2088  const MCInstrDesc &MCID, bool IsIndirect,
2089  Register Reg, const MDNode *Variable,
2090  const MDNode *Expr) {
2091  assert(isa<DILocalVariable>(Variable) && "not a variable");
2092  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2093  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2094  "Expected inlined-at fields to agree");
2095  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2096  if (IsIndirect)
2097  MIB.addImm(0U);
2098  else
2099  MIB.addReg(0U);
2100  return MIB.addMetadata(Variable).addMetadata(Expr);
2101 }
2102 
2104  const MCInstrDesc &MCID, bool IsIndirect,
2105  const MachineOperand &MO,
2106  const MDNode *Variable, const MDNode *Expr) {
2107  assert(isa<DILocalVariable>(Variable) && "not a variable");
2108  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2109  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2110  "Expected inlined-at fields to agree");
2111  if (MO.isReg())
2112  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2113 
2114  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2115  if (IsIndirect)
2116  MIB.addImm(0U);
2117  else
2118  MIB.addReg(0U);
2119  return MIB.addMetadata(Variable).addMetadata(Expr);
2120 }
2121 
2123  const MCInstrDesc &MCID, bool IsIndirect,
2125  const MDNode *Variable, const MDNode *Expr) {
2126  assert(isa<DILocalVariable>(Variable) && "not a variable");
2127  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2128  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2129  "Expected inlined-at fields to agree");
2130  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2131  return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2132 
2133  auto MIB = BuildMI(MF, DL, MCID);
2134  MIB.addMetadata(Variable).addMetadata(Expr);
2135  for (const MachineOperand &MO : MOs)
2136  if (MO.isReg())
2137  MIB.addReg(MO.getReg());
2138  else
2139  MIB.add(MO);
2140  return MIB;
2141 }
2142 
2145  const DebugLoc &DL, const MCInstrDesc &MCID,
2146  bool IsIndirect, Register Reg,
2147  const MDNode *Variable, const MDNode *Expr) {
2148  MachineFunction &MF = *BB.getParent();
2149  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2150  BB.insert(I, MI);
2151  return MachineInstrBuilder(MF, MI);
2152 }
2153 
2156  const DebugLoc &DL, const MCInstrDesc &MCID,
2157  bool IsIndirect, MachineOperand &MO,
2158  const MDNode *Variable, const MDNode *Expr) {
2159  MachineFunction &MF = *BB.getParent();
2160  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2161  BB.insert(I, MI);
2162  return MachineInstrBuilder(MF, *MI);
2163 }
2164 
2167  const DebugLoc &DL, const MCInstrDesc &MCID,
2168  bool IsIndirect, ArrayRef<MachineOperand> MOs,
2169  const MDNode *Variable, const MDNode *Expr) {
2170  MachineFunction &MF = *BB.getParent();
2171  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2172  BB.insert(I, MI);
2173  return MachineInstrBuilder(MF, *MI);
2174 }
2175 
2176 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2177 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2178 static const DIExpression *
2180  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2181  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2182  "Expected inlined-at fields to agree");
2183 
2184  const DIExpression *Expr = MI.getDebugExpression();
2185  if (MI.isIndirectDebugValue()) {
2186  assert(MI.getDebugOffset().getImm() == 0 &&
2187  "DBG_VALUE with nonzero offset");
2189  } else if (MI.isDebugValueList()) {
2190  // We will replace the spilled register with a frame index, so
2191  // immediately deref all references to the spilled register.
2192  std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2193  for (const MachineOperand *Op : SpilledOperands) {
2194  unsigned OpIdx = MI.getDebugOperandIndex(Op);
2195  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2196  }
2197  }
2198  return Expr;
2199 }
2201  Register SpillReg) {
2202  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2204  for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2205  SpillOperands.push_back(&Op);
2206  return computeExprForSpill(MI, SpillOperands);
2207 }
2208 
2211  const MachineInstr &Orig,
2212  int FrameIndex, Register SpillReg) {
2213  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2214  MachineInstrBuilder NewMI =
2215  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2216  // Non-Variadic Operands: Location, Offset, Variable, Expression
2217  // Variadic Operands: Variable, Expression, Locations...
2218  if (Orig.isNonListDebugValue())
2219  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2220  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2221  if (Orig.isDebugValueList()) {
2222  for (const MachineOperand &Op : Orig.debug_operands())
2223  if (Op.isReg() && Op.getReg() == SpillReg)
2224  NewMI.addFrameIndex(FrameIndex);
2225  else
2226  NewMI.add(MachineOperand(Op));
2227  }
2228  return NewMI;
2229 }
2232  const MachineInstr &Orig, int FrameIndex,
2233  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2234  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2235  MachineInstrBuilder NewMI =
2236  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2237  // Non-Variadic Operands: Location, Offset, Variable, Expression
2238  // Variadic Operands: Variable, Expression, Locations...
2239  if (Orig.isNonListDebugValue())
2240  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2241  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2242  if (Orig.isDebugValueList()) {
2243  for (const MachineOperand &Op : Orig.debug_operands())
2244  if (is_contained(SpilledOperands, &Op))
2245  NewMI.addFrameIndex(FrameIndex);
2246  else
2247  NewMI.add(MachineOperand(Op));
2248  }
2249  return NewMI;
2250 }
2251 
2253  Register Reg) {
2254  const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2255  if (Orig.isNonListDebugValue())
2256  Orig.getDebugOffset().ChangeToImmediate(0U);
2258  Op.ChangeToFrameIndex(FrameIndex);
2259  Orig.getDebugExpressionOp().setMetadata(Expr);
2260 }
2261 
2263  SmallVectorImpl<MachineInstr *> &DbgValues) {
2264  MachineInstr &MI = *this;
2265  if (!MI.getOperand(0).isReg())
2266  return;
2267 
2268  MachineBasicBlock::iterator DI = MI; ++DI;
2269  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2270  DI != DE; ++DI) {
2271  if (!DI->isDebugValue())
2272  return;
2273  if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2274  DbgValues.push_back(&*DI);
2275  }
2276 }
2277 
2279  // Collect matching debug values.
2281 
2282  if (!getOperand(0).isReg())
2283  return;
2284 
2285  Register DefReg = getOperand(0).getReg();
2286  auto *MRI = getRegInfo();
2287  for (auto &MO : MRI->use_operands(DefReg)) {
2288  auto *DI = MO.getParent();
2289  if (!DI->isDebugValue())
2290  continue;
2291  if (DI->hasDebugOperandForReg(DefReg)) {
2292  DbgValues.push_back(DI);
2293  }
2294  }
2295 
2296  // Propagate Reg to debug value instructions.
2297  for (auto *DBI : DbgValues)
2298  for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2299  Op.setReg(Reg);
2300 }
2301 
2303 
2304 static unsigned getSpillSlotSize(const MMOList &Accesses,
2305  const MachineFrameInfo &MFI) {
2306  unsigned Size = 0;
2307  for (auto A : Accesses)
2308  if (MFI.isSpillSlotObjectIndex(
2309  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2310  ->getFrameIndex()))
2311  Size += A->getSize();
2312  return Size;
2313 }
2314 
2317  int FI;
2318  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2319  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2320  if (MFI.isSpillSlotObjectIndex(FI))
2321  return (*memoperands_begin())->getSize();
2322  }
2323  return None;
2324 }
2325 
2328  MMOList Accesses;
2329  if (TII->hasStoreToStackSlot(*this, Accesses))
2330  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2331  return None;
2332 }
2333 
2336  int FI;
2337  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2338  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2339  if (MFI.isSpillSlotObjectIndex(FI))
2340  return (*memoperands_begin())->getSize();
2341  }
2342  return None;
2343 }
2344 
2347  MMOList Accesses;
2348  if (TII->hasLoadFromStackSlot(*this, Accesses))
2349  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2350  return None;
2351 }
2352 
2354  if (DebugInstrNum == 0)
2355  DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2356  return DebugInstrNum;
2357 }
2358 
2360  if (DebugInstrNum == 0)
2361  DebugInstrNum = MF.getNewDebugInstrNum();
2362  return DebugInstrNum;
2363 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1305
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1210
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:751
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:842
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
CmpMode::FP
@ FP
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:365
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:1991
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2025
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2353
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1938
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:170
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1663
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:321
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2051
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
Metadata.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1215
Loads.h
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:640
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1028
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:709
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:708
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:741
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:537
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:395
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:306
llvm::InlineAsm::AD_ATT
@ AD_ATT
Definition: InlineAsm.h:34
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:675
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1229
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:731
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1142
InlineAsm.h
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:227
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::AAResults::isNoAlias
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Definition: AliasAnalysis.h:561
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:409
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:742
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1197
MachineBasicBlock.h
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2007
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1459
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1427
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:684
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:350
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MachineFunction::getNewDebugInstrNum
unsigned getNewDebugInstrNum()
Definition: MachineFunction.h:1233
Module.h
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:384
TargetInstrInfo.h
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:98
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4761
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:963
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:469
llvm::FastMathFlags::noSignedZeros
bool noSignedZeros() const
Definition: Operator.h:213
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:666
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::Optional< unsigned >
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:801
llvm::SmallPtrSet< const MachineInstr *, 16 >
Operator.h
Hashing.h
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:797
hasIdenticalMMOs
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
Definition: MachineInstr.cpp:416
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:238
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:849
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:165
llvm::FastMathFlags::noNaNs
bool noNaNs() const
Definition: Operator.h:211
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4821
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:258
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:304
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::PossiblyExactOperator
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:125
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:329
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:385
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:821
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1359
MachineRegisterInfo.h
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1552
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:567
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:582
llvm::MDNode::getNumOperands
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1143
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1298
AliasAnalysis.h
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1109
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:521
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:325
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:539
CommandLine.h
FormattedStream.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:153
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:231
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1321
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
getSpillSlotSize
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
Definition: MachineInstr.cpp:2304
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:228
llvm::FastMathFlags::approxFunc
bool approxFunc() const
Definition: Operator.h:216
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:508
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:947
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:243
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:204
Constants.h
llvm::AAResults
Definition: AliasAnalysis.h:507
SmallString.h
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3104
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1471
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:657
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:374
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:211
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
Intrinsics.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2209
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2327
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1185
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:562
InstrTypes.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1140
llvm::fdbgs
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
Definition: FormattedStream.cpp:152
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:427
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:225
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1311
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
MCSymbol.h
llvm::FastMathFlags::allowReassoc
bool allowReassoc() const
Flag queries.
Definition: Operator.h:210
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:670
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:769
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1216
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:104
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:224
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition: MachineInstr.cpp:81
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1859
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:90
llvm::FastMathFlags::allowReciprocal
bool allowReciprocal() const
Definition: Operator.h:214
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:230
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:346
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:240
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1192
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:703
MachineInstrBundle.h
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:951
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:197
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:214
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:778
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:478
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:595
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:776
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:104
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1452
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1551
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:92
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:193
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1204
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:333
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:285
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:767
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:759
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:646
llvm::MDNode::getOperand
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1137
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:575
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:108
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:592
llvm::MachineFunction::deallocateOperandArray
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
Definition: MachineFunction.h:988
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:248
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1496
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:423
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:555
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::FastMathFlags::noInfs
bool noInfs() const
Definition: Operator.h:212
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:35
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2065
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:854
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:726
uint64_t
llvm::MachineFunction::createMIExtraInfo
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
Definition: MachineFunction.cpp:512
TiedMax
const unsigned TiedMax
Definition: MachineInstr.cpp:1068
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2252
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1939
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:826
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:393
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:100
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MemoryLocation.h
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:233
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:1999
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:284
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
MCRegisterInfo.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1714
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:768
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::make_pointee_range
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2262
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:339
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:760
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1925
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2804
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:232
llvm::FPMathOperator
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:265
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1707
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:995
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.h:2915
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:715
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:337
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:345
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1249
MachineModuleInfo.h
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:787
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1381
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:528
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:588
llvm::DebugLoc::hasTrivialDestructor
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1144
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1521
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:685
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:838
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:106
llvm::InlineAsm::MIOp_AsmString
@ MIOp_AsmString
Definition: InlineAsm.h:223
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:793
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition: MachineInstr.cpp:90
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:967
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1255
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1820
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:523
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:753
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2346
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:511
Compiler.h
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1052
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:110
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1558
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:847
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1213
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:729
llvm::OverflowingBinaryOperator
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:71
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:414
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1202
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:863
MemOperandsHaveAlias
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
Definition: MachineInstr.cpp:1244
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1193
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:884
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
FoldingSet.h
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:931
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
std
Definition: BitVector.h:838
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:531
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:359
uint16_t
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:349
moveOperands
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
Definition: MachineInstr.cpp:194
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:517
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1440
llvm::Module::getContext
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:259
Casting.h
llvm::MachineFunction::allocateOperandArray
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
Definition: MachineFunction.h:981
Function.h
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:858
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:256
StackMaps.h
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:690
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:96
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:686
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:239
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:397
llvm::AAResults::pointsToConstantMemory
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Definition: AliasAnalysis.cpp:163
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:720
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1281
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
computeExprForSpill
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
Definition: MachineInstr.cpp:2179
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1214
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:656
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:217
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1024
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:344
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:102
RegisterBank.h
TargetIntrinsicInfo.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
SmallBitVector.h
N
#define N
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:401
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::hash_combine_range
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:483
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:366
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:94
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:690
ModuleSlotTracker.h
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1479
llvm::SmallVectorImpl< unsigned >
llvm::MachineBasicBlock::erase_instr
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.h:918
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
DerivedTypes.h
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2335
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:902
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1143
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3194
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1253
LLVMContext.h
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:402
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:332
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FastMathFlags::allowContract
bool allowContract() const
Definition: Operator.h:215
raw_ostream.h
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1082
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1038
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:634
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1207
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1452
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
Value.h
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:173
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:765
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:975
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1303
TargetRegisterInfo.h
Debug.h
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:229
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:493
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:559
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:209
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2316
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:728
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:335
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1198
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:287
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:205
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2278
llvm::LLT
Definition: LowLevelTypeImpl.h:39