LLVM  13.0.0git
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/Analysis/Loads.h"
37 #include "llvm/CodeGen/StackMaps.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/InstrTypes.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Module.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/Value.h"
57 #include "llvm/MC/MCInstrDesc.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/Compiler.h"
63 #include "llvm/Support/Debug.h"
71 #include <algorithm>
72 #include <cassert>
73 #include <cstddef>
74 #include <cstdint>
75 #include <cstring>
76 #include <iterator>
77 #include <utility>
78 
79 using namespace llvm;
80 
82  if (const MachineBasicBlock *MBB = MI.getParent())
83  if (const MachineFunction *MF = MBB->getParent())
84  return MF;
85  return nullptr;
86 }
87 
88 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 // it.
90 static void tryToGetTargetInfo(const MachineInstr &MI,
91  const TargetRegisterInfo *&TRI,
92  const MachineRegisterInfo *&MRI,
93  const TargetIntrinsicInfo *&IntrinsicInfo,
94  const TargetInstrInfo *&TII) {
95 
96  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97  TRI = MF->getSubtarget().getRegisterInfo();
98  MRI = &MF->getRegInfo();
99  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100  TII = MF->getSubtarget().getInstrInfo();
101  }
102 }
103 
105  if (MCID->ImplicitDefs)
106  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107  ++ImpDefs)
108  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109  if (MCID->ImplicitUses)
110  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111  ++ImpUses)
112  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 }
114 
115 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116 /// implicit operands. It reserves space for the number of operands specified by
117 /// the MCInstrDesc.
118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119  DebugLoc dl, bool NoImp)
120  : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
122 
123  // Reserve space for the expected number of operands.
124  if (unsigned NumOps = MCID->getNumOperands() +
125  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126  CapOperands = OperandCapacity::get(NumOps);
127  Operands = MF.allocateOperandArray(CapOperands);
128  }
129 
130  if (!NoImp)
132 }
133 
134 /// MachineInstr ctor - Copies MachineInstr arg exactly.
135 /// Does not copy the number from debug instruction numbering, to preserve
136 /// uniqueness.
137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138  : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139  DebugInstrNum(0) {
140  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
141 
142  CapOperands = OperandCapacity::get(MI.getNumOperands());
143  Operands = MF.allocateOperandArray(CapOperands);
144 
145  // Copy operands.
146  for (const MachineOperand &MO : MI.operands())
147  addOperand(MF, MO);
148 
149  // Copy all the sensible flags.
150  setFlags(MI.Flags);
151 }
152 
154  MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155 }
156 
157 /// getRegInfo - If this instruction is embedded into a MachineFunction,
158 /// return the MachineRegisterInfo object for the current function, otherwise
159 /// return null.
160 MachineRegisterInfo *MachineInstr::getRegInfo() {
162  return &MBB->getParent()->getRegInfo();
163  return nullptr;
164 }
165 
166 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167 /// this instruction from their respective use lists. This requires that the
168 /// operands already be on their use lists.
169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170  for (MachineOperand &MO : operands())
171  if (MO.isReg())
173 }
174 
175 /// AddRegOperandsToUseLists - Add all of the register operands in
176 /// this instruction from their respective use lists. This requires that the
177 /// operands not be on their use lists yet.
178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179  for (MachineOperand &MO : operands())
180  if (MO.isReg())
182 }
183 
186  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
187  MachineFunction *MF = MBB->getParent();
188  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
189  addOperand(*MF, Op);
190 }
191 
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193 /// ranges. If MRI is non-null also update use-def chains.
195  unsigned NumOps, MachineRegisterInfo *MRI) {
196  if (MRI)
197  return MRI->moveOperands(Dst, Src, NumOps);
198  // MachineOperand is a trivially copyable type so we can just use memmove.
199  assert(Dst && Src && "Unknown operands");
200  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201 }
202 
203 /// addOperand - Add the specified operand to the instruction. If it is an
204 /// implicit operand, it is added to the end of the operand list. If it is
205 /// an explicit operand it is added at the end of the explicit operand list
206 /// (before the first implicit operand).
208  assert(MCID && "Cannot add operands before providing an instr descriptor");
209 
210  // Check if we're adding one of our existing operands.
211  if (&Op >= Operands && &Op < Operands + NumOperands) {
212  // This is unusual: MI->addOperand(MI->getOperand(i)).
213  // If adding Op requires reallocating or moving existing operands around,
214  // the Op reference could go stale. Support it by copying Op.
215  MachineOperand CopyOp(Op);
216  return addOperand(MF, CopyOp);
217  }
218 
219  // Find the insert location for the new operand. Implicit registers go at
220  // the end, everything else goes before the implicit regs.
221  //
222  // FIXME: Allow mixed explicit and implicit operands on inline asm.
223  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224  // implicit-defs, but they must not be moved around. See the FIXME in
225  // InstrEmitter.cpp.
226  unsigned OpNo = getNumOperands();
227  bool isImpReg = Op.isReg() && Op.isImplicit();
228  if (!isImpReg && !isInlineAsm()) {
229  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230  --OpNo;
231  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
232  }
233  }
234 
235 #ifndef NDEBUG
236  bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237  Op.getType() == MachineOperand::MO_MCSymbol;
238  // OpNo now points as the desired insertion point. Unless this is a variadic
239  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240  // RegMask operands go between the explicit and implicit operands.
241  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
242  OpNo < MCID->getNumOperands() || isDebugOp) &&
243  "Trying to add an operand to a machine instr that is already done!");
244 #endif
245 
246  MachineRegisterInfo *MRI = getRegInfo();
247 
248  // Determine if the Operands array needs to be reallocated.
249  // Save the old capacity and operand array.
250  OperandCapacity OldCap = CapOperands;
251  MachineOperand *OldOperands = Operands;
252  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254  Operands = MF.allocateOperandArray(CapOperands);
255  // Move the operands before the insertion point.
256  if (OpNo)
257  moveOperands(Operands, OldOperands, OpNo, MRI);
258  }
259 
260  // Move the operands following the insertion point.
261  if (OpNo != NumOperands)
262  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263  MRI);
264  ++NumOperands;
265 
266  // Deallocate the old operand array.
267  if (OldOperands != Operands && OldOperands)
268  MF.deallocateOperandArray(OldCap, OldOperands);
269 
270  // Copy Op into place. It still needs to be inserted into the MRI use lists.
271  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272  NewMO->ParentMI = this;
273 
274  // When adding a register operand, tell MRI about it.
275  if (NewMO->isReg()) {
276  // Ensure isOnRegUseList() returns false, regardless of Op's status.
277  NewMO->Contents.Reg.Prev = nullptr;
278  // Ignore existing ties. This is not a property that can be copied.
279  NewMO->TiedTo = 0;
280  // Add the new operand to MRI, but only for instructions in an MBB.
281  if (MRI)
282  MRI->addRegOperandToUseList(NewMO);
283  // The MCID operand information isn't accurate until we start adding
284  // explicit operands. The implicit operands are added first, then the
285  // explicits are inserted before them.
286  if (!isImpReg) {
287  // Tie uses to defs as indicated in MCInstrDesc.
288  if (NewMO->isUse()) {
289  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290  if (DefIdx != -1)
291  tieOperands(DefIdx, OpNo);
292  }
293  // If the register operand is flagged as early, mark the operand as such.
294  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295  NewMO->setIsEarlyClobber(true);
296  }
297  }
298 }
299 
300 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
301 /// fewer operand than it started with.
302 ///
303 void MachineInstr::RemoveOperand(unsigned OpNo) {
304  assert(OpNo < getNumOperands() && "Invalid operand number");
305  untieRegOperand(OpNo);
306 
307 #ifndef NDEBUG
308  // Moving tied operands would break the ties.
309  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
310  if (Operands[i].isReg())
311  assert(!Operands[i].isTied() && "Cannot move tied operands");
312 #endif
313 
314  MachineRegisterInfo *MRI = getRegInfo();
315  if (MRI && Operands[OpNo].isReg())
316  MRI->removeRegOperandFromUseList(Operands + OpNo);
317 
318  // Don't call the MachineOperand destructor. A lot of this code depends on
319  // MachineOperand having a trivial destructor anyway, and adding a call here
320  // wouldn't make it 'destructor-correct'.
321 
322  if (unsigned N = NumOperands - 1 - OpNo)
323  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
324  --NumOperands;
325 }
326 
327 void MachineInstr::setExtraInfo(MachineFunction &MF,
329  MCSymbol *PreInstrSymbol,
330  MCSymbol *PostInstrSymbol,
331  MDNode *HeapAllocMarker) {
332  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
333  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
334  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
335  int NumPointers =
336  MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
337 
338  // Drop all extra info if there is none.
339  if (NumPointers <= 0) {
340  Info.clear();
341  return;
342  }
343 
344  // If more than one pointer, then store out of line. Store heap alloc markers
345  // out of line because PointerSumType cannot hold more than 4 tag types with
346  // 32-bit pointers.
347  // FIXME: Maybe we should make the symbols in the extra info mutable?
348  else if (NumPointers > 1 || HasHeapAllocMarker) {
349  Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
350  MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
351  return;
352  }
353 
354  // Otherwise store the single pointer inline.
355  if (HasPreInstrSymbol)
356  Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
357  else if (HasPostInstrSymbol)
358  Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
359  else
360  Info.set<EIIK_MMO>(MMOs[0]);
361 }
362 
364  if (memoperands_empty())
365  return;
366 
367  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
369 }
370 
373  if (MMOs.empty()) {
374  dropMemRefs(MF);
375  return;
376  }
377 
378  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
380 }
381 
383  MachineMemOperand *MO) {
386  MMOs.push_back(MO);
387  setMemRefs(MF, MMOs);
388 }
389 
391  if (this == &MI)
392  // Nothing to do for a self-clone!
393  return;
394 
395  assert(&MF == MI.getMF() &&
396  "Invalid machine functions when cloning memory refrences!");
397  // See if we can just steal the extra info already allocated for the
398  // instruction. We can do this whenever the pre- and post-instruction symbols
399  // are the same (including null).
400  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
401  getPostInstrSymbol() == MI.getPostInstrSymbol() &&
402  getHeapAllocMarker() == MI.getHeapAllocMarker()) {
403  Info = MI.Info;
404  return;
405  }
406 
407  // Otherwise, fall back on a copy-based clone.
408  setMemRefs(MF, MI.memoperands());
409 }
410 
411 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
412 /// identical.
415  if (LHS.size() != RHS.size())
416  return false;
417 
418  auto LHSPointees = make_pointee_range(LHS);
419  auto RHSPointees = make_pointee_range(RHS);
420  return std::equal(LHSPointees.begin(), LHSPointees.end(),
421  RHSPointees.begin());
422 }
423 
426  // Try handling easy numbers of MIs with simpler mechanisms.
427  if (MIs.empty()) {
428  dropMemRefs(MF);
429  return;
430  }
431  if (MIs.size() == 1) {
432  cloneMemRefs(MF, *MIs[0]);
433  return;
434  }
435  // Because an empty memoperands list provides *no* information and must be
436  // handled conservatively (assuming the instruction can do anything), the only
437  // way to merge with it is to drop all other memoperands.
438  if (MIs[0]->memoperands_empty()) {
439  dropMemRefs(MF);
440  return;
441  }
442 
443  // Handle the general case.
445  // Start with the first instruction.
446  assert(&MF == MIs[0]->getMF() &&
447  "Invalid machine functions when cloning memory references!");
448  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
449  // Now walk all the other instructions and accumulate any different MMOs.
450  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
451  assert(&MF == MI.getMF() &&
452  "Invalid machine functions when cloning memory references!");
453 
454  // Skip MIs with identical operands to the first. This is a somewhat
455  // arbitrary hack but will catch common cases without being quadratic.
456  // TODO: We could fully implement merge semantics here if needed.
457  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
458  continue;
459 
460  // Because an empty memoperands list provides *no* information and must be
461  // handled conservatively (assuming the instruction can do anything), the
462  // only way to merge with it is to drop all other memoperands.
463  if (MI.memoperands_empty()) {
464  dropMemRefs(MF);
465  return;
466  }
467 
468  // Otherwise accumulate these into our temporary buffer of the merged state.
469  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
470  }
471 
472  setMemRefs(MF, MergedMMOs);
473 }
474 
476  // Do nothing if old and new symbols are the same.
477  if (Symbol == getPreInstrSymbol())
478  return;
479 
480  // If there was only one symbol and we're removing it, just clear info.
481  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
482  Info.clear();
483  return;
484  }
485 
486  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
488 }
489 
491  // Do nothing if old and new symbols are the same.
492  if (Symbol == getPostInstrSymbol())
493  return;
494 
495  // If there was only one symbol and we're removing it, just clear info.
496  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
497  Info.clear();
498  return;
499  }
500 
501  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
503 }
504 
506  // Do nothing if old and new symbols are the same.
507  if (Marker == getHeapAllocMarker())
508  return;
509 
510  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
511  Marker);
512 }
513 
515  const MachineInstr &MI) {
516  if (this == &MI)
517  // Nothing to do for a self-clone!
518  return;
519 
520  assert(&MF == MI.getMF() &&
521  "Invalid machine functions when cloning instruction symbols!");
522 
523  setPreInstrSymbol(MF, MI.getPreInstrSymbol());
524  setPostInstrSymbol(MF, MI.getPostInstrSymbol());
525  setHeapAllocMarker(MF, MI.getHeapAllocMarker());
526 }
527 
529  // For now, the just return the union of the flags. If the flags get more
530  // complicated over time, we might need more logic here.
531  return getFlags() | Other.getFlags();
532 }
533 
535  uint16_t MIFlags = 0;
536  // Copy the wrapping flags.
537  if (const OverflowingBinaryOperator *OB =
538  dyn_cast<OverflowingBinaryOperator>(&I)) {
539  if (OB->hasNoSignedWrap())
540  MIFlags |= MachineInstr::MIFlag::NoSWrap;
541  if (OB->hasNoUnsignedWrap())
542  MIFlags |= MachineInstr::MIFlag::NoUWrap;
543  }
544 
545  // Copy the exact flag.
546  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
547  if (PE->isExact())
548  MIFlags |= MachineInstr::MIFlag::IsExact;
549 
550  // Copy the fast-math flags.
551  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
552  const FastMathFlags Flags = FP->getFastMathFlags();
553  if (Flags.noNaNs())
554  MIFlags |= MachineInstr::MIFlag::FmNoNans;
555  if (Flags.noInfs())
556  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
557  if (Flags.noSignedZeros())
558  MIFlags |= MachineInstr::MIFlag::FmNsz;
559  if (Flags.allowReciprocal())
560  MIFlags |= MachineInstr::MIFlag::FmArcp;
561  if (Flags.allowContract())
562  MIFlags |= MachineInstr::MIFlag::FmContract;
563  if (Flags.approxFunc())
564  MIFlags |= MachineInstr::MIFlag::FmAfn;
565  if (Flags.allowReassoc())
566  MIFlags |= MachineInstr::MIFlag::FmReassoc;
567  }
568 
569  return MIFlags;
570 }
571 
573  Flags = copyFlagsFromInstruction(I);
574 }
575 
576 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
577  assert(!isBundledWithPred() && "Must be called on bundle header");
579  if (MII->getDesc().getFlags() & Mask) {
580  if (Type == AnyInBundle)
581  return true;
582  } else {
583  if (Type == AllInBundle && !MII->isBundle())
584  return false;
585  }
586  // This was the last instruction in the bundle.
587  if (!MII->isBundledWithSucc())
588  return Type == AllInBundle;
589  }
590 }
591 
593  MICheckType Check) const {
594  // If opcodes or number of operands are not the same then the two
595  // instructions are obviously not identical.
596  if (Other.getOpcode() != getOpcode() ||
597  Other.getNumOperands() != getNumOperands())
598  return false;
599 
600  if (isBundle()) {
601  // We have passed the test above that both instructions have the same
602  // opcode, so we know that both instructions are bundles here. Let's compare
603  // MIs inside the bundle.
604  assert(Other.isBundle() && "Expected that both instructions are bundles.");
607  // Loop until we analysed the last intruction inside at least one of the
608  // bundles.
609  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
610  ++I1;
611  ++I2;
612  if (!I1->isIdenticalTo(*I2, Check))
613  return false;
614  }
615  // If we've reached the end of just one of the two bundles, but not both,
616  // the instructions are not identical.
617  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
618  return false;
619  }
620 
621  // Check operands to make sure they match.
622  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
623  const MachineOperand &MO = getOperand(i);
624  const MachineOperand &OMO = Other.getOperand(i);
625  if (!MO.isReg()) {
626  if (!MO.isIdenticalTo(OMO))
627  return false;
628  continue;
629  }
630 
631  // Clients may or may not want to ignore defs when testing for equality.
632  // For example, machine CSE pass only cares about finding common
633  // subexpressions, so it's safe to ignore virtual register defs.
634  if (MO.isDef()) {
635  if (Check == IgnoreDefs)
636  continue;
637  else if (Check == IgnoreVRegDefs) {
638  if (!Register::isVirtualRegister(MO.getReg()) ||
640  if (!MO.isIdenticalTo(OMO))
641  return false;
642  } else {
643  if (!MO.isIdenticalTo(OMO))
644  return false;
645  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
646  return false;
647  }
648  } else {
649  if (!MO.isIdenticalTo(OMO))
650  return false;
651  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
652  return false;
653  }
654  }
655  // If DebugLoc does not match then two debug instructions are not identical.
656  if (isDebugInstr())
657  if (getDebugLoc() && Other.getDebugLoc() &&
658  getDebugLoc() != Other.getDebugLoc())
659  return false;
660  return true;
661 }
662 
664  return getParent()->getParent();
665 }
666 
668  assert(getParent() && "Not embedded in a basic block!");
669  return getParent()->remove(this);
670 }
671 
673  assert(getParent() && "Not embedded in a basic block!");
674  return getParent()->remove_instr(this);
675 }
676 
678  assert(getParent() && "Not embedded in a basic block!");
679  getParent()->erase(this);
680 }
681 
683  assert(getParent() && "Not embedded in a basic block!");
685  MachineFunction *MF = MBB->getParent();
686  assert(MF && "Not embedded in a function!");
687 
688  MachineInstr *MI = (MachineInstr *)this;
690 
691  for (const MachineOperand &MO : MI->operands()) {
692  if (!MO.isReg() || !MO.isDef())
693  continue;
694  Register Reg = MO.getReg();
695  if (!Reg.isVirtual())
696  continue;
698  }
699  MI->eraseFromParent();
700 }
701 
703  assert(getParent() && "Not embedded in a basic block!");
704  getParent()->erase_instr(this);
705 }
706 
708  if (!isCall(Type))
709  return false;
710  switch (getOpcode()) {
711  case TargetOpcode::PATCHPOINT:
712  case TargetOpcode::STACKMAP:
713  case TargetOpcode::STATEPOINT:
714  case TargetOpcode::FENTRY_CALL:
715  return false;
716  }
717  return true;
718 }
719 
721  if (isBundle())
724 }
725 
727  unsigned NumOperands = MCID->getNumOperands();
728  if (!MCID->isVariadic())
729  return NumOperands;
730 
731  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
732  const MachineOperand &MO = getOperand(I);
733  // The operands must always be in the following order:
734  // - explicit reg defs,
735  // - other explicit operands (reg uses, immediates, etc.),
736  // - implicit reg defs
737  // - implicit reg uses
738  if (MO.isReg() && MO.isImplicit())
739  break;
740  ++NumOperands;
741  }
742  return NumOperands;
743 }
744 
746  unsigned NumDefs = MCID->getNumDefs();
747  if (!MCID->isVariadic())
748  return NumDefs;
749 
750  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
751  const MachineOperand &MO = getOperand(I);
752  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
753  break;
754  ++NumDefs;
755  }
756  return NumDefs;
757 }
758 
760  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
763  --Pred;
764  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
765  Pred->setFlag(BundledSucc);
766 }
767 
769  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
772  ++Succ;
773  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
774  Succ->setFlag(BundledPred);
775 }
776 
778  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
781  --Pred;
782  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
783  Pred->clearFlag(BundledSucc);
784 }
785 
787  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
790  ++Succ;
791  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
792  Succ->clearFlag(BundledPred);
793 }
794 
796  if (isInlineAsm()) {
797  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
798  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
799  return true;
800  }
801  return false;
802 }
803 
805  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
806  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
807  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
808 }
809 
811  unsigned *GroupNo) const {
812  assert(isInlineAsm() && "Expected an inline asm instruction");
813  assert(OpIdx < getNumOperands() && "OpIdx out of range");
814 
815  // Ignore queries about the initial operands.
816  if (OpIdx < InlineAsm::MIOp_FirstOperand)
817  return -1;
818 
819  unsigned Group = 0;
820  unsigned NumOps;
821  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
822  i += NumOps) {
823  const MachineOperand &FlagMO = getOperand(i);
824  // If we reach the implicit register operands, stop looking.
825  if (!FlagMO.isImm())
826  return -1;
827  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
828  if (i + NumOps > OpIdx) {
829  if (GroupNo)
830  *GroupNo = Group;
831  return i;
832  }
833  ++Group;
834  }
835  return -1;
836 }
837 
839  assert(isDebugLabel() && "not a DBG_LABEL");
840  return cast<DILabel>(getOperand(0).getMetadata());
841 }
842 
844  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
845  unsigned VariableOp = isDebugValueList() ? 0 : 2;
846  return getOperand(VariableOp);
847 }
848 
850  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
851  unsigned VariableOp = isDebugValueList() ? 0 : 2;
852  return getOperand(VariableOp);
853 }
854 
856  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
857 }
858 
860  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
861  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
862  return getOperand(ExpressionOp);
863 }
864 
866  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
867  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
868  return getOperand(ExpressionOp);
869 }
870 
872  return cast<DIExpression>(getDebugExpressionOp().getMetadata());
873 }
874 
877 }
878 
879 const TargetRegisterClass*
881  const TargetInstrInfo *TII,
882  const TargetRegisterInfo *TRI) const {
883  assert(getParent() && "Can't have an MBB reference here!");
884  assert(getMF() && "Can't have an MF reference here!");
885  const MachineFunction &MF = *getMF();
886 
887  // Most opcodes have fixed constraints in their MCInstrDesc.
888  if (!isInlineAsm())
889  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
890 
891  if (!getOperand(OpIdx).isReg())
892  return nullptr;
893 
894  // For tied uses on inline asm, get the constraint from the def.
895  unsigned DefIdx;
896  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
897  OpIdx = DefIdx;
898 
899  // Inline asm stores register class constraints in the flag word.
900  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
901  if (FlagIdx < 0)
902  return nullptr;
903 
904  unsigned Flag = getOperand(FlagIdx).getImm();
905  unsigned RCID;
910  return TRI->getRegClass(RCID);
911 
912  // Assume that all registers in a memory operand are pointers.
914  return TRI->getPointerRegClass(MF);
915 
916  return nullptr;
917 }
918 
920  Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
921  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
922  // Check every operands inside the bundle if we have
923  // been asked to.
924  if (ExploreBundle)
925  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
926  ++OpndIt)
927  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
928  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
929  else
930  // Otherwise, just check the current operands.
931  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
932  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
933  return CurRC;
934 }
935 
936 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
937  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
938  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
939  assert(CurRC && "Invalid initial register class");
940  // Check if Reg is constrained by some of its use/def from MI.
941  const MachineOperand &MO = getOperand(OpIdx);
942  if (!MO.isReg() || MO.getReg() != Reg)
943  return CurRC;
944  // If yes, accumulate the constraints through the operand.
945  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
946 }
947 
949  unsigned OpIdx, const TargetRegisterClass *CurRC,
950  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
951  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
952  const MachineOperand &MO = getOperand(OpIdx);
953  assert(MO.isReg() &&
954  "Cannot get register constraints for non-register operand");
955  assert(CurRC && "Invalid initial register class");
956  if (unsigned SubIdx = MO.getSubReg()) {
957  if (OpRC)
958  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
959  else
960  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
961  } else if (OpRC)
962  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
963  return CurRC;
964 }
965 
966 /// Return the number of instructions inside the MI bundle, not counting the
967 /// header instruction.
968 unsigned MachineInstr::getBundleSize() const {
970  unsigned Size = 0;
971  while (I->isBundledWithSucc()) {
972  ++Size;
973  ++I;
974  }
975  return Size;
976 }
977 
978 /// Returns true if the MachineInstr has an implicit-use operand of exactly
979 /// the given register (not considering sub/super-registers).
981  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982  const MachineOperand &MO = getOperand(i);
983  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
984  return true;
985  }
986  return false;
987 }
988 
989 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
990 /// the specific register or -1 if it is not found. It further tightens
991 /// the search criteria to a use that kills the register if isKill is true.
993  Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
994  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
995  const MachineOperand &MO = getOperand(i);
996  if (!MO.isReg() || !MO.isUse())
997  continue;
998  Register MOReg = MO.getReg();
999  if (!MOReg)
1000  continue;
1001  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1002  if (!isKill || MO.isKill())
1003  return i;
1004  }
1005  return -1;
1006 }
1007 
1008 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1009 /// indicating if this instruction reads or writes Reg. This also considers
1010 /// partial defines.
1011 std::pair<bool,bool>
1013  SmallVectorImpl<unsigned> *Ops) const {
1014  bool PartDef = false; // Partial redefine.
1015  bool FullDef = false; // Full define.
1016  bool Use = false;
1017 
1018  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1019  const MachineOperand &MO = getOperand(i);
1020  if (!MO.isReg() || MO.getReg() != Reg)
1021  continue;
1022  if (Ops)
1023  Ops->push_back(i);
1024  if (MO.isUse())
1025  Use |= !MO.isUndef();
1026  else if (MO.getSubReg() && !MO.isUndef())
1027  // A partial def undef doesn't count as reading the register.
1028  PartDef = true;
1029  else
1030  FullDef = true;
1031  }
1032  // A partial redefine uses Reg unless there is also a full define.
1033  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1034 }
1035 
1036 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1037 /// the specified register or -1 if it is not found. If isDead is true, defs
1038 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1039 /// also checks if there is a def of a super-register.
1040 int
1042  const TargetRegisterInfo *TRI) const {
1043  bool isPhys = Register::isPhysicalRegister(Reg);
1044  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1045  const MachineOperand &MO = getOperand(i);
1046  // Accept regmask operands when Overlap is set.
1047  // Ignore them when looking for a specific def operand (Overlap == false).
1048  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1049  return i;
1050  if (!MO.isReg() || !MO.isDef())
1051  continue;
1052  Register MOReg = MO.getReg();
1053  bool Found = (MOReg == Reg);
1054  if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1055  if (Overlap)
1056  Found = TRI->regsOverlap(MOReg, Reg);
1057  else
1058  Found = TRI->isSubRegister(MOReg, Reg);
1059  }
1060  if (Found && (!isDead || MO.isDead()))
1061  return i;
1062  }
1063  return -1;
1064 }
1065 
1066 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1067 /// operand list that is used to represent the predicate. It returns -1 if
1068 /// none is found.
1070  // Don't call MCID.findFirstPredOperandIdx() because this variant
1071  // is sometimes called on an instruction that's not yet complete, and
1072  // so the number of operands is less than the MCID indicates. In
1073  // particular, the PTX target does this.
1074  const MCInstrDesc &MCID = getDesc();
1075  if (MCID.isPredicable()) {
1076  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1077  if (MCID.OpInfo[i].isPredicate())
1078  return i;
1079  }
1080 
1081  return -1;
1082 }
1083 
1084 // MachineOperand::TiedTo is 4 bits wide.
1085 const unsigned TiedMax = 15;
1086 
1087 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1088 ///
1089 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1090 /// field. TiedTo can have these values:
1091 ///
1092 /// 0: Operand is not tied to anything.
1093 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1094 /// TiedMax: Tied to an operand >= TiedMax-1.
1095 ///
1096 /// The tied def must be one of the first TiedMax operands on a normal
1097 /// instruction. INLINEASM instructions allow more tied defs.
1098 ///
1099 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1100  MachineOperand &DefMO = getOperand(DefIdx);
1101  MachineOperand &UseMO = getOperand(UseIdx);
1102  assert(DefMO.isDef() && "DefIdx must be a def operand");
1103  assert(UseMO.isUse() && "UseIdx must be a use operand");
1104  assert(!DefMO.isTied() && "Def is already tied to another use");
1105  assert(!UseMO.isTied() && "Use is already tied to another def");
1106 
1107  if (DefIdx < TiedMax)
1108  UseMO.TiedTo = DefIdx + 1;
1109  else {
1110  // Inline asm can use the group descriptors to find tied operands,
1111  // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1112  // but on normal instruction, the tied def must be within the first TiedMax
1113  // operands.
1114  assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1115  "DefIdx out of range");
1116  UseMO.TiedTo = TiedMax;
1117  }
1118 
1119  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1120  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1121 }
1122 
1123 /// Given the index of a tied register operand, find the operand it is tied to.
1124 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1125 /// which must exist.
1126 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1127  const MachineOperand &MO = getOperand(OpIdx);
1128  assert(MO.isTied() && "Operand isn't tied");
1129 
1130  // Normally TiedTo is in range.
1131  if (MO.TiedTo < TiedMax)
1132  return MO.TiedTo - 1;
1133 
1134  // Uses on normal instructions can be out of range.
1135  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1136  // Normal tied defs must be in the 0..TiedMax-1 range.
1137  if (MO.isUse())
1138  return TiedMax - 1;
1139  // MO is a def. Search for the tied use.
1140  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1141  const MachineOperand &UseMO = getOperand(i);
1142  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1143  return i;
1144  }
1145  llvm_unreachable("Can't find tied use");
1146  }
1147 
1148  if (getOpcode() == TargetOpcode::STATEPOINT) {
1149  // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1150  // on registers.
1151  StatepointOpers SO(this);
1152  unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1153  assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1154  unsigned NumDefs = getNumDefs();
1155  for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1156  while (!getOperand(CurUseIdx).isReg())
1157  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1158  if (OpIdx == CurDefIdx)
1159  return CurUseIdx;
1160  if (OpIdx == CurUseIdx)
1161  return CurDefIdx;
1162  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1163  }
1164  llvm_unreachable("Can't find tied use");
1165  }
1166 
1167  // Now deal with inline asm by parsing the operand group descriptor flags.
1168  // Find the beginning of each operand group.
1169  SmallVector<unsigned, 8> GroupIdx;
1170  unsigned OpIdxGroup = ~0u;
1171  unsigned NumOps;
1172  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1173  i += NumOps) {
1174  const MachineOperand &FlagMO = getOperand(i);
1175  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1176  unsigned CurGroup = GroupIdx.size();
1177  GroupIdx.push_back(i);
1178  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1179  // OpIdx belongs to this operand group.
1180  if (OpIdx > i && OpIdx < i + NumOps)
1181  OpIdxGroup = CurGroup;
1182  unsigned TiedGroup;
1183  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1184  continue;
1185  // Operands in this group are tied to operands in TiedGroup which must be
1186  // earlier. Find the number of operands between the two groups.
1187  unsigned Delta = i - GroupIdx[TiedGroup];
1188 
1189  // OpIdx is a use tied to TiedGroup.
1190  if (OpIdxGroup == CurGroup)
1191  return OpIdx - Delta;
1192 
1193  // OpIdx is a def tied to this use group.
1194  if (OpIdxGroup == TiedGroup)
1195  return OpIdx + Delta;
1196  }
1197  llvm_unreachable("Invalid tied operand on inline asm");
1198 }
1199 
1200 /// clearKillInfo - Clears kill flags on all operands.
1201 ///
1203  for (MachineOperand &MO : operands()) {
1204  if (MO.isReg() && MO.isUse())
1205  MO.setIsKill(false);
1206  }
1207 }
1208 
1210  unsigned SubIdx,
1211  const TargetRegisterInfo &RegInfo) {
1212  if (Register::isPhysicalRegister(ToReg)) {
1213  if (SubIdx)
1214  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1215  for (MachineOperand &MO : operands()) {
1216  if (!MO.isReg() || MO.getReg() != FromReg)
1217  continue;
1218  MO.substPhysReg(ToReg, RegInfo);
1219  }
1220  } else {
1221  for (MachineOperand &MO : operands()) {
1222  if (!MO.isReg() || MO.getReg() != FromReg)
1223  continue;
1224  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1225  }
1226  }
1227 }
1228 
1229 /// isSafeToMove - Return true if it is safe to move this instruction. If
1230 /// SawStore is set to true, it means that there is a store (or call) between
1231 /// the instruction's location and its intended destination.
1232 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1233  // Ignore stuff that we obviously can't move.
1234  //
1235  // Treat volatile loads as stores. This is not strictly necessary for
1236  // volatiles, but it is required for atomic loads. It is not allowed to move
1237  // a load across an atomic load with Ordering > Monotonic.
1238  if (mayStore() || isCall() || isPHI() ||
1239  (mayLoad() && hasOrderedMemoryRef())) {
1240  SawStore = true;
1241  return false;
1242  }
1243 
1244  if (isPosition() || isDebugInstr() || isTerminator() ||
1246  return false;
1247 
1248  // See if this instruction does a load. If so, we have to guarantee that the
1249  // loaded value doesn't change between the load and the its intended
1250  // destination. The check for isInvariantLoad gives the target the chance to
1251  // classify the load as always returning a constant, e.g. a constant pool
1252  // load.
1254  // Otherwise, this is a real load. If there is a store between the load and
1255  // end of block, we can't move it.
1256  return !SawStore;
1257 
1258  return true;
1259 }
1260 
1262  bool UseTBAA, const MachineMemOperand *MMOa,
1263  const MachineMemOperand *MMOb) {
1264  // The following interface to AA is fashioned after DAGCombiner::isAlias and
1265  // operates with MachineMemOperand offset with some important assumptions:
1266  // - LLVM fundamentally assumes flat address spaces.
1267  // - MachineOperand offset can *only* result from legalization and cannot
1268  // affect queries other than the trivial case of overlap checking.
1269  // - These offsets never wrap and never step outside of allocated objects.
1270  // - There should never be any negative offsets here.
1271  //
1272  // FIXME: Modify API to hide this math from "user"
1273  // Even before we go to AA we can reason locally about some memory objects. It
1274  // can save compile time, and possibly catch some corner cases not currently
1275  // covered.
1276 
1277  int64_t OffsetA = MMOa->getOffset();
1278  int64_t OffsetB = MMOb->getOffset();
1279  int64_t MinOffset = std::min(OffsetA, OffsetB);
1280 
1281  uint64_t WidthA = MMOa->getSize();
1282  uint64_t WidthB = MMOb->getSize();
1283  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1284  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1285 
1286  const Value *ValA = MMOa->getValue();
1287  const Value *ValB = MMOb->getValue();
1288  bool SameVal = (ValA && ValB && (ValA == ValB));
1289  if (!SameVal) {
1290  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1291  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1292  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1293  return false;
1294  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1295  return false;
1296  if (PSVa && PSVb && (PSVa == PSVb))
1297  SameVal = true;
1298  }
1299 
1300  if (SameVal) {
1301  if (!KnownWidthA || !KnownWidthB)
1302  return true;
1303  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1304  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1305  return (MinOffset + LowWidth > MaxOffset);
1306  }
1307 
1308  if (!AA)
1309  return true;
1310 
1311  if (!ValA || !ValB)
1312  return true;
1313 
1314  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1315  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1316 
1317  int64_t OverlapA =
1318  KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1319  int64_t OverlapB =
1320  KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1321 
1322  return !AA->isNoAlias(
1323  MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1324  MemoryLocation(ValB, OverlapB,
1325  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1326 }
1327 
1329  bool UseTBAA) const {
1330  const MachineFunction *MF = getMF();
1331  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1332  const MachineFrameInfo &MFI = MF->getFrameInfo();
1333 
1334  // Exclude call instruction which may alter the memory but can not be handled
1335  // by this function.
1336  if (isCall() || Other.isCall())
1337  return true;
1338 
1339  // If neither instruction stores to memory, they can't alias in any
1340  // meaningful way, even if they read from the same address.
1341  if (!mayStore() && !Other.mayStore())
1342  return false;
1343 
1344  // Both instructions must be memory operations to be able to alias.
1345  if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1346  return false;
1347 
1348  // Let the target decide if memory accesses cannot possibly overlap.
1350  return false;
1351 
1352  // Memory operations without memory operands may access anything. Be
1353  // conservative and assume `MayAlias`.
1354  if (memoperands_empty() || Other.memoperands_empty())
1355  return true;
1356 
1357  // Skip if there are too many memory operands.
1358  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1359  if (NumChecks > TII->getMemOperandAACheckLimit())
1360  return true;
1361 
1362  // Check each pair of memory operands from both instructions, which can't
1363  // alias only if all pairs won't alias.
1364  for (auto *MMOa : memoperands())
1365  for (auto *MMOb : Other.memoperands())
1366  if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1367  return true;
1368 
1369  return false;
1370 }
1371 
1372 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1373 /// or volatile memory reference, or if the information describing the memory
1374 /// reference is not available. Return false if it is known to have no ordered
1375 /// memory references.
1377  // An instruction known never to access memory won't have a volatile access.
1378  if (!mayStore() &&
1379  !mayLoad() &&
1380  !isCall() &&
1382  return false;
1383 
1384  // Otherwise, if the instruction has no memory reference information,
1385  // conservatively assume it wasn't preserved.
1386  if (memoperands_empty())
1387  return true;
1388 
1389  // Check if any of our memory operands are ordered.
1390  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1391  return !MMO->isUnordered();
1392  });
1393 }
1394 
1395 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1396 /// trap and is loading from a location whose value is invariant across a run of
1397 /// this function.
1399  // If the instruction doesn't load at all, it isn't an invariant load.
1400  if (!mayLoad())
1401  return false;
1402 
1403  // If the instruction has lost its memoperands, conservatively assume that
1404  // it may not be an invariant load.
1405  if (memoperands_empty())
1406  return false;
1407 
1408  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1409 
1410  for (MachineMemOperand *MMO : memoperands()) {
1411  if (!MMO->isUnordered())
1412  // If the memory operand has ordering side effects, we can't move the
1413  // instruction. Such an instruction is technically an invariant load,
1414  // but the caller code would need updated to expect that.
1415  return false;
1416  if (MMO->isStore()) return false;
1417  if (MMO->isInvariant() && MMO->isDereferenceable())
1418  continue;
1419 
1420  // A load from a constant PseudoSourceValue is invariant.
1421  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1422  if (PSV->isConstant(&MFI))
1423  continue;
1424 
1425  if (const Value *V = MMO->getValue()) {
1426  // If we have an AliasAnalysis, ask it whether the memory is constant.
1427  if (AA &&
1429  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1430  continue;
1431  }
1432 
1433  // Otherwise assume conservatively.
1434  return false;
1435  }
1436 
1437  // Everything checks out.
1438  return true;
1439 }
1440 
1441 /// isConstantValuePHI - If the specified instruction is a PHI that always
1442 /// merges together the same virtual register, return the register, otherwise
1443 /// return 0.
1445  if (!isPHI())
1446  return 0;
1447  assert(getNumOperands() >= 3 &&
1448  "It's illegal to have a PHI without source operands");
1449 
1450  Register Reg = getOperand(1).getReg();
1451  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1452  if (getOperand(i).getReg() != Reg)
1453  return 0;
1454  return Reg;
1455 }
1456 
1459  return true;
1460  if (isInlineAsm()) {
1461  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1462  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1463  return true;
1464  }
1465 
1466  return false;
1467 }
1468 
1470  return mayStore() || isCall() ||
1472 }
1473 
1474 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1475 ///
1477  for (const MachineOperand &MO : operands()) {
1478  if (!MO.isReg() || MO.isUse())
1479  continue;
1480  if (!MO.isDead())
1481  return false;
1482  }
1483  return true;
1484 }
1485 
1486 /// copyImplicitOps - Copy implicit register operands from specified
1487 /// instruction to this instruction.
1489  const MachineInstr &MI) {
1490  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1491  i != e; ++i) {
1492  const MachineOperand &MO = MI.getOperand(i);
1493  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1494  addOperand(MF, MO);
1495  }
1496 }
1497 
1499  const MCInstrDesc &MCID = getDesc();
1500  if (MCID.Opcode == TargetOpcode::STATEPOINT)
1501  return true;
1502  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1503  const auto &Operand = getOperand(I);
1504  if (!Operand.isReg() || Operand.isDef())
1505  // Ignore the defined registers as MCID marks only the uses as tied.
1506  continue;
1507  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1508  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1509  if (ExpectedTiedIdx != TiedIdx)
1510  return true;
1511  }
1512  return false;
1513 }
1514 
1515 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1516  const MachineRegisterInfo &MRI) const {
1517  const MachineOperand &Op = getOperand(OpIdx);
1518  if (!Op.isReg())
1519  return LLT{};
1520 
1521  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1522  return MRI.getType(Op.getReg());
1523 
1524  auto &OpInfo = getDesc().OpInfo[OpIdx];
1525  if (!OpInfo.isGenericType())
1526  return MRI.getType(Op.getReg());
1527 
1528  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1529  return LLT{};
1530 
1531  LLT TypeToPrint = MRI.getType(Op.getReg());
1532  // Don't mark the type index printed if it wasn't actually printed: maybe
1533  // another operand with the same type index has an actual type attached:
1534  if (TypeToPrint.isValid())
1535  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1536  return TypeToPrint;
1537 }
1538 
1539 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1541  dbgs() << " ";
1542  print(dbgs());
1543 }
1544 
1545 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1546  const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1547  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1548  if (Depth >= MaxDepth)
1549  return;
1550  if (!AlreadySeenInstrs.insert(this).second)
1551  return;
1552  // PadToColumn always inserts at least one space.
1553  // Don't mess up the alignment if we don't want any space.
1554  if (Depth)
1555  fdbgs().PadToColumn(Depth * 2);
1556  print(fdbgs());
1557  for (const MachineOperand &MO : operands()) {
1558  if (!MO.isReg() || MO.isDef())
1559  continue;
1560  Register Reg = MO.getReg();
1561  if (Reg.isPhysical())
1562  continue;
1563  const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1564  if (NewMI == nullptr)
1565  continue;
1566  NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1567  }
1568 }
1569 
1571  unsigned MaxDepth) const {
1572  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1573  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1574 }
1575 #endif
1576 
1577 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1578  bool SkipDebugLoc, bool AddNewLine,
1579  const TargetInstrInfo *TII) const {
1580  const Module *M = nullptr;
1581  const Function *F = nullptr;
1582  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1583  F = &MF->getFunction();
1584  M = F->getParent();
1585  if (!TII)
1586  TII = MF->getSubtarget().getInstrInfo();
1587  }
1588 
1589  ModuleSlotTracker MST(M);
1590  if (F)
1591  MST.incorporateFunction(*F);
1592  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1593 }
1594 
1596  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1597  bool AddNewLine, const TargetInstrInfo *TII) const {
1598  // We can be a bit tidier if we know the MachineFunction.
1599  const TargetRegisterInfo *TRI = nullptr;
1600  const MachineRegisterInfo *MRI = nullptr;
1601  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1602  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1603 
1604  if (isCFIInstruction())
1605  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1606 
1607  SmallBitVector PrintedTypes(8);
1608  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1609  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1610  if (!ShouldPrintRegisterTies)
1611  return 0U;
1612  const MachineOperand &MO = getOperand(OpIdx);
1613  if (MO.isReg() && MO.isTied() && !MO.isDef())
1614  return findTiedOperandIdx(OpIdx);
1615  return 0U;
1616  };
1617  unsigned StartOp = 0;
1618  unsigned e = getNumOperands();
1619 
1620  // Print explicitly defined operands on the left of an assignment syntax.
1621  while (StartOp < e) {
1622  const MachineOperand &MO = getOperand(StartOp);
1623  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1624  break;
1625 
1626  if (StartOp != 0)
1627  OS << ", ";
1628 
1629  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1630  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1631  MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1632  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1633  ++StartOp;
1634  }
1635 
1636  if (StartOp != 0)
1637  OS << " = ";
1638 
1640  OS << "frame-setup ";
1642  OS << "frame-destroy ";
1644  OS << "nnan ";
1646  OS << "ninf ";
1648  OS << "nsz ";
1650  OS << "arcp ";
1652  OS << "contract ";
1654  OS << "afn ";
1656  OS << "reassoc ";
1658  OS << "nuw ";
1660  OS << "nsw ";
1662  OS << "exact ";
1664  OS << "nofpexcept ";
1666  OS << "nomerge ";
1667 
1668  // Print the opcode name.
1669  if (TII)
1670  OS << TII->getName(getOpcode());
1671  else
1672  OS << "UNKNOWN";
1673 
1674  if (SkipOpers)
1675  return;
1676 
1677  // Print the rest of the operands.
1678  bool FirstOp = true;
1679  unsigned AsmDescOp = ~0u;
1680  unsigned AsmOpCount = 0;
1681 
1683  // Print asm string.
1684  OS << " ";
1685  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1686  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1687  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1688  getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1689  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1690  IntrinsicInfo);
1691 
1692  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1693  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1694  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1695  OS << " [sideeffect]";
1696  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1697  OS << " [mayload]";
1698  if (ExtraInfo & InlineAsm::Extra_MayStore)
1699  OS << " [maystore]";
1700  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1701  OS << " [isconvergent]";
1702  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1703  OS << " [alignstack]";
1705  OS << " [attdialect]";
1707  OS << " [inteldialect]";
1708 
1709  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1710  FirstOp = false;
1711  }
1712 
1713  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1714  const MachineOperand &MO = getOperand(i);
1715 
1716  if (FirstOp) FirstOp = false; else OS << ",";
1717  OS << " ";
1718 
1719  if (isDebugValue() && MO.isMetadata()) {
1720  // Pretty print DBG_VALUE* instructions.
1721  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1722  if (DIV && !DIV->getName().empty())
1723  OS << "!\"" << DIV->getName() << '\"';
1724  else {
1725  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1726  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1727  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1728  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1729  }
1730  } else if (isDebugLabel() && MO.isMetadata()) {
1731  // Pretty print DBG_LABEL instructions.
1732  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1733  if (DIL && !DIL->getName().empty())
1734  OS << "\"" << DIL->getName() << '\"';
1735  else {
1736  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1737  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1738  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1739  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1740  }
1741  } else if (i == AsmDescOp && MO.isImm()) {
1742  // Pretty print the inline asm operand descriptor.
1743  OS << '$' << AsmOpCount++;
1744  unsigned Flag = MO.getImm();
1745  OS << ":[";
1747 
1748  unsigned RCID = 0;
1751  if (TRI) {
1752  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1753  } else
1754  OS << ":RC" << RCID;
1755  }
1756 
1757  if (InlineAsm::isMemKind(Flag)) {
1758  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1759  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1760  }
1761 
1762  unsigned TiedTo = 0;
1764  OS << " tiedto:$" << TiedTo;
1765 
1766  OS << ']';
1767 
1768  // Compute the index of the next operand descriptor.
1769  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1770  } else {
1771  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1772  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1773  if (MO.isImm() && isOperandSubregIdx(i))
1775  else
1776  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1777  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1778  }
1779  }
1780 
1781  // Print any optional symbols attached to this instruction as-if they were
1782  // operands.
1783  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1784  if (!FirstOp) {
1785  FirstOp = false;
1786  OS << ',';
1787  }
1788  OS << " pre-instr-symbol ";
1789  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1790  }
1791  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1792  if (!FirstOp) {
1793  FirstOp = false;
1794  OS << ',';
1795  }
1796  OS << " post-instr-symbol ";
1797  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1798  }
1799  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1800  if (!FirstOp) {
1801  FirstOp = false;
1802  OS << ',';
1803  }
1804  OS << " heap-alloc-marker ";
1805  HeapAllocMarker->printAsOperand(OS, MST);
1806  }
1807 
1808  if (DebugInstrNum) {
1809  if (!FirstOp)
1810  OS << ",";
1811  OS << " debug-instr-number " << DebugInstrNum;
1812  }
1813 
1814  if (!SkipDebugLoc) {
1815  if (const DebugLoc &DL = getDebugLoc()) {
1816  if (!FirstOp)
1817  OS << ',';
1818  OS << " debug-location ";
1819  DL->printAsOperand(OS, MST);
1820  }
1821  }
1822 
1823  if (!memoperands_empty()) {
1825  const LLVMContext *Context = nullptr;
1826  std::unique_ptr<LLVMContext> CtxPtr;
1827  const MachineFrameInfo *MFI = nullptr;
1828  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1829  MFI = &MF->getFrameInfo();
1830  Context = &MF->getFunction().getContext();
1831  } else {
1832  CtxPtr = std::make_unique<LLVMContext>();
1833  Context = CtxPtr.get();
1834  }
1835 
1836  OS << " :: ";
1837  bool NeedComma = false;
1838  for (const MachineMemOperand *Op : memoperands()) {
1839  if (NeedComma)
1840  OS << ", ";
1841  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1842  NeedComma = true;
1843  }
1844  }
1845 
1846  if (SkipDebugLoc)
1847  return;
1848 
1849  bool HaveSemi = false;
1850 
1851  // Print debug location information.
1852  if (const DebugLoc &DL = getDebugLoc()) {
1853  if (!HaveSemi) {
1854  OS << ';';
1855  HaveSemi = true;
1856  }
1857  OS << ' ';
1858  DL.print(OS);
1859  }
1860 
1861  // Print extra comments for DEBUG_VALUE.
1862  if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1863  if (!HaveSemi) {
1864  OS << ";";
1865  HaveSemi = true;
1866  }
1867  auto *DV = getDebugVariable();
1868  OS << " line no:" << DV->getLine();
1869  if (isIndirectDebugValue())
1870  OS << " indirect";
1871  }
1872  // TODO: DBG_LABEL
1873 
1874  if (AddNewLine)
1875  OS << '\n';
1876 }
1877 
1879  const TargetRegisterInfo *RegInfo,
1880  bool AddIfNotFound) {
1881  bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1882  bool hasAliases = isPhysReg &&
1883  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1884  bool Found = false;
1885  SmallVector<unsigned,4> DeadOps;
1886  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1887  MachineOperand &MO = getOperand(i);
1888  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1889  continue;
1890 
1891  // DEBUG_VALUE nodes do not contribute to code generation and should
1892  // always be ignored. Failure to do so may result in trying to modify
1893  // KILL flags on DEBUG_VALUE nodes.
1894  if (MO.isDebug())
1895  continue;
1896 
1897  Register Reg = MO.getReg();
1898  if (!Reg)
1899  continue;
1900 
1901  if (Reg == IncomingReg) {
1902  if (!Found) {
1903  if (MO.isKill())
1904  // The register is already marked kill.
1905  return true;
1906  if (isPhysReg && isRegTiedToDefOperand(i))
1907  // Two-address uses of physregs must not be marked kill.
1908  return true;
1909  MO.setIsKill();
1910  Found = true;
1911  }
1912  } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1913  // A super-register kill already exists.
1914  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1915  return true;
1916  if (RegInfo->isSubRegister(IncomingReg, Reg))
1917  DeadOps.push_back(i);
1918  }
1919  }
1920 
1921  // Trim unneeded kill operands.
1922  while (!DeadOps.empty()) {
1923  unsigned OpIdx = DeadOps.back();
1924  if (getOperand(OpIdx).isImplicit() &&
1925  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1926  RemoveOperand(OpIdx);
1927  else
1928  getOperand(OpIdx).setIsKill(false);
1929  DeadOps.pop_back();
1930  }
1931 
1932  // If not found, this means an alias of one of the operands is killed. Add a
1933  // new implicit operand if required.
1934  if (!Found && AddIfNotFound) {
1936  false /*IsDef*/,
1937  true /*IsImp*/,
1938  true /*IsKill*/));
1939  return true;
1940  }
1941  return Found;
1942 }
1943 
1945  const TargetRegisterInfo *RegInfo) {
1947  RegInfo = nullptr;
1948  for (MachineOperand &MO : operands()) {
1949  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1950  continue;
1951  Register OpReg = MO.getReg();
1952  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1953  MO.setIsKill(false);
1954  }
1955 }
1956 
1958  const TargetRegisterInfo *RegInfo,
1959  bool AddIfNotFound) {
1960  bool isPhysReg = Register::isPhysicalRegister(Reg);
1961  bool hasAliases = isPhysReg &&
1962  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1963  bool Found = false;
1964  SmallVector<unsigned,4> DeadOps;
1965  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1966  MachineOperand &MO = getOperand(i);
1967  if (!MO.isReg() || !MO.isDef())
1968  continue;
1969  Register MOReg = MO.getReg();
1970  if (!MOReg)
1971  continue;
1972 
1973  if (MOReg == Reg) {
1974  MO.setIsDead();
1975  Found = true;
1976  } else if (hasAliases && MO.isDead() &&
1978  // There exists a super-register that's marked dead.
1979  if (RegInfo->isSuperRegister(Reg, MOReg))
1980  return true;
1981  if (RegInfo->isSubRegister(Reg, MOReg))
1982  DeadOps.push_back(i);
1983  }
1984  }
1985 
1986  // Trim unneeded dead operands.
1987  while (!DeadOps.empty()) {
1988  unsigned OpIdx = DeadOps.back();
1989  if (getOperand(OpIdx).isImplicit() &&
1990  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1991  RemoveOperand(OpIdx);
1992  else
1993  getOperand(OpIdx).setIsDead(false);
1994  DeadOps.pop_back();
1995  }
1996 
1997  // If not found, this means an alias of one of the operands is dead. Add a
1998  // new implicit operand if required.
1999  if (Found || !AddIfNotFound)
2000  return Found;
2001 
2003  true /*IsDef*/,
2004  true /*IsImp*/,
2005  false /*IsKill*/,
2006  true /*IsDead*/));
2007  return true;
2008 }
2009 
2011  for (MachineOperand &MO : operands()) {
2012  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2013  continue;
2014  MO.setIsDead(false);
2015  }
2016 }
2017 
2019  for (MachineOperand &MO : operands()) {
2020  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2021  continue;
2022  MO.setIsUndef(IsUndef);
2023  }
2024 }
2025 
2027  const TargetRegisterInfo *RegInfo) {
2029  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2030  if (MO)
2031  return;
2032  } else {
2033  for (const MachineOperand &MO : operands()) {
2034  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2035  MO.getSubReg() == 0)
2036  return;
2037  }
2038  }
2040  true /*IsDef*/,
2041  true /*IsImp*/));
2042 }
2043 
2045  const TargetRegisterInfo &TRI) {
2046  bool HasRegMask = false;
2047  for (MachineOperand &MO : operands()) {
2048  if (MO.isRegMask()) {
2049  HasRegMask = true;
2050  continue;
2051  }
2052  if (!MO.isReg() || !MO.isDef()) continue;
2053  Register Reg = MO.getReg();
2054  if (!Reg.isPhysical())
2055  continue;
2056  // If there are no uses, including partial uses, the def is dead.
2057  if (llvm::none_of(UsedRegs,
2058  [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2059  MO.setIsDead();
2060  }
2061 
2062  // This is a call with a register mask operand.
2063  // Mask clobbers are always dead, so add defs for the non-dead defines.
2064  if (HasRegMask)
2065  for (const Register &UsedReg : UsedRegs)
2066  addRegisterDefined(UsedReg, &TRI);
2067 }
2068 
2069 unsigned
2071  // Build up a buffer of hash code components.
2072  SmallVector<size_t, 16> HashComponents;
2073  HashComponents.reserve(MI->getNumOperands() + 1);
2074  HashComponents.push_back(MI->getOpcode());
2075  for (const MachineOperand &MO : MI->operands()) {
2076  if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2077  continue; // Skip virtual register defs.
2078 
2079  HashComponents.push_back(hash_value(MO));
2080  }
2081  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2082 }
2083 
2085  // Find the source location cookie.
2086  unsigned LocCookie = 0;
2087  const MDNode *LocMD = nullptr;
2088  for (unsigned i = getNumOperands(); i != 0; --i) {
2089  if (getOperand(i-1).isMetadata() &&
2090  (LocMD = getOperand(i-1).getMetadata()) &&
2091  LocMD->getNumOperands() != 0) {
2092  if (const ConstantInt *CI =
2093  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2094  LocCookie = CI->getZExtValue();
2095  break;
2096  }
2097  }
2098  }
2099 
2100  if (const MachineBasicBlock *MBB = getParent())
2101  if (const MachineFunction *MF = MBB->getParent())
2102  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2103  report_fatal_error(Msg);
2104 }
2105 
2107  const MCInstrDesc &MCID, bool IsIndirect,
2108  Register Reg, const MDNode *Variable,
2109  const MDNode *Expr) {
2110  assert(isa<DILocalVariable>(Variable) && "not a variable");
2111  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2112  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2113  "Expected inlined-at fields to agree");
2114  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2115  if (IsIndirect)
2116  MIB.addImm(0U);
2117  else
2118  MIB.addReg(0U, RegState::Debug);
2119  return MIB.addMetadata(Variable).addMetadata(Expr);
2120 }
2121 
2123  const MCInstrDesc &MCID, bool IsIndirect,
2124  const MachineOperand &MO,
2125  const MDNode *Variable, const MDNode *Expr) {
2126  assert(isa<DILocalVariable>(Variable) && "not a variable");
2127  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2128  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2129  "Expected inlined-at fields to agree");
2130  if (MO.isReg())
2131  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2132 
2133  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2134  if (IsIndirect)
2135  MIB.addImm(0U);
2136  else
2137  MIB.addReg(0U, RegState::Debug);
2138  return MIB.addMetadata(Variable).addMetadata(Expr);
2139 }
2140 
2142  const MCInstrDesc &MCID, bool IsIndirect,
2144  const MDNode *Variable, const MDNode *Expr) {
2145  assert(isa<DILocalVariable>(Variable) && "not a variable");
2146  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2147  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2148  "Expected inlined-at fields to agree");
2149  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2150  return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2151 
2152  auto MIB = BuildMI(MF, DL, MCID);
2153  MIB.addMetadata(Variable).addMetadata(Expr);
2154  for (const MachineOperand &MO : MOs)
2155  if (MO.isReg())
2156  MIB.addReg(MO.getReg(), RegState::Debug);
2157  else
2158  MIB.add(MO);
2159  return MIB;
2160 }
2161 
2164  const DebugLoc &DL, const MCInstrDesc &MCID,
2165  bool IsIndirect, Register Reg,
2166  const MDNode *Variable, const MDNode *Expr) {
2167  MachineFunction &MF = *BB.getParent();
2168  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2169  BB.insert(I, MI);
2170  return MachineInstrBuilder(MF, MI);
2171 }
2172 
2175  const DebugLoc &DL, const MCInstrDesc &MCID,
2176  bool IsIndirect, MachineOperand &MO,
2177  const MDNode *Variable, const MDNode *Expr) {
2178  MachineFunction &MF = *BB.getParent();
2179  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2180  BB.insert(I, MI);
2181  return MachineInstrBuilder(MF, *MI);
2182 }
2183 
2186  const DebugLoc &DL, const MCInstrDesc &MCID,
2187  bool IsIndirect, ArrayRef<MachineOperand> MOs,
2188  const MDNode *Variable, const MDNode *Expr) {
2189  MachineFunction &MF = *BB.getParent();
2190  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2191  BB.insert(I, MI);
2192  return MachineInstrBuilder(MF, *MI);
2193 }
2194 
2195 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2196 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2197 static const DIExpression *
2199  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2200  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2201  "Expected inlined-at fields to agree");
2202 
2203  const DIExpression *Expr = MI.getDebugExpression();
2204  if (MI.isIndirectDebugValue()) {
2205  assert(MI.getDebugOffset().getImm() == 0 &&
2206  "DBG_VALUE with nonzero offset");
2208  } else if (MI.isDebugValueList()) {
2209  // We will replace the spilled register with a frame index, so
2210  // immediately deref all references to the spilled register.
2211  std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2212  for (const MachineOperand *Op : SpilledOperands) {
2213  unsigned OpIdx = MI.getDebugOperandIndex(Op);
2214  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2215  }
2216  }
2217  return Expr;
2218 }
2220  Register SpillReg) {
2221  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2223  for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2224  SpillOperands.push_back(&Op);
2225  return computeExprForSpill(MI, SpillOperands);
2226 }
2227 
2230  const MachineInstr &Orig,
2231  int FrameIndex, Register SpillReg) {
2232  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2233  MachineInstrBuilder NewMI =
2234  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2235  // Non-Variadic Operands: Location, Offset, Variable, Expression
2236  // Variadic Operands: Variable, Expression, Locations...
2237  if (Orig.isNonListDebugValue())
2238  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2239  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2240  if (Orig.isDebugValueList()) {
2241  for (const MachineOperand &Op : Orig.debug_operands())
2242  if (Op.isReg() && Op.getReg() == SpillReg)
2243  NewMI.addFrameIndex(FrameIndex);
2244  else
2245  NewMI.add(MachineOperand(Op));
2246  }
2247  return NewMI;
2248 }
2251  const MachineInstr &Orig, int FrameIndex,
2252  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2253  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2254  MachineInstrBuilder NewMI =
2255  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2256  // Non-Variadic Operands: Location, Offset, Variable, Expression
2257  // Variadic Operands: Variable, Expression, Locations...
2258  if (Orig.isNonListDebugValue())
2259  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2260  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2261  if (Orig.isDebugValueList()) {
2262  for (const MachineOperand &Op : Orig.debug_operands())
2263  if (is_contained(SpilledOperands, &Op))
2264  NewMI.addFrameIndex(FrameIndex);
2265  else
2266  NewMI.add(MachineOperand(Op));
2267  }
2268  return NewMI;
2269 }
2270 
2272  Register Reg) {
2273  const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2274  if (Orig.isNonListDebugValue())
2275  Orig.getDebugOffset().ChangeToImmediate(0U);
2277  Op.ChangeToFrameIndex(FrameIndex);
2278  Orig.getDebugExpressionOp().setMetadata(Expr);
2279 }
2280 
2282  SmallVectorImpl<MachineInstr *> &DbgValues) {
2283  MachineInstr &MI = *this;
2284  if (!MI.getOperand(0).isReg())
2285  return;
2286 
2287  MachineBasicBlock::iterator DI = MI; ++DI;
2288  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2289  DI != DE; ++DI) {
2290  if (!DI->isDebugValue())
2291  return;
2292  if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2293  DbgValues.push_back(&*DI);
2294  }
2295 }
2296 
2298  // Collect matching debug values.
2300 
2301  if (!getOperand(0).isReg())
2302  return;
2303 
2304  Register DefReg = getOperand(0).getReg();
2305  auto *MRI = getRegInfo();
2306  for (auto &MO : MRI->use_operands(DefReg)) {
2307  auto *DI = MO.getParent();
2308  if (!DI->isDebugValue())
2309  continue;
2310  if (DI->hasDebugOperandForReg(DefReg)) {
2311  DbgValues.push_back(DI);
2312  }
2313  }
2314 
2315  // Propagate Reg to debug value instructions.
2316  for (auto *DBI : DbgValues)
2317  for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2318  Op.setReg(Reg);
2319 }
2320 
2322 
2323 static unsigned getSpillSlotSize(const MMOList &Accesses,
2324  const MachineFrameInfo &MFI) {
2325  unsigned Size = 0;
2326  for (auto A : Accesses)
2327  if (MFI.isSpillSlotObjectIndex(
2328  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2329  ->getFrameIndex()))
2330  Size += A->getSize();
2331  return Size;
2332 }
2333 
2336  int FI;
2337  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2338  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2339  if (MFI.isSpillSlotObjectIndex(FI))
2340  return (*memoperands_begin())->getSize();
2341  }
2342  return None;
2343 }
2344 
2347  MMOList Accesses;
2348  if (TII->hasStoreToStackSlot(*this, Accesses))
2349  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2350  return None;
2351 }
2352 
2355  int FI;
2356  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2357  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2358  if (MFI.isSpillSlotObjectIndex(FI))
2359  return (*memoperands_begin())->getSize();
2360  }
2361  return None;
2362 }
2363 
2366  MMOList Accesses;
2367  if (TII->hasLoadFromStackSlot(*this, Accesses))
2368  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2369  return None;
2370 }
2371 
2373  if (DebugInstrNum == 0)
2374  DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2375  return DebugInstrNum;
2376 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1267
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:223
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1205
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:768
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:859
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:597
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:244
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:363
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2010
llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
Definition: MachineRegisterInfo.cpp:532
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2044
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2372
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1957
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:171
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:499
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1519
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2070
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:788
Metadata.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1232
Loads.h
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:629
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1017
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:726
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:697
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:730
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:534
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:388
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:303
llvm::InlineAsm::AD_ATT
@ AD_ATT
Definition: InlineAsm.h:34
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:672
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:994
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:497
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1223
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:718
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1131
InlineAsm.h
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:216
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:438
llvm::AAResults::isNoAlias
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Definition: AliasAnalysis.h:510
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:759
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1192
MachineBasicBlock.h
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2026
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1476
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:233
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1444
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:681
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:316
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:475
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:343
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::MachineFunction::getNewDebugInstrNum
unsigned getNewDebugInstrNum()
Definition: MachineFunction.h:1130
Module.h
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:343
TargetInstrInfo.h
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:98
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4733
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:980
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:469
llvm::FastMathFlags::noSignedZeros
bool noSignedZeros() const
Definition: Operator.h:208
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:663
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::Optional< unsigned >
llvm::SmallPtrSet< const MachineInstr *, 16 >
Operator.h
Hashing.h
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:786
hasIdenticalMMOs
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
Definition: MachineInstr.cpp:413
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:892
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2559
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:160
llvm::FastMathFlags::noNaNs
bool noNaNs() const
Definition: Operator.h:206
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4803
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:243
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:280
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::PossiblyExactOperator
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:120
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:330
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:838
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1376
MachineRegisterInfo.h
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1547
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:556
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:577
llvm::MDNode::getNumOperands
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1108
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1324
AliasAnalysis.h
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1126
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:34
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:516
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:325
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:528
CommandLine.h
FormattedStream.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:153
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1283
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
getSpillSlotSize
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
Definition: MachineInstr.cpp:2323
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:812
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
llvm::FastMathFlags::approxFunc
bool approxFunc() const
Definition: Operator.h:211
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:505
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:843
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:205
Constants.h
llvm::AAResults
Definition: AliasAnalysis.h:456
SmallString.h
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3041
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:221
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:648
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:371
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:200
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:367
Intrinsics.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2228
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2346
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1202
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:563
InstrTypes.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1129
llvm::fdbgs
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
Definition: FormattedStream.cpp:152
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:424
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1328
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
MCSymbol.h
llvm::FastMathFlags::allowReassoc
bool allowReassoc() const
Flag queries.
Definition: Operator.h:205
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:667
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:786
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1210
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:104
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:582
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition: MachineInstr.cpp:81
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:231
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1878
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:90
llvm::FastMathFlags::allowReciprocal
bool allowReciprocal() const
Definition: Operator.h:209
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:346
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1209
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:585
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:720
MachineInstrBundle.h
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:968
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:402
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:225
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:198
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:795
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:475
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:284
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:592
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:765
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:104
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1469
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1570
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:92
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:193
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1199
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:326
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:278
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:756
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:743
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:643
llvm::MDNode::getOperand
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1102
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:572
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:506
llvm::MachineFunction::deallocateOperandArray
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
Definition: MachineFunction.h:885
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:230
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:153
llvm::LLVMContext::emitError
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:796
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1515
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:614
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:423
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:550
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:503
llvm::FastMathFlags::noInfs
bool noInfs() const
Definition: Operator.h:207
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:218
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:723
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:36
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2084
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:871
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:715
llvm::MachineFunction::createMIExtraInfo
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
Definition: MachineFunction.cpp:488
TiedMax
const unsigned TiedMax
Definition: MachineInstr.cpp:1085
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:330
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2271
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:729
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1898
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:843
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:390
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:100
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:226
MemoryLocation.h
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:382
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2018
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:277
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
MCRegisterInfo.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1570
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:757
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::make_pointee_range
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:312
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2281
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:339
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:777
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1944
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2753
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FPMathOperator
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:249
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1563
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1012
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.h:2863
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:270
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:704
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:330
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:207
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:342
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1243
MachineModuleInfo.h
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:804
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1398
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:577
llvm::DebugLoc::hasTrivialDestructor
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1133
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1540
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:702
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:855
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:106
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:810
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition: MachineInstr.cpp:90
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:224
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:863
llvm::RegState::Debug
@ Debug
Register 'use' is for debugging purpose.
Definition: MachineInstrBuilder.h:57
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1249
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1815
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:520
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:742
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2365
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:508
Compiler.h
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1069
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:110
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1577
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:836
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1208
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:718
llvm::OverflowingBinaryOperator
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:66
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:407
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1197
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:880
MemOperandsHaveAlias
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
Definition: MachineInstr.cpp:1261
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1188
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:853
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:362
FoldingSet.h
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:217
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:948
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
std
Definition: BitVector.h:838
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:528
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:352
uint16_t
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:346
moveOperands
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
Definition: MachineInstr.cpp:194
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:514
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1007
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:221
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1457
llvm::Module::getContext
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:261
Casting.h
llvm::MachineFunction::allocateOperandArray
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
Definition: MachineFunction.h:878
Function.h
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:875
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:257
StackMaps.h
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:88
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:214
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:707
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:96
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:707
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:397
llvm::AAResults::pointsToConstantMemory
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Definition: AliasAnalysis.cpp:161
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:709
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1275
llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:682
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:443
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:232
computeExprForSpill
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
Definition: MachineInstr.cpp:2198
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1209
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:656
llvm::InlineAsm::MIOp_AsmString
@ MIOp_AsmString
Definition: InlineAsm.h:216
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1041
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:337
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:102
RegisterBank.h
TargetIntrinsicInfo.h
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:222
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
SmallBitVector.h
N
#define N
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:401
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::hash_combine_range
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:482
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:363
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:94
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:237
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:679
ModuleSlotTracker.h
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1498
llvm::SmallVectorImpl< unsigned >
llvm::MachineBasicBlock::erase_instr
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.h:814
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1078
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
DerivedTypes.h
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2354
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:919
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1132
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3121
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1247
LLVMContext.h
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:361
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:332
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FastMathFlags::allowContract
bool allowContract() const
Definition: Operator.h:210
raw_ostream.h
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1027
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:624
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1202
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1444
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
Value.h
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:211
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:174
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:754
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:229
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:607
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:992
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1329
TargetRegisterInfo.h
Debug.h
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:490
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:560
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:209
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2335
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:745
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:335
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1163
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:236
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:282
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:206
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:202
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2297
llvm::LLT
Definition: LowLevelTypeImpl.h:40