LLVM  16.0.0git
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/Hashing.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Metadata.h"
43 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Operator.h"
46 #include "llvm/MC/MCInstrDesc.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstdint>
59 #include <cstring>
60 #include <utility>
61 
62 using namespace llvm;
63 
65  if (const MachineBasicBlock *MBB = MI.getParent())
66  if (const MachineFunction *MF = MBB->getParent())
67  return MF;
68  return nullptr;
69 }
70 
71 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
72 // it.
73 static void tryToGetTargetInfo(const MachineInstr &MI,
74  const TargetRegisterInfo *&TRI,
75  const MachineRegisterInfo *&MRI,
76  const TargetIntrinsicInfo *&IntrinsicInfo,
77  const TargetInstrInfo *&TII) {
78 
79  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
80  TRI = MF->getSubtarget().getRegisterInfo();
81  MRI = &MF->getRegInfo();
82  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83  TII = MF->getSubtarget().getInstrInfo();
84  }
85 }
86 
88  if (MCID->ImplicitDefs)
89  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
90  ++ImpDefs)
91  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
92  if (MCID->ImplicitUses)
93  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
94  ++ImpUses)
95  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
96 }
97 
98 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
99 /// implicit operands. It reserves space for the number of operands specified by
100 /// the MCInstrDesc.
101 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
102  DebugLoc DL, bool NoImp)
103  : MCID(&TID), DbgLoc(std::move(DL)), DebugInstrNum(0) {
104  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
105 
106  // Reserve space for the expected number of operands.
107  if (unsigned NumOps = MCID->getNumOperands() +
108  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
109  CapOperands = OperandCapacity::get(NumOps);
110  Operands = MF.allocateOperandArray(CapOperands);
111  }
112 
113  if (!NoImp)
115 }
116 
117 /// MachineInstr ctor - Copies MachineInstr arg exactly.
118 /// Does not copy the number from debug instruction numbering, to preserve
119 /// uniqueness.
120 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
121  : MCID(&MI.getDesc()), Info(MI.Info), DbgLoc(MI.getDebugLoc()),
122  DebugInstrNum(0) {
123  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
124 
125  CapOperands = OperandCapacity::get(MI.getNumOperands());
126  Operands = MF.allocateOperandArray(CapOperands);
127 
128  // Copy operands.
129  for (const MachineOperand &MO : MI.operands())
130  addOperand(MF, MO);
131 
132  // Replicate ties between the operands, which addOperand was not
133  // able to do reliably.
134  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
135  MachineOperand &NewMO = getOperand(i);
136  const MachineOperand &OrigMO = MI.getOperand(i);
137  NewMO.TiedTo = OrigMO.TiedTo;
138  }
139 
140  // Copy all the sensible flags.
141  setFlags(MI.Flags);
142 }
143 
145  MovePos->getParent()->splice(MovePos, getParent(), getIterator());
146 }
147 
148 /// getRegInfo - If this instruction is embedded into a MachineFunction,
149 /// return the MachineRegisterInfo object for the current function, otherwise
150 /// return null.
151 MachineRegisterInfo *MachineInstr::getRegInfo() {
153  return &MBB->getParent()->getRegInfo();
154  return nullptr;
155 }
156 
157 void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
158  for (MachineOperand &MO : operands())
159  if (MO.isReg())
161 }
162 
163 void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
164  for (MachineOperand &MO : operands())
165  if (MO.isReg())
167 }
168 
171  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
172  MachineFunction *MF = MBB->getParent();
173  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
174  addOperand(*MF, Op);
175 }
176 
177 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
178 /// ranges. If MRI is non-null also update use-def chains.
180  unsigned NumOps, MachineRegisterInfo *MRI) {
181  if (MRI)
182  return MRI->moveOperands(Dst, Src, NumOps);
183  // MachineOperand is a trivially copyable type so we can just use memmove.
184  assert(Dst && Src && "Unknown operands");
185  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
186 }
187 
188 /// addOperand - Add the specified operand to the instruction. If it is an
189 /// implicit operand, it is added to the end of the operand list. If it is
190 /// an explicit operand it is added at the end of the explicit operand list
191 /// (before the first implicit operand).
193  assert(MCID && "Cannot add operands before providing an instr descriptor");
194 
195  // Check if we're adding one of our existing operands.
196  if (&Op >= Operands && &Op < Operands + NumOperands) {
197  // This is unusual: MI->addOperand(MI->getOperand(i)).
198  // If adding Op requires reallocating or moving existing operands around,
199  // the Op reference could go stale. Support it by copying Op.
200  MachineOperand CopyOp(Op);
201  return addOperand(MF, CopyOp);
202  }
203 
204  // Find the insert location for the new operand. Implicit registers go at
205  // the end, everything else goes before the implicit regs.
206  //
207  // FIXME: Allow mixed explicit and implicit operands on inline asm.
208  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
209  // implicit-defs, but they must not be moved around. See the FIXME in
210  // InstrEmitter.cpp.
211  unsigned OpNo = getNumOperands();
212  bool isImpReg = Op.isReg() && Op.isImplicit();
213  if (!isImpReg && !isInlineAsm()) {
214  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
215  --OpNo;
216  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
217  }
218  }
219 
220  // OpNo now points as the desired insertion point. Unless this is a variadic
221  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
222  // RegMask operands go between the explicit and implicit operands.
223  assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||
224  Op.isValidExcessOperand()) &&
225  "Trying to add an operand to a machine instr that is already done!");
226 
227  MachineRegisterInfo *MRI = getRegInfo();
228 
229  // Determine if the Operands array needs to be reallocated.
230  // Save the old capacity and operand array.
231  OperandCapacity OldCap = CapOperands;
232  MachineOperand *OldOperands = Operands;
233  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
234  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
235  Operands = MF.allocateOperandArray(CapOperands);
236  // Move the operands before the insertion point.
237  if (OpNo)
238  moveOperands(Operands, OldOperands, OpNo, MRI);
239  }
240 
241  // Move the operands following the insertion point.
242  if (OpNo != NumOperands)
243  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
244  MRI);
245  ++NumOperands;
246 
247  // Deallocate the old operand array.
248  if (OldOperands != Operands && OldOperands)
249  MF.deallocateOperandArray(OldCap, OldOperands);
250 
251  // Copy Op into place. It still needs to be inserted into the MRI use lists.
252  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
253  NewMO->ParentMI = this;
254 
255  // When adding a register operand, tell MRI about it.
256  if (NewMO->isReg()) {
257  // Ensure isOnRegUseList() returns false, regardless of Op's status.
258  NewMO->Contents.Reg.Prev = nullptr;
259  // Ignore existing ties. This is not a property that can be copied.
260  NewMO->TiedTo = 0;
261  // Add the new operand to MRI, but only for instructions in an MBB.
262  if (MRI)
263  MRI->addRegOperandToUseList(NewMO);
264  // The MCID operand information isn't accurate until we start adding
265  // explicit operands. The implicit operands are added first, then the
266  // explicits are inserted before them.
267  if (!isImpReg) {
268  // Tie uses to defs as indicated in MCInstrDesc.
269  if (NewMO->isUse()) {
270  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
271  if (DefIdx != -1)
272  tieOperands(DefIdx, OpNo);
273  }
274  // If the register operand is flagged as early, mark the operand as such.
275  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
276  NewMO->setIsEarlyClobber(true);
277  }
278  // Ensure debug instructions set debug flag on register uses.
279  if (NewMO->isUse() && isDebugInstr())
280  NewMO->setIsDebug();
281  }
282 }
283 
284 void MachineInstr::removeOperand(unsigned OpNo) {
285  assert(OpNo < getNumOperands() && "Invalid operand number");
286  untieRegOperand(OpNo);
287 
288 #ifndef NDEBUG
289  // Moving tied operands would break the ties.
290  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
291  if (Operands[i].isReg())
292  assert(!Operands[i].isTied() && "Cannot move tied operands");
293 #endif
294 
295  MachineRegisterInfo *MRI = getRegInfo();
296  if (MRI && Operands[OpNo].isReg())
297  MRI->removeRegOperandFromUseList(Operands + OpNo);
298 
299  // Don't call the MachineOperand destructor. A lot of this code depends on
300  // MachineOperand having a trivial destructor anyway, and adding a call here
301  // wouldn't make it 'destructor-correct'.
302 
303  if (unsigned N = NumOperands - 1 - OpNo)
304  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
305  --NumOperands;
306 }
307 
308 void MachineInstr::setExtraInfo(MachineFunction &MF,
310  MCSymbol *PreInstrSymbol,
311  MCSymbol *PostInstrSymbol,
312  MDNode *HeapAllocMarker, MDNode *PCSections,
313  uint32_t CFIType) {
314  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
315  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
316  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
317  bool HasPCSections = PCSections != nullptr;
318  bool HasCFIType = CFIType != 0;
319  int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
320  HasHeapAllocMarker + HasPCSections + HasCFIType;
321 
322  // Drop all extra info if there is none.
323  if (NumPointers <= 0) {
324  Info.clear();
325  return;
326  }
327 
328  // If more than one pointer, then store out of line. Store heap alloc markers
329  // out of line because PointerSumType cannot hold more than 4 tag types with
330  // 32-bit pointers.
331  // FIXME: Maybe we should make the symbols in the extra info mutable?
332  else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
333  HasCFIType) {
334  Info.set<EIIK_OutOfLine>(
335  MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
336  HeapAllocMarker, PCSections, CFIType));
337  return;
338  }
339 
340  // Otherwise store the single pointer inline.
341  if (HasPreInstrSymbol)
342  Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
343  else if (HasPostInstrSymbol)
344  Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
345  else
346  Info.set<EIIK_MMO>(MMOs[0]);
347 }
348 
350  if (memoperands_empty())
351  return;
352 
353  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
355 }
356 
359  if (MMOs.empty()) {
360  dropMemRefs(MF);
361  return;
362  }
363 
364  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
366 }
367 
369  MachineMemOperand *MO) {
372  MMOs.push_back(MO);
373  setMemRefs(MF, MMOs);
374 }
375 
377  if (this == &MI)
378  // Nothing to do for a self-clone!
379  return;
380 
381  assert(&MF == MI.getMF() &&
382  "Invalid machine functions when cloning memory refrences!");
383  // See if we can just steal the extra info already allocated for the
384  // instruction. We can do this whenever the pre- and post-instruction symbols
385  // are the same (including null).
386  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
387  getPostInstrSymbol() == MI.getPostInstrSymbol() &&
388  getHeapAllocMarker() == MI.getHeapAllocMarker() &&
389  getPCSections() == MI.getPCSections()) {
390  Info = MI.Info;
391  return;
392  }
393 
394  // Otherwise, fall back on a copy-based clone.
395  setMemRefs(MF, MI.memoperands());
396 }
397 
398 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
399 /// identical.
402  if (LHS.size() != RHS.size())
403  return false;
404 
405  auto LHSPointees = make_pointee_range(LHS);
406  auto RHSPointees = make_pointee_range(RHS);
407  return std::equal(LHSPointees.begin(), LHSPointees.end(),
408  RHSPointees.begin());
409 }
410 
413  // Try handling easy numbers of MIs with simpler mechanisms.
414  if (MIs.empty()) {
415  dropMemRefs(MF);
416  return;
417  }
418  if (MIs.size() == 1) {
419  cloneMemRefs(MF, *MIs[0]);
420  return;
421  }
422  // Because an empty memoperands list provides *no* information and must be
423  // handled conservatively (assuming the instruction can do anything), the only
424  // way to merge with it is to drop all other memoperands.
425  if (MIs[0]->memoperands_empty()) {
426  dropMemRefs(MF);
427  return;
428  }
429 
430  // Handle the general case.
432  // Start with the first instruction.
433  assert(&MF == MIs[0]->getMF() &&
434  "Invalid machine functions when cloning memory references!");
435  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
436  // Now walk all the other instructions and accumulate any different MMOs.
437  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
438  assert(&MF == MI.getMF() &&
439  "Invalid machine functions when cloning memory references!");
440 
441  // Skip MIs with identical operands to the first. This is a somewhat
442  // arbitrary hack but will catch common cases without being quadratic.
443  // TODO: We could fully implement merge semantics here if needed.
444  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
445  continue;
446 
447  // Because an empty memoperands list provides *no* information and must be
448  // handled conservatively (assuming the instruction can do anything), the
449  // only way to merge with it is to drop all other memoperands.
450  if (MI.memoperands_empty()) {
451  dropMemRefs(MF);
452  return;
453  }
454 
455  // Otherwise accumulate these into our temporary buffer of the merged state.
456  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
457  }
458 
459  setMemRefs(MF, MergedMMOs);
460 }
461 
463  // Do nothing if old and new symbols are the same.
464  if (Symbol == getPreInstrSymbol())
465  return;
466 
467  // If there was only one symbol and we're removing it, just clear info.
468  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
469  Info.clear();
470  return;
471  }
472 
473  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
475 }
476 
478  // Do nothing if old and new symbols are the same.
479  if (Symbol == getPostInstrSymbol())
480  return;
481 
482  // If there was only one symbol and we're removing it, just clear info.
483  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
484  Info.clear();
485  return;
486  }
487 
488  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
490 }
491 
493  // Do nothing if old and new symbols are the same.
494  if (Marker == getHeapAllocMarker())
495  return;
496 
497  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
498  Marker, getPCSections(), getCFIType());
499 }
500 
502  // Do nothing if old and new symbols are the same.
503  if (PCSections == getPCSections())
504  return;
505 
506  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
507  getHeapAllocMarker(), PCSections, getCFIType());
508 }
509 
511  // Do nothing if old and new types are the same.
512  if (Type == getCFIType())
513  return;
514 
515  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
517 }
518 
520  const MachineInstr &MI) {
521  if (this == &MI)
522  // Nothing to do for a self-clone!
523  return;
524 
525  assert(&MF == MI.getMF() &&
526  "Invalid machine functions when cloning instruction symbols!");
527 
528  setPreInstrSymbol(MF, MI.getPreInstrSymbol());
529  setPostInstrSymbol(MF, MI.getPostInstrSymbol());
530  setHeapAllocMarker(MF, MI.getHeapAllocMarker());
531  setPCSections(MF, MI.getPCSections());
532 }
533 
535  // For now, the just return the union of the flags. If the flags get more
536  // complicated over time, we might need more logic here.
537  return getFlags() | Other.getFlags();
538 }
539 
541  uint16_t MIFlags = 0;
542  // Copy the wrapping flags.
543  if (const OverflowingBinaryOperator *OB =
544  dyn_cast<OverflowingBinaryOperator>(&I)) {
545  if (OB->hasNoSignedWrap())
546  MIFlags |= MachineInstr::MIFlag::NoSWrap;
547  if (OB->hasNoUnsignedWrap())
548  MIFlags |= MachineInstr::MIFlag::NoUWrap;
549  }
550 
551  // Copy the exact flag.
552  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
553  if (PE->isExact())
554  MIFlags |= MachineInstr::MIFlag::IsExact;
555 
556  // Copy the fast-math flags.
557  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
558  const FastMathFlags Flags = FP->getFastMathFlags();
559  if (Flags.noNaNs())
560  MIFlags |= MachineInstr::MIFlag::FmNoNans;
561  if (Flags.noInfs())
562  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
563  if (Flags.noSignedZeros())
564  MIFlags |= MachineInstr::MIFlag::FmNsz;
565  if (Flags.allowReciprocal())
566  MIFlags |= MachineInstr::MIFlag::FmArcp;
567  if (Flags.allowContract())
568  MIFlags |= MachineInstr::MIFlag::FmContract;
569  if (Flags.approxFunc())
570  MIFlags |= MachineInstr::MIFlag::FmAfn;
571  if (Flags.allowReassoc())
572  MIFlags |= MachineInstr::MIFlag::FmReassoc;
573  }
574 
575  return MIFlags;
576 }
577 
579  Flags = copyFlagsFromInstruction(I);
580 }
581 
582 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
583  assert(!isBundledWithPred() && "Must be called on bundle header");
585  if (MII->getDesc().getFlags() & Mask) {
586  if (Type == AnyInBundle)
587  return true;
588  } else {
589  if (Type == AllInBundle && !MII->isBundle())
590  return false;
591  }
592  // This was the last instruction in the bundle.
593  if (!MII->isBundledWithSucc())
594  return Type == AllInBundle;
595  }
596 }
597 
599  MICheckType Check) const {
600  // If opcodes or number of operands are not the same then the two
601  // instructions are obviously not identical.
602  if (Other.getOpcode() != getOpcode() ||
603  Other.getNumOperands() != getNumOperands())
604  return false;
605 
606  if (isBundle()) {
607  // We have passed the test above that both instructions have the same
608  // opcode, so we know that both instructions are bundles here. Let's compare
609  // MIs inside the bundle.
610  assert(Other.isBundle() && "Expected that both instructions are bundles.");
613  // Loop until we analysed the last intruction inside at least one of the
614  // bundles.
615  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
616  ++I1;
617  ++I2;
618  if (!I1->isIdenticalTo(*I2, Check))
619  return false;
620  }
621  // If we've reached the end of just one of the two bundles, but not both,
622  // the instructions are not identical.
623  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
624  return false;
625  }
626 
627  // Check operands to make sure they match.
628  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
629  const MachineOperand &MO = getOperand(i);
630  const MachineOperand &OMO = Other.getOperand(i);
631  if (!MO.isReg()) {
632  if (!MO.isIdenticalTo(OMO))
633  return false;
634  continue;
635  }
636 
637  // Clients may or may not want to ignore defs when testing for equality.
638  // For example, machine CSE pass only cares about finding common
639  // subexpressions, so it's safe to ignore virtual register defs.
640  if (MO.isDef()) {
641  if (Check == IgnoreDefs)
642  continue;
643  else if (Check == IgnoreVRegDefs) {
644  if (!Register::isVirtualRegister(MO.getReg()) ||
646  if (!MO.isIdenticalTo(OMO))
647  return false;
648  } else {
649  if (!MO.isIdenticalTo(OMO))
650  return false;
651  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
652  return false;
653  }
654  } else {
655  if (!MO.isIdenticalTo(OMO))
656  return false;
657  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
658  return false;
659  }
660  }
661  // If DebugLoc does not match then two debug instructions are not identical.
662  if (isDebugInstr())
663  if (getDebugLoc() && Other.getDebugLoc() &&
664  getDebugLoc() != Other.getDebugLoc())
665  return false;
666  // If pre- or post-instruction symbols do not match then the two instructions
667  // are not identical.
668  if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
669  getPostInstrSymbol() != Other.getPostInstrSymbol())
670  return false;
671  // Call instructions with different CFI types are not identical.
672  if (isCall() && getCFIType() != Other.getCFIType())
673  return false;
674 
675  return true;
676 }
677 
679  return getParent()->getParent();
680 }
681 
683  assert(getParent() && "Not embedded in a basic block!");
684  return getParent()->remove(this);
685 }
686 
688  assert(getParent() && "Not embedded in a basic block!");
689  return getParent()->remove_instr(this);
690 }
691 
693  assert(getParent() && "Not embedded in a basic block!");
694  getParent()->erase(this);
695 }
696 
698  assert(getParent() && "Not embedded in a basic block!");
699  getParent()->erase_instr(this);
700 }
701 
703  if (!isCall(Type))
704  return false;
705  switch (getOpcode()) {
708  case TargetOpcode::STATEPOINT:
709  case TargetOpcode::FENTRY_CALL:
710  return false;
711  }
712  return true;
713 }
714 
716  if (isBundle())
719 }
720 
722  unsigned NumOperands = MCID->getNumOperands();
723  if (!MCID->isVariadic())
724  return NumOperands;
725 
726  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
727  const MachineOperand &MO = getOperand(I);
728  // The operands must always be in the following order:
729  // - explicit reg defs,
730  // - other explicit operands (reg uses, immediates, etc.),
731  // - implicit reg defs
732  // - implicit reg uses
733  if (MO.isReg() && MO.isImplicit())
734  break;
735  ++NumOperands;
736  }
737  return NumOperands;
738 }
739 
741  unsigned NumDefs = MCID->getNumDefs();
742  if (!MCID->isVariadic())
743  return NumDefs;
744 
745  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
746  const MachineOperand &MO = getOperand(I);
747  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
748  break;
749  ++NumDefs;
750  }
751  return NumDefs;
752 }
753 
755  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
758  --Pred;
759  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
760  Pred->setFlag(BundledSucc);
761 }
762 
764  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
767  ++Succ;
768  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
769  Succ->setFlag(BundledPred);
770 }
771 
773  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
776  --Pred;
777  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
778  Pred->clearFlag(BundledSucc);
779 }
780 
782  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
785  ++Succ;
786  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
787  Succ->clearFlag(BundledPred);
788 }
789 
791  if (isInlineAsm()) {
792  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
793  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
794  return true;
795  }
796  return false;
797 }
798 
800  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
801  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
802  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
803 }
804 
806  unsigned *GroupNo) const {
807  assert(isInlineAsm() && "Expected an inline asm instruction");
808  assert(OpIdx < getNumOperands() && "OpIdx out of range");
809 
810  // Ignore queries about the initial operands.
811  if (OpIdx < InlineAsm::MIOp_FirstOperand)
812  return -1;
813 
814  unsigned Group = 0;
815  unsigned NumOps;
816  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
817  i += NumOps) {
818  const MachineOperand &FlagMO = getOperand(i);
819  // If we reach the implicit register operands, stop looking.
820  if (!FlagMO.isImm())
821  return -1;
822  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
823  if (i + NumOps > OpIdx) {
824  if (GroupNo)
825  *GroupNo = Group;
826  return i;
827  }
828  ++Group;
829  }
830  return -1;
831 }
832 
834  assert(isDebugLabel() && "not a DBG_LABEL");
835  return cast<DILabel>(getOperand(0).getMetadata());
836 }
837 
839  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
840  unsigned VariableOp = isDebugValueList() ? 0 : 2;
841  return getOperand(VariableOp);
842 }
843 
845  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
846  unsigned VariableOp = isDebugValueList() ? 0 : 2;
847  return getOperand(VariableOp);
848 }
849 
851  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
852 }
853 
855  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
856  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
857  return getOperand(ExpressionOp);
858 }
859 
861  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
862  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
863  return getOperand(ExpressionOp);
864 }
865 
867  return cast<DIExpression>(getDebugExpressionOp().getMetadata());
868 }
869 
872 }
873 
874 const TargetRegisterClass*
876  const TargetInstrInfo *TII,
877  const TargetRegisterInfo *TRI) const {
878  assert(getParent() && "Can't have an MBB reference here!");
879  assert(getMF() && "Can't have an MF reference here!");
880  const MachineFunction &MF = *getMF();
881 
882  // Most opcodes have fixed constraints in their MCInstrDesc.
883  if (!isInlineAsm())
884  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
885 
886  if (!getOperand(OpIdx).isReg())
887  return nullptr;
888 
889  // For tied uses on inline asm, get the constraint from the def.
890  unsigned DefIdx;
891  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
892  OpIdx = DefIdx;
893 
894  // Inline asm stores register class constraints in the flag word.
895  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
896  if (FlagIdx < 0)
897  return nullptr;
898 
899  unsigned Flag = getOperand(FlagIdx).getImm();
900  unsigned RCID;
905  return TRI->getRegClass(RCID);
906 
907  // Assume that all registers in a memory operand are pointers.
909  return TRI->getPointerRegClass(MF);
910 
911  return nullptr;
912 }
913 
915  Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
916  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
917  // Check every operands inside the bundle if we have
918  // been asked to.
919  if (ExploreBundle)
920  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
921  ++OpndIt)
922  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
923  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
924  else
925  // Otherwise, just check the current operands.
926  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
927  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
928  return CurRC;
929 }
930 
931 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
932  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
933  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
934  assert(CurRC && "Invalid initial register class");
935  // Check if Reg is constrained by some of its use/def from MI.
936  const MachineOperand &MO = getOperand(OpIdx);
937  if (!MO.isReg() || MO.getReg() != Reg)
938  return CurRC;
939  // If yes, accumulate the constraints through the operand.
940  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
941 }
942 
944  unsigned OpIdx, const TargetRegisterClass *CurRC,
945  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
946  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
947  const MachineOperand &MO = getOperand(OpIdx);
948  assert(MO.isReg() &&
949  "Cannot get register constraints for non-register operand");
950  assert(CurRC && "Invalid initial register class");
951  if (unsigned SubIdx = MO.getSubReg()) {
952  if (OpRC)
953  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
954  else
955  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
956  } else if (OpRC)
957  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
958  return CurRC;
959 }
960 
961 /// Return the number of instructions inside the MI bundle, not counting the
962 /// header instruction.
963 unsigned MachineInstr::getBundleSize() const {
965  unsigned Size = 0;
966  while (I->isBundledWithSucc()) {
967  ++Size;
968  ++I;
969  }
970  return Size;
971 }
972 
973 /// Returns true if the MachineInstr has an implicit-use operand of exactly
974 /// the given register (not considering sub/super-registers).
976  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
977  const MachineOperand &MO = getOperand(i);
978  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
979  return true;
980  }
981  return false;
982 }
983 
984 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
985 /// the specific register or -1 if it is not found. It further tightens
986 /// the search criteria to a use that kills the register if isKill is true.
988  Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
989  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
990  const MachineOperand &MO = getOperand(i);
991  if (!MO.isReg() || !MO.isUse())
992  continue;
993  Register MOReg = MO.getReg();
994  if (!MOReg)
995  continue;
996  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
997  if (!isKill || MO.isKill())
998  return i;
999  }
1000  return -1;
1001 }
1002 
1003 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1004 /// indicating if this instruction reads or writes Reg. This also considers
1005 /// partial defines.
1006 std::pair<bool,bool>
1008  SmallVectorImpl<unsigned> *Ops) const {
1009  bool PartDef = false; // Partial redefine.
1010  bool FullDef = false; // Full define.
1011  bool Use = false;
1012 
1013  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1014  const MachineOperand &MO = getOperand(i);
1015  if (!MO.isReg() || MO.getReg() != Reg)
1016  continue;
1017  if (Ops)
1018  Ops->push_back(i);
1019  if (MO.isUse())
1020  Use |= !MO.isUndef();
1021  else if (MO.getSubReg() && !MO.isUndef())
1022  // A partial def undef doesn't count as reading the register.
1023  PartDef = true;
1024  else
1025  FullDef = true;
1026  }
1027  // A partial redefine uses Reg unless there is also a full define.
1028  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1029 }
1030 
1031 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1032 /// the specified register or -1 if it is not found. If isDead is true, defs
1033 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1034 /// also checks if there is a def of a super-register.
1035 int
1037  const TargetRegisterInfo *TRI) const {
1038  bool isPhys = Register::isPhysicalRegister(Reg);
1039  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1040  const MachineOperand &MO = getOperand(i);
1041  // Accept regmask operands when Overlap is set.
1042  // Ignore them when looking for a specific def operand (Overlap == false).
1043  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1044  return i;
1045  if (!MO.isReg() || !MO.isDef())
1046  continue;
1047  Register MOReg = MO.getReg();
1048  bool Found = (MOReg == Reg);
1049  if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1050  if (Overlap)
1051  Found = TRI->regsOverlap(MOReg, Reg);
1052  else
1053  Found = TRI->isSubRegister(MOReg, Reg);
1054  }
1055  if (Found && (!isDead || MO.isDead()))
1056  return i;
1057  }
1058  return -1;
1059 }
1060 
1061 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1062 /// operand list that is used to represent the predicate. It returns -1 if
1063 /// none is found.
1065  // Don't call MCID.findFirstPredOperandIdx() because this variant
1066  // is sometimes called on an instruction that's not yet complete, and
1067  // so the number of operands is less than the MCID indicates. In
1068  // particular, the PTX target does this.
1069  const MCInstrDesc &MCID = getDesc();
1070  if (MCID.isPredicable()) {
1071  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1072  if (MCID.OpInfo[i].isPredicate())
1073  return i;
1074  }
1075 
1076  return -1;
1077 }
1078 
1079 // MachineOperand::TiedTo is 4 bits wide.
1080 const unsigned TiedMax = 15;
1081 
1082 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1083 ///
1084 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1085 /// field. TiedTo can have these values:
1086 ///
1087 /// 0: Operand is not tied to anything.
1088 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1089 /// TiedMax: Tied to an operand >= TiedMax-1.
1090 ///
1091 /// The tied def must be one of the first TiedMax operands on a normal
1092 /// instruction. INLINEASM instructions allow more tied defs.
1093 ///
1094 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1095  MachineOperand &DefMO = getOperand(DefIdx);
1096  MachineOperand &UseMO = getOperand(UseIdx);
1097  assert(DefMO.isDef() && "DefIdx must be a def operand");
1098  assert(UseMO.isUse() && "UseIdx must be a use operand");
1099  assert(!DefMO.isTied() && "Def is already tied to another use");
1100  assert(!UseMO.isTied() && "Use is already tied to another def");
1101 
1102  if (DefIdx < TiedMax)
1103  UseMO.TiedTo = DefIdx + 1;
1104  else {
1105  // Inline asm can use the group descriptors to find tied operands,
1106  // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1107  // but on normal instruction, the tied def must be within the first TiedMax
1108  // operands.
1109  assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1110  "DefIdx out of range");
1111  UseMO.TiedTo = TiedMax;
1112  }
1113 
1114  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1115  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1116 }
1117 
1118 /// Given the index of a tied register operand, find the operand it is tied to.
1119 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1120 /// which must exist.
1121 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1122  const MachineOperand &MO = getOperand(OpIdx);
1123  assert(MO.isTied() && "Operand isn't tied");
1124 
1125  // Normally TiedTo is in range.
1126  if (MO.TiedTo < TiedMax)
1127  return MO.TiedTo - 1;
1128 
1129  // Uses on normal instructions can be out of range.
1130  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1131  // Normal tied defs must be in the 0..TiedMax-1 range.
1132  if (MO.isUse())
1133  return TiedMax - 1;
1134  // MO is a def. Search for the tied use.
1135  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1136  const MachineOperand &UseMO = getOperand(i);
1137  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1138  return i;
1139  }
1140  llvm_unreachable("Can't find tied use");
1141  }
1142 
1143  if (getOpcode() == TargetOpcode::STATEPOINT) {
1144  // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1145  // on registers.
1146  StatepointOpers SO(this);
1147  unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1148  assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1149  unsigned NumDefs = getNumDefs();
1150  for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1151  while (!getOperand(CurUseIdx).isReg())
1152  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1153  if (OpIdx == CurDefIdx)
1154  return CurUseIdx;
1155  if (OpIdx == CurUseIdx)
1156  return CurDefIdx;
1157  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1158  }
1159  llvm_unreachable("Can't find tied use");
1160  }
1161 
1162  // Now deal with inline asm by parsing the operand group descriptor flags.
1163  // Find the beginning of each operand group.
1164  SmallVector<unsigned, 8> GroupIdx;
1165  unsigned OpIdxGroup = ~0u;
1166  unsigned NumOps;
1167  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1168  i += NumOps) {
1169  const MachineOperand &FlagMO = getOperand(i);
1170  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1171  unsigned CurGroup = GroupIdx.size();
1172  GroupIdx.push_back(i);
1173  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1174  // OpIdx belongs to this operand group.
1175  if (OpIdx > i && OpIdx < i + NumOps)
1176  OpIdxGroup = CurGroup;
1177  unsigned TiedGroup;
1178  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1179  continue;
1180  // Operands in this group are tied to operands in TiedGroup which must be
1181  // earlier. Find the number of operands between the two groups.
1182  unsigned Delta = i - GroupIdx[TiedGroup];
1183 
1184  // OpIdx is a use tied to TiedGroup.
1185  if (OpIdxGroup == CurGroup)
1186  return OpIdx - Delta;
1187 
1188  // OpIdx is a def tied to this use group.
1189  if (OpIdxGroup == TiedGroup)
1190  return OpIdx + Delta;
1191  }
1192  llvm_unreachable("Invalid tied operand on inline asm");
1193 }
1194 
1195 /// clearKillInfo - Clears kill flags on all operands.
1196 ///
1198  for (MachineOperand &MO : operands()) {
1199  if (MO.isReg() && MO.isUse())
1200  MO.setIsKill(false);
1201  }
1202 }
1203 
1205  unsigned SubIdx,
1206  const TargetRegisterInfo &RegInfo) {
1207  if (Register::isPhysicalRegister(ToReg)) {
1208  if (SubIdx)
1209  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1210  for (MachineOperand &MO : operands()) {
1211  if (!MO.isReg() || MO.getReg() != FromReg)
1212  continue;
1213  MO.substPhysReg(ToReg, RegInfo);
1214  }
1215  } else {
1216  for (MachineOperand &MO : operands()) {
1217  if (!MO.isReg() || MO.getReg() != FromReg)
1218  continue;
1219  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1220  }
1221  }
1222 }
1223 
1224 /// isSafeToMove - Return true if it is safe to move this instruction. If
1225 /// SawStore is set to true, it means that there is a store (or call) between
1226 /// the instruction's location and its intended destination.
1227 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1228  // Ignore stuff that we obviously can't move.
1229  //
1230  // Treat volatile loads as stores. This is not strictly necessary for
1231  // volatiles, but it is required for atomic loads. It is not allowed to move
1232  // a load across an atomic load with Ordering > Monotonic.
1233  if (mayStore() || isCall() || isPHI() ||
1234  (mayLoad() && hasOrderedMemoryRef())) {
1235  SawStore = true;
1236  return false;
1237  }
1238 
1239  if (isPosition() || isDebugInstr() || isTerminator() ||
1241  return false;
1242 
1243  // See if this instruction does a load. If so, we have to guarantee that the
1244  // loaded value doesn't change between the load and the its intended
1245  // destination. The check for isInvariantLoad gives the target the chance to
1246  // classify the load as always returning a constant, e.g. a constant pool
1247  // load.
1249  // Otherwise, this is a real load. If there is a store between the load and
1250  // end of block, we can't move it.
1251  return !SawStore;
1252 
1253  return true;
1254 }
1255 
1257  bool UseTBAA, const MachineMemOperand *MMOa,
1258  const MachineMemOperand *MMOb) {
1259  // The following interface to AA is fashioned after DAGCombiner::isAlias and
1260  // operates with MachineMemOperand offset with some important assumptions:
1261  // - LLVM fundamentally assumes flat address spaces.
1262  // - MachineOperand offset can *only* result from legalization and cannot
1263  // affect queries other than the trivial case of overlap checking.
1264  // - These offsets never wrap and never step outside of allocated objects.
1265  // - There should never be any negative offsets here.
1266  //
1267  // FIXME: Modify API to hide this math from "user"
1268  // Even before we go to AA we can reason locally about some memory objects. It
1269  // can save compile time, and possibly catch some corner cases not currently
1270  // covered.
1271 
1272  int64_t OffsetA = MMOa->getOffset();
1273  int64_t OffsetB = MMOb->getOffset();
1274  int64_t MinOffset = std::min(OffsetA, OffsetB);
1275 
1276  uint64_t WidthA = MMOa->getSize();
1277  uint64_t WidthB = MMOb->getSize();
1278  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1279  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1280 
1281  const Value *ValA = MMOa->getValue();
1282  const Value *ValB = MMOb->getValue();
1283  bool SameVal = (ValA && ValB && (ValA == ValB));
1284  if (!SameVal) {
1285  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1286  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1287  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1288  return false;
1289  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1290  return false;
1291  if (PSVa && PSVb && (PSVa == PSVb))
1292  SameVal = true;
1293  }
1294 
1295  if (SameVal) {
1296  if (!KnownWidthA || !KnownWidthB)
1297  return true;
1298  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1299  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1300  return (MinOffset + LowWidth > MaxOffset);
1301  }
1302 
1303  if (!AA)
1304  return true;
1305 
1306  if (!ValA || !ValB)
1307  return true;
1308 
1309  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1310  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1311 
1312  int64_t OverlapA =
1313  KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1314  int64_t OverlapB =
1315  KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1316 
1317  return !AA->isNoAlias(
1318  MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1319  MemoryLocation(ValB, OverlapB,
1320  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1321 }
1322 
1324  bool UseTBAA) const {
1325  const MachineFunction *MF = getMF();
1326  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1327  const MachineFrameInfo &MFI = MF->getFrameInfo();
1328 
1329  // Exclude call instruction which may alter the memory but can not be handled
1330  // by this function.
1331  if (isCall() || Other.isCall())
1332  return true;
1333 
1334  // If neither instruction stores to memory, they can't alias in any
1335  // meaningful way, even if they read from the same address.
1336  if (!mayStore() && !Other.mayStore())
1337  return false;
1338 
1339  // Both instructions must be memory operations to be able to alias.
1340  if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1341  return false;
1342 
1343  // Let the target decide if memory accesses cannot possibly overlap.
1345  return false;
1346 
1347  // Memory operations without memory operands may access anything. Be
1348  // conservative and assume `MayAlias`.
1349  if (memoperands_empty() || Other.memoperands_empty())
1350  return true;
1351 
1352  // Skip if there are too many memory operands.
1353  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1354  if (NumChecks > TII->getMemOperandAACheckLimit())
1355  return true;
1356 
1357  // Check each pair of memory operands from both instructions, which can't
1358  // alias only if all pairs won't alias.
1359  for (auto *MMOa : memoperands())
1360  for (auto *MMOb : Other.memoperands())
1361  if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1362  return true;
1363 
1364  return false;
1365 }
1366 
1367 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1368 /// or volatile memory reference, or if the information describing the memory
1369 /// reference is not available. Return false if it is known to have no ordered
1370 /// memory references.
1372  // An instruction known never to access memory won't have a volatile access.
1373  if (!mayStore() &&
1374  !mayLoad() &&
1375  !isCall() &&
1377  return false;
1378 
1379  // Otherwise, if the instruction has no memory reference information,
1380  // conservatively assume it wasn't preserved.
1381  if (memoperands_empty())
1382  return true;
1383 
1384  // Check if any of our memory operands are ordered.
1385  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1386  return !MMO->isUnordered();
1387  });
1388 }
1389 
1390 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1391 /// trap and is loading from a location whose value is invariant across a run of
1392 /// this function.
1394  // If the instruction doesn't load at all, it isn't an invariant load.
1395  if (!mayLoad())
1396  return false;
1397 
1398  // If the instruction has lost its memoperands, conservatively assume that
1399  // it may not be an invariant load.
1400  if (memoperands_empty())
1401  return false;
1402 
1403  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1404 
1405  for (MachineMemOperand *MMO : memoperands()) {
1406  if (!MMO->isUnordered())
1407  // If the memory operand has ordering side effects, we can't move the
1408  // instruction. Such an instruction is technically an invariant load,
1409  // but the caller code would need updated to expect that.
1410  return false;
1411  if (MMO->isStore()) return false;
1412  if (MMO->isInvariant() && MMO->isDereferenceable())
1413  continue;
1414 
1415  // A load from a constant PseudoSourceValue is invariant.
1416  if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1417  if (PSV->isConstant(&MFI))
1418  continue;
1419  }
1420 
1421  // Otherwise assume conservatively.
1422  return false;
1423  }
1424 
1425  // Everything checks out.
1426  return true;
1427 }
1428 
1429 /// isConstantValuePHI - If the specified instruction is a PHI that always
1430 /// merges together the same virtual register, return the register, otherwise
1431 /// return 0.
1433  if (!isPHI())
1434  return 0;
1435  assert(getNumOperands() >= 3 &&
1436  "It's illegal to have a PHI without source operands");
1437 
1438  Register Reg = getOperand(1).getReg();
1439  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1440  if (getOperand(i).getReg() != Reg)
1441  return 0;
1442  return Reg;
1443 }
1444 
1447  return true;
1448  if (isInlineAsm()) {
1449  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1450  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1451  return true;
1452  }
1453 
1454  return false;
1455 }
1456 
1458  return mayStore() || isCall() ||
1460 }
1461 
1462 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1463 ///
1465  for (const MachineOperand &MO : operands()) {
1466  if (!MO.isReg() || MO.isUse())
1467  continue;
1468  if (!MO.isDead())
1469  return false;
1470  }
1471  return true;
1472 }
1473 
1474 /// copyImplicitOps - Copy implicit register operands from specified
1475 /// instruction to this instruction.
1477  const MachineInstr &MI) {
1478  for (const MachineOperand &MO :
1479  llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1480  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1481  addOperand(MF, MO);
1482 }
1483 
1485  const MCInstrDesc &MCID = getDesc();
1486  if (MCID.Opcode == TargetOpcode::STATEPOINT)
1487  return true;
1488  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1489  const auto &Operand = getOperand(I);
1490  if (!Operand.isReg() || Operand.isDef())
1491  // Ignore the defined registers as MCID marks only the uses as tied.
1492  continue;
1493  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1494  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1495  if (ExpectedTiedIdx != TiedIdx)
1496  return true;
1497  }
1498  return false;
1499 }
1500 
1501 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1502  const MachineRegisterInfo &MRI) const {
1503  const MachineOperand &Op = getOperand(OpIdx);
1504  if (!Op.isReg())
1505  return LLT{};
1506 
1507  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1508  return MRI.getType(Op.getReg());
1509 
1510  auto &OpInfo = getDesc().OpInfo[OpIdx];
1511  if (!OpInfo.isGenericType())
1512  return MRI.getType(Op.getReg());
1513 
1514  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1515  return LLT{};
1516 
1517  LLT TypeToPrint = MRI.getType(Op.getReg());
1518  // Don't mark the type index printed if it wasn't actually printed: maybe
1519  // another operand with the same type index has an actual type attached:
1520  if (TypeToPrint.isValid())
1521  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1522  return TypeToPrint;
1523 }
1524 
1525 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1527  dbgs() << " ";
1528  print(dbgs());
1529 }
1530 
1531 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1532  const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1533  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1534  if (Depth >= MaxDepth)
1535  return;
1536  if (!AlreadySeenInstrs.insert(this).second)
1537  return;
1538  // PadToColumn always inserts at least one space.
1539  // Don't mess up the alignment if we don't want any space.
1540  if (Depth)
1541  fdbgs().PadToColumn(Depth * 2);
1542  print(fdbgs());
1543  for (const MachineOperand &MO : operands()) {
1544  if (!MO.isReg() || MO.isDef())
1545  continue;
1546  Register Reg = MO.getReg();
1547  if (Reg.isPhysical())
1548  continue;
1549  const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1550  if (NewMI == nullptr)
1551  continue;
1552  NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1553  }
1554 }
1555 
1557  unsigned MaxDepth) const {
1558  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1559  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1560 }
1561 #endif
1562 
1563 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1564  bool SkipDebugLoc, bool AddNewLine,
1565  const TargetInstrInfo *TII) const {
1566  const Module *M = nullptr;
1567  const Function *F = nullptr;
1568  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1569  F = &MF->getFunction();
1570  M = F->getParent();
1571  if (!TII)
1572  TII = MF->getSubtarget().getInstrInfo();
1573  }
1574 
1575  ModuleSlotTracker MST(M);
1576  if (F)
1577  MST.incorporateFunction(*F);
1578  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1579 }
1580 
1582  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1583  bool AddNewLine, const TargetInstrInfo *TII) const {
1584  // We can be a bit tidier if we know the MachineFunction.
1585  const TargetRegisterInfo *TRI = nullptr;
1586  const MachineRegisterInfo *MRI = nullptr;
1587  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1588  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1589 
1590  if (isCFIInstruction())
1591  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1592 
1593  SmallBitVector PrintedTypes(8);
1594  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1595  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1596  if (!ShouldPrintRegisterTies)
1597  return 0U;
1598  const MachineOperand &MO = getOperand(OpIdx);
1599  if (MO.isReg() && MO.isTied() && !MO.isDef())
1600  return findTiedOperandIdx(OpIdx);
1601  return 0U;
1602  };
1603  unsigned StartOp = 0;
1604  unsigned e = getNumOperands();
1605 
1606  // Print explicitly defined operands on the left of an assignment syntax.
1607  while (StartOp < e) {
1608  const MachineOperand &MO = getOperand(StartOp);
1609  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1610  break;
1611 
1612  if (StartOp != 0)
1613  OS << ", ";
1614 
1615  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1616  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1617  MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1618  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1619  ++StartOp;
1620  }
1621 
1622  if (StartOp != 0)
1623  OS << " = ";
1624 
1626  OS << "frame-setup ";
1628  OS << "frame-destroy ";
1630  OS << "nnan ";
1632  OS << "ninf ";
1634  OS << "nsz ";
1636  OS << "arcp ";
1638  OS << "contract ";
1640  OS << "afn ";
1642  OS << "reassoc ";
1644  OS << "nuw ";
1646  OS << "nsw ";
1648  OS << "exact ";
1650  OS << "nofpexcept ";
1652  OS << "nomerge ";
1653 
1654  // Print the opcode name.
1655  if (TII)
1656  OS << TII->getName(getOpcode());
1657  else
1658  OS << "UNKNOWN";
1659 
1660  if (SkipOpers)
1661  return;
1662 
1663  // Print the rest of the operands.
1664  bool FirstOp = true;
1665  unsigned AsmDescOp = ~0u;
1666  unsigned AsmOpCount = 0;
1667 
1669  // Print asm string.
1670  OS << " ";
1671  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1672  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1673  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1674  getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1675  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1676  IntrinsicInfo);
1677 
1678  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1679  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1680  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1681  OS << " [sideeffect]";
1682  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1683  OS << " [mayload]";
1684  if (ExtraInfo & InlineAsm::Extra_MayStore)
1685  OS << " [maystore]";
1686  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1687  OS << " [isconvergent]";
1688  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1689  OS << " [alignstack]";
1691  OS << " [attdialect]";
1693  OS << " [inteldialect]";
1694 
1695  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1696  FirstOp = false;
1697  }
1698 
1699  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1700  const MachineOperand &MO = getOperand(i);
1701 
1702  if (FirstOp) FirstOp = false; else OS << ",";
1703  OS << " ";
1704 
1705  if (isDebugValue() && MO.isMetadata()) {
1706  // Pretty print DBG_VALUE* instructions.
1707  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1708  if (DIV && !DIV->getName().empty())
1709  OS << "!\"" << DIV->getName() << '\"';
1710  else {
1711  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1712  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1713  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1714  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1715  }
1716  } else if (isDebugLabel() && MO.isMetadata()) {
1717  // Pretty print DBG_LABEL instructions.
1718  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1719  if (DIL && !DIL->getName().empty())
1720  OS << "\"" << DIL->getName() << '\"';
1721  else {
1722  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1723  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1724  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1725  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1726  }
1727  } else if (i == AsmDescOp && MO.isImm()) {
1728  // Pretty print the inline asm operand descriptor.
1729  OS << '$' << AsmOpCount++;
1730  unsigned Flag = MO.getImm();
1731  OS << ":[";
1733 
1734  unsigned RCID = 0;
1737  if (TRI) {
1738  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1739  } else
1740  OS << ":RC" << RCID;
1741  }
1742 
1743  if (InlineAsm::isMemKind(Flag)) {
1744  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1745  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1746  }
1747 
1748  unsigned TiedTo = 0;
1750  OS << " tiedto:$" << TiedTo;
1751 
1752  OS << ']';
1753 
1754  // Compute the index of the next operand descriptor.
1755  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1756  } else {
1757  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1758  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1759  if (MO.isImm() && isOperandSubregIdx(i))
1761  else
1762  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1763  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1764  }
1765  }
1766 
1767  // Print any optional symbols attached to this instruction as-if they were
1768  // operands.
1769  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1770  if (!FirstOp) {
1771  FirstOp = false;
1772  OS << ',';
1773  }
1774  OS << " pre-instr-symbol ";
1775  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1776  }
1777  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1778  if (!FirstOp) {
1779  FirstOp = false;
1780  OS << ',';
1781  }
1782  OS << " post-instr-symbol ";
1783  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1784  }
1785  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1786  if (!FirstOp) {
1787  FirstOp = false;
1788  OS << ',';
1789  }
1790  OS << " heap-alloc-marker ";
1791  HeapAllocMarker->printAsOperand(OS, MST);
1792  }
1793  if (MDNode *PCSections = getPCSections()) {
1794  if (!FirstOp) {
1795  FirstOp = false;
1796  OS << ',';
1797  }
1798  OS << " pcsections ";
1799  PCSections->printAsOperand(OS, MST);
1800  }
1801  if (uint32_t CFIType = getCFIType()) {
1802  if (!FirstOp)
1803  OS << ',';
1804  OS << " cfi-type " << CFIType;
1805  }
1806 
1807  if (DebugInstrNum) {
1808  if (!FirstOp)
1809  OS << ",";
1810  OS << " debug-instr-number " << DebugInstrNum;
1811  }
1812 
1813  if (!SkipDebugLoc) {
1814  if (const DebugLoc &DL = getDebugLoc()) {
1815  if (!FirstOp)
1816  OS << ',';
1817  OS << " debug-location ";
1818  DL->printAsOperand(OS, MST);
1819  }
1820  }
1821 
1822  if (!memoperands_empty()) {
1824  const LLVMContext *Context = nullptr;
1825  std::unique_ptr<LLVMContext> CtxPtr;
1826  const MachineFrameInfo *MFI = nullptr;
1827  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1828  MFI = &MF->getFrameInfo();
1829  Context = &MF->getFunction().getContext();
1830  } else {
1831  CtxPtr = std::make_unique<LLVMContext>();
1832  Context = CtxPtr.get();
1833  }
1834 
1835  OS << " :: ";
1836  bool NeedComma = false;
1837  for (const MachineMemOperand *Op : memoperands()) {
1838  if (NeedComma)
1839  OS << ", ";
1840  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1841  NeedComma = true;
1842  }
1843  }
1844 
1845  if (SkipDebugLoc)
1846  return;
1847 
1848  bool HaveSemi = false;
1849 
1850  // Print debug location information.
1851  if (const DebugLoc &DL = getDebugLoc()) {
1852  if (!HaveSemi) {
1853  OS << ';';
1854  HaveSemi = true;
1855  }
1856  OS << ' ';
1857  DL.print(OS);
1858  }
1859 
1860  // Print extra comments for DEBUG_VALUE.
1861  if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1862  if (!HaveSemi) {
1863  OS << ";";
1864  HaveSemi = true;
1865  }
1866  auto *DV = getDebugVariable();
1867  OS << " line no:" << DV->getLine();
1868  if (isIndirectDebugValue())
1869  OS << " indirect";
1870  }
1871  // TODO: DBG_LABEL
1872 
1873  if (AddNewLine)
1874  OS << '\n';
1875 }
1876 
1878  const TargetRegisterInfo *RegInfo,
1879  bool AddIfNotFound) {
1880  bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1881  bool hasAliases = isPhysReg &&
1882  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1883  bool Found = false;
1884  SmallVector<unsigned,4> DeadOps;
1885  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1886  MachineOperand &MO = getOperand(i);
1887  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1888  continue;
1889 
1890  // DEBUG_VALUE nodes do not contribute to code generation and should
1891  // always be ignored. Failure to do so may result in trying to modify
1892  // KILL flags on DEBUG_VALUE nodes.
1893  if (MO.isDebug())
1894  continue;
1895 
1896  Register Reg = MO.getReg();
1897  if (!Reg)
1898  continue;
1899 
1900  if (Reg == IncomingReg) {
1901  if (!Found) {
1902  if (MO.isKill())
1903  // The register is already marked kill.
1904  return true;
1905  if (isPhysReg && isRegTiedToDefOperand(i))
1906  // Two-address uses of physregs must not be marked kill.
1907  return true;
1908  MO.setIsKill();
1909  Found = true;
1910  }
1911  } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1912  // A super-register kill already exists.
1913  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1914  return true;
1915  if (RegInfo->isSubRegister(IncomingReg, Reg))
1916  DeadOps.push_back(i);
1917  }
1918  }
1919 
1920  // Trim unneeded kill operands.
1921  while (!DeadOps.empty()) {
1922  unsigned OpIdx = DeadOps.back();
1923  if (getOperand(OpIdx).isImplicit() &&
1924  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1925  removeOperand(OpIdx);
1926  else
1927  getOperand(OpIdx).setIsKill(false);
1928  DeadOps.pop_back();
1929  }
1930 
1931  // If not found, this means an alias of one of the operands is killed. Add a
1932  // new implicit operand if required.
1933  if (!Found && AddIfNotFound) {
1935  false /*IsDef*/,
1936  true /*IsImp*/,
1937  true /*IsKill*/));
1938  return true;
1939  }
1940  return Found;
1941 }
1942 
1944  const TargetRegisterInfo *RegInfo) {
1946  RegInfo = nullptr;
1947  for (MachineOperand &MO : operands()) {
1948  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1949  continue;
1950  Register OpReg = MO.getReg();
1951  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1952  MO.setIsKill(false);
1953  }
1954 }
1955 
1957  const TargetRegisterInfo *RegInfo,
1958  bool AddIfNotFound) {
1959  bool isPhysReg = Register::isPhysicalRegister(Reg);
1960  bool hasAliases = isPhysReg &&
1961  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1962  bool Found = false;
1963  SmallVector<unsigned,4> DeadOps;
1964  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1965  MachineOperand &MO = getOperand(i);
1966  if (!MO.isReg() || !MO.isDef())
1967  continue;
1968  Register MOReg = MO.getReg();
1969  if (!MOReg)
1970  continue;
1971 
1972  if (MOReg == Reg) {
1973  MO.setIsDead();
1974  Found = true;
1975  } else if (hasAliases && MO.isDead() &&
1977  // There exists a super-register that's marked dead.
1978  if (RegInfo->isSuperRegister(Reg, MOReg))
1979  return true;
1980  if (RegInfo->isSubRegister(Reg, MOReg))
1981  DeadOps.push_back(i);
1982  }
1983  }
1984 
1985  // Trim unneeded dead operands.
1986  while (!DeadOps.empty()) {
1987  unsigned OpIdx = DeadOps.back();
1988  if (getOperand(OpIdx).isImplicit() &&
1989  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1990  removeOperand(OpIdx);
1991  else
1992  getOperand(OpIdx).setIsDead(false);
1993  DeadOps.pop_back();
1994  }
1995 
1996  // If not found, this means an alias of one of the operands is dead. Add a
1997  // new implicit operand if required.
1998  if (Found || !AddIfNotFound)
1999  return Found;
2000 
2002  true /*IsDef*/,
2003  true /*IsImp*/,
2004  false /*IsKill*/,
2005  true /*IsDead*/));
2006  return true;
2007 }
2008 
2010  for (MachineOperand &MO : operands()) {
2011  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2012  continue;
2013  MO.setIsDead(false);
2014  }
2015 }
2016 
2018  for (MachineOperand &MO : operands()) {
2019  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2020  continue;
2021  MO.setIsUndef(IsUndef);
2022  }
2023 }
2024 
2026  const TargetRegisterInfo *RegInfo) {
2028  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2029  if (MO)
2030  return;
2031  } else {
2032  for (const MachineOperand &MO : operands()) {
2033  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2034  MO.getSubReg() == 0)
2035  return;
2036  }
2037  }
2039  true /*IsDef*/,
2040  true /*IsImp*/));
2041 }
2042 
2044  const TargetRegisterInfo &TRI) {
2045  bool HasRegMask = false;
2046  for (MachineOperand &MO : operands()) {
2047  if (MO.isRegMask()) {
2048  HasRegMask = true;
2049  continue;
2050  }
2051  if (!MO.isReg() || !MO.isDef()) continue;
2052  Register Reg = MO.getReg();
2053  if (!Reg.isPhysical())
2054  continue;
2055  // If there are no uses, including partial uses, the def is dead.
2056  if (llvm::none_of(UsedRegs,
2057  [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2058  MO.setIsDead();
2059  }
2060 
2061  // This is a call with a register mask operand.
2062  // Mask clobbers are always dead, so add defs for the non-dead defines.
2063  if (HasRegMask)
2064  for (const Register &UsedReg : UsedRegs)
2065  addRegisterDefined(UsedReg, &TRI);
2066 }
2067 
2068 unsigned
2070  // Build up a buffer of hash code components.
2071  SmallVector<size_t, 16> HashComponents;
2072  HashComponents.reserve(MI->getNumOperands() + 1);
2073  HashComponents.push_back(MI->getOpcode());
2074  for (const MachineOperand &MO : MI->operands()) {
2075  if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2076  continue; // Skip virtual register defs.
2077 
2078  HashComponents.push_back(hash_value(MO));
2079  }
2080  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2081 }
2082 
2084  // Find the source location cookie.
2085  uint64_t LocCookie = 0;
2086  const MDNode *LocMD = nullptr;
2087  for (unsigned i = getNumOperands(); i != 0; --i) {
2088  if (getOperand(i-1).isMetadata() &&
2089  (LocMD = getOperand(i-1).getMetadata()) &&
2090  LocMD->getNumOperands() != 0) {
2091  if (const ConstantInt *CI =
2092  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2093  LocCookie = CI->getZExtValue();
2094  break;
2095  }
2096  }
2097  }
2098 
2099  if (const MachineBasicBlock *MBB = getParent())
2100  if (const MachineFunction *MF = MBB->getParent())
2101  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2103 }
2104 
2106  const MCInstrDesc &MCID, bool IsIndirect,
2107  Register Reg, const MDNode *Variable,
2108  const MDNode *Expr) {
2109  assert(isa<DILocalVariable>(Variable) && "not a variable");
2110  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2111  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2112  "Expected inlined-at fields to agree");
2113  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2114  if (IsIndirect)
2115  MIB.addImm(0U);
2116  else
2117  MIB.addReg(0U);
2118  return MIB.addMetadata(Variable).addMetadata(Expr);
2119 }
2120 
2122  const MCInstrDesc &MCID, bool IsIndirect,
2123  const MachineOperand &MO,
2124  const MDNode *Variable, const MDNode *Expr) {
2125  assert(isa<DILocalVariable>(Variable) && "not a variable");
2126  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2127  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2128  "Expected inlined-at fields to agree");
2129  if (MO.isReg())
2130  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2131 
2132  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2133  if (IsIndirect)
2134  MIB.addImm(0U);
2135  else
2136  MIB.addReg(0U);
2137  return MIB.addMetadata(Variable).addMetadata(Expr);
2138 }
2139 
2141  const MCInstrDesc &MCID, bool IsIndirect,
2143  const MDNode *Variable, const MDNode *Expr) {
2144  assert(isa<DILocalVariable>(Variable) && "not a variable");
2145  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2146  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2147  "Expected inlined-at fields to agree");
2148  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2149  return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2150 
2151  auto MIB = BuildMI(MF, DL, MCID);
2152  MIB.addMetadata(Variable).addMetadata(Expr);
2153  for (const MachineOperand &MO : MOs)
2154  if (MO.isReg())
2155  MIB.addReg(MO.getReg());
2156  else
2157  MIB.add(MO);
2158  return MIB;
2159 }
2160 
2163  const DebugLoc &DL, const MCInstrDesc &MCID,
2164  bool IsIndirect, Register Reg,
2165  const MDNode *Variable, const MDNode *Expr) {
2166  MachineFunction &MF = *BB.getParent();
2167  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2168  BB.insert(I, MI);
2169  return MachineInstrBuilder(MF, MI);
2170 }
2171 
2174  const DebugLoc &DL, const MCInstrDesc &MCID,
2175  bool IsIndirect, MachineOperand &MO,
2176  const MDNode *Variable, const MDNode *Expr) {
2177  MachineFunction &MF = *BB.getParent();
2178  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2179  BB.insert(I, MI);
2180  return MachineInstrBuilder(MF, *MI);
2181 }
2182 
2185  const DebugLoc &DL, const MCInstrDesc &MCID,
2186  bool IsIndirect, ArrayRef<MachineOperand> MOs,
2187  const MDNode *Variable, const MDNode *Expr) {
2188  MachineFunction &MF = *BB.getParent();
2189  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2190  BB.insert(I, MI);
2191  return MachineInstrBuilder(MF, *MI);
2192 }
2193 
2194 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2195 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2196 static const DIExpression *
2198  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2199  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2200  "Expected inlined-at fields to agree");
2201 
2202  const DIExpression *Expr = MI.getDebugExpression();
2203  if (MI.isIndirectDebugValue()) {
2204  assert(MI.getDebugOffset().getImm() == 0 &&
2205  "DBG_VALUE with nonzero offset");
2207  } else if (MI.isDebugValueList()) {
2208  // We will replace the spilled register with a frame index, so
2209  // immediately deref all references to the spilled register.
2210  std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2211  for (const MachineOperand *Op : SpilledOperands) {
2212  unsigned OpIdx = MI.getDebugOperandIndex(Op);
2213  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2214  }
2215  }
2216  return Expr;
2217 }
2219  Register SpillReg) {
2220  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2222  for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2223  SpillOperands.push_back(&Op);
2224  return computeExprForSpill(MI, SpillOperands);
2225 }
2226 
2229  const MachineInstr &Orig,
2230  int FrameIndex, Register SpillReg) {
2231  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2232  MachineInstrBuilder NewMI =
2233  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2234  // Non-Variadic Operands: Location, Offset, Variable, Expression
2235  // Variadic Operands: Variable, Expression, Locations...
2236  if (Orig.isNonListDebugValue())
2237  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2238  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2239  if (Orig.isDebugValueList()) {
2240  for (const MachineOperand &Op : Orig.debug_operands())
2241  if (Op.isReg() && Op.getReg() == SpillReg)
2242  NewMI.addFrameIndex(FrameIndex);
2243  else
2244  NewMI.add(MachineOperand(Op));
2245  }
2246  return NewMI;
2247 }
2250  const MachineInstr &Orig, int FrameIndex,
2251  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2252  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2253  MachineInstrBuilder NewMI =
2254  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2255  // Non-Variadic Operands: Location, Offset, Variable, Expression
2256  // Variadic Operands: Variable, Expression, Locations...
2257  if (Orig.isNonListDebugValue())
2258  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2259  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2260  if (Orig.isDebugValueList()) {
2261  for (const MachineOperand &Op : Orig.debug_operands())
2262  if (is_contained(SpilledOperands, &Op))
2263  NewMI.addFrameIndex(FrameIndex);
2264  else
2265  NewMI.add(MachineOperand(Op));
2266  }
2267  return NewMI;
2268 }
2269 
2271  Register Reg) {
2272  const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2273  if (Orig.isNonListDebugValue())
2274  Orig.getDebugOffset().ChangeToImmediate(0U);
2276  Op.ChangeToFrameIndex(FrameIndex);
2277  Orig.getDebugExpressionOp().setMetadata(Expr);
2278 }
2279 
2281  SmallVectorImpl<MachineInstr *> &DbgValues) {
2282  MachineInstr &MI = *this;
2283  if (!MI.getOperand(0).isReg())
2284  return;
2285 
2286  MachineBasicBlock::iterator DI = MI; ++DI;
2287  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2288  DI != DE; ++DI) {
2289  if (!DI->isDebugValue())
2290  return;
2291  if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2292  DbgValues.push_back(&*DI);
2293  }
2294 }
2295 
2297  // Collect matching debug values.
2299 
2300  if (!getOperand(0).isReg())
2301  return;
2302 
2303  Register DefReg = getOperand(0).getReg();
2304  auto *MRI = getRegInfo();
2305  for (auto &MO : MRI->use_operands(DefReg)) {
2306  auto *DI = MO.getParent();
2307  if (!DI->isDebugValue())
2308  continue;
2309  if (DI->hasDebugOperandForReg(DefReg)) {
2310  DbgValues.push_back(DI);
2311  }
2312  }
2313 
2314  // Propagate Reg to debug value instructions.
2315  for (auto *DBI : DbgValues)
2316  for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2317  Op.setReg(Reg);
2318 }
2319 
2321 
2322 static unsigned getSpillSlotSize(const MMOList &Accesses,
2323  const MachineFrameInfo &MFI) {
2324  unsigned Size = 0;
2325  for (const auto *A : Accesses)
2326  if (MFI.isSpillSlotObjectIndex(
2327  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2328  ->getFrameIndex()))
2329  Size += A->getSize();
2330  return Size;
2331 }
2332 
2335  int FI;
2336  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2337  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2338  if (MFI.isSpillSlotObjectIndex(FI))
2339  return (*memoperands_begin())->getSize();
2340  }
2341  return None;
2342 }
2343 
2346  MMOList Accesses;
2347  if (TII->hasStoreToStackSlot(*this, Accesses))
2348  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2349  return None;
2350 }
2351 
2354  int FI;
2355  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2356  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2357  if (MFI.isSpillSlotObjectIndex(FI))
2358  return (*memoperands_begin())->getSize();
2359  }
2360  return None;
2361 }
2362 
2365  MMOList Accesses;
2366  if (TII->hasLoadFromStackSlot(*this, Accesses))
2367  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2368  return None;
2369 }
2370 
2372  if (DebugInstrNum == 0)
2373  DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2374  return DebugInstrNum;
2375 }
2376 
2378  if (DebugInstrNum == 0)
2379  DebugInstrNum = MF.getNewDebugInstrNum();
2380  return DebugInstrNum;
2381 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1492
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1261
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:763
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:854
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:637
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
CmpMode::FP
@ FP
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:366
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:2009
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2043
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2371
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1956
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:172
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:271
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:35
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1748
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2069
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
Metadata.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1227
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:663
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1079
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:721
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:731
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:764
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:540
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:414
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::InlineAsm::AD_ATT
@ AD_ATT
Definition: InlineAsm.h:36
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:687
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1280
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:742
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1193
InlineAsm.h
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AAResults::isNoAlias
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
Definition: AliasAnalysis.h:348
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:754
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1248
MachineBasicBlock.h
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2025
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1464
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1432
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:53
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:693
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:369
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MachineFunction::getNewDebugInstrNum
unsigned getNewDebugInstrNum()
Definition: MachineFunction.h:1268
Module.h
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:385
TargetInstrInfo.h
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:100
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4865
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:975
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:477
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:678
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::Optional< unsigned >
llvm::SmallPtrSet< const MachineInstr *, 16 >
Operator.h
Hashing.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:840
hasIdenticalMMOs
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
Definition: MachineInstr.cpp:400
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:861
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:303
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PossiblyExactOperator
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:126
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:335
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:368
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:833
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1371
MachineRegisterInfo.h
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1579
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:594
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:593
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:245
llvm::MDNode::getNumOperands
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1298
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
AliasAnalysis.h
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1121
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:532
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:352
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:566
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
FormattedStream.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:144
llvm::MachineFunction::createMIExtraInfo
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
Definition: MachineFunction.cpp:531
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1508
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
getSpillSlotSize
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
Definition: MachineInstr.cpp:2322
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:872
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:492
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:989
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:206
Constants.h
llvm::AAResults
Definition: AliasAnalysis.h:294
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3096
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1476
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:357
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2227
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2345
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1197
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:568
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1191
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:227
llvm::fdbgs
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
Definition: FormattedStream.cpp:152
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:411
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1323
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:682
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:781
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1267
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:87
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition: MachineInstr.cpp:64
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1877
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:92
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:157
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:240
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:373
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1204
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:715
MachineInstrBundle.h
llvm::MachineInstr::getCFIType
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:796
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:963
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:199
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:790
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:462
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:598
llvm::SmallVectorImpl::append
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:819
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1457
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1556
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:94
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:194
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1255
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:351
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:301
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:810
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:791
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:655
llvm::MDNode::getOperand
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1292
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:578
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:608
llvm::MachineFunction::deallocateOperandArray
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
Definition: MachineFunction.h:1019
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1501
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:450
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:567
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:422
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:771
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:78
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:36
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2083
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:866
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:749
uint64_t
TiedMax
const unsigned TiedMax
Definition: MachineInstr.cpp:1080
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:357
llvm::MachineInstr::getPCSections
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:786
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2270
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:777
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1978
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:838
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:376
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:102
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
MemoryLocation.h
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:2017
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:300
MCRegisterInfo.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:811
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::make_pointee_range
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2280
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:366
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:772
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1943
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2802
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FPMathOperator
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:167
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1861
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:1007
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:738
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:355
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:344
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1300
MachineModuleInfo.h
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:799
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:234
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:806
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:537
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:612
llvm::DebugLoc::hasTrivialDestructor
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1195
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1526
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:697
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:850
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:108
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:110
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:805
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition: MachineInstr.cpp:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:37
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1741
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1306
llvm::InlineAsm::MIOp_AsmString
@ MIOp_AsmString
Definition: InlineAsm.h:225
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1854
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:532
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:776
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:233
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2364
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
uint32_t
Compiler.h
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1064
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:112
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:230
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1563
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:896
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1264
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:752
llvm::OverflowingBinaryOperator
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:72
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:434
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1253
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:235
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:875
MemOperandsHaveAlias
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
Definition: MachineInstr.cpp:1256
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1244
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:1082
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:943
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
std
Definition: BitVector.h:851
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.cpp:1249
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:534
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:378
uint16_t
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:348
moveOperands
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
Definition: MachineInstr.cpp:179
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:519
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1069
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1445
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1393
llvm::Module::getContext
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:262
Casting.h
llvm::MachineFunction::allocateOperandArray
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
Definition: MachineFunction.h:1012
Function.h
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:870
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
llvm::MachineInstr::setPCSections
void setPCSections(MachineFunction &MF, MDNode *MD)
Definition: MachineInstr.cpp:501
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:242
StackMaps.h
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:90
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:702
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:98
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:718
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:424
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:743
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1332
llvm::hash_value
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:127
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:284
computeExprForSpill
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
Definition: MachineInstr.cpp:2197
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1265
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:659
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:184
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:215
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:1036
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:241
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:363
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:104
SmallBitVector.h
N
#define N
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:428
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::hash_combine_range
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:483
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:192
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:89
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineInstr::setCFIType
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
Definition: MachineInstr.cpp:510
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:349
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:96
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:713
ModuleSlotTracker.h
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1484
llvm::SmallVectorImpl< unsigned >
llvm::MachineBasicBlock::erase_instr
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.h:960
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:88
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:226
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2353
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:914
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1194
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3186
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1304
LLVMContext.h
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:231
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:403
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:330
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
raw_ostream.h
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1094
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1089
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:667
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:88
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1258
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1479
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:692
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:150
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:331
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:808
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:987
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1319
TargetRegisterInfo.h
Debug.h
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:477
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:210
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2334
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:740
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:362
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:232
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1251
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:288
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:207
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2296
llvm::LLT
Definition: LowLevelTypeImpl.h:39