LLVM  15.0.0git
MachineInstr.cpp
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1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/Hashing.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Metadata.h"
43 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Operator.h"
46 #include "llvm/MC/MCInstrDesc.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstdint>
59 #include <cstring>
60 #include <utility>
61 
62 using namespace llvm;
63 
65  if (const MachineBasicBlock *MBB = MI.getParent())
66  if (const MachineFunction *MF = MBB->getParent())
67  return MF;
68  return nullptr;
69 }
70 
71 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
72 // it.
73 static void tryToGetTargetInfo(const MachineInstr &MI,
74  const TargetRegisterInfo *&TRI,
75  const MachineRegisterInfo *&MRI,
76  const TargetIntrinsicInfo *&IntrinsicInfo,
77  const TargetInstrInfo *&TII) {
78 
79  if (const MachineFunction *MF = getMFIfAvailable(MI)) {
80  TRI = MF->getSubtarget().getRegisterInfo();
81  MRI = &MF->getRegInfo();
82  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83  TII = MF->getSubtarget().getInstrInfo();
84  }
85 }
86 
88  if (MCID->ImplicitDefs)
89  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
90  ++ImpDefs)
91  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
92  if (MCID->ImplicitUses)
93  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
94  ++ImpUses)
95  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
96 }
97 
98 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
99 /// implicit operands. It reserves space for the number of operands specified by
100 /// the MCInstrDesc.
101 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
102  DebugLoc DL, bool NoImp)
103  : MCID(&TID), DbgLoc(std::move(DL)), DebugInstrNum(0) {
104  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
105 
106  // Reserve space for the expected number of operands.
107  if (unsigned NumOps = MCID->getNumOperands() +
108  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
109  CapOperands = OperandCapacity::get(NumOps);
110  Operands = MF.allocateOperandArray(CapOperands);
111  }
112 
113  if (!NoImp)
115 }
116 
117 /// MachineInstr ctor - Copies MachineInstr arg exactly.
118 /// Does not copy the number from debug instruction numbering, to preserve
119 /// uniqueness.
120 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
121  : MCID(&MI.getDesc()), Info(MI.Info), DbgLoc(MI.getDebugLoc()),
122  DebugInstrNum(0) {
123  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
124 
125  CapOperands = OperandCapacity::get(MI.getNumOperands());
126  Operands = MF.allocateOperandArray(CapOperands);
127 
128  // Copy operands.
129  for (const MachineOperand &MO : MI.operands())
130  addOperand(MF, MO);
131 
132  // Copy all the sensible flags.
133  setFlags(MI.Flags);
134 }
135 
137  MovePos->getParent()->splice(MovePos, getParent(), getIterator());
138 }
139 
140 /// getRegInfo - If this instruction is embedded into a MachineFunction,
141 /// return the MachineRegisterInfo object for the current function, otherwise
142 /// return null.
143 MachineRegisterInfo *MachineInstr::getRegInfo() {
145  return &MBB->getParent()->getRegInfo();
146  return nullptr;
147 }
148 
149 void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
150  for (MachineOperand &MO : operands())
151  if (MO.isReg())
153 }
154 
155 void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
156  for (MachineOperand &MO : operands())
157  if (MO.isReg())
159 }
160 
163  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
164  MachineFunction *MF = MBB->getParent();
165  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
166  addOperand(*MF, Op);
167 }
168 
169 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
170 /// ranges. If MRI is non-null also update use-def chains.
172  unsigned NumOps, MachineRegisterInfo *MRI) {
173  if (MRI)
174  return MRI->moveOperands(Dst, Src, NumOps);
175  // MachineOperand is a trivially copyable type so we can just use memmove.
176  assert(Dst && Src && "Unknown operands");
177  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
178 }
179 
180 /// addOperand - Add the specified operand to the instruction. If it is an
181 /// implicit operand, it is added to the end of the operand list. If it is
182 /// an explicit operand it is added at the end of the explicit operand list
183 /// (before the first implicit operand).
185  assert(MCID && "Cannot add operands before providing an instr descriptor");
186 
187  // Check if we're adding one of our existing operands.
188  if (&Op >= Operands && &Op < Operands + NumOperands) {
189  // This is unusual: MI->addOperand(MI->getOperand(i)).
190  // If adding Op requires reallocating or moving existing operands around,
191  // the Op reference could go stale. Support it by copying Op.
192  MachineOperand CopyOp(Op);
193  return addOperand(MF, CopyOp);
194  }
195 
196  // Find the insert location for the new operand. Implicit registers go at
197  // the end, everything else goes before the implicit regs.
198  //
199  // FIXME: Allow mixed explicit and implicit operands on inline asm.
200  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
201  // implicit-defs, but they must not be moved around. See the FIXME in
202  // InstrEmitter.cpp.
203  unsigned OpNo = getNumOperands();
204  bool isImpReg = Op.isReg() && Op.isImplicit();
205  if (!isImpReg && !isInlineAsm()) {
206  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
207  --OpNo;
208  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
209  }
210  }
211 
212  // OpNo now points as the desired insertion point. Unless this is a variadic
213  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
214  // RegMask operands go between the explicit and implicit operands.
215  assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||
216  Op.isValidExcessOperand()) &&
217  "Trying to add an operand to a machine instr that is already done!");
218 
219  MachineRegisterInfo *MRI = getRegInfo();
220 
221  // Determine if the Operands array needs to be reallocated.
222  // Save the old capacity and operand array.
223  OperandCapacity OldCap = CapOperands;
224  MachineOperand *OldOperands = Operands;
225  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
226  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
227  Operands = MF.allocateOperandArray(CapOperands);
228  // Move the operands before the insertion point.
229  if (OpNo)
230  moveOperands(Operands, OldOperands, OpNo, MRI);
231  }
232 
233  // Move the operands following the insertion point.
234  if (OpNo != NumOperands)
235  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
236  MRI);
237  ++NumOperands;
238 
239  // Deallocate the old operand array.
240  if (OldOperands != Operands && OldOperands)
241  MF.deallocateOperandArray(OldCap, OldOperands);
242 
243  // Copy Op into place. It still needs to be inserted into the MRI use lists.
244  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
245  NewMO->ParentMI = this;
246 
247  // When adding a register operand, tell MRI about it.
248  if (NewMO->isReg()) {
249  // Ensure isOnRegUseList() returns false, regardless of Op's status.
250  NewMO->Contents.Reg.Prev = nullptr;
251  // Ignore existing ties. This is not a property that can be copied.
252  NewMO->TiedTo = 0;
253  // Add the new operand to MRI, but only for instructions in an MBB.
254  if (MRI)
255  MRI->addRegOperandToUseList(NewMO);
256  // The MCID operand information isn't accurate until we start adding
257  // explicit operands. The implicit operands are added first, then the
258  // explicits are inserted before them.
259  if (!isImpReg) {
260  // Tie uses to defs as indicated in MCInstrDesc.
261  if (NewMO->isUse()) {
262  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
263  if (DefIdx != -1)
264  tieOperands(DefIdx, OpNo);
265  }
266  // If the register operand is flagged as early, mark the operand as such.
267  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
268  NewMO->setIsEarlyClobber(true);
269  }
270  // Ensure debug instructions set debug flag on register uses.
271  if (NewMO->isUse() && isDebugInstr())
272  NewMO->setIsDebug();
273  }
274 }
275 
276 void MachineInstr::removeOperand(unsigned OpNo) {
277  assert(OpNo < getNumOperands() && "Invalid operand number");
278  untieRegOperand(OpNo);
279 
280 #ifndef NDEBUG
281  // Moving tied operands would break the ties.
282  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
283  if (Operands[i].isReg())
284  assert(!Operands[i].isTied() && "Cannot move tied operands");
285 #endif
286 
287  MachineRegisterInfo *MRI = getRegInfo();
288  if (MRI && Operands[OpNo].isReg())
289  MRI->removeRegOperandFromUseList(Operands + OpNo);
290 
291  // Don't call the MachineOperand destructor. A lot of this code depends on
292  // MachineOperand having a trivial destructor anyway, and adding a call here
293  // wouldn't make it 'destructor-correct'.
294 
295  if (unsigned N = NumOperands - 1 - OpNo)
296  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
297  --NumOperands;
298 }
299 
300 void MachineInstr::setExtraInfo(MachineFunction &MF,
302  MCSymbol *PreInstrSymbol,
303  MCSymbol *PostInstrSymbol,
304  MDNode *HeapAllocMarker) {
305  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
306  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
307  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
308  int NumPointers =
309  MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
310 
311  // Drop all extra info if there is none.
312  if (NumPointers <= 0) {
313  Info.clear();
314  return;
315  }
316 
317  // If more than one pointer, then store out of line. Store heap alloc markers
318  // out of line because PointerSumType cannot hold more than 4 tag types with
319  // 32-bit pointers.
320  // FIXME: Maybe we should make the symbols in the extra info mutable?
321  else if (NumPointers > 1 || HasHeapAllocMarker) {
322  Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
323  MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
324  return;
325  }
326 
327  // Otherwise store the single pointer inline.
328  if (HasPreInstrSymbol)
329  Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
330  else if (HasPostInstrSymbol)
331  Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
332  else
333  Info.set<EIIK_MMO>(MMOs[0]);
334 }
335 
337  if (memoperands_empty())
338  return;
339 
340  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
342 }
343 
346  if (MMOs.empty()) {
347  dropMemRefs(MF);
348  return;
349  }
350 
351  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
353 }
354 
356  MachineMemOperand *MO) {
359  MMOs.push_back(MO);
360  setMemRefs(MF, MMOs);
361 }
362 
364  if (this == &MI)
365  // Nothing to do for a self-clone!
366  return;
367 
368  assert(&MF == MI.getMF() &&
369  "Invalid machine functions when cloning memory refrences!");
370  // See if we can just steal the extra info already allocated for the
371  // instruction. We can do this whenever the pre- and post-instruction symbols
372  // are the same (including null).
373  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
374  getPostInstrSymbol() == MI.getPostInstrSymbol() &&
375  getHeapAllocMarker() == MI.getHeapAllocMarker()) {
376  Info = MI.Info;
377  return;
378  }
379 
380  // Otherwise, fall back on a copy-based clone.
381  setMemRefs(MF, MI.memoperands());
382 }
383 
384 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
385 /// identical.
388  if (LHS.size() != RHS.size())
389  return false;
390 
391  auto LHSPointees = make_pointee_range(LHS);
392  auto RHSPointees = make_pointee_range(RHS);
393  return std::equal(LHSPointees.begin(), LHSPointees.end(),
394  RHSPointees.begin());
395 }
396 
399  // Try handling easy numbers of MIs with simpler mechanisms.
400  if (MIs.empty()) {
401  dropMemRefs(MF);
402  return;
403  }
404  if (MIs.size() == 1) {
405  cloneMemRefs(MF, *MIs[0]);
406  return;
407  }
408  // Because an empty memoperands list provides *no* information and must be
409  // handled conservatively (assuming the instruction can do anything), the only
410  // way to merge with it is to drop all other memoperands.
411  if (MIs[0]->memoperands_empty()) {
412  dropMemRefs(MF);
413  return;
414  }
415 
416  // Handle the general case.
418  // Start with the first instruction.
419  assert(&MF == MIs[0]->getMF() &&
420  "Invalid machine functions when cloning memory references!");
421  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
422  // Now walk all the other instructions and accumulate any different MMOs.
423  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
424  assert(&MF == MI.getMF() &&
425  "Invalid machine functions when cloning memory references!");
426 
427  // Skip MIs with identical operands to the first. This is a somewhat
428  // arbitrary hack but will catch common cases without being quadratic.
429  // TODO: We could fully implement merge semantics here if needed.
430  if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
431  continue;
432 
433  // Because an empty memoperands list provides *no* information and must be
434  // handled conservatively (assuming the instruction can do anything), the
435  // only way to merge with it is to drop all other memoperands.
436  if (MI.memoperands_empty()) {
437  dropMemRefs(MF);
438  return;
439  }
440 
441  // Otherwise accumulate these into our temporary buffer of the merged state.
442  MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
443  }
444 
445  setMemRefs(MF, MergedMMOs);
446 }
447 
449  // Do nothing if old and new symbols are the same.
450  if (Symbol == getPreInstrSymbol())
451  return;
452 
453  // If there was only one symbol and we're removing it, just clear info.
454  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
455  Info.clear();
456  return;
457  }
458 
459  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
461 }
462 
464  // Do nothing if old and new symbols are the same.
465  if (Symbol == getPostInstrSymbol())
466  return;
467 
468  // If there was only one symbol and we're removing it, just clear info.
469  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
470  Info.clear();
471  return;
472  }
473 
474  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
476 }
477 
479  // Do nothing if old and new symbols are the same.
480  if (Marker == getHeapAllocMarker())
481  return;
482 
483  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
484  Marker);
485 }
486 
488  const MachineInstr &MI) {
489  if (this == &MI)
490  // Nothing to do for a self-clone!
491  return;
492 
493  assert(&MF == MI.getMF() &&
494  "Invalid machine functions when cloning instruction symbols!");
495 
496  setPreInstrSymbol(MF, MI.getPreInstrSymbol());
497  setPostInstrSymbol(MF, MI.getPostInstrSymbol());
498  setHeapAllocMarker(MF, MI.getHeapAllocMarker());
499 }
500 
502  // For now, the just return the union of the flags. If the flags get more
503  // complicated over time, we might need more logic here.
504  return getFlags() | Other.getFlags();
505 }
506 
508  uint16_t MIFlags = 0;
509  // Copy the wrapping flags.
510  if (const OverflowingBinaryOperator *OB =
511  dyn_cast<OverflowingBinaryOperator>(&I)) {
512  if (OB->hasNoSignedWrap())
513  MIFlags |= MachineInstr::MIFlag::NoSWrap;
514  if (OB->hasNoUnsignedWrap())
515  MIFlags |= MachineInstr::MIFlag::NoUWrap;
516  }
517 
518  // Copy the exact flag.
519  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
520  if (PE->isExact())
521  MIFlags |= MachineInstr::MIFlag::IsExact;
522 
523  // Copy the fast-math flags.
524  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
525  const FastMathFlags Flags = FP->getFastMathFlags();
526  if (Flags.noNaNs())
527  MIFlags |= MachineInstr::MIFlag::FmNoNans;
528  if (Flags.noInfs())
529  MIFlags |= MachineInstr::MIFlag::FmNoInfs;
530  if (Flags.noSignedZeros())
531  MIFlags |= MachineInstr::MIFlag::FmNsz;
532  if (Flags.allowReciprocal())
533  MIFlags |= MachineInstr::MIFlag::FmArcp;
534  if (Flags.allowContract())
535  MIFlags |= MachineInstr::MIFlag::FmContract;
536  if (Flags.approxFunc())
537  MIFlags |= MachineInstr::MIFlag::FmAfn;
538  if (Flags.allowReassoc())
539  MIFlags |= MachineInstr::MIFlag::FmReassoc;
540  }
541 
542  return MIFlags;
543 }
544 
546  Flags = copyFlagsFromInstruction(I);
547 }
548 
549 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
550  assert(!isBundledWithPred() && "Must be called on bundle header");
552  if (MII->getDesc().getFlags() & Mask) {
553  if (Type == AnyInBundle)
554  return true;
555  } else {
556  if (Type == AllInBundle && !MII->isBundle())
557  return false;
558  }
559  // This was the last instruction in the bundle.
560  if (!MII->isBundledWithSucc())
561  return Type == AllInBundle;
562  }
563 }
564 
566  MICheckType Check) const {
567  // If opcodes or number of operands are not the same then the two
568  // instructions are obviously not identical.
569  if (Other.getOpcode() != getOpcode() ||
570  Other.getNumOperands() != getNumOperands())
571  return false;
572 
573  if (isBundle()) {
574  // We have passed the test above that both instructions have the same
575  // opcode, so we know that both instructions are bundles here. Let's compare
576  // MIs inside the bundle.
577  assert(Other.isBundle() && "Expected that both instructions are bundles.");
580  // Loop until we analysed the last intruction inside at least one of the
581  // bundles.
582  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
583  ++I1;
584  ++I2;
585  if (!I1->isIdenticalTo(*I2, Check))
586  return false;
587  }
588  // If we've reached the end of just one of the two bundles, but not both,
589  // the instructions are not identical.
590  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
591  return false;
592  }
593 
594  // Check operands to make sure they match.
595  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
596  const MachineOperand &MO = getOperand(i);
597  const MachineOperand &OMO = Other.getOperand(i);
598  if (!MO.isReg()) {
599  if (!MO.isIdenticalTo(OMO))
600  return false;
601  continue;
602  }
603 
604  // Clients may or may not want to ignore defs when testing for equality.
605  // For example, machine CSE pass only cares about finding common
606  // subexpressions, so it's safe to ignore virtual register defs.
607  if (MO.isDef()) {
608  if (Check == IgnoreDefs)
609  continue;
610  else if (Check == IgnoreVRegDefs) {
611  if (!Register::isVirtualRegister(MO.getReg()) ||
613  if (!MO.isIdenticalTo(OMO))
614  return false;
615  } else {
616  if (!MO.isIdenticalTo(OMO))
617  return false;
618  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
619  return false;
620  }
621  } else {
622  if (!MO.isIdenticalTo(OMO))
623  return false;
624  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
625  return false;
626  }
627  }
628  // If DebugLoc does not match then two debug instructions are not identical.
629  if (isDebugInstr())
630  if (getDebugLoc() && Other.getDebugLoc() &&
631  getDebugLoc() != Other.getDebugLoc())
632  return false;
633  return true;
634 }
635 
637  return getParent()->getParent();
638 }
639 
641  assert(getParent() && "Not embedded in a basic block!");
642  return getParent()->remove(this);
643 }
644 
646  assert(getParent() && "Not embedded in a basic block!");
647  return getParent()->remove_instr(this);
648 }
649 
651  assert(getParent() && "Not embedded in a basic block!");
652  getParent()->erase(this);
653 }
654 
656  assert(getParent() && "Not embedded in a basic block!");
657  getParent()->erase_instr(this);
658 }
659 
661  if (!isCall(Type))
662  return false;
663  switch (getOpcode()) {
664  case TargetOpcode::PATCHPOINT:
665  case TargetOpcode::STACKMAP:
666  case TargetOpcode::STATEPOINT:
667  case TargetOpcode::FENTRY_CALL:
668  return false;
669  }
670  return true;
671 }
672 
674  if (isBundle())
677 }
678 
680  unsigned NumOperands = MCID->getNumOperands();
681  if (!MCID->isVariadic())
682  return NumOperands;
683 
684  for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
685  const MachineOperand &MO = getOperand(I);
686  // The operands must always be in the following order:
687  // - explicit reg defs,
688  // - other explicit operands (reg uses, immediates, etc.),
689  // - implicit reg defs
690  // - implicit reg uses
691  if (MO.isReg() && MO.isImplicit())
692  break;
693  ++NumOperands;
694  }
695  return NumOperands;
696 }
697 
699  unsigned NumDefs = MCID->getNumDefs();
700  if (!MCID->isVariadic())
701  return NumDefs;
702 
703  for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
704  const MachineOperand &MO = getOperand(I);
705  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
706  break;
707  ++NumDefs;
708  }
709  return NumDefs;
710 }
711 
713  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
716  --Pred;
717  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
718  Pred->setFlag(BundledSucc);
719 }
720 
722  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
725  ++Succ;
726  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
727  Succ->setFlag(BundledPred);
728 }
729 
731  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
734  --Pred;
735  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
736  Pred->clearFlag(BundledSucc);
737 }
738 
740  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
743  ++Succ;
744  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
745  Succ->clearFlag(BundledPred);
746 }
747 
749  if (isInlineAsm()) {
750  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
751  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
752  return true;
753  }
754  return false;
755 }
756 
758  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
759  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
760  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
761 }
762 
764  unsigned *GroupNo) const {
765  assert(isInlineAsm() && "Expected an inline asm instruction");
766  assert(OpIdx < getNumOperands() && "OpIdx out of range");
767 
768  // Ignore queries about the initial operands.
769  if (OpIdx < InlineAsm::MIOp_FirstOperand)
770  return -1;
771 
772  unsigned Group = 0;
773  unsigned NumOps;
774  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
775  i += NumOps) {
776  const MachineOperand &FlagMO = getOperand(i);
777  // If we reach the implicit register operands, stop looking.
778  if (!FlagMO.isImm())
779  return -1;
780  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
781  if (i + NumOps > OpIdx) {
782  if (GroupNo)
783  *GroupNo = Group;
784  return i;
785  }
786  ++Group;
787  }
788  return -1;
789 }
790 
792  assert(isDebugLabel() && "not a DBG_LABEL");
793  return cast<DILabel>(getOperand(0).getMetadata());
794 }
795 
797  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
798  unsigned VariableOp = isDebugValueList() ? 0 : 2;
799  return getOperand(VariableOp);
800 }
801 
803  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
804  unsigned VariableOp = isDebugValueList() ? 0 : 2;
805  return getOperand(VariableOp);
806 }
807 
809  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
810 }
811 
813  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
814  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
815  return getOperand(ExpressionOp);
816 }
817 
819  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
820  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
821  return getOperand(ExpressionOp);
822 }
823 
825  return cast<DIExpression>(getDebugExpressionOp().getMetadata());
826 }
827 
830 }
831 
832 const TargetRegisterClass*
834  const TargetInstrInfo *TII,
835  const TargetRegisterInfo *TRI) const {
836  assert(getParent() && "Can't have an MBB reference here!");
837  assert(getMF() && "Can't have an MF reference here!");
838  const MachineFunction &MF = *getMF();
839 
840  // Most opcodes have fixed constraints in their MCInstrDesc.
841  if (!isInlineAsm())
842  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
843 
844  if (!getOperand(OpIdx).isReg())
845  return nullptr;
846 
847  // For tied uses on inline asm, get the constraint from the def.
848  unsigned DefIdx;
849  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
850  OpIdx = DefIdx;
851 
852  // Inline asm stores register class constraints in the flag word.
853  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
854  if (FlagIdx < 0)
855  return nullptr;
856 
857  unsigned Flag = getOperand(FlagIdx).getImm();
858  unsigned RCID;
863  return TRI->getRegClass(RCID);
864 
865  // Assume that all registers in a memory operand are pointers.
867  return TRI->getPointerRegClass(MF);
868 
869  return nullptr;
870 }
871 
873  Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
874  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
875  // Check every operands inside the bundle if we have
876  // been asked to.
877  if (ExploreBundle)
878  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
879  ++OpndIt)
880  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
881  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
882  else
883  // Otherwise, just check the current operands.
884  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
885  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
886  return CurRC;
887 }
888 
889 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
890  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
891  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
892  assert(CurRC && "Invalid initial register class");
893  // Check if Reg is constrained by some of its use/def from MI.
894  const MachineOperand &MO = getOperand(OpIdx);
895  if (!MO.isReg() || MO.getReg() != Reg)
896  return CurRC;
897  // If yes, accumulate the constraints through the operand.
898  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
899 }
900 
902  unsigned OpIdx, const TargetRegisterClass *CurRC,
903  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
904  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
905  const MachineOperand &MO = getOperand(OpIdx);
906  assert(MO.isReg() &&
907  "Cannot get register constraints for non-register operand");
908  assert(CurRC && "Invalid initial register class");
909  if (unsigned SubIdx = MO.getSubReg()) {
910  if (OpRC)
911  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
912  else
913  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
914  } else if (OpRC)
915  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
916  return CurRC;
917 }
918 
919 /// Return the number of instructions inside the MI bundle, not counting the
920 /// header instruction.
921 unsigned MachineInstr::getBundleSize() const {
923  unsigned Size = 0;
924  while (I->isBundledWithSucc()) {
925  ++Size;
926  ++I;
927  }
928  return Size;
929 }
930 
931 /// Returns true if the MachineInstr has an implicit-use operand of exactly
932 /// the given register (not considering sub/super-registers).
934  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
935  const MachineOperand &MO = getOperand(i);
936  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
937  return true;
938  }
939  return false;
940 }
941 
942 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
943 /// the specific register or -1 if it is not found. It further tightens
944 /// the search criteria to a use that kills the register if isKill is true.
946  Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
947  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
948  const MachineOperand &MO = getOperand(i);
949  if (!MO.isReg() || !MO.isUse())
950  continue;
951  Register MOReg = MO.getReg();
952  if (!MOReg)
953  continue;
954  if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
955  if (!isKill || MO.isKill())
956  return i;
957  }
958  return -1;
959 }
960 
961 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
962 /// indicating if this instruction reads or writes Reg. This also considers
963 /// partial defines.
964 std::pair<bool,bool>
966  SmallVectorImpl<unsigned> *Ops) const {
967  bool PartDef = false; // Partial redefine.
968  bool FullDef = false; // Full define.
969  bool Use = false;
970 
971  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
972  const MachineOperand &MO = getOperand(i);
973  if (!MO.isReg() || MO.getReg() != Reg)
974  continue;
975  if (Ops)
976  Ops->push_back(i);
977  if (MO.isUse())
978  Use |= !MO.isUndef();
979  else if (MO.getSubReg() && !MO.isUndef())
980  // A partial def undef doesn't count as reading the register.
981  PartDef = true;
982  else
983  FullDef = true;
984  }
985  // A partial redefine uses Reg unless there is also a full define.
986  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
987 }
988 
989 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
990 /// the specified register or -1 if it is not found. If isDead is true, defs
991 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
992 /// also checks if there is a def of a super-register.
993 int
995  const TargetRegisterInfo *TRI) const {
996  bool isPhys = Register::isPhysicalRegister(Reg);
997  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
998  const MachineOperand &MO = getOperand(i);
999  // Accept regmask operands when Overlap is set.
1000  // Ignore them when looking for a specific def operand (Overlap == false).
1001  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1002  return i;
1003  if (!MO.isReg() || !MO.isDef())
1004  continue;
1005  Register MOReg = MO.getReg();
1006  bool Found = (MOReg == Reg);
1007  if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1008  if (Overlap)
1009  Found = TRI->regsOverlap(MOReg, Reg);
1010  else
1011  Found = TRI->isSubRegister(MOReg, Reg);
1012  }
1013  if (Found && (!isDead || MO.isDead()))
1014  return i;
1015  }
1016  return -1;
1017 }
1018 
1019 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1020 /// operand list that is used to represent the predicate. It returns -1 if
1021 /// none is found.
1023  // Don't call MCID.findFirstPredOperandIdx() because this variant
1024  // is sometimes called on an instruction that's not yet complete, and
1025  // so the number of operands is less than the MCID indicates. In
1026  // particular, the PTX target does this.
1027  const MCInstrDesc &MCID = getDesc();
1028  if (MCID.isPredicable()) {
1029  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1030  if (MCID.OpInfo[i].isPredicate())
1031  return i;
1032  }
1033 
1034  return -1;
1035 }
1036 
1037 // MachineOperand::TiedTo is 4 bits wide.
1038 const unsigned TiedMax = 15;
1039 
1040 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1041 ///
1042 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1043 /// field. TiedTo can have these values:
1044 ///
1045 /// 0: Operand is not tied to anything.
1046 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1047 /// TiedMax: Tied to an operand >= TiedMax-1.
1048 ///
1049 /// The tied def must be one of the first TiedMax operands on a normal
1050 /// instruction. INLINEASM instructions allow more tied defs.
1051 ///
1052 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1053  MachineOperand &DefMO = getOperand(DefIdx);
1054  MachineOperand &UseMO = getOperand(UseIdx);
1055  assert(DefMO.isDef() && "DefIdx must be a def operand");
1056  assert(UseMO.isUse() && "UseIdx must be a use operand");
1057  assert(!DefMO.isTied() && "Def is already tied to another use");
1058  assert(!UseMO.isTied() && "Use is already tied to another def");
1059 
1060  if (DefIdx < TiedMax)
1061  UseMO.TiedTo = DefIdx + 1;
1062  else {
1063  // Inline asm can use the group descriptors to find tied operands,
1064  // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1065  // but on normal instruction, the tied def must be within the first TiedMax
1066  // operands.
1067  assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1068  "DefIdx out of range");
1069  UseMO.TiedTo = TiedMax;
1070  }
1071 
1072  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1073  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1074 }
1075 
1076 /// Given the index of a tied register operand, find the operand it is tied to.
1077 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1078 /// which must exist.
1079 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1080  const MachineOperand &MO = getOperand(OpIdx);
1081  assert(MO.isTied() && "Operand isn't tied");
1082 
1083  // Normally TiedTo is in range.
1084  if (MO.TiedTo < TiedMax)
1085  return MO.TiedTo - 1;
1086 
1087  // Uses on normal instructions can be out of range.
1088  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1089  // Normal tied defs must be in the 0..TiedMax-1 range.
1090  if (MO.isUse())
1091  return TiedMax - 1;
1092  // MO is a def. Search for the tied use.
1093  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1094  const MachineOperand &UseMO = getOperand(i);
1095  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1096  return i;
1097  }
1098  llvm_unreachable("Can't find tied use");
1099  }
1100 
1101  if (getOpcode() == TargetOpcode::STATEPOINT) {
1102  // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1103  // on registers.
1104  StatepointOpers SO(this);
1105  unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1106  assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1107  unsigned NumDefs = getNumDefs();
1108  for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1109  while (!getOperand(CurUseIdx).isReg())
1110  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1111  if (OpIdx == CurDefIdx)
1112  return CurUseIdx;
1113  if (OpIdx == CurUseIdx)
1114  return CurDefIdx;
1115  CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1116  }
1117  llvm_unreachable("Can't find tied use");
1118  }
1119 
1120  // Now deal with inline asm by parsing the operand group descriptor flags.
1121  // Find the beginning of each operand group.
1122  SmallVector<unsigned, 8> GroupIdx;
1123  unsigned OpIdxGroup = ~0u;
1124  unsigned NumOps;
1125  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1126  i += NumOps) {
1127  const MachineOperand &FlagMO = getOperand(i);
1128  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1129  unsigned CurGroup = GroupIdx.size();
1130  GroupIdx.push_back(i);
1131  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1132  // OpIdx belongs to this operand group.
1133  if (OpIdx > i && OpIdx < i + NumOps)
1134  OpIdxGroup = CurGroup;
1135  unsigned TiedGroup;
1136  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1137  continue;
1138  // Operands in this group are tied to operands in TiedGroup which must be
1139  // earlier. Find the number of operands between the two groups.
1140  unsigned Delta = i - GroupIdx[TiedGroup];
1141 
1142  // OpIdx is a use tied to TiedGroup.
1143  if (OpIdxGroup == CurGroup)
1144  return OpIdx - Delta;
1145 
1146  // OpIdx is a def tied to this use group.
1147  if (OpIdxGroup == TiedGroup)
1148  return OpIdx + Delta;
1149  }
1150  llvm_unreachable("Invalid tied operand on inline asm");
1151 }
1152 
1153 /// clearKillInfo - Clears kill flags on all operands.
1154 ///
1156  for (MachineOperand &MO : operands()) {
1157  if (MO.isReg() && MO.isUse())
1158  MO.setIsKill(false);
1159  }
1160 }
1161 
1163  unsigned SubIdx,
1164  const TargetRegisterInfo &RegInfo) {
1165  if (Register::isPhysicalRegister(ToReg)) {
1166  if (SubIdx)
1167  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1168  for (MachineOperand &MO : operands()) {
1169  if (!MO.isReg() || MO.getReg() != FromReg)
1170  continue;
1171  MO.substPhysReg(ToReg, RegInfo);
1172  }
1173  } else {
1174  for (MachineOperand &MO : operands()) {
1175  if (!MO.isReg() || MO.getReg() != FromReg)
1176  continue;
1177  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1178  }
1179  }
1180 }
1181 
1182 /// isSafeToMove - Return true if it is safe to move this instruction. If
1183 /// SawStore is set to true, it means that there is a store (or call) between
1184 /// the instruction's location and its intended destination.
1185 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1186  // Ignore stuff that we obviously can't move.
1187  //
1188  // Treat volatile loads as stores. This is not strictly necessary for
1189  // volatiles, but it is required for atomic loads. It is not allowed to move
1190  // a load across an atomic load with Ordering > Monotonic.
1191  if (mayStore() || isCall() || isPHI() ||
1192  (mayLoad() && hasOrderedMemoryRef())) {
1193  SawStore = true;
1194  return false;
1195  }
1196 
1197  if (isPosition() || isDebugInstr() || isTerminator() ||
1199  return false;
1200 
1201  // See if this instruction does a load. If so, we have to guarantee that the
1202  // loaded value doesn't change between the load and the its intended
1203  // destination. The check for isInvariantLoad gives the target the chance to
1204  // classify the load as always returning a constant, e.g. a constant pool
1205  // load.
1207  // Otherwise, this is a real load. If there is a store between the load and
1208  // end of block, we can't move it.
1209  return !SawStore;
1210 
1211  return true;
1212 }
1213 
1215  bool UseTBAA, const MachineMemOperand *MMOa,
1216  const MachineMemOperand *MMOb) {
1217  // The following interface to AA is fashioned after DAGCombiner::isAlias and
1218  // operates with MachineMemOperand offset with some important assumptions:
1219  // - LLVM fundamentally assumes flat address spaces.
1220  // - MachineOperand offset can *only* result from legalization and cannot
1221  // affect queries other than the trivial case of overlap checking.
1222  // - These offsets never wrap and never step outside of allocated objects.
1223  // - There should never be any negative offsets here.
1224  //
1225  // FIXME: Modify API to hide this math from "user"
1226  // Even before we go to AA we can reason locally about some memory objects. It
1227  // can save compile time, and possibly catch some corner cases not currently
1228  // covered.
1229 
1230  int64_t OffsetA = MMOa->getOffset();
1231  int64_t OffsetB = MMOb->getOffset();
1232  int64_t MinOffset = std::min(OffsetA, OffsetB);
1233 
1234  uint64_t WidthA = MMOa->getSize();
1235  uint64_t WidthB = MMOb->getSize();
1236  bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1237  bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1238 
1239  const Value *ValA = MMOa->getValue();
1240  const Value *ValB = MMOb->getValue();
1241  bool SameVal = (ValA && ValB && (ValA == ValB));
1242  if (!SameVal) {
1243  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1244  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1245  if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1246  return false;
1247  if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1248  return false;
1249  if (PSVa && PSVb && (PSVa == PSVb))
1250  SameVal = true;
1251  }
1252 
1253  if (SameVal) {
1254  if (!KnownWidthA || !KnownWidthB)
1255  return true;
1256  int64_t MaxOffset = std::max(OffsetA, OffsetB);
1257  int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1258  return (MinOffset + LowWidth > MaxOffset);
1259  }
1260 
1261  if (!AA)
1262  return true;
1263 
1264  if (!ValA || !ValB)
1265  return true;
1266 
1267  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1268  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1269 
1270  int64_t OverlapA =
1271  KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1272  int64_t OverlapB =
1273  KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1274 
1275  return !AA->isNoAlias(
1276  MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1277  MemoryLocation(ValB, OverlapB,
1278  UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1279 }
1280 
1282  bool UseTBAA) const {
1283  const MachineFunction *MF = getMF();
1284  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1285  const MachineFrameInfo &MFI = MF->getFrameInfo();
1286 
1287  // Exclude call instruction which may alter the memory but can not be handled
1288  // by this function.
1289  if (isCall() || Other.isCall())
1290  return true;
1291 
1292  // If neither instruction stores to memory, they can't alias in any
1293  // meaningful way, even if they read from the same address.
1294  if (!mayStore() && !Other.mayStore())
1295  return false;
1296 
1297  // Both instructions must be memory operations to be able to alias.
1298  if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1299  return false;
1300 
1301  // Let the target decide if memory accesses cannot possibly overlap.
1303  return false;
1304 
1305  // Memory operations without memory operands may access anything. Be
1306  // conservative and assume `MayAlias`.
1307  if (memoperands_empty() || Other.memoperands_empty())
1308  return true;
1309 
1310  // Skip if there are too many memory operands.
1311  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1312  if (NumChecks > TII->getMemOperandAACheckLimit())
1313  return true;
1314 
1315  // Check each pair of memory operands from both instructions, which can't
1316  // alias only if all pairs won't alias.
1317  for (auto *MMOa : memoperands())
1318  for (auto *MMOb : Other.memoperands())
1319  if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1320  return true;
1321 
1322  return false;
1323 }
1324 
1325 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1326 /// or volatile memory reference, or if the information describing the memory
1327 /// reference is not available. Return false if it is known to have no ordered
1328 /// memory references.
1330  // An instruction known never to access memory won't have a volatile access.
1331  if (!mayStore() &&
1332  !mayLoad() &&
1333  !isCall() &&
1335  return false;
1336 
1337  // Otherwise, if the instruction has no memory reference information,
1338  // conservatively assume it wasn't preserved.
1339  if (memoperands_empty())
1340  return true;
1341 
1342  // Check if any of our memory operands are ordered.
1343  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1344  return !MMO->isUnordered();
1345  });
1346 }
1347 
1348 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1349 /// trap and is loading from a location whose value is invariant across a run of
1350 /// this function.
1352  // If the instruction doesn't load at all, it isn't an invariant load.
1353  if (!mayLoad())
1354  return false;
1355 
1356  // If the instruction has lost its memoperands, conservatively assume that
1357  // it may not be an invariant load.
1358  if (memoperands_empty())
1359  return false;
1360 
1361  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1362 
1363  for (MachineMemOperand *MMO : memoperands()) {
1364  if (!MMO->isUnordered())
1365  // If the memory operand has ordering side effects, we can't move the
1366  // instruction. Such an instruction is technically an invariant load,
1367  // but the caller code would need updated to expect that.
1368  return false;
1369  if (MMO->isStore()) return false;
1370  if (MMO->isInvariant() && MMO->isDereferenceable())
1371  continue;
1372 
1373  // A load from a constant PseudoSourceValue is invariant.
1374  if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1375  if (PSV->isConstant(&MFI))
1376  continue;
1377  } else if (const Value *V = MMO->getValue()) {
1378  // If we have an AliasAnalysis, ask it whether the memory is constant.
1379  if (AA &&
1380  AA->pointsToConstantMemory(
1381  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1382  continue;
1383  }
1384 
1385  // Otherwise assume conservatively.
1386  return false;
1387  }
1388 
1389  // Everything checks out.
1390  return true;
1391 }
1392 
1393 /// isConstantValuePHI - If the specified instruction is a PHI that always
1394 /// merges together the same virtual register, return the register, otherwise
1395 /// return 0.
1397  if (!isPHI())
1398  return 0;
1399  assert(getNumOperands() >= 3 &&
1400  "It's illegal to have a PHI without source operands");
1401 
1402  Register Reg = getOperand(1).getReg();
1403  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1404  if (getOperand(i).getReg() != Reg)
1405  return 0;
1406  return Reg;
1407 }
1408 
1411  return true;
1412  if (isInlineAsm()) {
1413  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1414  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1415  return true;
1416  }
1417 
1418  return false;
1419 }
1420 
1422  return mayStore() || isCall() ||
1424 }
1425 
1426 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1427 ///
1429  for (const MachineOperand &MO : operands()) {
1430  if (!MO.isReg() || MO.isUse())
1431  continue;
1432  if (!MO.isDead())
1433  return false;
1434  }
1435  return true;
1436 }
1437 
1438 /// copyImplicitOps - Copy implicit register operands from specified
1439 /// instruction to this instruction.
1441  const MachineInstr &MI) {
1442  for (const MachineOperand &MO :
1443  llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1444  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1445  addOperand(MF, MO);
1446 }
1447 
1449  const MCInstrDesc &MCID = getDesc();
1450  if (MCID.Opcode == TargetOpcode::STATEPOINT)
1451  return true;
1452  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1453  const auto &Operand = getOperand(I);
1454  if (!Operand.isReg() || Operand.isDef())
1455  // Ignore the defined registers as MCID marks only the uses as tied.
1456  continue;
1457  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1458  int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1459  if (ExpectedTiedIdx != TiedIdx)
1460  return true;
1461  }
1462  return false;
1463 }
1464 
1465 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1466  const MachineRegisterInfo &MRI) const {
1467  const MachineOperand &Op = getOperand(OpIdx);
1468  if (!Op.isReg())
1469  return LLT{};
1470 
1471  if (isVariadic() || OpIdx >= getNumExplicitOperands())
1472  return MRI.getType(Op.getReg());
1473 
1474  auto &OpInfo = getDesc().OpInfo[OpIdx];
1475  if (!OpInfo.isGenericType())
1476  return MRI.getType(Op.getReg());
1477 
1478  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1479  return LLT{};
1480 
1481  LLT TypeToPrint = MRI.getType(Op.getReg());
1482  // Don't mark the type index printed if it wasn't actually printed: maybe
1483  // another operand with the same type index has an actual type attached:
1484  if (TypeToPrint.isValid())
1485  PrintedTypes.set(OpInfo.getGenericTypeIndex());
1486  return TypeToPrint;
1487 }
1488 
1489 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1491  dbgs() << " ";
1492  print(dbgs());
1493 }
1494 
1495 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1496  const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1497  SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1498  if (Depth >= MaxDepth)
1499  return;
1500  if (!AlreadySeenInstrs.insert(this).second)
1501  return;
1502  // PadToColumn always inserts at least one space.
1503  // Don't mess up the alignment if we don't want any space.
1504  if (Depth)
1505  fdbgs().PadToColumn(Depth * 2);
1506  print(fdbgs());
1507  for (const MachineOperand &MO : operands()) {
1508  if (!MO.isReg() || MO.isDef())
1509  continue;
1510  Register Reg = MO.getReg();
1511  if (Reg.isPhysical())
1512  continue;
1513  const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1514  if (NewMI == nullptr)
1515  continue;
1516  NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1517  }
1518 }
1519 
1521  unsigned MaxDepth) const {
1522  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1523  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1524 }
1525 #endif
1526 
1527 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1528  bool SkipDebugLoc, bool AddNewLine,
1529  const TargetInstrInfo *TII) const {
1530  const Module *M = nullptr;
1531  const Function *F = nullptr;
1532  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1533  F = &MF->getFunction();
1534  M = F->getParent();
1535  if (!TII)
1536  TII = MF->getSubtarget().getInstrInfo();
1537  }
1538 
1539  ModuleSlotTracker MST(M);
1540  if (F)
1541  MST.incorporateFunction(*F);
1542  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1543 }
1544 
1546  bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1547  bool AddNewLine, const TargetInstrInfo *TII) const {
1548  // We can be a bit tidier if we know the MachineFunction.
1549  const TargetRegisterInfo *TRI = nullptr;
1550  const MachineRegisterInfo *MRI = nullptr;
1551  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1552  tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1553 
1554  if (isCFIInstruction())
1555  assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1556 
1557  SmallBitVector PrintedTypes(8);
1558  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1559  auto getTiedOperandIdx = [&](unsigned OpIdx) {
1560  if (!ShouldPrintRegisterTies)
1561  return 0U;
1562  const MachineOperand &MO = getOperand(OpIdx);
1563  if (MO.isReg() && MO.isTied() && !MO.isDef())
1564  return findTiedOperandIdx(OpIdx);
1565  return 0U;
1566  };
1567  unsigned StartOp = 0;
1568  unsigned e = getNumOperands();
1569 
1570  // Print explicitly defined operands on the left of an assignment syntax.
1571  while (StartOp < e) {
1572  const MachineOperand &MO = getOperand(StartOp);
1573  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1574  break;
1575 
1576  if (StartOp != 0)
1577  OS << ", ";
1578 
1579  LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1580  unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1581  MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1582  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1583  ++StartOp;
1584  }
1585 
1586  if (StartOp != 0)
1587  OS << " = ";
1588 
1590  OS << "frame-setup ";
1592  OS << "frame-destroy ";
1594  OS << "nnan ";
1596  OS << "ninf ";
1598  OS << "nsz ";
1600  OS << "arcp ";
1602  OS << "contract ";
1604  OS << "afn ";
1606  OS << "reassoc ";
1608  OS << "nuw ";
1610  OS << "nsw ";
1612  OS << "exact ";
1614  OS << "nofpexcept ";
1616  OS << "nomerge ";
1617 
1618  // Print the opcode name.
1619  if (TII)
1620  OS << TII->getName(getOpcode());
1621  else
1622  OS << "UNKNOWN";
1623 
1624  if (SkipOpers)
1625  return;
1626 
1627  // Print the rest of the operands.
1628  bool FirstOp = true;
1629  unsigned AsmDescOp = ~0u;
1630  unsigned AsmOpCount = 0;
1631 
1633  // Print asm string.
1634  OS << " ";
1635  const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1636  LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1637  unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1638  getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1639  ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1640  IntrinsicInfo);
1641 
1642  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1643  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1644  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1645  OS << " [sideeffect]";
1646  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1647  OS << " [mayload]";
1648  if (ExtraInfo & InlineAsm::Extra_MayStore)
1649  OS << " [maystore]";
1650  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1651  OS << " [isconvergent]";
1652  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1653  OS << " [alignstack]";
1655  OS << " [attdialect]";
1657  OS << " [inteldialect]";
1658 
1659  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1660  FirstOp = false;
1661  }
1662 
1663  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1664  const MachineOperand &MO = getOperand(i);
1665 
1666  if (FirstOp) FirstOp = false; else OS << ",";
1667  OS << " ";
1668 
1669  if (isDebugValue() && MO.isMetadata()) {
1670  // Pretty print DBG_VALUE* instructions.
1671  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1672  if (DIV && !DIV->getName().empty())
1673  OS << "!\"" << DIV->getName() << '\"';
1674  else {
1675  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1676  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1677  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1678  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1679  }
1680  } else if (isDebugLabel() && MO.isMetadata()) {
1681  // Pretty print DBG_LABEL instructions.
1682  auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1683  if (DIL && !DIL->getName().empty())
1684  OS << "\"" << DIL->getName() << '\"';
1685  else {
1686  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1687  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1688  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1689  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1690  }
1691  } else if (i == AsmDescOp && MO.isImm()) {
1692  // Pretty print the inline asm operand descriptor.
1693  OS << '$' << AsmOpCount++;
1694  unsigned Flag = MO.getImm();
1695  OS << ":[";
1697 
1698  unsigned RCID = 0;
1701  if (TRI) {
1702  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1703  } else
1704  OS << ":RC" << RCID;
1705  }
1706 
1707  if (InlineAsm::isMemKind(Flag)) {
1708  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1709  OS << ":" << InlineAsm::getMemConstraintName(MCID);
1710  }
1711 
1712  unsigned TiedTo = 0;
1714  OS << " tiedto:$" << TiedTo;
1715 
1716  OS << ']';
1717 
1718  // Compute the index of the next operand descriptor.
1719  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1720  } else {
1721  LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1722  unsigned TiedOperandIdx = getTiedOperandIdx(i);
1723  if (MO.isImm() && isOperandSubregIdx(i))
1725  else
1726  MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1727  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1728  }
1729  }
1730 
1731  // Print any optional symbols attached to this instruction as-if they were
1732  // operands.
1733  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1734  if (!FirstOp) {
1735  FirstOp = false;
1736  OS << ',';
1737  }
1738  OS << " pre-instr-symbol ";
1739  MachineOperand::printSymbol(OS, *PreInstrSymbol);
1740  }
1741  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1742  if (!FirstOp) {
1743  FirstOp = false;
1744  OS << ',';
1745  }
1746  OS << " post-instr-symbol ";
1747  MachineOperand::printSymbol(OS, *PostInstrSymbol);
1748  }
1749  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1750  if (!FirstOp) {
1751  FirstOp = false;
1752  OS << ',';
1753  }
1754  OS << " heap-alloc-marker ";
1755  HeapAllocMarker->printAsOperand(OS, MST);
1756  }
1757 
1758  if (DebugInstrNum) {
1759  if (!FirstOp)
1760  OS << ",";
1761  OS << " debug-instr-number " << DebugInstrNum;
1762  }
1763 
1764  if (!SkipDebugLoc) {
1765  if (const DebugLoc &DL = getDebugLoc()) {
1766  if (!FirstOp)
1767  OS << ',';
1768  OS << " debug-location ";
1769  DL->printAsOperand(OS, MST);
1770  }
1771  }
1772 
1773  if (!memoperands_empty()) {
1775  const LLVMContext *Context = nullptr;
1776  std::unique_ptr<LLVMContext> CtxPtr;
1777  const MachineFrameInfo *MFI = nullptr;
1778  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1779  MFI = &MF->getFrameInfo();
1780  Context = &MF->getFunction().getContext();
1781  } else {
1782  CtxPtr = std::make_unique<LLVMContext>();
1783  Context = CtxPtr.get();
1784  }
1785 
1786  OS << " :: ";
1787  bool NeedComma = false;
1788  for (const MachineMemOperand *Op : memoperands()) {
1789  if (NeedComma)
1790  OS << ", ";
1791  Op->print(OS, MST, SSNs, *Context, MFI, TII);
1792  NeedComma = true;
1793  }
1794  }
1795 
1796  if (SkipDebugLoc)
1797  return;
1798 
1799  bool HaveSemi = false;
1800 
1801  // Print debug location information.
1802  if (const DebugLoc &DL = getDebugLoc()) {
1803  if (!HaveSemi) {
1804  OS << ';';
1805  HaveSemi = true;
1806  }
1807  OS << ' ';
1808  DL.print(OS);
1809  }
1810 
1811  // Print extra comments for DEBUG_VALUE.
1812  if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1813  if (!HaveSemi) {
1814  OS << ";";
1815  HaveSemi = true;
1816  }
1817  auto *DV = getDebugVariable();
1818  OS << " line no:" << DV->getLine();
1819  if (isIndirectDebugValue())
1820  OS << " indirect";
1821  }
1822  // TODO: DBG_LABEL
1823 
1824  if (AddNewLine)
1825  OS << '\n';
1826 }
1827 
1829  const TargetRegisterInfo *RegInfo,
1830  bool AddIfNotFound) {
1831  bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1832  bool hasAliases = isPhysReg &&
1833  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1834  bool Found = false;
1835  SmallVector<unsigned,4> DeadOps;
1836  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1837  MachineOperand &MO = getOperand(i);
1838  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1839  continue;
1840 
1841  // DEBUG_VALUE nodes do not contribute to code generation and should
1842  // always be ignored. Failure to do so may result in trying to modify
1843  // KILL flags on DEBUG_VALUE nodes.
1844  if (MO.isDebug())
1845  continue;
1846 
1847  Register Reg = MO.getReg();
1848  if (!Reg)
1849  continue;
1850 
1851  if (Reg == IncomingReg) {
1852  if (!Found) {
1853  if (MO.isKill())
1854  // The register is already marked kill.
1855  return true;
1856  if (isPhysReg && isRegTiedToDefOperand(i))
1857  // Two-address uses of physregs must not be marked kill.
1858  return true;
1859  MO.setIsKill();
1860  Found = true;
1861  }
1862  } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1863  // A super-register kill already exists.
1864  if (RegInfo->isSuperRegister(IncomingReg, Reg))
1865  return true;
1866  if (RegInfo->isSubRegister(IncomingReg, Reg))
1867  DeadOps.push_back(i);
1868  }
1869  }
1870 
1871  // Trim unneeded kill operands.
1872  while (!DeadOps.empty()) {
1873  unsigned OpIdx = DeadOps.back();
1874  if (getOperand(OpIdx).isImplicit() &&
1875  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1876  removeOperand(OpIdx);
1877  else
1878  getOperand(OpIdx).setIsKill(false);
1879  DeadOps.pop_back();
1880  }
1881 
1882  // If not found, this means an alias of one of the operands is killed. Add a
1883  // new implicit operand if required.
1884  if (!Found && AddIfNotFound) {
1886  false /*IsDef*/,
1887  true /*IsImp*/,
1888  true /*IsKill*/));
1889  return true;
1890  }
1891  return Found;
1892 }
1893 
1895  const TargetRegisterInfo *RegInfo) {
1897  RegInfo = nullptr;
1898  for (MachineOperand &MO : operands()) {
1899  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1900  continue;
1901  Register OpReg = MO.getReg();
1902  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1903  MO.setIsKill(false);
1904  }
1905 }
1906 
1908  const TargetRegisterInfo *RegInfo,
1909  bool AddIfNotFound) {
1910  bool isPhysReg = Register::isPhysicalRegister(Reg);
1911  bool hasAliases = isPhysReg &&
1912  MCRegAliasIterator(Reg, RegInfo, false).isValid();
1913  bool Found = false;
1914  SmallVector<unsigned,4> DeadOps;
1915  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1916  MachineOperand &MO = getOperand(i);
1917  if (!MO.isReg() || !MO.isDef())
1918  continue;
1919  Register MOReg = MO.getReg();
1920  if (!MOReg)
1921  continue;
1922 
1923  if (MOReg == Reg) {
1924  MO.setIsDead();
1925  Found = true;
1926  } else if (hasAliases && MO.isDead() &&
1928  // There exists a super-register that's marked dead.
1929  if (RegInfo->isSuperRegister(Reg, MOReg))
1930  return true;
1931  if (RegInfo->isSubRegister(Reg, MOReg))
1932  DeadOps.push_back(i);
1933  }
1934  }
1935 
1936  // Trim unneeded dead operands.
1937  while (!DeadOps.empty()) {
1938  unsigned OpIdx = DeadOps.back();
1939  if (getOperand(OpIdx).isImplicit() &&
1940  (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1941  removeOperand(OpIdx);
1942  else
1943  getOperand(OpIdx).setIsDead(false);
1944  DeadOps.pop_back();
1945  }
1946 
1947  // If not found, this means an alias of one of the operands is dead. Add a
1948  // new implicit operand if required.
1949  if (Found || !AddIfNotFound)
1950  return Found;
1951 
1953  true /*IsDef*/,
1954  true /*IsImp*/,
1955  false /*IsKill*/,
1956  true /*IsDead*/));
1957  return true;
1958 }
1959 
1961  for (MachineOperand &MO : operands()) {
1962  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1963  continue;
1964  MO.setIsDead(false);
1965  }
1966 }
1967 
1969  for (MachineOperand &MO : operands()) {
1970  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1971  continue;
1972  MO.setIsUndef(IsUndef);
1973  }
1974 }
1975 
1977  const TargetRegisterInfo *RegInfo) {
1979  MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1980  if (MO)
1981  return;
1982  } else {
1983  for (const MachineOperand &MO : operands()) {
1984  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1985  MO.getSubReg() == 0)
1986  return;
1987  }
1988  }
1990  true /*IsDef*/,
1991  true /*IsImp*/));
1992 }
1993 
1995  const TargetRegisterInfo &TRI) {
1996  bool HasRegMask = false;
1997  for (MachineOperand &MO : operands()) {
1998  if (MO.isRegMask()) {
1999  HasRegMask = true;
2000  continue;
2001  }
2002  if (!MO.isReg() || !MO.isDef()) continue;
2003  Register Reg = MO.getReg();
2004  if (!Reg.isPhysical())
2005  continue;
2006  // If there are no uses, including partial uses, the def is dead.
2007  if (llvm::none_of(UsedRegs,
2008  [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2009  MO.setIsDead();
2010  }
2011 
2012  // This is a call with a register mask operand.
2013  // Mask clobbers are always dead, so add defs for the non-dead defines.
2014  if (HasRegMask)
2015  for (const Register &UsedReg : UsedRegs)
2016  addRegisterDefined(UsedReg, &TRI);
2017 }
2018 
2019 unsigned
2021  // Build up a buffer of hash code components.
2022  SmallVector<size_t, 16> HashComponents;
2023  HashComponents.reserve(MI->getNumOperands() + 1);
2024  HashComponents.push_back(MI->getOpcode());
2025  for (const MachineOperand &MO : MI->operands()) {
2026  if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2027  continue; // Skip virtual register defs.
2028 
2029  HashComponents.push_back(hash_value(MO));
2030  }
2031  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2032 }
2033 
2035  // Find the source location cookie.
2036  uint64_t LocCookie = 0;
2037  const MDNode *LocMD = nullptr;
2038  for (unsigned i = getNumOperands(); i != 0; --i) {
2039  if (getOperand(i-1).isMetadata() &&
2040  (LocMD = getOperand(i-1).getMetadata()) &&
2041  LocMD->getNumOperands() != 0) {
2042  if (const ConstantInt *CI =
2043  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2044  LocCookie = CI->getZExtValue();
2045  break;
2046  }
2047  }
2048  }
2049 
2050  if (const MachineBasicBlock *MBB = getParent())
2051  if (const MachineFunction *MF = MBB->getParent())
2052  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2054 }
2055 
2057  const MCInstrDesc &MCID, bool IsIndirect,
2058  Register Reg, const MDNode *Variable,
2059  const MDNode *Expr) {
2060  assert(isa<DILocalVariable>(Variable) && "not a variable");
2061  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2062  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2063  "Expected inlined-at fields to agree");
2064  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2065  if (IsIndirect)
2066  MIB.addImm(0U);
2067  else
2068  MIB.addReg(0U);
2069  return MIB.addMetadata(Variable).addMetadata(Expr);
2070 }
2071 
2073  const MCInstrDesc &MCID, bool IsIndirect,
2074  const MachineOperand &MO,
2075  const MDNode *Variable, const MDNode *Expr) {
2076  assert(isa<DILocalVariable>(Variable) && "not a variable");
2077  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2078  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2079  "Expected inlined-at fields to agree");
2080  if (MO.isReg())
2081  return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2082 
2083  auto MIB = BuildMI(MF, DL, MCID).add(MO);
2084  if (IsIndirect)
2085  MIB.addImm(0U);
2086  else
2087  MIB.addReg(0U);
2088  return MIB.addMetadata(Variable).addMetadata(Expr);
2089 }
2090 
2092  const MCInstrDesc &MCID, bool IsIndirect,
2094  const MDNode *Variable, const MDNode *Expr) {
2095  assert(isa<DILocalVariable>(Variable) && "not a variable");
2096  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2097  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2098  "Expected inlined-at fields to agree");
2099  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2100  return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2101 
2102  auto MIB = BuildMI(MF, DL, MCID);
2103  MIB.addMetadata(Variable).addMetadata(Expr);
2104  for (const MachineOperand &MO : MOs)
2105  if (MO.isReg())
2106  MIB.addReg(MO.getReg());
2107  else
2108  MIB.add(MO);
2109  return MIB;
2110 }
2111 
2114  const DebugLoc &DL, const MCInstrDesc &MCID,
2115  bool IsIndirect, Register Reg,
2116  const MDNode *Variable, const MDNode *Expr) {
2117  MachineFunction &MF = *BB.getParent();
2118  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2119  BB.insert(I, MI);
2120  return MachineInstrBuilder(MF, MI);
2121 }
2122 
2125  const DebugLoc &DL, const MCInstrDesc &MCID,
2126  bool IsIndirect, MachineOperand &MO,
2127  const MDNode *Variable, const MDNode *Expr) {
2128  MachineFunction &MF = *BB.getParent();
2129  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2130  BB.insert(I, MI);
2131  return MachineInstrBuilder(MF, *MI);
2132 }
2133 
2136  const DebugLoc &DL, const MCInstrDesc &MCID,
2137  bool IsIndirect, ArrayRef<MachineOperand> MOs,
2138  const MDNode *Variable, const MDNode *Expr) {
2139  MachineFunction &MF = *BB.getParent();
2140  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2141  BB.insert(I, MI);
2142  return MachineInstrBuilder(MF, *MI);
2143 }
2144 
2145 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2146 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2147 static const DIExpression *
2149  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2150  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2151  "Expected inlined-at fields to agree");
2152 
2153  const DIExpression *Expr = MI.getDebugExpression();
2154  if (MI.isIndirectDebugValue()) {
2155  assert(MI.getDebugOffset().getImm() == 0 &&
2156  "DBG_VALUE with nonzero offset");
2158  } else if (MI.isDebugValueList()) {
2159  // We will replace the spilled register with a frame index, so
2160  // immediately deref all references to the spilled register.
2161  std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2162  for (const MachineOperand *Op : SpilledOperands) {
2163  unsigned OpIdx = MI.getDebugOperandIndex(Op);
2164  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2165  }
2166  }
2167  return Expr;
2168 }
2170  Register SpillReg) {
2171  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2173  for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2174  SpillOperands.push_back(&Op);
2175  return computeExprForSpill(MI, SpillOperands);
2176 }
2177 
2180  const MachineInstr &Orig,
2181  int FrameIndex, Register SpillReg) {
2182  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2183  MachineInstrBuilder NewMI =
2184  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2185  // Non-Variadic Operands: Location, Offset, Variable, Expression
2186  // Variadic Operands: Variable, Expression, Locations...
2187  if (Orig.isNonListDebugValue())
2188  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2189  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2190  if (Orig.isDebugValueList()) {
2191  for (const MachineOperand &Op : Orig.debug_operands())
2192  if (Op.isReg() && Op.getReg() == SpillReg)
2193  NewMI.addFrameIndex(FrameIndex);
2194  else
2195  NewMI.add(MachineOperand(Op));
2196  }
2197  return NewMI;
2198 }
2201  const MachineInstr &Orig, int FrameIndex,
2202  SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2203  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2204  MachineInstrBuilder NewMI =
2205  BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2206  // Non-Variadic Operands: Location, Offset, Variable, Expression
2207  // Variadic Operands: Variable, Expression, Locations...
2208  if (Orig.isNonListDebugValue())
2209  NewMI.addFrameIndex(FrameIndex).addImm(0U);
2210  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2211  if (Orig.isDebugValueList()) {
2212  for (const MachineOperand &Op : Orig.debug_operands())
2213  if (is_contained(SpilledOperands, &Op))
2214  NewMI.addFrameIndex(FrameIndex);
2215  else
2216  NewMI.add(MachineOperand(Op));
2217  }
2218  return NewMI;
2219 }
2220 
2222  Register Reg) {
2223  const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2224  if (Orig.isNonListDebugValue())
2225  Orig.getDebugOffset().ChangeToImmediate(0U);
2227  Op.ChangeToFrameIndex(FrameIndex);
2228  Orig.getDebugExpressionOp().setMetadata(Expr);
2229 }
2230 
2232  SmallVectorImpl<MachineInstr *> &DbgValues) {
2233  MachineInstr &MI = *this;
2234  if (!MI.getOperand(0).isReg())
2235  return;
2236 
2237  MachineBasicBlock::iterator DI = MI; ++DI;
2238  for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2239  DI != DE; ++DI) {
2240  if (!DI->isDebugValue())
2241  return;
2242  if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2243  DbgValues.push_back(&*DI);
2244  }
2245 }
2246 
2248  // Collect matching debug values.
2250 
2251  if (!getOperand(0).isReg())
2252  return;
2253 
2254  Register DefReg = getOperand(0).getReg();
2255  auto *MRI = getRegInfo();
2256  for (auto &MO : MRI->use_operands(DefReg)) {
2257  auto *DI = MO.getParent();
2258  if (!DI->isDebugValue())
2259  continue;
2260  if (DI->hasDebugOperandForReg(DefReg)) {
2261  DbgValues.push_back(DI);
2262  }
2263  }
2264 
2265  // Propagate Reg to debug value instructions.
2266  for (auto *DBI : DbgValues)
2267  for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2268  Op.setReg(Reg);
2269 }
2270 
2272 
2273 static unsigned getSpillSlotSize(const MMOList &Accesses,
2274  const MachineFrameInfo &MFI) {
2275  unsigned Size = 0;
2276  for (auto A : Accesses)
2277  if (MFI.isSpillSlotObjectIndex(
2278  cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2279  ->getFrameIndex()))
2280  Size += A->getSize();
2281  return Size;
2282 }
2283 
2286  int FI;
2287  if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2288  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2289  if (MFI.isSpillSlotObjectIndex(FI))
2290  return (*memoperands_begin())->getSize();
2291  }
2292  return None;
2293 }
2294 
2297  MMOList Accesses;
2298  if (TII->hasStoreToStackSlot(*this, Accesses))
2299  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2300  return None;
2301 }
2302 
2305  int FI;
2306  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2307  const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2308  if (MFI.isSpillSlotObjectIndex(FI))
2309  return (*memoperands_begin())->getSize();
2310  }
2311  return None;
2312 }
2313 
2316  MMOList Accesses;
2317  if (TII->hasLoadFromStackSlot(*this, Accesses))
2318  return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2319  return None;
2320 }
2321 
2323  if (DebugInstrNum == 0)
2324  DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2325  return DebugInstrNum;
2326 }
2327 
2329  if (DebugInstrNum == 0)
2330  DebugInstrNum = MF.getNewDebugInstrNum();
2331  return DebugInstrNum;
2332 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1451
llvm::MachineInstr::isDebugValue
bool isDebugValue() const
Definition: MachineInstr.h:1217
llvm::MachineInstr::bundleWithSucc
void bundleWithSucc()
Bundle this instruction with its successor.
Definition: MachineInstr.cpp:721
i
i
Definition: README.txt:29
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:812
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:624
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
CmpMode::FP
@ FP
llvm::SmallBitVector::set
SmallBitVector & set()
Definition: SmallBitVector.h:366
llvm::MachineInstr::clearRegisterDeads
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
Definition: MachineInstr.cpp:1960
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:1994
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2322
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1907
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::MCID::UnmodeledSideEffects
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:172
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:494
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::LLVMContext::emitError
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:266
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::InlineAsm::AsmDialect
AsmDialect
Definition: InlineAsm.h:33
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1631
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:280
llvm::MachineInstrExpressionTrait::getHashValue
static unsigned getHashValue(const MachineInstr *const &MI)
Definition: MachineInstr.cpp:2020
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
Metadata.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::isSafeToMove
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Definition: MachineInstr.cpp:1185
llvm::MachineInstr::debug_operands
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:641
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1035
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:679
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:709
llvm::MachineInstr::getPostInstrSymbol
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:742
llvm::MachineInstr::copyFlagsFromInstruction
static uint16_t copyFlagsFromInstruction(const Instruction &I)
Definition: MachineInstr.cpp:507
llvm::InlineAsm::getKindName
static StringRef getKindName(unsigned Kind)
Definition: InlineAsm.h:406
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:239
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::InlineAsm::AD_ATT
@ AD_ATT
Definition: InlineAsm.h:34
llvm::MachineInstr::removeFromBundle
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Definition: MachineInstr.cpp:645
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1012
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1236
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:729
llvm::MachineInstr::CheckKillDead
@ CheckKillDead
Definition: MachineInstr.h:1149
InlineAsm.h
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::MachineInstr::bundleWithPred
void bundleWithPred()
Bundle this instruction with its predecessor.
Definition: MachineInstr.cpp:712
llvm::MachineInstr::isPseudoProbe
bool isPseudoProbe() const
Definition: MachineInstr.h:1204
MachineBasicBlock.h
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:1976
llvm::MachineInstr::allDefsAreDead
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Definition: MachineInstr.cpp:1428
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1396
llvm::PseudoSourceValue::mayAlias
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Definition: PseudoSourceValue.cpp:53
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:693
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:488
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:361
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MachineFunction::getNewDebugInstrNum
unsigned getNewDebugInstrNum()
Definition: MachineFunction.h:1266
Module.h
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:385
TargetInstrInfo.h
llvm::MachineInstr::FmAfn
@ FmAfn
Definition: MachineInstr.h:100
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4779
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineInstr::hasRegisterImplicitUseOperand
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
Definition: MachineInstr.cpp:933
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:477
llvm::FastMathFlags::noSignedZeros
bool noSignedZeros() const
Definition: FMF.h:69
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:636
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:233
llvm::Optional< unsigned >
llvm::SmallPtrSet< const MachineInstr *, 16 >
Operator.h
Hashing.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineInstr::isVariadic
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:798
hasIdenticalMMOs
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
Definition: MachineInstr.cpp:386
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:852
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::FastMathFlags::noNaNs
bool noNaNs() const
Definition: FMF.h:67
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4828
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:303
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PossiblyExactOperator
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:126
llvm::MCInstrDesc::isPredicable
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:335
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:225
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:355
llvm::MachineInstr::getDebugLabel
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
Definition: MachineInstr.cpp:791
I1
@ I1
Definition: DXILOpLowering.cpp:38
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1329
MachineRegisterInfo.h
llvm::MachineInstr::isRegTiedToDefOperand
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
Definition: MachineInstr.h:1535
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::MachineInstr::getNumDefs
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:569
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:580
llvm::MDNode::getNumOperands
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1284
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
AliasAnalysis.h
llvm::MachineInstr::findTiedOperandIdx
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Definition: MachineInstr.cpp:1079
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:519
llvm::MachineInstr::getFlags
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:327
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::MachineInstr::getDebugOperandsForReg
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:541
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
FormattedStream.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:229
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineInstr::moveBefore
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
Definition: MachineInstr.cpp:136
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1467
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
getSpillSlotSize
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
Definition: MachineInstr.cpp:2273
llvm::InlineAsm::Extra_MayStore
@ Extra_MayStore
Definition: InlineAsm.h:232
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:228
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:830
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::formatted_raw_ostream::PadToColumn
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
Definition: FormattedStream.cpp:115
llvm::FastMathFlags::approxFunc
bool approxFunc() const
Definition: FMF.h:72
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:478
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:962
llvm::MCInstrDesc::ImplicitUses
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:206
Constants.h
llvm::AAResults
Definition: AliasAnalysis.h:511
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:230
llvm::DILocalVariable
Local variable.
Definition: DebugInfoMetadata.h:3058
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1440
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:667
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineInstr::setMemRefs
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:344
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2178
llvm::MachineInstr::getFoldedSpillSize
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
Definition: MachineInstr.cpp:2296
llvm::MachineInstr::clearKillInfo
void clearKillInfo()
Clears kill flags on all operands.
Definition: MachineInstr.cpp:1155
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:568
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineInstr::MICheckType
MICheckType
Definition: MachineInstr.h:1147
llvm::fdbgs
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
Definition: FormattedStream.cpp:152
llvm::MachineInstr::cloneMergedMemRefs
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
Definition: MachineInstr.cpp:397
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineInstr::mayAlias
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
Definition: MachineInstr.cpp:1281
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::FastMathFlags::allowReassoc
bool allowReassoc() const
Flag queries.
Definition: FMF.h:66
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:640
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::MachineInstr::unbundleFromSucc
void unbundleFromSucc()
Break bundle below this instruction.
Definition: MachineInstr.cpp:739
llvm::MachineInstr::isDebugInstr
bool isDebugInstr() const
Definition: MachineInstr.h:1223
llvm::MachineInstr::addImplicitDefUseOperands
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
Definition: MachineInstr.cpp:87
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
Definition: MachineInstr.cpp:64
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1828
llvm::MachineInstr::FmNoInfs
@ FmNoInfs
Definition: MachineInstr.h:92
llvm::FastMathFlags::allowReciprocal
bool allowReciprocal() const
Definition: FMF.h:70
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::InlineAsm::MIOp_ExtraInfo
@ MIOp_ExtraInfo
Definition: InlineAsm.h:224
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineInstr::clearFlag
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:348
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineInstr::substituteRegister
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
Definition: MachineInstr.cpp:1162
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::MachineInstr::shouldUpdateCallSiteInfo
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
Definition: MachineInstr.cpp:673
MachineInstrBundle.h
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:238
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::MachineInstr::getBundleSize
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
Definition: MachineInstr.cpp:921
llvm::MCInstrDesc::Opcode
unsigned short Opcode
Definition: MCInstrDesc.h:199
DebugLoc.h
llvm::MachineInstr::isStackAligningInlineAsm
bool isStackAligningInlineAsm() const
Definition: MachineInstr.cpp:748
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:448
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::MachineInstr::isIdenticalTo
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Definition: MachineInstr.cpp:565
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MachineInstr::hasProperty
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:777
llvm::MachineInstr::NoSWrap
@ NoSWrap
Definition: MachineInstr.h:106
llvm::MachineInstr::isLoadFoldBarrier
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
Definition: MachineInstr.cpp:1421
llvm::MachineInstr::dumpr
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
Definition: MachineInstr.cpp:1520
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachineInstr::FmNsz
@ FmNsz
Definition: MachineInstr.h:94
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:194
llvm::None
const NoneType None
Definition: None.h:24
llvm::MachineInstr::isNonListDebugValue
bool isNonListDebugValue() const
Definition: MachineInstr.h:1211
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:344
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::InlineAsm::isMemKind
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:296
llvm::MachineInstr::AnyInBundle
@ AnyInBundle
Definition: MachineInstr.h:768
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:770
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:655
llvm::MDNode::getOperand
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1278
llvm::MachineInstr::copyIRFlags
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
Definition: MachineInstr.cpp:545
llvm::MCOperandInfo::isPredicate
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:109
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:607
llvm::MachineFunction::deallocateOperandArray
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
Definition: MachineFunction.h:1018
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::MachineInstr::getTypeToPrint
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
Definition: MachineInstr.cpp:1465
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::MachineInstr::getDebugOffset
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:425
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:552
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:419
llvm::FastMathFlags::noInfs
bool noInfs() const
Definition: FMF.h:68
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:75
llvm::MCOI::EARLY_CLOBBER
@ EARLY_CLOBBER
Definition: MCInstrDesc.h:36
llvm::MachineInstr::emitError
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
Definition: MachineInstr.cpp:2034
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:824
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineInstr::getNumMemOperands
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:727
uint64_t
llvm::MachineFunction::createMIExtraInfo
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr)
Allocate and construct an extra info structure for a MachineInstr.
Definition: MachineFunction.cpp:531
TiedMax
const unsigned TiedMax
Definition: MachineInstr.cpp:1038
llvm::MachineInstr::getFlag
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:332
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2221
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:756
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1977
llvm::MachineInstr::getDebugVariableOp
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:796
llvm::MachineInstr::cloneMemRefs
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
Definition: MachineInstr.cpp:363
llvm::MachineInstr::FmReassoc
@ FmReassoc
Definition: MachineInstr.h:102
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MemoryLocation.h
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
llvm::MachineInstr::setRegisterDefReadUndef
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
Definition: MachineInstr.cpp:1968
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::InlineAsm::isImmKind
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:295
MCRegisterInfo.h
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1682
llvm::MachineInstr::AllInBundle
@ AllInBundle
Definition: MachineInstr.h:769
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::make_pointee_range
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineInstr::collectDebugValues
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
Definition: MachineInstr.cpp:2231
llvm::MachineInstr::setFlags
void setFlags(unsigned flags)
Definition: MachineInstr.h:341
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:730
llvm::MachineInstr::clearRegisterKills
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
Definition: MachineInstr.cpp:1894
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2764
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FPMathOperator
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:167
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1675
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:965
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:716
llvm::InlineAsm::getMemoryConstraintID
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:348
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:344
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1256
MachineModuleInfo.h
llvm::MachineInstr::getInlineAsmDialect
InlineAsm::AsmDialect getInlineAsmDialect() const
Definition: MachineInstr.cpp:757
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::isDereferenceableInvariantLoad
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
Definition: MachineInstr.cpp:1351
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:537
UseTBAA
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
llvm::MachineInstr::isOperandSubregIdx
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:590
llvm::DebugLoc::hasTrivialDestructor
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineInstr::IgnoreVRegDefs
@ IgnoreVRegDefs
Definition: MachineInstr.h:1151
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1490
llvm::MachineInstr::eraseFromBundle
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
Definition: MachineInstr.cpp:655
llvm::MachineInstr::getDebugVariable
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:808
llvm::MachineInstr::IsExact
@ IsExact
Definition: MachineInstr.h:108
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:110
llvm::MachineInstr::findInlineAsmFlagIdx
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
Definition: MachineInstr.cpp:763
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
Definition: MachineInstr.cpp:73
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::InlineAsm::AD_Intel
@ AD_Intel
Definition: InlineAsm.h:35
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:240
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:982
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1262
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineInstr::untieRegOperand
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
Definition: MachineInstr.h:1803
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:532
llvm::MachineInstr::getHeapAllocMarker
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:754
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineInstr::getFoldedRestoreSize
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
Definition: MachineInstr.cpp:2315
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
Compiler.h
llvm::MachineInstr::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MachineInstr.cpp:1022
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:112
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::print
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
Definition: MachineInstr.cpp:1527
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:854
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineInstr::isDebugLabel
bool isDebugLabel() const
Definition: MachineInstr.h:1220
llvm::MachineInstr::getPreInstrSymbol
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:730
llvm::OverflowingBinaryOperator
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:72
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
llvm::InlineAsm::getMemConstraintName
static StringRef getMemConstraintName(unsigned Constraint)
Definition: InlineAsm.h:425
llvm::MachineInstr::isPosition
bool isPosition() const
Definition: MachineInstr.h:1209
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:243
llvm::MachineInstr::getRegClassConstraint
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
Definition: MachineInstr.cpp:833
MemOperandsHaveAlias
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
Definition: MachineInstr.cpp:1214
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::isCFIInstruction
bool isCFIInstruction() const
Definition: MachineInstr.h:1200
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:918
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::MachineInstr::getRegClassConstraintEffect
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Definition: MachineInstr.cpp:901
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
std
Definition: BitVector.h:851
llvm::DIExpression::isEntryValue
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
Definition: DebugInfoMetadata.cpp:1218
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::MachineInstr::mergeFlagsWith
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
Definition: MachineInstr.cpp:501
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:370
uint16_t
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:348
moveOperands
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
Definition: MachineInstr.cpp:171
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::MachineInstr::cloneInstrSymbols
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
Definition: MachineInstr.cpp:487
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1025
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineInstr::hasUnmodeledSideEffects
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
Definition: MachineInstr.cpp:1409
llvm::Module::getContext
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:262
Casting.h
llvm::MachineFunction::allocateOperandArray
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
Definition: MachineFunction.h:1011
Function.h
llvm::X86II::OB
@ OB
Definition: X86BaseInfo.h:801
llvm::MachineInstr::isDebugEntryValue
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
Definition: MachineInstr.cpp:828
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
StackMaps.h
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MachineInstr::FmNoNans
@ FmNoNans
Definition: MachineInstr.h:90
llvm::MachineInstr::isCandidateForCallSiteEntry
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
Definition: MachineInstr.cpp:660
llvm::MachineInstr::FmContract
@ FmContract
Definition: MachineInstr.h:98
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:710
llvm::MachineInstr::isBundledWithPred
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:399
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::memoperands_empty
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:721
llvm::MachineInstr::isBundle
bool isBundle() const
Definition: MachineInstr.h:1288
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:276
computeExprForSpill
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
Definition: MachineInstr.cpp:2148
AA
llvm::MachineInstr::isDebugRef
bool isDebugRef() const
Definition: MachineInstr.h:1221
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:659
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:187
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:215
llvm::MachineInstr::findRegisterDefOperandIdx
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
Definition: MachineInstr.cpp:994
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:355
llvm::MachineInstr::NoUWrap
@ NoUWrap
Definition: MachineInstr.h:104
llvm::InlineAsm::MIOp_AsmString
@ MIOp_AsmString
Definition: InlineAsm.h:223
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
SmallBitVector.h
N
#define N
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:403
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::hash_combine_range
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:483
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:184
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:89
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineInstr::dropMemRefs
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
Definition: MachineInstr.cpp:336
llvm::MachineInstr::FmArcp
@ FmArcp
Definition: MachineInstr.h:96
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineInstr::memoperands
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:691
ModuleSlotTracker.h
MachineMemOperand.h
llvm::MachineInstr::hasComplexRegisterTies
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MachineInstr.cpp:1448
llvm::SmallVectorImpl< unsigned >
llvm::MachineBasicBlock::erase_instr
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.h:933
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:85
llvm::SmallPtrSetImpl< const MachineInstr * >
llvm::MachineInstr::getRestoreSize
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
Definition: MachineInstr.cpp:2304
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineInstr::getRegClassConstraintEffectForVReg
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
Definition: MachineInstr.cpp:872
llvm::MachineInstr::IgnoreDefs
@ IgnoreDefs
Definition: MachineInstr.h:1150
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::DILabel
Label.
Definition: DebugInfoMetadata.h:3148
llvm::MachineInstr::isKill
bool isKill() const
Definition: MachineInstr.h:1260
LLVMContext.h
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:403
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:329
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FastMathFlags::allowContract
bool allowContract() const
Definition: FMF.h:71
raw_ostream.h
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1052
llvm::MachineInstr::mayRaiseFPException
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:1045
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:644
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:88
llvm::MachineInstr::isDebugValueList
bool isDebugValueList() const
Definition: MachineInstr.h:1214
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1435
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:650
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:151
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:331
llvm::MachineInstr::QueryType
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:766
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:619
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:945
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1304
llvm::InlineAsm::Extra_MayLoad
@ Extra_MayLoad
Definition: InlineAsm.h:231
TargetRegisterInfo.h
Debug.h
llvm::MachineInstr::setPostInstrSymbol
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
Definition: MachineInstr.cpp:463
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::MemoryLocation
Representation for a specific memory location.
Definition: MemoryLocation.h:210
llvm::MachineInstr::getSpillSize
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
Definition: MachineInstr.cpp:2285
llvm::MachineInstr::getNumExplicitDefs
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition: MachineInstr.cpp:698
llvm::MachineInstr::setFlag
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:337
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1237
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:285
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:207
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::MachineInstr::changeDebugValuesDefReg
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
Definition: MachineInstr.cpp:2247
llvm::LLT
Definition: LowLevelTypeImpl.h:39