LLVM  14.0.0git
HexagonMCChecker.cpp
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1 //===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the checking of insns inside a bundle according to the
10 // packet constraint rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
19 
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include <cassert>
28 
29 using namespace llvm;
30 
31 static cl::opt<bool>
32  RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore,
33  cl::Hidden, cl::desc("Relax checks of new-value validity"));
34 
35 const HexagonMCChecker::PredSense
36  HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
37 
38 void HexagonMCChecker::init() {
39  // Initialize read-only registers set.
40  ReadOnly.insert(Hexagon::PC);
41  ReadOnly.insert(Hexagon::C9_8);
42 
43  // Figure out the loop-registers definitions.
45  Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
46  Defs[Hexagon::LC0].insert(Unconditional);
47  }
49  Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
50  Defs[Hexagon::LC1].insert(Unconditional);
51  }
52 
54  // Unfurl a bundle.
55  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
56  MCInst const &Inst = *I.getInst();
57  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
58  init(*Inst.getOperand(0).getInst());
59  init(*Inst.getOperand(1).getInst());
60  } else
61  init(Inst);
62  }
63  else
64  init(MCB);
65 }
66 
67 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
68  bool &isTrue) {
69  if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
71  // Note an used predicate register.
72  PredReg = R;
73  isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
74 
75  // Note use of new predicate register.
77  NewPreds.insert(PredReg);
78  } else
79  // Note register use. Super-registers are not tracked directly,
80  // but their components.
81  for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
82  SRI.isValid(); ++SRI)
83  if (!MCSubRegIterator(*SRI, &RI).isValid())
84  // Skip super-registers used indirectly.
85  Uses.insert(*SRI);
86 
88  ReversePairs.insert(R);
89 }
90 
91 void HexagonMCChecker::init(MCInst const &MCI) {
92  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
93  unsigned PredReg = Hexagon::NoRegister;
94  bool isTrue = false;
95 
96  // Get used registers.
97  for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
98  if (MCI.getOperand(i).isReg())
99  initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
100  for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)
101  initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
102 
103  const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) ||
104  HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) &&
105  STI.getFeatureBits()[Hexagon::ArchV69];
106 
107  // Get implicit register definitions.
108  if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
109  for (; *ImpDef; ++ImpDef) {
110  unsigned R = *ImpDef;
111 
112  if (Hexagon::R31 != R && MCID.isCall())
113  // Any register other than the LR and the PC are actually volatile ones
114  // as defined by the ABI, not modified implicitly by the call insn.
115  continue;
116  if (Hexagon::PC == R)
117  // Branches are the only insns that can change the PC,
118  // otherwise a read-only register.
119  continue;
120 
121  if (Hexagon::USR_OVF == R)
122  // Many insns change the USR implicitly, but only one or another flag.
123  // The instruction table models the USR.OVF flag, which can be
124  // implicitly modified more than once, but cannot be modified in the
125  // same packet with an instruction that modifies is explicitly. Deal
126  // with such situations individually.
127  SoftDefs.insert(R);
128  else if (HexagonMCInstrInfo::isPredReg(RI, R) &&
130  // Include implicit late predicates.
131  LatePreds.insert(R);
132  else if (!IgnoreTmpDst)
133  Defs[R].insert(PredSense(PredReg, isTrue));
134  }
135 
136  // Figure out explicit register definitions.
137  for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
138  unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
139  // USR has subregisters (while C8 does not for technical reasons), so
140  // reset R to USR, since we know how to handle multiple defs of USR,
141  // taking into account its subregisters.
142  if (R == Hexagon::C8)
143  R = Hexagon::USR;
144 
146  ReversePairs.insert(R);
147 
148  // Note register definitions, direct ones as well as indirect side-effects.
149  // Super-registers are not tracked directly, but their components.
150  for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
151  SRI.isValid(); ++SRI) {
152  if (MCSubRegIterator(*SRI, &RI).isValid())
153  // Skip super-registers defined indirectly.
154  continue;
155 
156  if (R == *SRI) {
157  if (S == R)
158  // Avoid scoring the defined register multiple times.
159  continue;
160  else
161  // Note that the defined register has already been scored.
162  S = R;
163  }
164 
165  if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
166  // P3:0 is a special case, since multiple predicate register definitions
167  // in a packet is allowed as the equivalent of their logical "and".
168  // Only an explicit definition of P3:0 is noted as such; if a
169  // side-effect, then note as a soft definition.
170  SoftDefs.insert(*SRI);
171  else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) &&
173  // Some insns produce predicates too late to be used in the same packet.
174  LatePreds.insert(*SRI);
175  else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
177  // Temporary loads should be used in the same packet, but don't commit
178  // results, so it should be disregarded if another insn changes the same
179  // register.
180  // TODO: relies on the impossibility of a current and a temporary loads
181  // in the same packet.
182  TmpDefs.insert(*SRI);
183  else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
184  // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
185  // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
186  Uses.insert(*SRI);
187  else if (!IgnoreTmpDst)
188  Defs[*SRI].insert(PredSense(PredReg, isTrue));
189  }
190  }
191 
192  // Figure out definitions of new predicate registers.
194  for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
195  if (MCI.getOperand(i).isReg()) {
196  unsigned P = MCI.getOperand(i).getReg();
197 
199  NewPreds.insert(P);
200  }
201 }
202 
204  MCSubtargetInfo const &STI, MCInst &mcb,
205  MCRegisterInfo const &ri, bool ReportErrors)
206  : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
207  ReportErrors(ReportErrors) {
208  init();
209 }
210 
212  MCSubtargetInfo const &STI,
213  bool CopyReportErrors)
214  : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
215  STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {
216  init();
217 }
218 
219 bool HexagonMCChecker::check(bool FullCheck) {
220  bool chkP = checkPredicates();
221  bool chkNV = checkNewValues();
222  bool chkR = checkRegisters();
223  bool chkRRO = checkRegistersReadOnly();
224  checkRegisterCurDefs();
225  bool chkS = checkSolo();
226  bool chkSh = true;
227  if (FullCheck)
228  chkSh = checkShuffle();
229  bool chkSl = true;
230  if (FullCheck)
231  chkSl = checkSlots();
232  bool chkAXOK = checkAXOK();
233  bool chkCofMax1 = checkCOFMax1();
234  bool chkHWLoop = checkHWLoop();
235  bool chkValidTmpDst = FullCheck ? checkValidTmpDst() : true;
236  bool chkLegalVecRegPair = checkLegalVecRegPair();
237  bool ChkHVXAccum = checkHVXAccum();
238  bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl &&
239  chkAXOK && chkCofMax1 && chkHWLoop && chkValidTmpDst &&
240  chkLegalVecRegPair && ChkHVXAccum;
241 
242  return chk;
243 }
244 
245 static bool isDuplexAGroup(unsigned Opcode) {
246  switch (Opcode) {
247  case Hexagon::SA1_addi:
248  case Hexagon::SA1_addrx:
249  case Hexagon::SA1_addsp:
250  case Hexagon::SA1_and1:
251  case Hexagon::SA1_clrf:
252  case Hexagon::SA1_clrfnew:
253  case Hexagon::SA1_clrt:
254  case Hexagon::SA1_clrtnew:
255  case Hexagon::SA1_cmpeqi:
256  case Hexagon::SA1_combine0i:
257  case Hexagon::SA1_combine1i:
258  case Hexagon::SA1_combine2i:
259  case Hexagon::SA1_combine3i:
260  case Hexagon::SA1_combinerz:
261  case Hexagon::SA1_combinezr:
262  case Hexagon::SA1_dec:
263  case Hexagon::SA1_inc:
264  case Hexagon::SA1_seti:
265  case Hexagon::SA1_setin1:
266  case Hexagon::SA1_sxtb:
267  case Hexagon::SA1_sxth:
268  case Hexagon::SA1_tfr:
269  case Hexagon::SA1_zxtb:
270  case Hexagon::SA1_zxth:
271  return true;
272  break;
273  default:
274  return false;
275  }
276 }
277 
278 static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
279  if (HexagonMCInstrInfo::isFloat(MCII, ID))
280  return true;
281  unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
282  switch (Type) {
289  case HexagonII::TypeM:
291  return false;
292  case HexagonII::TypeSUBINSN: {
293  return !isDuplexAGroup(ID.getOpcode());
294  }
296  llvm_unreachable("unexpected duplex instruction");
297  default:
298  return true;
299  }
300 }
301 
302 bool HexagonMCChecker::checkAXOK() {
303  MCInst const *HasSoloAXInst = nullptr;
304  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
305  if (HexagonMCInstrInfo::isSoloAX(MCII, I)) {
306  HasSoloAXInst = &I;
307  }
308  }
309  if (!HasSoloAXInst)
310  return true;
311  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
312  if (&I != HasSoloAXInst && isNeitherAnorX(MCII, I)) {
313  reportError(
314  HasSoloAXInst->getLoc(),
315  Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
316  "instructions"));
317  reportError(I.getLoc(),
318  Twine("Not an ALU or non-FPU XTYPE instruction"));
319  return false;
320  }
321  }
322  return true;
323 }
324 
326  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
327  if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
328  reportNote(I.getLoc(), "Branching instruction");
329  }
330 }
331 
332 bool HexagonMCChecker::checkHWLoop() {
335  return true;
336  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
337  if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I)) {
338  reportError(MCB.getLoc(),
339  "Branches cannot be in a packet with hardware loops");
341  return false;
342  }
343  }
344  return true;
345 }
346 
347 bool HexagonMCChecker::checkCOFMax1() {
348  SmallVector<MCInst const *, 2> BranchLocations;
349  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
350  if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
351  BranchLocations.push_back(&I);
352  }
353  for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) {
354  MCInst const &I = *BranchLocations[J];
355  if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
356  bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
357  bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
358  if (N > 1 && !Relax1 && !Relax2) {
359  reportError(I.getLoc(),
360  "Instruction may not be in a packet with other branches");
362  return false;
363  }
364  if (N > 1 && J == 0 && !Relax1) {
365  reportError(I.getLoc(),
366  "Instruction may not be the first branch in packet");
368  return false;
369  }
370  if (N > 1 && J == 1 && !Relax2) {
371  reportError(I.getLoc(),
372  "Instruction may not be the second branch in packet");
374  return false;
375  }
376  }
377  }
378  return true;
379 }
380 
381 bool HexagonMCChecker::checkSlots() {
382  if (HexagonMCInstrInfo::slotsConsumed(MCII, STI, MCB) >
384  reportError("invalid instruction packet: out of slots");
385  return false;
386  }
387  return true;
388 }
389 
390 // Check legal use of predicate registers.
391 bool HexagonMCChecker::checkPredicates() {
392  // Check for proper use of new predicate registers.
393  for (const auto &I : NewPreds) {
394  unsigned P = I;
395 
396  if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
397  // Error out if the new predicate register is not defined,
398  // or defined "late"
399  // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
401  return false;
402  }
403  }
404 
405  // Check for proper use of auto-anded of predicate registers.
406  for (const auto &I : LatePreds) {
407  unsigned P = I;
408 
409  if (LatePreds.count(P) > 1 || Defs.count(P)) {
410  // Error out if predicate register defined "late" multiple times or
411  // defined late and regularly defined
412  // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
414  return false;
415  }
416  }
417 
418  return true;
419 }
420 
421 // Check legal use of new values.
422 bool HexagonMCChecker::checkNewValues() {
423  for (auto const &ConsumerInst :
425  if (!HexagonMCInstrInfo::isNewValue(MCII, ConsumerInst))
426  continue;
427 
428  const HexagonMCInstrInfo::PredicateInfo ConsumerPredInfo =
429  HexagonMCInstrInfo::predicateInfo(MCII, ConsumerInst);
430 
431  bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch();
432  MCOperand const &Op =
433  HexagonMCInstrInfo::getNewValueOperand(MCII, ConsumerInst);
434  assert(Op.isReg());
435 
436  auto Producer = registerProducer(Op.getReg(), ConsumerPredInfo);
437  const MCInst *const ProducerInst = std::get<0>(Producer);
438  const HexagonMCInstrInfo::PredicateInfo ProducerPredInfo =
439  std::get<2>(Producer);
440 
441  if (ProducerInst == nullptr) {
442  reportError(ConsumerInst.getLoc(),
443  "New value register consumer has no producer");
444  return false;
445  }
446  if (!RelaxNVChecks) {
447  // Checks that statically prove correct new value consumption
448  if (ProducerPredInfo.isPredicated() &&
449  (!ConsumerPredInfo.isPredicated() ||
450  llvm::HexagonMCInstrInfo::getType(MCII, ConsumerInst) ==
452  reportNote(
453  ProducerInst->getLoc(),
454  "Register producer is predicated and consumer is unconditional");
455  reportError(ConsumerInst.getLoc(),
456  "Instruction does not have a valid new register producer");
457  return false;
458  }
459  if (ProducerPredInfo.Register != Hexagon::NoRegister &&
460  ProducerPredInfo.Register != ConsumerPredInfo.Register) {
461  reportNote(ProducerInst->getLoc(),
462  "Register producer does not use the same predicate "
463  "register as the consumer");
464  reportError(ConsumerInst.getLoc(),
465  "Instruction does not have a valid new register producer");
466  return false;
467  }
468  }
469  if (ProducerPredInfo.Register == ConsumerPredInfo.Register &&
470  ConsumerPredInfo.PredicatedTrue != ProducerPredInfo.PredicatedTrue) {
471  reportNote(
472  ProducerInst->getLoc(),
473  "Register producer has the opposite predicate sense as consumer");
474  reportError(ConsumerInst.getLoc(),
475  "Instruction does not have a valid new register producer");
476  return false;
477  }
478 
479  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst);
480  const unsigned ProducerOpIndex = std::get<1>(Producer);
481 
482  if (Desc.OpInfo[ProducerOpIndex].RegClass ==
483  Hexagon::DoubleRegsRegClassID) {
484  reportNote(ProducerInst->getLoc(),
485  "Double registers cannot be new-value producers");
486  reportError(ConsumerInst.getLoc(),
487  "Instruction does not have a valid new register producer");
488  return false;
489  }
490 
491  // The ProducerOpIsMemIndex logic checks for the index of the producer
492  // register operand. Z-reg load instructions have an implicit operand
493  // that's not encoded, so the producer won't appear as the 1-th def, it
494  // will be at the 0-th.
495  const unsigned ProducerOpSearchIndex =
496  (HexagonMCInstrInfo::getType(MCII, *ProducerInst) ==
498  ? 0
499  : 1;
500 
501  const bool ProducerOpIsMemIndex =
502  ((Desc.mayLoad() && ProducerOpIndex == ProducerOpSearchIndex) ||
503  (Desc.mayStore() && ProducerOpIndex == 0));
504 
505  if (ProducerOpIsMemIndex) {
506  unsigned Mode = HexagonMCInstrInfo::getAddrMode(MCII, *ProducerInst);
507 
508  StringRef ModeError;
510  ModeError = "Absolute-set";
511  if (Mode == HexagonII::PostInc)
512  ModeError = "Auto-increment";
513  if (!ModeError.empty()) {
514  reportNote(ProducerInst->getLoc(),
515  ModeError + " registers cannot be a new-value "
516  "producer");
517  reportError(ConsumerInst.getLoc(),
518  "Instruction does not have a valid new register producer");
519  return false;
520  }
521  }
522  if (Branch && HexagonMCInstrInfo::isFloat(MCII, *ProducerInst)) {
523  reportNote(ProducerInst->getLoc(),
524  "FPU instructions cannot be new-value producers for jumps");
525  reportError(ConsumerInst.getLoc(),
526  "Instruction does not have a valid new register producer");
527  return false;
528  }
529  }
530  return true;
531 }
532 
533 bool HexagonMCChecker::checkRegistersReadOnly() {
534  for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
535  MCInst const &Inst = *I.getInst();
536  unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
537  for (unsigned j = 0; j < Defs; ++j) {
538  MCOperand const &Operand = Inst.getOperand(j);
539  assert(Operand.isReg() && "Def is not a register");
540  unsigned Register = Operand.getReg();
541  if (ReadOnly.find(Register) != ReadOnly.end()) {
542  reportError(Inst.getLoc(), "Cannot write to read-only register `" +
543  Twine(RI.getName(Register)) + "'");
544  return false;
545  }
546  }
547  }
548  return true;
549 }
550 
551 bool HexagonMCChecker::registerUsed(unsigned Register) {
552  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
553  for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
554  n = I.getNumOperands();
555  j < n; ++j) {
556  MCOperand const &Operand = I.getOperand(j);
557  if (Operand.isReg() && Operand.getReg() == Register)
558  return true;
559  }
560  return false;
561 }
562 
563 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
564 HexagonMCChecker::registerProducer(
565  unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
566  std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
567  WrongSense;
568 
569  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
570  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
571  auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
572 
573  for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
574  for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
575  K.isValid(); ++K)
576  if (*K == Register) {
577  if (RelaxNVChecks ||
578  (ProducerPredicate.Register == ConsumerPredicate.Register &&
579  (ProducerPredicate.Register == Hexagon::NoRegister ||
580  ProducerPredicate.PredicatedTrue ==
581  ConsumerPredicate.PredicatedTrue)))
582  return std::make_tuple(&I, J, ProducerPredicate);
583  std::get<0>(WrongSense) = &I;
584  std::get<1>(WrongSense) = J;
585  std::get<2>(WrongSense) = ProducerPredicate;
586  }
587  if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I))
588  return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
589  }
590  return WrongSense;
591 }
592 
593 void HexagonMCChecker::checkRegisterCurDefs() {
594  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
595  if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
596  HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
597  const unsigned RegDef = I.getOperand(0).getReg();
598 
599  bool HasRegDefUse = false;
600  for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();
601  ++Alias)
602  HasRegDefUse = HasRegDefUse || registerUsed(*Alias);
603 
604  if (!HasRegDefUse)
605  reportWarning("Register `" + Twine(RI.getName(RegDef)) +
606  "' used with `.cur' "
607  "but not used in the same packet");
608  }
609  }
610 }
611 
612 // Check for legal register uses and definitions.
613 bool HexagonMCChecker::checkRegisters() {
614  // Check for proper register definitions.
615  for (const auto &I : Defs) {
616  unsigned R = I.first;
617 
618  if (isLoopRegister(R) && Defs.count(R) > 1 &&
621  // Error out for definitions of loop registers at the end of a loop.
622  reportError("loop-setup and some branch instructions "
623  "cannot be in the same packet");
624  return false;
625  }
626  if (SoftDefs.count(R)) {
627  // Error out for explicit changes to registers also weakly defined
628  // (e.g., "{ usr = r0; r0 = sfadd(...) }").
629  unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
630  unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
631  reportErrorRegisters(BadR);
632  return false;
633  }
634  if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) {
635  // Check for multiple register definitions.
636  PredSet &PM = Defs[R];
637 
638  // Check for multiple unconditional register definitions.
639  if (PM.count(Unconditional)) {
640  // Error out on an unconditional change when there are any other
641  // changes, conditional or not.
642  unsigned UsrR = Hexagon::USR;
643  unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
644  reportErrorRegisters(BadR);
645  return false;
646  }
647  // Check for multiple conditional register definitions.
648  for (const auto &J : PM) {
649  PredSense P = J;
650 
651  // Check for multiple uses of the same condition.
652  if (PM.count(P) > 1) {
653  // Error out on conditional changes based on the same predicate
654  // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
656  return false;
657  }
658  // Check for the use of the complementary condition.
659  P.second = !P.second;
660  if (PM.count(P) && PM.size() > 2) {
661  // Error out on conditional changes based on the same predicate
662  // multiple times
663  // (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
665  return false;
666  }
667  }
668  }
669  }
670 
671  // Check for use of temporary definitions.
672  for (const auto &I : TmpDefs) {
673  unsigned R = I;
674 
675  if (!Uses.count(R)) {
676  // special case for vhist
677  bool vHistFound = false;
678  for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
679  if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
681  vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
682  break;
683  }
684  }
685  // Warn on an unused temporary definition.
686  if (!vHistFound) {
687  reportWarning("register `" + Twine(RI.getName(R)) +
688  "' used with `.tmp' but not used in the same packet");
689  return true;
690  }
691  }
692  }
693 
694  return true;
695 }
696 
697 // Check for legal use of solo insns.
698 bool HexagonMCChecker::checkSolo() {
699  if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
700  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
701  if (HexagonMCInstrInfo::isSolo(MCII, I)) {
702  reportError(I.getLoc(), "Instruction is marked `isSolo' and "
703  "cannot have other instructions in "
704  "the same packet");
705  return false;
706  }
707  }
708 
709  return true;
710 }
711 
712 bool HexagonMCChecker::checkShuffle() {
713  HexagonMCShuffler MCSDX(Context, ReportErrors, MCII, STI, MCB);
714  return MCSDX.check();
715 }
716 
717 bool HexagonMCChecker::checkValidTmpDst() {
718  if (!STI.getFeatureBits()[Hexagon::ArchV69]) {
719  return true;
720  }
721  auto HasTmp = [&](MCInst const &I) {
722  return HexagonMCInstrInfo::hasTmpDst(MCII, I) ||
724  };
725  unsigned HasTmpCount =
727 
728  if (HasTmpCount > 1) {
729  reportError(
730  MCB.getLoc(),
731  "this packet has more than one HVX vtmp/.tmp destination instruction");
732 
733  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
734  if (HasTmp(I))
735  reportNote(I.getLoc(),
736  "this is an HVX vtmp/.tmp destination instruction");
737 
738  return false;
739  }
740  return true;
741 }
742 
743 void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
744  switch (Register) {
745  default:
746  break;
747  case Hexagon::R15:
748  Register = Hexagon::R23;
749  break;
750  case Hexagon::R14:
751  Register = Hexagon::R22;
752  break;
753  case Hexagon::R13:
754  Register = Hexagon::R21;
755  break;
756  case Hexagon::R12:
757  Register = Hexagon::R20;
758  break;
759  case Hexagon::R11:
760  Register = Hexagon::R19;
761  break;
762  case Hexagon::R10:
763  Register = Hexagon::R18;
764  break;
765  case Hexagon::R9:
766  Register = Hexagon::R17;
767  break;
768  case Hexagon::R8:
769  Register = Hexagon::R16;
770  break;
771  }
772 }
773 
775  reportError("register `" + Twine(RI.getName(Register)) +
776  "' modified more than once");
777 }
778 
780  reportError("register `" + Twine(RI.getName(Register)) +
781  "' used with `.new' "
782  "but not validly modified in the same packet");
783 }
784 
786  reportError(MCB.getLoc(), Msg);
787 }
788 
790  if (ReportErrors)
791  Context.reportError(Loc, Msg);
792 }
793 
795  if (ReportErrors) {
796  auto SM = Context.getSourceManager();
797  if (SM)
798  SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
799  }
800 }
801 
803  if (ReportErrors)
804  Context.reportWarning(MCB.getLoc(), Msg);
805 }
806 
807 bool HexagonMCChecker::checkLegalVecRegPair() {
808  const bool IsPermitted = STI.getFeatureBits()[Hexagon::ArchV67];
809  const bool HasReversePairs = ReversePairs.size() != 0;
810 
811  if (!IsPermitted && HasReversePairs) {
812  for (auto R : ReversePairs)
813  reportError("register pair `" + Twine(RI.getName(R)) +
814  "' is not permitted for this architecture");
815  return false;
816  }
817  return true;
818 }
819 
820 // Vd.tmp can't be accumulated
821 bool HexagonMCChecker::checkHVXAccum()
822 {
823  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
824  bool IsTarget =
825  HexagonMCInstrInfo::isAccumulator(MCII, I) && I.getOperand(0).isReg();
826  if (!IsTarget)
827  continue;
828  unsigned int R = I.getOperand(0).getReg();
829  TmpDefsIterator It = TmpDefs.find(R);
830  if (It != TmpDefs.end()) {
831  reportError("register `" + Twine(RI.getName(R)) + ".tmp" +
832  "' is accumulated in this packet");
833  return false;
834  }
835  }
836  return true;
837 }
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::HexagonII::TypeALU32_ADDI
@ TypeALU32_ADDI
Definition: HexagonDepITypes.h:20
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::HexagonMCInstrInfo::isAccumulator
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
Definition: HexagonMCInstrInfo.cpp:533
llvm::HexagonMCInstrInfo::isPredReg
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:755
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:298
MCInstrDesc.h
llvm::HexagonMCInstrInfo::IsABranchingInst
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
Definition: HexagonMCInstrInfo.cpp:1046
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::HexagonMCInstrInfo::isCofMax1
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:584
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::HexagonMCInstrInfo::isCofRelax2
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:595
llvm::HexagonII::TypeEXTENDER
@ TypeEXTENDER
Definition: HexagonDepITypes.h:52
llvm::HexagonII::PostInc
@ PostInc
Definition: HexagonBaseInfo.h:37
llvm::HexagonII::TypeALU32_3op
@ TypeALU32_3op
Definition: HexagonDepITypes.h:19
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::HexagonMCChecker::reportError
void reportError(SMLoc Loc, Twine const &Msg)
Definition: HexagonMCChecker.cpp:789
llvm::HexagonMCInstrInfo::hasTmpDst
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:946
llvm::HexagonII::TypeCVI_HIST
@ TypeCVI_HIST
Definition: HexagonDepITypes.h:28
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::HexagonMCInstrInfo::PredicateInfo::isPredicated
bool isPredicated() const
Definition: HexagonMCInstrInfo.cpp:35
llvm::HexagonII::TypeCVI_ZW
@ TypeCVI_ZW
Definition: HexagonDepITypes.h:49
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::SourceMgr::DK_Note
@ DK_Note
Definition: SourceMgr.h:37
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCChecker::reportNote
void reportNote(SMLoc Loc, Twine const &Msg)
Definition: HexagonMCChecker.cpp:794
llvm::HexagonMCShuffler
Definition: HexagonMCShuffler.h:29
llvm::HexagonII::AbsoluteSet
@ AbsoluteSet
Definition: HexagonBaseInfo.h:33
llvm::HexagonMCInstrInfo::isCofRelax1
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:589
llvm::count_if
auto count_if(R &&Range, UnaryPredicate P)
Wrapper function around std::count_if to count the number of times an element satisfying a given pred...
Definition: STLExtras.h:1739
llvm::HexagonII::TypeSUBINSN
@ TypeSUBINSN
Definition: HexagonDepITypes.h:60
HexagonBaseInfo.h
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:207
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::HexagonMCInstrInfo::PredicateInfo::PredicatedTrue
bool PredicatedTrue
Definition: HexagonMCInstrInfo.h:343
CommandLine.h
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:335
HexagonMCShuffler.h
llvm::HexagonMCChecker::reportWarning
void reportWarning(Twine const &Msg)
Definition: HexagonMCChecker.cpp:802
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:748
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
HexagonMCChecker.h
HexagonMCInstrInfo.h
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:662
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:725
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition: MCInst.h:124
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:562
Twine.h
MCContext.h
isNeitherAnorX
static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID)
Definition: HexagonMCChecker.cpp:278
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
llvm::HexagonMCInstrInfo::predicateInfo
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:930
MCInst.h
false
Definition: StackSlotColoring.cpp:142
llvm::HexagonMCChecker::check
bool check(bool FullCheck=true)
Definition: HexagonMCChecker.cpp:219
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::HexagonMCInstrInfo::hasHvxTmp
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:961
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
SourceMgr.h
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::HexagonII::TypeS_2op
@ TypeS_2op
Definition: HexagonDepITypes.h:61
llvm::HexagonMCChecker::reportErrorNewValue
void reportErrorNewValue(unsigned Register)
Definition: HexagonMCChecker.cpp:779
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:429
llvm::cl::opt< bool >
llvm::HexagonMCInstrInfo::isSoloAX
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
Definition: HexagonMCInstrInfo.cpp:769
llvm::HexagonMCInstrInfo::isCVINew
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:606
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:279
llvm::HexagonII::TypeALU64
@ TypeALU64
Definition: HexagonDepITypes.h:21
llvm::SourceMgr::PrintMessage
void PrintMessage(raw_ostream &OS, SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}, bool ShowColors=true) const
Emit a message about the specified location with the specified string.
Definition: SourceMgr.cpp:340
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::HexagonMCChecker::reportBranchErrors
void reportBranchErrors()
Definition: HexagonMCChecker.cpp:325
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
MCRegisterInfo.h
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:616
llvm::HexagonMCChecker::HexagonMCChecker
HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, const MCRegisterInfo &ri, bool ReportErrors=true)
Definition: HexagonMCChecker.cpp:203
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:691
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:963
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::HexagonMCInstrInfo::isFloat
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
Definition: HexagonMCInstrInfo.cpp:632
llvm::HexagonII::TypeALU32_2op
@ TypeALU32_2op
Definition: HexagonDepITypes.h:18
llvm::HexagonMCChecker::reportErrorRegisters
void reportErrorRegisters(unsigned Register)
Definition: HexagonMCChecker.cpp:774
llvm::MCInstrDesc::mayStore
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:435
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1630
llvm::HexagonMCInstrInfo::isOuterLoop
bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:680
llvm::HexagonMCInstrInfo::PredicateInfo::Register
unsigned Register
Definition: HexagonMCInstrInfo.h:341
llvm::HexagonII::TypeDUPLEX
@ TypeDUPLEX
Definition: HexagonDepITypes.h:50
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCInstrInfo::getNewValueOperand
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:385
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::DenseMapBase::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::HexagonMCInstrInfo::getAddrMode
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
j
return j(j<< 16)
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInst::getLoc
SMLoc getLoc() const
Definition: MCInst.h:204
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:423
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::HexagonII::TypeS_3op
@ TypeS_3op
Definition: HexagonDepITypes.h:62
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:156
LC0
into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp eax movdqa LC0
Definition: README-SSE.txt:632
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::HexagonMCInstrInfo::packetSizeSlots
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
Definition: HexagonMCInstrInfo.cpp:909
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:217
llvm::MCContext::getSourceManager
const SourceMgr * getSourceManager() const
Definition: MCContext.h:410
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isSolo
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
Definition: HexagonMCInstrInfo.cpp:790
isDuplexAGroup
static bool isDuplexAGroup(unsigned Opcode)
Definition: HexagonMCChecker.cpp:245
llvm::cl::desc
Definition: CommandLine.h:412
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::HexagonMCInstrInfo::slotsConsumed
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:977
llvm::HexagonMCInstrInfo::isPredicateLate
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:735
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::HexagonII::TypeCVI_VM_TMP_LD
@ TypeCVI_VM_TMP_LD
Definition: HexagonDepITypes.h:40
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
RelaxNVChecks
static cl::opt< bool > RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore, cl::Hidden, cl::desc("Relax checks of new-value validity"))
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:559
llvm::HexagonII::TypeM
@ TypeM
Definition: HexagonDepITypes.h:55
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1198
llvm::HexagonMCInstrInfo::isPredicatedNew
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
Definition: HexagonMCInstrInfo.cpp:742
llvm::MCContext::reportWarning
void reportWarning(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:970
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:646