LLVM  13.0.0git
ARMTargetTransformInfo.h
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1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19 
20 #include "ARM.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/IR/Constant.h"
27 #include "llvm/IR/Function.h"
29 
30 namespace llvm {
31 
32 class APInt;
33 class ARMTargetLowering;
34 class Instruction;
35 class Loop;
36 class SCEV;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40 
41 namespace TailPredication {
42  enum Mode {
43  Disabled = 0,
48  };
49 }
50 
51 // For controlling conversion of memcpy into Tail Predicated loop.
52 namespace TPLoop {
54 }
55 
56 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
58  using TTI = TargetTransformInfo;
59 
60  friend BaseT;
61 
62  const ARMSubtarget *ST;
63  const ARMTargetLowering *TLI;
64 
65  // Currently the following features are excluded from InlineFeaturesAllowed.
66  // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
67  // Depending on whether they are set or unset, different
68  // instructions/registers are available. For example, inlining a callee with
69  // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
70  // fail if the callee uses ARM only instructions, e.g. in inline asm.
71  const FeatureBitset InlineFeaturesAllowed = {
72  ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73  ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
74  ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
75  ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
76  ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
77  ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
78  ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
79  ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
80  ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
81  ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
82  ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
83  ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
84  ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
85  ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
86  ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
87  ARM::FeatureHasSlowFPVMLx, ARM::FeatureHasSlowFPVFMx,
88  ARM::FeatureVMLxForwarding, ARM::FeaturePref32BitThumb,
89  ARM::FeatureAvoidPartialCPSR, ARM::FeatureCheapPredicableCPSR,
90  ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
91  ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
92  ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
93  ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
94  ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
95  ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
96  };
97 
98  const ARMSubtarget *getST() const { return ST; }
99  const ARMTargetLowering *getTLI() const { return TLI; }
100 
101 public:
102  explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
103  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
104  TLI(ST->getTargetLowering()) {}
105 
106  bool areInlineCompatible(const Function *Caller,
107  const Function *Callee) const;
108 
109  bool enableInterleavedAccessVectorization() { return true; }
110 
112  getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const;
113 
114  /// Floating-point computation using ARMv8 AArch32 Advanced
115  /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
116  /// and Arm MVE are IEEE-754 compliant.
118  return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
119  }
120 
122  IntrinsicInst &II) const;
123 
124  /// \name Scalar TTI Implementations
125  /// @{
126 
127  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
128  const APInt &Imm, Type *Ty);
129 
130  using BaseT::getIntImmCost;
131  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
133 
134  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
135  const APInt &Imm, Type *Ty,
137  Instruction *Inst = nullptr);
138 
139  /// @}
140 
141  /// \name Vector TTI Implementations
142  /// @{
143 
144  unsigned getNumberOfRegisters(unsigned ClassID) const {
145  bool Vector = (ClassID == 1);
146  if (Vector) {
147  if (ST->hasNEON())
148  return 16;
149  if (ST->hasMVEIntegerOps())
150  return 8;
151  return 0;
152  }
153 
154  if (ST->isThumb1Only())
155  return 8;
156  return 13;
157  }
158 
160  switch (K) {
162  return TypeSize::getFixed(32);
164  if (ST->hasNEON())
165  return TypeSize::getFixed(128);
166  if (ST->hasMVEIntegerOps())
167  return TypeSize::getFixed(128);
168  return TypeSize::getFixed(0);
170  return TypeSize::getScalable(0);
171  }
172  llvm_unreachable("Unsupported register kind");
173  }
174 
175  unsigned getMaxInterleaveFactor(unsigned VF) {
176  return ST->getMaxInterleaveFactor();
177  }
178 
180 
181  bool isLegalMaskedLoad(Type *DataTy, Align Alignment);
182 
183  bool isLegalMaskedStore(Type *DataTy, Align Alignment) {
184  return isLegalMaskedLoad(DataTy, Alignment);
185  }
186 
187  bool isLegalMaskedGather(Type *Ty, Align Alignment);
188 
189  bool isLegalMaskedScatter(Type *Ty, Align Alignment) {
190  return isLegalMaskedGather(Ty, Alignment);
191  }
192 
194 
195  int getNumMemOps(const IntrinsicInst *I) const;
196 
198  ArrayRef<int> Mask, int Index,
199  VectorType *SubTp);
200 
201  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
202  TTI::ReductionFlags Flags) const;
203 
204  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
205  TTI::ReductionFlags Flags) const;
206 
207  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
208 
210  const Instruction *I = nullptr);
211 
212  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
215  const Instruction *I = nullptr);
216 
217  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
218  CmpInst::Predicate VecPred,
220  const Instruction *I = nullptr);
221 
222  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
223  unsigned Index);
224 
226  const SCEV *Ptr);
227 
229  unsigned Opcode, Type *Ty,
236  const Instruction *CxtI = nullptr);
237 
238  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
239  MaybeAlign Alignment, unsigned AddressSpace,
241  const Instruction *I = nullptr);
242 
243  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
244  Align Alignment, unsigned AddressSpace,
246 
248  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
249  Align Alignment, unsigned AddressSpace,
251  bool UseMaskForCond = false, bool UseMaskForGaps = false);
252 
253  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
254  const Value *Ptr, bool VariableMask,
255  Align Alignment,
257  const Instruction *I = nullptr);
258 
259  InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
260  bool IsPairwiseForm,
262  InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned,
263  Type *ResTy, VectorType *ValTy,
265 
268 
270  bool isLoweredToCall(const Function *F);
272  AssumptionCache &AC,
273  TargetLibraryInfo *LibInfo,
274  HardwareLoopInfo &HWLoopInfo);
276  ScalarEvolution &SE,
277  AssumptionCache &AC,
278  TargetLibraryInfo *TLI,
279  DominatorTree *DT,
280  const LoopAccessInfo *LAI);
283 
284  bool emitGetActiveLaneMask() const;
285 
289  // In the ROPI and RWPI relocation models we can't have pointers to global
290  // variables or functions in constant data, so don't convert switches to
291  // lookup tables if any of the values would need relocation.
292  if (ST->isROPI() || ST->isRWPI())
293  return !C->needsDynamicRelocation();
294 
295  return true;
296  }
297  /// @}
298 };
299 
300 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
301 /// instruction with the specified blocksize. (The order of the elements
302 /// within each block of the vector is reversed.)
303 inline bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
304  assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
305  "Only possible block sizes for VREV are: 16, 32, 64");
306 
307  unsigned EltSz = VT.getScalarSizeInBits();
308  if (EltSz != 8 && EltSz != 16 && EltSz != 32)
309  return false;
310 
311  unsigned BlockElts = M[0] + 1;
312  // If the first shuffle index is UNDEF, be optimistic.
313  if (M[0] < 0)
314  BlockElts = BlockSize / EltSz;
315 
316  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
317  return false;
318 
319  for (unsigned i = 0, e = M.size(); i < e; ++i) {
320  if (M[i] < 0)
321  continue; // ignore UNDEF indices
322  if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
323  return false;
324  }
325 
326  return true;
327 }
328 
329 } // end namespace llvm
330 
331 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: ARMTargetTransformInfo.h:288
llvm
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1340
BlockSize
static const int BlockSize
Definition: TarWriter.cpp:33
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: ARMTargetTransformInfo.h:159
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::ARMTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: ARMTargetTransformInfo.cpp:1141
llvm::ARMTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: ARMTargetTransformInfo.cpp:85
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:929
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::ARMTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1491
llvm::ARMTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:382
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:381
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::Optional
Definition: APInt.h:33
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:355
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TailPredication::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:47
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ARMTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1021
llvm::ARMTTIImpl::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
Definition: ARMTargetTransformInfo.cpp:1846
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
SubtargetFeature.h
llvm::ARMTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: ARMTargetTransformInfo.h:144
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:908
llvm::ARMTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: ARMTargetTransformInfo.cpp:327
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:850
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1084
llvm::TailPredication::Enabled
@ Enabled
Definition: ARMTargetTransformInfo.h:45
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMTTIImpl::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
Definition: ARMTargetTransformInfo.cpp:286
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::Instruction
Definition: Instruction.h:45
llvm::ARMTTIImpl::isLoweredToCall
bool isLoweredToCall(const Function *F)
Definition: ARMTargetTransformInfo.cpp:1698
llvm::ARMTTIImpl::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: ARMTargetTransformInfo.cpp:2121
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:929
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::isVREVMask
bool isVREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize...
Definition: ARMTargetTransformInfo.h:303
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: ARMTargetTransformInfo.h:207
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::ARMTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: ARMTargetTransformInfo.cpp:1450
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::ARMTTIImpl::getNumMemOps
int getNumMemOps(const IntrinsicInst *I) const
Given a memcpy/memset/memmove instruction, return the number of memory operations performed,...
Definition: ARMTargetTransformInfo.cpp:1065
llvm::ARMTTIImpl::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1004
llvm::ARMTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: ARMTargetTransformInfo.cpp:2131
llvm::ARMTTIImpl::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI)
Definition: ARMTargetTransformInfo.cpp:2071
llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe()
Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv...
Definition: ARMTargetTransformInfo.h:117
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::ARMTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1386
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::ARMTTIImpl::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *ValTy, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1615
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TailPredication::Mode
Mode
Definition: ARMTargetTransformInfo.h:42
llvm::ARMTTIImpl::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1131
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::ARMTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
Definition: ARMTargetTransformInfo.cpp:982
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TPLoop::ForceDisabled
@ ForceDisabled
Definition: ARMTargetTransformInfo.h:53
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:908
llvm::ARMTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1635
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:519
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
ArrayRef.h
TemplateParamKind::Type
@ Type
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1433
llvm::ARMTTIImpl::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2211
ARM.h
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:900
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::ARMTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: ARMTargetTransformInfo.cpp:104
llvm::ArrayRef< int >
llvm::LoopInfo
Definition: LoopInfo.h:1080
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:345
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::ARMTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1041
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:214
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:767
llvm::ARMTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:836
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:901
Constant.h
llvm::TPLoop::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:53
llvm::ARMTTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: ARMTargetTransformInfo.h:109
llvm::ARMTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:251
llvm::TypeSize
Definition: TypeSize.h:417
Function.h
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::ARMTTIImpl::ARMTTIImpl
ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
Definition: ARMTargetTransformInfo.h:102
llvm::ARMTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.h:189
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:929
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:94
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::ARMTTIImpl::maybeLoweredToCall
bool maybeLoweredToCall(Instruction &I)
Definition: ARMTargetTransformInfo.cpp:1759
llvm::ARMTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:396
llvm::TPLoop::MemTransfer
MemTransfer
Definition: ARMTargetTransformInfo.h:53
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:929
llvm::TailPredication::EnabledNoReductions
@ EnabledNoReductions
Definition: ARMTargetTransformInfo.h:44
llvm::TPLoop::Allow
@ Allow
Definition: ARMTargetTransformInfo.h:53
llvm::ARMTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:183
TargetTransformInfo.h
llvm::ARMTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: ARMTargetTransformInfo.cpp:2206
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTTIImpl::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2225
llvm::ARMTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: ARMTargetTransformInfo.cpp:800
llvm::ARMTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: ARMTargetTransformInfo.h:175
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
BasicTTIImpl.h
ARMTargetMachine.h
llvm::ARMTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: ARMTargetTransformInfo.cpp:1244
llvm::ARMTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: ARMTargetTransformInfo.cpp:120
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::ARMTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, bool IsPairwiseForm, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1591
llvm::TailPredication::ForceEnabledNoReductions
@ ForceEnabledNoReductions
Definition: ARMTargetTransformInfo.h:46