LLVM  16.0.0git
ARMTargetTransformInfo.h
Go to the documentation of this file.
1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19 
20 #include "ARM.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/IR/Constant.h"
27 #include "llvm/IR/Function.h"
29 
30 namespace llvm {
31 
32 class APInt;
33 class ARMTargetLowering;
34 class Instruction;
35 class Loop;
36 class SCEV;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40 
41 namespace TailPredication {
42  enum Mode {
43  Disabled = 0,
48  };
49 }
50 
51 // For controlling conversion of memcpy into Tail Predicated loop.
52 namespace TPLoop {
54 }
55 
56 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
58  using TTI = TargetTransformInfo;
59 
60  friend BaseT;
61 
62  const ARMSubtarget *ST;
63  const ARMTargetLowering *TLI;
64 
65  // Currently the following features are excluded from InlineFeaturesAllowed.
66  // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
67  // Depending on whether they are set or unset, different
68  // instructions/registers are available. For example, inlining a callee with
69  // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
70  // fail if the callee uses ARM only instructions, e.g. in inline asm.
71  const FeatureBitset InlineFeaturesAllowed = {
72  ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73  ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
74  ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
75  ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
76  ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
77  ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
78  ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
79  ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
80  ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
81  ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
82  ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
83  ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
84  ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
85  ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
86  ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
87  ARM::FeatureHasSlowFPVMLx, ARM::FeatureHasSlowFPVFMx,
88  ARM::FeatureVMLxForwarding, ARM::FeaturePref32BitThumb,
89  ARM::FeatureAvoidPartialCPSR, ARM::FeatureCheapPredicableCPSR,
90  ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
91  ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
92  ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
93  ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
94  ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
95  ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
96  };
97 
98  const ARMSubtarget *getST() const { return ST; }
99  const ARMTargetLowering *getTLI() const { return TLI; }
100 
101 public:
102  explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
103  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
104  TLI(ST->getTargetLowering()) {}
105 
106  bool areInlineCompatible(const Function *Caller,
107  const Function *Callee) const;
108 
109  bool enableInterleavedAccessVectorization() { return true; }
110 
112  getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const;
113 
114  /// Floating-point computation using ARMv8 AArch32 Advanced
115  /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
116  /// and Arm MVE are IEEE-754 compliant.
118  return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
119  }
120 
122  IntrinsicInst &II) const;
124  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
125  APInt &UndefElts2, APInt &UndefElts3,
126  std::function<void(Instruction *, unsigned, APInt, APInt &)>
127  SimplifyAndSetOp) const;
128 
129  /// \name Scalar TTI Implementations
130  /// @{
131 
132  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
133  const APInt &Imm, Type *Ty);
134 
135  using BaseT::getIntImmCost;
138 
139  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
140  const APInt &Imm, Type *Ty,
142  Instruction *Inst = nullptr);
143 
144  /// @}
145 
146  /// \name Vector TTI Implementations
147  /// @{
148 
149  unsigned getNumberOfRegisters(unsigned ClassID) const {
150  bool Vector = (ClassID == 1);
151  if (Vector) {
152  if (ST->hasNEON())
153  return 16;
154  if (ST->hasMVEIntegerOps())
155  return 8;
156  return 0;
157  }
158 
159  if (ST->isThumb1Only())
160  return 8;
161  return 13;
162  }
163 
165  switch (K) {
167  return TypeSize::getFixed(32);
169  if (ST->hasNEON())
170  return TypeSize::getFixed(128);
171  if (ST->hasMVEIntegerOps())
172  return TypeSize::getFixed(128);
173  return TypeSize::getFixed(0);
175  return TypeSize::getScalable(0);
176  }
177  llvm_unreachable("Unsupported register kind");
178  }
179 
180  unsigned getMaxInterleaveFactor(unsigned VF) {
181  return ST->getMaxInterleaveFactor();
182  }
183 
185 
186  bool isLegalMaskedLoad(Type *DataTy, Align Alignment);
187 
188  bool isLegalMaskedStore(Type *DataTy, Align Alignment) {
189  return isLegalMaskedLoad(DataTy, Alignment);
190  }
191 
193  // For MVE, we have a custom lowering pass that will already have custom
194  // legalised any gathers that we can lower to MVE intrinsics, and want to
195  // expand all the rest. The pass runs before the masked intrinsic lowering
196  // pass.
197  return true;
198  }
199 
201  return forceScalarizeMaskedGather(VTy, Alignment);
202  }
203 
204  bool isLegalMaskedGather(Type *Ty, Align Alignment);
205 
206  bool isLegalMaskedScatter(Type *Ty, Align Alignment) {
207  return isLegalMaskedGather(Ty, Alignment);
208  }
209 
211 
212  int getNumMemOps(const IntrinsicInst *I) const;
213 
217  VectorType *SubTp,
219 
220  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
221  TTI::ReductionFlags Flags) const;
222 
223  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
224  TTI::ReductionFlags Flags) const;
225 
226  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
227 
229  const Instruction *I = nullptr);
230 
231  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
234  const Instruction *I = nullptr);
235 
236  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
237  CmpInst::Predicate VecPred,
239  const Instruction *I = nullptr);
240 
242  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
243  unsigned Index);
244 
246  const SCEV *Ptr);
247 
249  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
251  TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
252  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
253  const Instruction *CxtI = nullptr);
254 
255  InstructionCost
256  getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
258  TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
259  const Instruction *I = nullptr);
260 
261  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
262  Align Alignment, unsigned AddressSpace,
264 
265  InstructionCost getInterleavedMemoryOpCost(
266  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
267  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
268  bool UseMaskForCond = false, bool UseMaskForGaps = false);
269 
270  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
271  const Value *Ptr, bool VariableMask,
272  Align Alignment,
274  const Instruction *I = nullptr);
275 
276  InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
277  Optional<FastMathFlags> FMF,
279  InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
280  Type *ResTy, VectorType *ValTy,
281  Optional<FastMathFlags> FMF,
283  InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy,
284  VectorType *ValTy,
286 
287  InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
289 
290  /// getScalingFactorCost - Return the cost of the scaling used in
291  /// addressing mode represented by AM.
292  /// If the AM is supported, the return value must be >= 0.
293  /// If the AM is not supported, the return value must be negative.
294  InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
295  int64_t BaseOffset, bool HasBaseReg,
296  int64_t Scale, unsigned AddrSpace) const;
297 
298  bool maybeLoweredToCall(Instruction &I);
299  bool isLoweredToCall(const Function *F);
300  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
301  AssumptionCache &AC,
302  TargetLibraryInfo *LibInfo,
303  HardwareLoopInfo &HWLoopInfo);
304  bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
305  AssumptionCache &AC, TargetLibraryInfo *TLI,
306  DominatorTree *DT,
307  LoopVectorizationLegality *LVL,
308  InterleavedAccessInfo *IAI);
309  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
310  TTI::UnrollingPreferences &UP,
311  OptimizationRemarkEmitter *ORE);
312 
314 
315  void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
316  TTI::PeelingPreferences &PP);
318  // In the ROPI and RWPI relocation models we can't have pointers to global
319  // variables or functions in constant data, so don't convert switches to
320  // lookup tables if any of the values would need relocation.
321  if (ST->isROPI() || ST->isRWPI())
322  return !C->needsDynamicRelocation();
323 
324  return true;
325  }
326  /// @}
327 };
328 
329 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
330 /// instruction with the specified blocksize. (The order of the elements
331 /// within each block of the vector is reversed.)
332 inline bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
333  assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
334  "Only possible block sizes for VREV are: 16, 32, 64");
335 
336  unsigned EltSz = VT.getScalarSizeInBits();
337  if (EltSz != 8 && EltSz != 16 && EltSz != 32)
338  return false;
339 
340  unsigned BlockElts = M[0] + 1;
341  // If the first shuffle index is UNDEF, be optimistic.
342  if (M[0] < 0)
343  BlockElts = BlockSize / EltSz;
344 
345  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
346  return false;
347 
348  for (unsigned i = 0, e = M.size(); i < e; ++i) {
349  if (M[i] < 0)
350  continue; // ignore UNDEF indices
351  if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
352  return false;
353  }
354 
355  return true;
356 }
357 
358 } // end namespace llvm
359 
360 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: ARMTargetTransformInfo.h:317
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1454
BlockSize
static const int BlockSize
Definition: TarWriter.cpp:33
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: ARMTargetTransformInfo.h:164
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::ARMTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: ARMTargetTransformInfo.cpp:1514
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::ARMTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: ARMTargetTransformInfo.cpp:86
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:964
llvm::ARMTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1555
llvm::ARMTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:457
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:390
llvm::ARMTTIImpl::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:192
llvm::Optional
Definition: APInt.h:33
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:392
VectorType
Definition: ItaniumDemangle.h:1075
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:923
llvm::ARMTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: ARMTargetTransformInfo.cpp:2288
llvm::TailPredication::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:47
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ARMTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1094
llvm::ARMTTIImpl::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
Definition: ARMTargetTransformInfo.cpp:1994
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
SubtargetFeature.h
llvm::ARMTTIImpl::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: ARMTargetTransformInfo.cpp:2278
llvm::ARMTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: ARMTargetTransformInfo.h:149
llvm::BasicTTIImplBase< ARMTTIImpl >::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:1187
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:915
llvm::ARMTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: ARMTargetTransformInfo.cpp:386
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1138
llvm::TailPredication::Enabled
@ Enabled
Definition: ARMTargetTransformInfo.h:45
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1449
llvm::ARMTTIImpl::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
Definition: ARMTargetTransformInfo.cpp:2230
llvm::ARMTTIImpl::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
Definition: ARMTargetTransformInfo.cpp:329
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::ARMTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: ARMTargetTransformInfo.cpp:1309
llvm::Instruction
Definition: Instruction.h:42
llvm::ARMTTIImpl::isLoweredToCall
bool isLoweredToCall(const Function *F)
Definition: ARMTargetTransformInfo.cpp:1846
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:964
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::isVREVMask
bool isVREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize...
Definition: ARMTargetTransformInfo.h:332
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: ARMTargetTransformInfo.h:226
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::ARMTTIImpl::getNumMemOps
int getNumMemOps(const IntrinsicInst *I) const
Given a memcpy/memset/memmove instruction, return the number of memory operations performed,...
Definition: ARMTargetTransformInfo.cpp:1126
llvm::ARMTTIImpl::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1077
llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe()
Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv...
Definition: ARMTargetTransformInfo.h:117
llvm::ARMTTIImpl::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:200
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TailPredication::Mode
Mode
Definition: ARMTargetTransformInfo.h:42
llvm::ARMTTIImpl::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1192
llvm::ARMTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
Definition: ARMTargetTransformInfo.cpp:1055
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::TPLoop::ForceDisabled
@ ForceDisabled
Definition: ARMTargetTransformInfo.h:53
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1741
llvm::ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: ARMTargetTransformInfo.cpp:252
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:78
ArrayRef.h
TemplateParamKind::Type
@ Type
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1497
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::ARMTTIImpl::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2396
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
ARM.h
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::ARMTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: ARMTargetTransformInfo.cpp:105
llvm::ArrayRef< int >
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:352
llvm::ARMTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1114
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:805
llvm::ARMTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:911
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:632
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:907
Constant.h
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::TPLoop::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:53
llvm::ARMTTIImpl::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1679
llvm::ARMTTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: ARMTargetTransformInfo.h:109
llvm::ARMTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:294
llvm::TypeSize
Definition: TypeSize.h:435
Function.h
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ARMTTIImpl::ARMTTIImpl
ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
Definition: ARMTargetTransformInfo.h:102
llvm::ARMTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.h:206
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:165
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:964
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ARMTTIImpl::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
Definition: ARMTargetTransformInfo.cpp:2417
llvm::ARMTTIImpl::maybeLoweredToCall
bool maybeLoweredToCall(Instruction &I)
Definition: ARMTargetTransformInfo.cpp:1907
llvm::ARMTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:471
llvm::TPLoop::MemTransfer
MemTransfer
Definition: ARMTargetTransformInfo.h:53
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:964
llvm::ARMTTIImpl::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *ValTy, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1714
llvm::TailPredication::EnabledNoReductions
@ EnabledNoReductions
Definition: ARMTargetTransformInfo.h:44
llvm::TPLoop::Allow
@ Allow
Definition: ARMTargetTransformInfo.h:53
llvm::ARMTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:188
TargetTransformInfo.h
llvm::ARMTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: ARMTargetTransformInfo.cpp:2391
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTTIImpl::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2410
llvm::ARMTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: ARMTargetTransformInfo.cpp:875
llvm::ARMTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: ARMTargetTransformInfo.h:180
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
ARMTargetMachine.h
llvm::ARMTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: ARMTargetTransformInfo.cpp:121
llvm::ARMTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: ARMTargetTransformInfo.cpp:1202
llvm::ARMTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1655
llvm::TailPredication::ForceEnabledNoReductions
@ ForceEnabledNoReductions
Definition: ARMTargetTransformInfo.h:46