LLVM  13.0.0git
HexagonSplitConst32AndConst64.cpp
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1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // When the compiler is invoked with no small data, for instance, with the -G0
10 // command line option, then all CONST* opcodes should be broken down into
11 // appropriate LO and HI instructions. This splitting is done by this pass.
12 // The only reason this is not done in the DAG lowering itself is that there
13 // is no simple way of getting the register allocator to allot the same hard
14 // register to the result of LO and HI instructions. This pass is always
15 // scheduled after register allocation.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
24 #include "llvm/CodeGen/Passes.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "xfer"
31 
32 namespace llvm {
35 }
36 
37 namespace {
38  class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
39  public:
40  static char ID;
41  HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {
44  }
45  StringRef getPassName() const override {
46  return "Hexagon Split Const32s and Const64s";
47  }
48  bool runOnMachineFunction(MachineFunction &Fn) override;
49  MachineFunctionProperties getRequiredProperties() const override {
52  }
53  };
54 }
55 
57 
58 INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
59  "Hexagon Split Const32s and Const64s", false, false)
60 
61 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
62  auto &HST = Fn.getSubtarget<HexagonSubtarget>();
63  auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
64  auto &TLOF = *HTM.getObjFileLowering();
65  if (HST.useSmallData() && TLOF.isSmallDataEnabled(HTM))
66  return false;
67 
68  const TargetInstrInfo *TII = HST.getInstrInfo();
69  const TargetRegisterInfo *TRI = HST.getRegisterInfo();
70 
71  // Loop over all of the basic blocks
72  for (MachineBasicBlock &B : Fn) {
73  for (auto I = B.begin(), E = B.end(); I != E; ) {
74  MachineInstr &MI = *I;
75  ++I;
76  unsigned Opc = MI.getOpcode();
77 
78  if (Opc == Hexagon::CONST32) {
79  Register DestReg = MI.getOperand(0).getReg();
80  uint64_t ImmValue = MI.getOperand(1).getImm();
81  const DebugLoc &DL = MI.getDebugLoc();
82  BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
83  .addImm(ImmValue);
84  B.erase(&MI);
85  } else if (Opc == Hexagon::CONST64) {
86  Register DestReg = MI.getOperand(0).getReg();
87  int64_t ImmValue = MI.getOperand(1).getImm();
88  const DebugLoc &DL = MI.getDebugLoc();
89  Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90  Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
91 
92  int32_t LowWord = (ImmValue & 0xFFFFFFFF);
93  int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
94 
95  BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
96  .addImm(LowWord);
97  BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
98  .addImm(HighWord);
99  B.erase(&MI);
100  }
101  }
102  }
103 
104  return true;
105 }
106 
107 
108 //===----------------------------------------------------------------------===//
109 // Public Constructor Functions
110 //===----------------------------------------------------------------------===//
112  return new HexagonSplitConst32AndConst64();
113 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
Definition: AllocatorList.h:23
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
TargetInstrInfo.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
HexagonTargetMachine.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:133
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
Passes.h
llvm::HexagonISD::CONST32
@ CONST32
Definition: HexagonISelLowering.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::createHexagonSplitConst32AndConst64
FunctionPass * createHexagonSplitConst32AndConst64()
Definition: HexagonSplitConst32AndConst64.cpp:111
INITIALIZE_PASS
INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata", "Hexagon Split Const32s and Const64s", false, false) bool HexagonSplitConst32AndConst64
Definition: HexagonSplitConst32AndConst64.cpp:58
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
HexagonTargetObjectFile.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:42
llvm::initializeHexagonSplitConst32AndConst64Pass
void initializeHexagonSplitConst32AndConst64Pass(PassRegistry &)
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1098
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
TargetRegisterInfo.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38