LLVM  16.0.0git
HexagonTargetTransformInfo.cpp
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1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
16 #include "HexagonSubtarget.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "hexagontti"
30 
31 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
32  cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
33 
35  "force-hvx-float", cl::Hidden,
36  cl::desc("Enable auto-vectorization of floatint point types on v68."));
37 
38 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
39  cl::init(true), cl::Hidden,
40  cl::desc("Control lookup table emission on Hexagon target"));
41 
42 static cl::opt<bool> HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true),
43  cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
44 
45 // Constant "cost factor" to make floating point operations more expensive
46 // in terms of vectorization cost. This isn't the best way, but it should
47 // do. Ultimately, the cost should use cycles.
48 static const unsigned FloatFactor = 4;
49 
50 bool HexagonTTIImpl::useHVX() const {
51  return ST.useHVXOps() && HexagonAutoHVX;
52 }
53 
54 bool HexagonTTIImpl::isHVXVectorType(Type *Ty) const {
55  auto *VecTy = dyn_cast<VectorType>(Ty);
56  if (!VecTy)
57  return false;
58  if (!ST.isTypeForHVX(VecTy))
59  return false;
60  if (ST.useHVXV69Ops() || !VecTy->getElementType()->isFloatingPointTy())
61  return true;
62  return ST.useHVXV68Ops() && EnableV68FloatAutoHVX;
63 }
64 
65 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
66  if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
67  return VTy->getNumElements();
68  assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
69  "Expecting scalar type");
70  return 1;
71 }
72 
74 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
75  // Return fast hardware support as every input < 64 bits will be promoted
76  // to 64 bits.
78 }
79 
80 // The Hexagon target can unroll loops with run-time trip counts.
84  UP.Runtime = UP.Partial = true;
85 }
86 
90  // Only try to peel innermost loops with small runtime trip counts.
91  if (L && L->isInnermost() && canPeel(L) &&
92  SE.getSmallConstantTripCount(L) == 0 &&
93  SE.getSmallConstantMaxTripCount(L) > 0 &&
94  SE.getSmallConstantMaxTripCount(L) <= 5) {
95  PP.PeelCount = 2;
96  }
97 }
98 
101  ScalarEvolution *SE) const {
102  return TTI::AMK_PostIndexed;
103 }
104 
105 /// --- Vector TTI begin ---
106 
107 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
108  if (Vector)
109  return useHVX() ? 32 : 0;
110  return 32;
111 }
112 
114  return useHVX() ? 2 : 1;
115 }
116 
117 TypeSize
119  switch (K) {
121  return TypeSize::getFixed(32);
125  return TypeSize::getScalable(0);
126  }
127 
128  llvm_unreachable("Unsupported register kind");
129 }
130 
132  return useHVX() ? ST.getVectorLength()*8 : 32;
133 }
134 
136  bool IsScalable) const {
137  assert(!IsScalable && "Scalable VFs are not supported for Hexagon");
138  return ElementCount::getFixed((8 * ST.getVectorLength()) / ElemWidth);
139 }
140 
142  VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) {
143  return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
144 }
145 
148  ArrayRef<Type *> Tys) {
150 }
151 
153  ArrayRef<Type *> Tys,
155  return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind);
156 }
157 
161  if (ICA.getID() == Intrinsic::bswap) {
162  std::pair<InstructionCost, MVT> LT =
164  return LT.first + 2;
165  }
167 }
168 
170  ScalarEvolution *SE,
171  const SCEV *S) {
172  return 0;
173 }
174 
176  MaybeAlign Alignment,
177  unsigned AddressSpace,
179  TTI::OperandValueInfo OpInfo,
180  const Instruction *I) {
181  assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
182  // TODO: Handle other cost kinds.
184  return 1;
185 
186  if (Opcode == Instruction::Store)
187  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
188  CostKind, OpInfo, I);
189 
190  if (Src->isVectorTy()) {
191  VectorType *VecTy = cast<VectorType>(Src);
192  unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
193  if (isHVXVectorType(VecTy)) {
194  unsigned RegWidth =
196  .getFixedSize();
197  assert(RegWidth && "Non-zero vector register width expected");
198  // Cost of HVX loads.
199  if (VecWidth % RegWidth == 0)
200  return VecWidth / RegWidth;
201  // Cost of constructing HVX vector from scalar loads
202  const Align RegAlign(RegWidth / 8);
203  if (!Alignment || *Alignment > RegAlign)
204  Alignment = RegAlign;
205  assert(Alignment);
206  unsigned AlignWidth = 8 * Alignment->value();
207  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
208  return 3 * NumLoads;
209  }
210 
211  // Non-HVX vectors.
212  // Add extra cost for floating point types.
213  unsigned Cost =
214  VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
215 
216  // At this point unspecified alignment is considered as Align(1).
217  const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
218  unsigned AlignWidth = 8 * BoundAlignment.value();
219  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
220  if (Alignment == Align(4) || Alignment == Align(8))
221  return Cost * NumLoads;
222  // Loads of less than 32 bits will need extra inserts to compose a vector.
223  assert(BoundAlignment <= Align(8));
224  unsigned LogA = Log2(BoundAlignment);
225  return (3 - LogA) * Cost * NumLoads;
226  }
227 
228  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind,
229  OpInfo, I);
230 }
231 
234  Align Alignment, unsigned AddressSpace,
236  return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
237  CostKind);
238 }
239 
243  int Index, Type *SubTp,
245  return 1;
246 }
247 
249  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
250  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
251  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
252  Alignment, CostKind, I);
253 }
254 
256  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
257  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
258  bool UseMaskForCond, bool UseMaskForGaps) {
259  if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
260  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
261  Alignment, AddressSpace,
262  CostKind,
263  UseMaskForCond, UseMaskForGaps);
264  return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
265  CostKind);
266 }
267 
269  Type *CondTy,
270  CmpInst::Predicate VecPred,
272  const Instruction *I) {
273  if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) {
274  if (!isHVXVectorType(ValTy) && ValTy->isFPOrFPVectorTy())
275  return InstructionCost::getMax();
276  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
277  if (Opcode == Instruction::FCmp)
278  return LT.first + FloatFactor * getTypeNumElements(ValTy);
279  }
280  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
281 }
282 
284  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
287  const Instruction *CxtI) {
288  // TODO: Handle more cost kinds.
290  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
291  Op2Info, Args, CxtI);
292 
293  if (Ty->isVectorTy()) {
294  if (!isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy())
295  return InstructionCost::getMax();
296  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
297  if (LT.second.isFloatingPoint())
298  return LT.first + FloatFactor * getTypeNumElements(Ty);
299  }
300  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
301  Args, CxtI);
302 }
303 
305  Type *SrcTy,
308  const Instruction *I) {
309  auto isNonHVXFP = [this] (Type *Ty) {
310  return Ty->isVectorTy() && !isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy();
311  };
312  if (isNonHVXFP(SrcTy) || isNonHVXFP(DstTy))
313  return InstructionCost::getMax();
314 
315  if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
316  unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
317  unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
318 
319  std::pair<InstructionCost, MVT> SrcLT = getTypeLegalizationCost(SrcTy);
320  std::pair<InstructionCost, MVT> DstLT = getTypeLegalizationCost(DstTy);
322  std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
323  // TODO: Allow non-throughput costs that aren't binary.
325  return Cost == 0 ? 0 : 1;
326  return Cost;
327  }
328  return 1;
329 }
330 
332  unsigned Index) {
333  Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
334  : Val;
335  if (Opcode == Instruction::InsertElement) {
336  // Need two rotations for non-zero index.
337  unsigned Cost = (Index != 0) ? 2 : 0;
338  if (ElemTy->isIntegerTy(32))
339  return Cost;
340  // If it's not a 32-bit value, there will need to be an extract.
341  return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
342  }
343 
344  if (Opcode == Instruction::ExtractElement)
345  return 2;
346 
347  return 1;
348 }
349 
351  // This function is called from scalarize-masked-mem-intrin, which runs
352  // in pre-isel. Use ST directly instead of calling isHVXVectorType.
354 }
355 
357  // This function is called from scalarize-masked-mem-intrin, which runs
358  // in pre-isel. Use ST directly instead of calling isHVXVectorType.
360 }
361 
362 /// --- Vector TTI end ---
363 
365  return ST.getL1PrefetchDistance();
366 }
367 
369  return ST.getL1CacheLineSize();
370 }
371 
376  auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
377  if (!CI->isIntegerCast())
378  return false;
379  // Only extensions from an integer type shorter than 32-bit to i32
380  // can be folded into the load.
381  const DataLayout &DL = getDataLayout();
382  unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
383  unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
384  if (DBW != 32 || SBW >= DBW)
385  return false;
386 
387  const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
388  // Technically, this code could allow multiple uses of the load, and
389  // check if all the uses are the same extension operation, but this
390  // should be sufficient for most cases.
391  return LI && LI->hasOneUse();
392  };
393 
394  if (const CastInst *CI = dyn_cast<const CastInst>(U))
395  if (isCastFoldedIntoLoad(CI))
398 }
399 
401  return EmitLookupTables;
402 }
llvm::InstructionCost
Definition: InstructionCost.h:30
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:586
llvm::HexagonTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: HexagonTargetTransformInfo.cpp:131
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:313
ValueTypes.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:474
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm::BasicTTIImplBase< HexagonTTIImpl >::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: BasicTTIImpl.h:747
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::HexagonTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: HexagonTargetTransformInfo.cpp:283
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:444
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::TargetTransformInfo::AMK_PostIndexed
@ AMK_PostIndexed
Definition: TargetTransformInfo.h:635
llvm::TargetTransformInfoImplCRTPBase< HexagonTTIImpl >::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:1015
llvm::HexagonTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:175
HexagonSubtarget.h
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:153
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
EnableV68FloatAutoHVX
static cl::opt< bool > EnableV68FloatAutoHVX("force-hvx-float", cl::Hidden, cl::desc("Enable auto-vectorization of floatint point types on v68."))
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:965
llvm::Type::isFPOrFPVectorTy
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
Definition: Type.h:198
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::HexagonTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, ArrayRef< const Value * > Args=None)
Definition: HexagonTargetTransformInfo.cpp:240
HexagonTargetTransformInfo.h
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:470
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::MaybeAlign::valueOrOne
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:142
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::VectorType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:422
llvm::HexagonTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: HexagonTargetTransformInfo.cpp:113
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::canPeel
bool canPeel(const Loop *L)
Definition: LoopPeel.cpp:84
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:184
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:924
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:214
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::HexagonSubtarget::useHVXV69Ops
bool useHVXV69Ops() const
Definition: HexagonSubtarget.h:255
llvm::HexagonTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: HexagonTargetTransformInfo.cpp:248
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
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unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:719
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constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: BasicTTIImpl.h:789
HexagonMaskedVMem
static cl::opt< bool > HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true), cl::Hidden, cl::desc("Enable masked loads/stores for HVX"))
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: HexagonTargetTransformInfo.cpp:331
llvm::HexagonTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: HexagonTargetTransformInfo.cpp:74
InlinePriorityMode::Cost
@ Cost
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:887
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CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1139
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Definition: User.h:44
InstrTypes.h
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:209
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bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:246
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Index
Definition: Dwarf.h:472
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This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::BasicTTIImplBase< HexagonTTIImpl >::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: BasicTTIImpl.h:825
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:234
llvm::Instruction
Definition: Instruction.h:42
llvm::HexagonTTIImpl::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: HexagonTargetTransformInfo.cpp:400
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:965
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This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::BasicTTIImplBase< HexagonTTIImpl >::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1137
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static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
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Definition: TargetTransformInfo.h:120
Operands
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Definition: MIRNamerPass.cpp:74
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:723
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bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:210
llvm::ScalarEvolution::getSmallConstantTripCount
unsigned getSmallConstantTripCount(const Loop *L)
Returns the exact trip count of the loop if we can compute it, and the result is a small constant.
Definition: ScalarEvolution.cpp:8016
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::HexagonTTIImpl::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:373
llvm::ScalarEvolution::getSmallConstantMaxTripCount
unsigned getSmallConstantMaxTripCount(const Loop *L)
Returns the upper bound of the loop trip count as a normal unsigned value.
Definition: ScalarEvolution.cpp:8032
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:417
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::HexagonTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: HexagonTargetTransformInfo.cpp:255
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::BasicTTIImplBase< HexagonTTIImpl >::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: BasicTTIImpl.h:1291
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1231
llvm::HexagonTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:350
llvm::HexagonTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:304
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::HexagonTTIImpl::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:152
llvm::HexagonSubtarget::useHVXV68Ops
bool useHVXV68Ops() const
Definition: HexagonSubtarget.h:252
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:244
llvm::TargetTransformInfo::PeelingPreferences::PeelCount
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Definition: TargetTransformInfo.h:533
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::HexagonTTIImpl::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Definition: HexagonTargetTransformInfo.cpp:147
llvm::BasicTTIImplBase< HexagonTTIImpl >::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract)
Estimate the overhead of scalarizing an instruction.
Definition: BasicTTIImpl.h:707
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::HexagonTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: HexagonTargetTransformInfo.cpp:118
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:429
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
HexagonAutoHVX
static cl::opt< bool > HexagonAutoHVX("hexagon-autohvx", cl::init(false), cl::Hidden, cl::desc("Enable loop vectorizer for HVX"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:596
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::HexagonTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:233
llvm::LoopBase::isInnermost
bool isInnermost() const
Return true if the loop does not contain any (natural) loops.
Definition: LoopInfo.h:182
llvm::HexagonTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: HexagonTargetTransformInfo.cpp:87
llvm::BasicTTIImplBase< HexagonTTIImpl >::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
Compute a cost of the given call instruction.
Definition: BasicTTIImpl.h:2155
llvm::InstructionCost::getMax
static InstructionCost getMax()
Definition: InstructionCost.h:72
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TypeSize
Definition: TypeSize.h:435
Casting.h
EmitLookupTables
static cl::opt< bool > EmitLookupTables("hexagon-emit-lookup-tables", cl::init(true), cl::Hidden, cl::desc("Control lookup table emission on Hexagon target"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1275
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::HexagonTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S)
Definition: HexagonTargetTransformInfo.cpp:169
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:965
llvm::BasicTTIImplBase< HexagonTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1282
Instructions.h
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:151
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:965
User.h
DataType
llvm::HexagonTTIImpl::getPrefetchDistance
unsigned getPrefetchDistance() const override
— Vector TTI end —
Definition: HexagonTargetTransformInfo.cpp:364
llvm::BasicTTIImplBase< HexagonTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1435
llvm::HexagonTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:159
UnrollLoop.h
llvm::HexagonTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Bias LSR towards creating post-increment opportunities.
Definition: HexagonTargetTransformInfo.cpp:100
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::HexagonTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:268
TargetTransformInfo.h
llvm::Optional::value
constexpr const T & value() const &
Definition: Optional.h:281
llvm::HexagonTTIImpl::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: HexagonTargetTransformInfo.cpp:368
llvm::HexagonTTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: HexagonTargetTransformInfo.cpp:141
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::cl::desc
Definition: CommandLine.h:413
llvm::HexagonTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:356
llvm::HexagonTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool vector) const
— Vector TTI begin —
Definition: HexagonTargetTransformInfo.cpp:107
llvm::HexagonTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: HexagonTargetTransformInfo.cpp:81
LoopPeel.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:219
FloatFactor
static const unsigned FloatFactor
Definition: HexagonTargetTransformInfo.cpp:48
llvm::HexagonTTIImpl::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: HexagonTargetTransformInfo.cpp:135
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164