LLVM  14.0.0git
HexagonTargetTransformInfo.cpp
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1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
16 #include "HexagonSubtarget.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "hexagontti"
30 
31 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
32  cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
33 
34 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
35  cl::init(true), cl::Hidden,
36  cl::desc("Control lookup table emission on Hexagon target"));
37 
38 static cl::opt<bool> HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true),
39  cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
40 
41 // Constant "cost factor" to make floating point operations more expensive
42 // in terms of vectorization cost. This isn't the best way, but it should
43 // do. Ultimately, the cost should use cycles.
44 static const unsigned FloatFactor = 4;
45 
46 bool HexagonTTIImpl::useHVX() const {
47  return ST.useHVXOps() && HexagonAutoHVX;
48 }
49 
50 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
51  if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
52  return VTy->getNumElements();
53  assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
54  "Expecting scalar type");
55  return 1;
56 }
57 
59 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
60  // Return fast hardware support as every input < 64 bits will be promoted
61  // to 64 bits.
63 }
64 
65 // The Hexagon target can unroll loops with run-time trip counts.
69  UP.Runtime = UP.Partial = true;
70 }
71 
75  // Only try to peel innermost loops with small runtime trip counts.
76  if (L && L->isInnermost() && canPeel(L) &&
77  SE.getSmallConstantTripCount(L) == 0 &&
78  SE.getSmallConstantMaxTripCount(L) > 0 &&
79  SE.getSmallConstantMaxTripCount(L) <= 5) {
80  PP.PeelCount = 2;
81  }
82 }
83 
86  ScalarEvolution *SE) const {
87  return TTI::AMK_PostIndexed;
88 }
89 
90 /// --- Vector TTI begin ---
91 
92 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
93  if (Vector)
94  return useHVX() ? 32 : 0;
95  return 32;
96 }
97 
99  return useHVX() ? 2 : 1;
100 }
101 
102 TypeSize
104  switch (K) {
106  return TypeSize::getFixed(32);
110  return TypeSize::getScalable(0);
111  }
112 
113  llvm_unreachable("Unsupported register kind");
114 }
115 
117  return useHVX() ? ST.getVectorLength()*8 : 32;
118 }
119 
121  bool IsScalable) const {
122  assert(!IsScalable && "Scalable VFs are not supported for Hexagon");
123  return ElementCount::getFixed((8 * ST.getVectorLength()) / ElemWidth);
124 }
125 
127  VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) {
128  return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
129 }
130 
133  ArrayRef<Type *> Tys) {
135 }
136 
138  ArrayRef<Type *> Tys,
140  return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind);
141 }
142 
146  if (ICA.getID() == Intrinsic::bswap) {
147  std::pair<InstructionCost, MVT> LT =
149  return LT.first + 2;
150  }
152 }
153 
155  ScalarEvolution *SE,
156  const SCEV *S) {
157  return 0;
158 }
159 
161  MaybeAlign Alignment,
162  unsigned AddressSpace,
164  const Instruction *I) {
165  assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
166  // TODO: Handle other cost kinds.
168  return 1;
169 
170  if (Opcode == Instruction::Store)
171  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
172  CostKind, I);
173 
174  if (Src->isVectorTy()) {
175  VectorType *VecTy = cast<VectorType>(Src);
176  unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
177  if (useHVX() && ST.isTypeForHVX(VecTy)) {
178  unsigned RegWidth =
180  .getFixedSize();
181  assert(RegWidth && "Non-zero vector register width expected");
182  // Cost of HVX loads.
183  if (VecWidth % RegWidth == 0)
184  return VecWidth / RegWidth;
185  // Cost of constructing HVX vector from scalar loads
186  const Align RegAlign(RegWidth / 8);
187  if (!Alignment || *Alignment > RegAlign)
188  Alignment = RegAlign;
189  assert(Alignment);
190  unsigned AlignWidth = 8 * Alignment->value();
191  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
192  return 3 * NumLoads;
193  }
194 
195  // Non-HVX vectors.
196  // Add extra cost for floating point types.
197  unsigned Cost =
198  VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
199 
200  // At this point unspecified alignment is considered as Align(1).
201  const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
202  unsigned AlignWidth = 8 * BoundAlignment.value();
203  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
204  if (Alignment == Align(4) || Alignment == Align(8))
205  return Cost * NumLoads;
206  // Loads of less than 32 bits will need extra inserts to compose a vector.
207  assert(BoundAlignment <= Align(8));
208  unsigned LogA = Log2(BoundAlignment);
209  return (3 - LogA) * Cost * NumLoads;
210  }
211 
212  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
213  CostKind, I);
214 }
215 
218  Align Alignment, unsigned AddressSpace,
220  return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
221  CostKind);
222 }
223 
225  ArrayRef<int> Mask, int Index,
226  Type *SubTp) {
227  return 1;
228 }
229 
231  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
232  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
233  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
234  Alignment, CostKind, I);
235 }
236 
238  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
239  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
240  bool UseMaskForCond, bool UseMaskForGaps) {
241  if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
242  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
243  Alignment, AddressSpace,
244  CostKind,
245  UseMaskForCond, UseMaskForGaps);
246  return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
247  CostKind);
248 }
249 
251  Type *CondTy,
252  CmpInst::Predicate VecPred,
254  const Instruction *I) {
255  if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) {
256  std::pair<InstructionCost, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy);
257  if (Opcode == Instruction::FCmp)
258  return LT.first + FloatFactor * getTypeNumElements(ValTy);
259  }
260  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
261 }
262 
264  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
265  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
266  TTI::OperandValueProperties Opd1PropInfo,
268  const Instruction *CxtI) {
269  // TODO: Handle more cost kinds.
271  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
272  Opd2Info, Opd1PropInfo,
273  Opd2PropInfo, Args, CxtI);
274 
275  if (Ty->isVectorTy()) {
276  std::pair<InstructionCost, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty);
277  if (LT.second.isFloatingPoint())
278  return LT.first + FloatFactor * getTypeNumElements(Ty);
279  }
280  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
281  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
282 }
283 
285  Type *SrcTy,
288  const Instruction *I) {
289  if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
290  unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
291  unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
292 
293  std::pair<InstructionCost, MVT> SrcLT =
294  TLI.getTypeLegalizationCost(DL, SrcTy);
295  std::pair<InstructionCost, MVT> DstLT =
296  TLI.getTypeLegalizationCost(DL, DstTy);
297  InstructionCost Cost =
298  std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
299  // TODO: Allow non-throughput costs that aren't binary.
301  return Cost == 0 ? 0 : 1;
302  return Cost;
303  }
304  return 1;
305 }
306 
308  unsigned Index) {
309  Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
310  : Val;
311  if (Opcode == Instruction::InsertElement) {
312  // Need two rotations for non-zero index.
313  unsigned Cost = (Index != 0) ? 2 : 0;
314  if (ElemTy->isIntegerTy(32))
315  return Cost;
316  // If it's not a 32-bit value, there will need to be an extract.
317  return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
318  }
319 
320  if (Opcode == Instruction::ExtractElement)
321  return 2;
322 
323  return 1;
324 }
325 
326 bool HexagonTTIImpl::isLegalMaskedStore(Type *DataType, Align /*Alignment*/) {
327  return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
328 }
329 
330 bool HexagonTTIImpl::isLegalMaskedLoad(Type *DataType, Align /*Alignment*/) {
331  return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
332 }
333 
334 /// --- Vector TTI end ---
335 
337  return ST.getL1PrefetchDistance();
338 }
339 
341  return ST.getL1CacheLineSize();
342 }
343 
347  auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
348  if (!CI->isIntegerCast())
349  return false;
350  // Only extensions from an integer type shorter than 32-bit to i32
351  // can be folded into the load.
352  const DataLayout &DL = getDataLayout();
353  unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
354  unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
355  if (DBW != 32 || SBW >= DBW)
356  return false;
357 
358  const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
359  // Technically, this code could allow multiple uses of the load, and
360  // check if all the uses are the same extension operation, but this
361  // should be sufficient for most cases.
362  return LI && LI->hasOneUse();
363  };
364 
365  if (const CastInst *CI = dyn_cast<const CastInst>(U))
366  if (isCastFoldedIntoLoad(CI))
369 }
370 
372  return EmitLookupTables;
373 }
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:588
llvm::HexagonTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: HexagonTargetTransformInfo.cpp:116
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:274
ValueTypes.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:38
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:481
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::BasicTTIImplBase< HexagonTTIImpl >::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: BasicTTIImpl.h:707
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:435
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:588
llvm::TargetTransformInfoImplCRTPBase< HexagonTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:924
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:655
llvm::TargetTransformInfo::AMK_PostIndexed
@ AMK_PostIndexed
Definition: TargetTransformInfo.h:637
HexagonSubtarget.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: BasicTTIImpl.h:750
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:150
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:900
llvm::Type::isFPOrFPVectorTy
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
Definition: Type.h:189
llvm::HexagonTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:160
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
HexagonTargetTransformInfo.h
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:477
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::HexagonTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: HexagonTargetTransformInfo.cpp:217
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:531
llvm::MaybeAlign::valueOrOne
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:134
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1838
llvm::VectorType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:421
llvm::HexagonTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: HexagonTargetTransformInfo.cpp:98
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:165
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::canPeel
bool canPeel(Loop *L)
Definition: LoopPeel.cpp:89
llvm::HexagonTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: HexagonTargetTransformInfo.cpp:230
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:651
CommandLine.h
HexagonMaskedVMem
static cl::opt< bool > HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true), cl::Hidden, cl::desc("Enable masked loads/stores for HVX"))
llvm::HexagonTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: HexagonTargetTransformInfo.cpp:307
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::HexagonTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: HexagonTargetTransformInfo.cpp:59
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:852
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1055
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Definition: User.h:44
llvm::HexagonTTIImpl::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:344
InstrTypes.h
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:237
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:204
llvm::Instruction
Definition: Instruction.h:45
llvm::HexagonTTIImpl::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Definition: HexagonTargetTransformInfo.cpp:371
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:900
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This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
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AddressSpace
Definition: NVPTXBaseInfo.h:21
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InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1060
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static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
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Kind
Definition: LLToken.h:18
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Definition: TargetTransformInfo.h:118
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
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unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:655
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bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:201
llvm::ScalarEvolution::getSmallConstantTripCount
unsigned getSmallConstantTripCount(const Loop *L)
Returns the exact trip count of the loop if we can compute it, and the result is a small constant.
Definition: ScalarEvolution.cpp:7167
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:388
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::ScalarEvolution::getSmallConstantMaxTripCount
unsigned getSmallConstantMaxTripCount(const Loop *L)
Returns the upper bound of the loop trip count as a normal unsigned value.
Definition: ScalarEvolution.cpp:7183
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Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:424
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:879
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initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, int Index, Type *SubTp)
Definition: HexagonTargetTransformInfo.cpp:224
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::BasicTTIImplBase< HexagonTTIImpl >::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: BasicTTIImpl.h:1176
llvm::HexagonTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:326
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:871
llvm::HexagonTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:284
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::HexagonTTIImpl::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:137
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::TargetTransformInfo::PeelingPreferences::PeelCount
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Definition: TargetTransformInfo.h:535
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::HexagonTTIImpl::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Definition: HexagonTargetTransformInfo.cpp:132
llvm::BasicTTIImplBase< HexagonTTIImpl >::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract)
Estimate the overhead of scalarizing an instruction.
Definition: BasicTTIImpl.h:671
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::HexagonTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: HexagonTargetTransformInfo.cpp:103
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:430
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:635
HexagonAutoHVX
static cl::opt< bool > HexagonAutoHVX("hexagon-autohvx", cl::init(false), cl::Hidden, cl::desc("Enable loop vectorizer for HVX"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:559
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::BasicTTIImplBase< HexagonTTIImpl >::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Compute a cost of the given call instruction.
Definition: BasicTTIImpl.h:1989
llvm::LoopBase::isInnermost
bool isInnermost() const
Return true if the loop does not contain any (natural) loops.
Definition: LoopInfo.h:165
llvm::HexagonTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: HexagonTargetTransformInfo.cpp:72
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::TypeSize
Definition: TypeSize.h:417
Casting.h
EmitLookupTables
static cl::opt< bool > EmitLookupTables("hexagon-emit-lookup-tables", cl::init(true), cl::Hidden, cl::desc("Control lookup table emission on Hexagon target"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1160
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::HexagonTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S)
Definition: HexagonTargetTransformInfo.cpp:154
llvm::HexagonTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: HexagonTargetTransformInfo.cpp:237
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:900
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::BasicTTIImplBase< HexagonTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1167
Instructions.h
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:148
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:900
User.h
llvm::HexagonTTIImpl::getPrefetchDistance
unsigned getPrefetchDistance() const override
— Vector TTI end —
Definition: HexagonTargetTransformInfo.cpp:336
llvm::BasicTTIImplBase< HexagonTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1325
llvm::HexagonTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:144
UnrollLoop.h
llvm::HexagonTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Bias LSR towards creating post-increment opportunities.
Definition: HexagonTargetTransformInfo.cpp:85
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::HexagonTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:250
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1116
llvm::HexagonTTIImpl::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: HexagonTargetTransformInfo.cpp:340
llvm::HexagonTTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: HexagonTargetTransformInfo.cpp:126
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:414
llvm::HexagonTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:330
llvm::HexagonTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool vector) const
— Vector TTI begin —
Definition: HexagonTargetTransformInfo.cpp:92
llvm::HexagonTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: HexagonTargetTransformInfo.cpp:66
LoopPeel.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
FloatFactor
static const unsigned FloatFactor
Definition: HexagonTargetTransformInfo.cpp:44
llvm::HexagonTTIImpl::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: HexagonTargetTransformInfo.cpp:120
llvm::HexagonTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: HexagonTargetTransformInfo.cpp:263
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:128