15#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
16#define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
24class MachineInstrBuilder;
43 bool EmitDebugInstrRefs;
47 void EmitCopyFromReg(
SDNode *
Node,
unsigned ResNo,
bool IsClone,
53 bool IsClone,
bool IsCloned,
69 bool IsDebug,
bool IsClone,
bool IsCloned);
80 bool IsDebug,
bool IsClone,
bool IsCloned);
91 bool IsClone,
bool IsCloned);
103 bool IsClone,
bool IsCloned);
144 if (
Node->isMachineOpcode())
145 EmitMachineNode(
Node, IsClone, IsCloned, VRBaseMap);
147 EmitSpecialNode(
Node, IsClone, IsCloned, VRBaseMap);
162 void EmitMachineNode(
SDNode *
Node,
bool IsClone,
bool IsCloned,
164 void EmitSpecialNode(
SDNode *
Node,
bool IsClone,
bool IsCloned,
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define LLVM_LIBRARY_VISIBILITY
This file defines the DenseMap class.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
const char LLVMTargetMachineRef TM
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, Register > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
Describe properties that are true of each instruction in the target description file.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Holds the information from a dbg_label node through SDISel.
Holds the information from a dbg_value node through SDISel.
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
TargetInstrInfo - Interface to description of machine instruction set.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.