LLVM  14.0.0git
InstrEmitter.h
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1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This declares the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
17 
18 #include "llvm/ADT/DenseMap.h"
21 
22 namespace llvm {
23 
24 class MachineInstrBuilder;
25 class MCInstrDesc;
26 class SDDbgLabel;
27 class SDDbgValue;
28 class SDDbgOperand;
29 class TargetLowering;
30 class TargetMachine;
31 
33  MachineFunction *MF;
35  const TargetInstrInfo *TII;
36  const TargetRegisterInfo *TRI;
37  const TargetLowering *TLI;
38 
41 
42  /// Should we try to produce DBG_INSTR_REF instructions?
43  bool EmitDebugInstrRefs;
44 
45  /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
46  /// implicit physical register output.
47  void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
48  bool IsClone, bool IsCloned,
49  Register SrcReg,
50  DenseMap<SDValue, Register> &VRBaseMap);
51 
52  void CreateVirtualRegisters(SDNode *Node,
54  const MCInstrDesc &II,
55  bool IsClone, bool IsCloned,
56  DenseMap<SDValue, Register> &VRBaseMap);
57 
58  /// getVR - Return the virtual register corresponding to the specified result
59  /// of the specified node.
60  Register getVR(SDValue Op,
61  DenseMap<SDValue, Register> &VRBaseMap);
62 
63  /// AddRegisterOperand - Add the specified register as an operand to the
64  /// specified machine instr. Insert register copies if the register is
65  /// not in the required register class.
66  void AddRegisterOperand(MachineInstrBuilder &MIB,
67  SDValue Op,
68  unsigned IIOpNum,
69  const MCInstrDesc *II,
70  DenseMap<SDValue, Register> &VRBaseMap,
71  bool IsDebug, bool IsClone, bool IsCloned);
72 
73  /// AddOperand - Add the specified operand to the specified machine instr. II
74  /// specifies the instruction information for the node, and IIOpNum is the
75  /// operand number (in the II) that we are adding. IIOpNum and II are used for
76  /// assertions only.
77  void AddOperand(MachineInstrBuilder &MIB,
78  SDValue Op,
79  unsigned IIOpNum,
80  const MCInstrDesc *II,
81  DenseMap<SDValue, Register> &VRBaseMap,
82  bool IsDebug, bool IsClone, bool IsCloned);
83 
84  /// ConstrainForSubReg - Try to constrain VReg to a register class that
85  /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
86  /// Return the virtual register to use.
87  Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
88  bool isDivergent, const DebugLoc &DL);
89 
90  /// EmitSubregNode - Generate machine code for subreg nodes.
91  ///
92  void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
93  bool IsClone, bool IsCloned);
94 
95  /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
96  /// COPY_TO_REGCLASS is just a normal copy, except that the destination
97  /// register is constrained to be in a particular register class.
98  ///
99  void EmitCopyToRegClassNode(SDNode *Node,
100  DenseMap<SDValue, Register> &VRBaseMap);
101 
102  /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
103  ///
104  void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
105  bool IsClone, bool IsCloned);
106 public:
107  /// CountResults - The results of target nodes have register or immediate
108  /// operands first, then an optional chain, and optional flag operands
109  /// (which do not go into the machine instrs.)
110  static unsigned CountResults(SDNode *Node);
111 
112  void AddDbgValueLocationOps(MachineInstrBuilder &MIB,
113  const MCInstrDesc &DbgValDesc,
114  ArrayRef<SDDbgOperand> Locations,
115  DenseMap<SDValue, Register> &VRBaseMap);
116 
117  /// EmitDbgValue - Generate machine instruction for a dbg_value node.
118  ///
119  MachineInstr *EmitDbgValue(SDDbgValue *SD,
120  DenseMap<SDValue, Register> &VRBaseMap);
121 
122  /// Emit a dbg_value as a DBG_INSTR_REF. May produce DBG_VALUE $noreg instead
123  /// if there is no variable location; alternately a half-formed DBG_INSTR_REF
124  /// that refers to a virtual register and is corrected later in isel.
125  MachineInstr *EmitDbgInstrRef(SDDbgValue *SD,
126  DenseMap<SDValue, Register> &VRBaseMap);
127 
128  /// Emit a DBG_VALUE $noreg, indicating a variable has no location.
129  MachineInstr *EmitDbgNoLocation(SDDbgValue *SD);
130 
131  /// Emit a DBG_VALUE from the operands to SDDbgValue.
132  MachineInstr *EmitDbgValueFromSingleOp(SDDbgValue *SD,
133  DenseMap<SDValue, Register> &VRBaseMap);
134 
135  /// Generate machine instruction for a dbg_label node.
136  MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
137 
138  /// EmitNode - Generate machine code for a node and needed dependencies.
139  ///
140  void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
141  DenseMap<SDValue, Register> &VRBaseMap) {
142  if (Node->isMachineOpcode())
143  EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
144  else
145  EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
146  }
147 
148  /// getBlock - Return the current basic block.
150 
151  /// getInsertPos - Return the current insertion position.
153 
154  /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
155  /// at the given position in the given block.
157  MachineBasicBlock::iterator insertpos);
158 
159 private:
160  void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
161  DenseMap<SDValue, Register> &VRBaseMap);
162  void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
163  DenseMap<SDValue, Register> &VRBaseMap);
164 };
165 } // namespace llvm
166 
167 #endif
llvm::InstrEmitter
Definition: InstrEmitter.h:32
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:132
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
DenseMap.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::SDDbgLabel
Holds the information from a dbg_label node through SDISel.
Definition: SDNodeDbgValue.h:241
SelectionDAGNodes.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::InstrEmitter::getInsertPos
MachineBasicBlock::iterator getInsertPos()
getInsertPos - Return the current insertion position.
Definition: InstrEmitter.h:152
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::InstrEmitter::getBlock
MachineBasicBlock * getBlock()
getBlock - Return the current basic block.
Definition: InstrEmitter.h:149
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::DenseMap
Definition: DenseMap.h:714
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
LLVM_LIBRARY_VISIBILITY
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
Definition: Compiler.h:131
Node
Definition: ItaniumDemangle.h:235
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::InstrEmitter::EmitNode
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, DenseMap< SDValue, Register > &VRBaseMap)
EmitNode - Generate machine code for a node and needed dependencies.
Definition: InstrEmitter.h:140
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >