LLVM  14.0.0git
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/PseudoProbe.h"
30 #include "llvm/Support/Debug.h"
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "instr-emitter"
37 
38 /// MinRCSize - Smallest register class we allow when constraining virtual
39 /// registers. If satisfying all register class constraints would require
40 /// using a smaller register class, emit a COPY to a new virtual register
41 /// instead.
42 const unsigned MinRCSize = 4;
43 
44 /// CountResults - The results of target nodes have register or immediate
45 /// operands first, then an optional chain, and optional glue operands (which do
46 /// not go into the resulting MachineInstr).
48  unsigned N = Node->getNumValues();
49  while (N && Node->getValueType(N - 1) == MVT::Glue)
50  --N;
51  if (N && Node->getValueType(N - 1) == MVT::Other)
52  --N; // Skip over chain result.
53  return N;
54 }
55 
56 /// countOperands - The inputs to target nodes have any actual inputs first,
57 /// followed by an optional chain operand, then an optional glue operand.
58 /// Compute the number of actual operands that will go into the resulting
59 /// MachineInstr.
60 ///
61 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
62 /// the chain and glue. These operands may be implicit on the machine instr.
63 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
64  unsigned &NumImpUses) {
65  unsigned N = Node->getNumOperands();
66  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
67  --N;
68  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
69  --N; // Ignore chain if it exists.
70 
71  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
72  NumImpUses = N - NumExpUses;
73  for (unsigned I = N; I > NumExpUses; --I) {
74  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
75  continue;
76  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
77  if (Register::isPhysicalRegister(RN->getReg()))
78  continue;
79  NumImpUses = N - I;
80  break;
81  }
82 
83  return N;
84 }
85 
86 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
87 /// implicit physical register output.
88 void InstrEmitter::
89 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
90  Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
91  Register VRBase;
92  if (SrcReg.isVirtual()) {
93  // Just use the input register directly!
94  SDValue Op(Node, ResNo);
95  if (IsClone)
96  VRBaseMap.erase(Op);
97  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
98  (void)isNew; // Silence compiler warning.
99  assert(isNew && "Node emitted out of order - early");
100  return;
101  }
102 
103  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
104  // the CopyToReg'd destination register instead of creating a new vreg.
105  bool MatchReg = true;
106  const TargetRegisterClass *UseRC = nullptr;
107  MVT VT = Node->getSimpleValueType(ResNo);
108 
109  // Stick to the preferred register classes for legal types.
110  if (TLI->isTypeLegal(VT))
111  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
112 
113  if (!IsClone && !IsCloned)
114  for (SDNode *User : Node->uses()) {
115  bool Match = true;
116  if (User->getOpcode() == ISD::CopyToReg &&
117  User->getOperand(2).getNode() == Node &&
118  User->getOperand(2).getResNo() == ResNo) {
119  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
120  if (DestReg.isVirtual()) {
121  VRBase = DestReg;
122  Match = false;
123  } else if (DestReg != SrcReg)
124  Match = false;
125  } else {
126  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
127  SDValue Op = User->getOperand(i);
128  if (Op.getNode() != Node || Op.getResNo() != ResNo)
129  continue;
130  MVT VT = Node->getSimpleValueType(Op.getResNo());
131  if (VT == MVT::Other || VT == MVT::Glue)
132  continue;
133  Match = false;
134  if (User->isMachineOpcode()) {
135  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
136  const TargetRegisterClass *RC = nullptr;
137  if (i+II.getNumDefs() < II.getNumOperands()) {
138  RC = TRI->getAllocatableClass(
139  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
140  }
141  if (!UseRC)
142  UseRC = RC;
143  else if (RC) {
144  const TargetRegisterClass *ComRC =
145  TRI->getCommonSubClass(UseRC, RC);
146  // If multiple uses expect disjoint register classes, we emit
147  // copies in AddRegisterOperand.
148  if (ComRC)
149  UseRC = ComRC;
150  }
151  }
152  }
153  }
154  MatchReg &= Match;
155  if (VRBase)
156  break;
157  }
158 
159  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
160  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
161 
162  // Figure out the register class to create for the destreg.
163  if (VRBase) {
164  DstRC = MRI->getRegClass(VRBase);
165  } else if (UseRC) {
166  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
167  "Incompatible phys register def and uses!");
168  DstRC = UseRC;
169  } else
170  DstRC = SrcRC;
171 
172  // If all uses are reading from the src physical register and copying the
173  // register is either impossible or very expensive, then don't create a copy.
174  if (MatchReg && SrcRC->getCopyCost() < 0) {
175  VRBase = SrcReg;
176  } else {
177  // Create the reg, emit the copy.
178  VRBase = MRI->createVirtualRegister(DstRC);
179  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
180  VRBase).addReg(SrcReg);
181  }
182 
183  SDValue Op(Node, ResNo);
184  if (IsClone)
185  VRBaseMap.erase(Op);
186  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
187  (void)isNew; // Silence compiler warning.
188  assert(isNew && "Node emitted out of order - early");
189 }
190 
191 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
192  MachineInstrBuilder &MIB,
193  const MCInstrDesc &II,
194  bool IsClone, bool IsCloned,
195  DenseMap<SDValue, Register> &VRBaseMap) {
196  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
197  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
198 
199  unsigned NumResults = CountResults(Node);
200  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
201  II.isVariadic() && II.variadicOpsAreDefs();
202  unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
203  if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
204  NumVRegs = NumResults;
205  for (unsigned i = 0; i < NumVRegs; ++i) {
206  // If the specific node value is only used by a CopyToReg and the dest reg
207  // is a vreg in the same register class, use the CopyToReg'd destination
208  // register instead of creating a new vreg.
209  Register VRBase;
210  const TargetRegisterClass *RC =
211  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
212  // Always let the value type influence the used register class. The
213  // constraints on the instruction may be too lax to represent the value
214  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
215  // the 32-bit float super-class (X86::FR32).
216  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
217  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
218  Node->getSimpleValueType(i),
219  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
220  if (RC)
221  VTRC = TRI->getCommonSubClass(RC, VTRC);
222  if (VTRC)
223  RC = VTRC;
224  }
225 
226  if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
227  // Optional def must be a physical register.
228  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
229  assert(VRBase.isPhysical());
230  MIB.addReg(VRBase, RegState::Define);
231  }
232 
233  if (!VRBase && !IsClone && !IsCloned)
234  for (SDNode *User : Node->uses()) {
235  if (User->getOpcode() == ISD::CopyToReg &&
236  User->getOperand(2).getNode() == Node &&
237  User->getOperand(2).getResNo() == i) {
238  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
240  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
241  if (RegRC == RC) {
242  VRBase = Reg;
243  MIB.addReg(VRBase, RegState::Define);
244  break;
245  }
246  }
247  }
248  }
249 
250  // Create the result registers for this node and add the result regs to
251  // the machine instruction.
252  if (VRBase == 0) {
253  assert(RC && "Isn't a register operand!");
254  VRBase = MRI->createVirtualRegister(RC);
255  MIB.addReg(VRBase, RegState::Define);
256  }
257 
258  // If this def corresponds to a result of the SDNode insert the VRBase into
259  // the lookup map.
260  if (i < NumResults) {
261  SDValue Op(Node, i);
262  if (IsClone)
263  VRBaseMap.erase(Op);
264  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
265  (void)isNew; // Silence compiler warning.
266  assert(isNew && "Node emitted out of order - early");
267  }
268  }
269 }
270 
271 /// getVR - Return the virtual register corresponding to the specified result
272 /// of the specified node.
273 Register InstrEmitter::getVR(SDValue Op,
274  DenseMap<SDValue, Register> &VRBaseMap) {
275  if (Op.isMachineOpcode() &&
276  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
277  // Add an IMPLICIT_DEF instruction before every use.
278  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
279  // does not include operand register class info.
280  const TargetRegisterClass *RC = TLI->getRegClassFor(
281  Op.getSimpleValueType(), Op.getNode()->isDivergent());
282  Register VReg = MRI->createVirtualRegister(RC);
283  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
284  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
285  return VReg;
286  }
287 
289  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
290  return I->second;
291 }
292 
293 
294 /// AddRegisterOperand - Add the specified register as an operand to the
295 /// specified machine instr. Insert register copies if the register is
296 /// not in the required register class.
297 void
298 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
299  SDValue Op,
300  unsigned IIOpNum,
301  const MCInstrDesc *II,
302  DenseMap<SDValue, Register> &VRBaseMap,
303  bool IsDebug, bool IsClone, bool IsCloned) {
304  assert(Op.getValueType() != MVT::Other &&
305  Op.getValueType() != MVT::Glue &&
306  "Chain and glue operands should occur at end of operand list!");
307  // Get/emit the operand.
308  Register VReg = getVR(Op, VRBaseMap);
309 
310  const MCInstrDesc &MCID = MIB->getDesc();
311  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
312  MCID.OpInfo[IIOpNum].isOptionalDef();
313 
314  // If the instruction requires a register in a different class, create
315  // a new virtual register and copy the value into it, but first attempt to
316  // shrink VReg's register class within reason. For example, if VReg == GR32
317  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
318  if (II) {
319  const TargetRegisterClass *OpRC = nullptr;
320  if (IIOpNum < II->getNumOperands())
321  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
322 
323  if (OpRC) {
324  const TargetRegisterClass *ConstrainedRC
325  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
326  if (!ConstrainedRC) {
327  OpRC = TRI->getAllocatableClass(OpRC);
328  assert(OpRC && "Constraints cannot be fulfilled for allocation");
329  Register NewVReg = MRI->createVirtualRegister(OpRC);
330  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
331  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
332  VReg = NewVReg;
333  } else {
334  assert(ConstrainedRC->isAllocatable() &&
335  "Constraining an allocatable VReg produced an unallocatable class?");
336  }
337  }
338  }
339 
340  // If this value has only one use, that use is a kill. This is a
341  // conservative approximation. InstrEmitter does trivial coalescing
342  // with CopyFromReg nodes, so don't emit kill flags for them.
343  // Avoid kill flags on Schedule cloned nodes, since there will be
344  // multiple uses.
345  // Tied operands are never killed, so we need to check that. And that
346  // means we need to determine the index of the operand.
347  bool isKill = Op.hasOneUse() &&
348  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
349  !IsDebug &&
350  !(IsClone || IsCloned);
351  if (isKill) {
352  unsigned Idx = MIB->getNumOperands();
353  while (Idx > 0 &&
354  MIB->getOperand(Idx-1).isReg() &&
355  MIB->getOperand(Idx-1).isImplicit())
356  --Idx;
357  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
358  if (isTied)
359  isKill = false;
360  }
361 
362  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
363  getDebugRegState(IsDebug));
364 }
365 
366 /// AddOperand - Add the specified operand to the specified machine instr. II
367 /// specifies the instruction information for the node, and IIOpNum is the
368 /// operand number (in the II) that we are adding.
369 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
370  SDValue Op,
371  unsigned IIOpNum,
372  const MCInstrDesc *II,
373  DenseMap<SDValue, Register> &VRBaseMap,
374  bool IsDebug, bool IsClone, bool IsCloned) {
375  if (Op.isMachineOpcode()) {
376  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
377  IsDebug, IsClone, IsCloned);
378  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
379  MIB.addImm(C->getSExtValue());
380  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
381  MIB.addFPImm(F->getConstantFPValue());
382  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
383  Register VReg = R->getReg();
384  MVT OpVT = Op.getSimpleValueType();
385  const TargetRegisterClass *IIRC =
386  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
387  : nullptr;
388  const TargetRegisterClass *OpRC =
389  TLI->isTypeLegal(OpVT)
390  ? TLI->getRegClassFor(OpVT,
391  Op.getNode()->isDivergent() ||
392  (IIRC && TRI->isDivergentRegClass(IIRC)))
393  : nullptr;
394 
395  if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
396  Register NewVReg = MRI->createVirtualRegister(IIRC);
397  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
398  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
399  VReg = NewVReg;
400  }
401  // Turn additional physreg operands into implicit uses on non-variadic
402  // instructions. This is used by call and return instructions passing
403  // arguments in registers.
404  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
405  MIB.addReg(VReg, getImplRegState(Imp));
406  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
407  MIB.addRegMask(RM->getRegMask());
408  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
409  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
410  TGA->getTargetFlags());
411  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
412  MIB.addMBB(BBNode->getBasicBlock());
413  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
414  MIB.addFrameIndex(FI->getIndex());
415  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
416  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
417  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
418  int Offset = CP->getOffset();
419  Align Alignment = CP->getAlign();
420 
421  unsigned Idx;
423  if (CP->isMachineConstantPoolEntry())
424  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
425  else
426  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
427  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
428  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
429  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
430  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
431  MIB.addSym(SymNode->getMCSymbol());
432  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
433  MIB.addBlockAddress(BA->getBlockAddress(),
434  BA->getOffset(),
435  BA->getTargetFlags());
436  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
437  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
438  } else {
439  assert(Op.getValueType() != MVT::Other &&
440  Op.getValueType() != MVT::Glue &&
441  "Chain and glue operands should occur at end of operand list!");
442  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
443  IsDebug, IsClone, IsCloned);
444  }
445 }
446 
447 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
448  MVT VT, bool isDivergent, const DebugLoc &DL) {
449  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
450  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
451 
452  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
453  // within reason.
454  if (RC && RC != VRC)
455  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
456 
457  // VReg has been adjusted. It can be used with SubIdx operands now.
458  if (RC)
459  return VReg;
460 
461  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
462  // register instead.
463  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
464  assert(RC && "No legal register class for VT supports that SubIdx");
465  Register NewReg = MRI->createVirtualRegister(RC);
466  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
467  .addReg(VReg);
468  return NewReg;
469 }
470 
471 /// EmitSubregNode - Generate machine code for subreg nodes.
472 ///
473 void InstrEmitter::EmitSubregNode(SDNode *Node,
474  DenseMap<SDValue, Register> &VRBaseMap,
475  bool IsClone, bool IsCloned) {
476  Register VRBase;
477  unsigned Opc = Node->getMachineOpcode();
478 
479  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
480  // the CopyToReg'd destination register instead of creating a new vreg.
481  for (SDNode *User : Node->uses()) {
482  if (User->getOpcode() == ISD::CopyToReg &&
483  User->getOperand(2).getNode() == Node) {
484  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
485  if (DestReg.isVirtual()) {
486  VRBase = DestReg;
487  break;
488  }
489  }
490  }
491 
492  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
493  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
494  // constraints on the %dst register, COPY can target all legal register
495  // classes.
496  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
497  const TargetRegisterClass *TRC =
498  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
499 
500  Register Reg;
502  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
503  if (R && Register::isPhysicalRegister(R->getReg())) {
504  Reg = R->getReg();
505  DefMI = nullptr;
506  } else {
507  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
508  DefMI = MRI->getVRegDef(Reg);
509  }
510 
511  Register SrcReg, DstReg;
512  unsigned DefSubIdx;
513  if (DefMI &&
514  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
515  SubIdx == DefSubIdx &&
516  TRC == MRI->getRegClass(SrcReg)) {
517  // Optimize these:
518  // r1025 = s/zext r1024, 4
519  // r1026 = extract_subreg r1025, 4
520  // to a copy
521  // r1026 = copy r1024
522  VRBase = MRI->createVirtualRegister(TRC);
523  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
524  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
525  MRI->clearKillFlags(SrcReg);
526  } else {
527  // Reg may not support a SubIdx sub-register, and we may need to
528  // constrain its register class or issue a COPY to a compatible register
529  // class.
530  if (Reg.isVirtual())
531  Reg = ConstrainForSubReg(Reg, SubIdx,
532  Node->getOperand(0).getSimpleValueType(),
533  Node->isDivergent(), Node->getDebugLoc());
534  // Create the destreg if it is missing.
535  if (!VRBase)
536  VRBase = MRI->createVirtualRegister(TRC);
537 
538  // Create the extract_subreg machine instruction.
539  MachineInstrBuilder CopyMI =
540  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
541  TII->get(TargetOpcode::COPY), VRBase);
542  if (Reg.isVirtual())
543  CopyMI.addReg(Reg, 0, SubIdx);
544  else
545  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
546  }
547  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
548  Opc == TargetOpcode::SUBREG_TO_REG) {
549  SDValue N0 = Node->getOperand(0);
550  SDValue N1 = Node->getOperand(1);
551  SDValue N2 = Node->getOperand(2);
552  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
553 
554  // Figure out the register class to create for the destreg. It should be
555  // the largest legal register class supporting SubIdx sub-registers.
556  // RegisterCoalescer will constrain it further if it decides to eliminate
557  // the INSERT_SUBREG instruction.
558  //
559  // %dst = INSERT_SUBREG %src, %sub, SubIdx
560  //
561  // is lowered by TwoAddressInstructionPass to:
562  //
563  // %dst = COPY %src
564  // %dst:SubIdx = COPY %sub
565  //
566  // There is no constraint on the %src register class.
567  //
568  const TargetRegisterClass *SRC =
569  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
570  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
571  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
572 
573  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
574  VRBase = MRI->createVirtualRegister(SRC);
575 
576  // Create the insert_subreg or subreg_to_reg machine instruction.
577  MachineInstrBuilder MIB =
578  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
579 
580  // If creating a subreg_to_reg, then the first input operand
581  // is an implicit value immediate, otherwise it's a register
582  if (Opc == TargetOpcode::SUBREG_TO_REG) {
583  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
584  MIB.addImm(SD->getZExtValue());
585  } else
586  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
587  IsClone, IsCloned);
588  // Add the subregister being inserted
589  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
590  IsClone, IsCloned);
591  MIB.addImm(SubIdx);
592  MBB->insert(InsertPos, MIB);
593  } else
594  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
595 
596  SDValue Op(Node, 0);
597  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
598  (void)isNew; // Silence compiler warning.
599  assert(isNew && "Node emitted out of order - early");
600 }
601 
602 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
603 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
604 /// register is constrained to be in a particular register class.
605 ///
606 void
607 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
608  DenseMap<SDValue, Register> &VRBaseMap) {
609  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
610 
611  // Create the new VReg in the destination class and emit a copy.
612  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
613  const TargetRegisterClass *DstRC =
614  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
615  Register NewVReg = MRI->createVirtualRegister(DstRC);
616  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
617  NewVReg).addReg(VReg);
618 
619  SDValue Op(Node, 0);
620  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
621  (void)isNew; // Silence compiler warning.
622  assert(isNew && "Node emitted out of order - early");
623 }
624 
625 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
626 ///
627 void InstrEmitter::EmitRegSequence(SDNode *Node,
628  DenseMap<SDValue, Register> &VRBaseMap,
629  bool IsClone, bool IsCloned) {
630  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
631  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
632  Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
633  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
634  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
635  unsigned NumOps = Node->getNumOperands();
636  // If the input pattern has a chain, then the root of the corresponding
637  // output pattern will get a chain as well. This can happen to be a
638  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
639  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
640  --NumOps; // Ignore chain if it exists.
641 
642  assert((NumOps & 1) == 1 &&
643  "REG_SEQUENCE must have an odd number of operands!");
644  for (unsigned i = 1; i != NumOps; ++i) {
645  SDValue Op = Node->getOperand(i);
646  if ((i & 1) == 0) {
647  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
648  // Skip physical registers as they don't have a vreg to get and we'll
649  // insert copies for them in TwoAddressInstructionPass anyway.
650  if (!R || !Register::isPhysicalRegister(R->getReg())) {
651  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
652  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
653  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
654  const TargetRegisterClass *SRC =
655  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
656  if (SRC && SRC != RC) {
657  MRI->setRegClass(NewVReg, SRC);
658  RC = SRC;
659  }
660  }
661  }
662  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
663  IsClone, IsCloned);
664  }
665 
666  MBB->insert(InsertPos, MIB);
667  SDValue Op(Node, 0);
668  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
669  (void)isNew; // Silence compiler warning.
670  assert(isNew && "Node emitted out of order - early");
671 }
672 
673 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
674 ///
675 MachineInstr *
677  DenseMap<SDValue, Register> &VRBaseMap) {
678  MDNode *Var = SD->getVariable();
679  MDNode *Expr = SD->getExpression();
680  DebugLoc DL = SD->getDebugLoc();
681  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
682  "Expected inlined-at fields to agree");
683 
684  SD->setIsEmitted();
685 
686  ArrayRef<SDDbgOperand> LocationOps = SD->getLocationOps();
687  assert(!LocationOps.empty() && "dbg_value with no location operands?");
688 
689  if (SD->isInvalidated())
690  return EmitDbgNoLocation(SD);
691 
692  // Emit variadic dbg_value nodes as DBG_VALUE_LIST.
693  if (SD->isVariadic()) {
694  // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
695  const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
696  // Build the DBG_VALUE_LIST instruction base.
697  auto MIB = BuildMI(*MF, DL, DbgValDesc);
698  MIB.addMetadata(Var);
699  MIB.addMetadata(Expr);
700  AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps, VRBaseMap);
701  return &*MIB;
702  }
703 
704  // Attempt to produce a DBG_INSTR_REF if we've been asked to.
705  // We currently exclude the possibility of instruction references for
706  // variadic nodes; if at some point we enable them, this should be moved
707  // above the variadic block.
708  if (EmitDebugInstrRefs)
709  if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
710  return InstrRef;
711 
712  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
713 }
714 
716  MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
717  ArrayRef<SDDbgOperand> LocationOps,
718  DenseMap<SDValue, Register> &VRBaseMap) {
719  for (const SDDbgOperand &Op : LocationOps) {
720  switch (Op.getKind()) {
722  MIB.addFrameIndex(Op.getFrameIx());
723  break;
724  case SDDbgOperand::VREG:
725  MIB.addReg(Op.getVReg());
726  break;
727  case SDDbgOperand::SDNODE: {
728  SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
729  // It's possible we replaced this SDNode with other(s) and therefore
730  // didn't generate code for it. It's better to catch these cases where
731  // they happen and transfer the debug info, but trying to guarantee that
732  // in all cases would be very fragile; this is a safeguard for any
733  // that were missed.
734  if (VRBaseMap.count(V) == 0)
735  MIB.addReg(0U); // undef
736  else
737  AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
738  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
739  } break;
740  case SDDbgOperand::CONST: {
741  const Value *V = Op.getConst();
742  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
743  if (CI->getBitWidth() > 64)
744  MIB.addCImm(CI);
745  else
746  MIB.addImm(CI->getSExtValue());
747  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
748  MIB.addFPImm(CF);
749  } else if (isa<ConstantPointerNull>(V)) {
750  // Note: This assumes that all nullptr constants are zero-valued.
751  MIB.addImm(0);
752  } else {
753  // Could be an Undef. In any case insert an Undef so we can see what we
754  // dropped.
755  MIB.addReg(0U);
756  }
757  } break;
758  }
759  }
760 }
761 
762 MachineInstr *
764  DenseMap<SDValue, Register> &VRBaseMap) {
765  assert(!SD->isVariadic());
766  SDDbgOperand DbgOperand = SD->getLocationOps()[0];
767  MDNode *Var = SD->getVariable();
768  DIExpression *Expr = (DIExpression*)SD->getExpression();
769  DebugLoc DL = SD->getDebugLoc();
770  const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
771 
772  // Handle variable locations that don't actually depend on the instructions
773  // in the program: constants and stack locations.
774  if (DbgOperand.getKind() == SDDbgOperand::FRAMEIX ||
775  DbgOperand.getKind() == SDDbgOperand::CONST)
776  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
777 
778  // Immediately fold any indirectness from the LLVM-IR intrinsic into the
779  // expression:
780  if (SD->isIndirect()) {
781  std::vector<uint64_t> Elts = {dwarf::DW_OP_deref};
782  Expr = DIExpression::append(Expr, Elts);
783  }
784 
785  // It may not be immediately possible to identify the MachineInstr that
786  // defines a VReg, it can depend for example on the order blocks are
787  // emitted in. When this happens, or when further analysis is needed later,
788  // produce an instruction like this:
789  //
790  // DBG_INSTR_REF %0:gr64, 0, !123, !456
791  //
792  // i.e., point the instruction at the vreg, and patch it up later in
793  // MachineFunction::finalizeDebugInstrRefs.
794  auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
795  auto MIB = BuildMI(*MF, DL, RefII);
796  MIB.addReg(VReg);
797  MIB.addImm(0);
798  MIB.addMetadata(Var);
799  MIB.addMetadata(Expr);
800  return MIB;
801  };
802 
803  // Try to find both the defined register and the instruction defining it.
804  MachineInstr *DefMI = nullptr;
805  unsigned VReg;
806 
807  if (DbgOperand.getKind() == SDDbgOperand::VREG) {
808  VReg = DbgOperand.getVReg();
809 
810  // No definition means that block hasn't been emitted yet. Leave a vreg
811  // reference to be fixed later.
812  if (!MRI->hasOneDef(VReg))
813  return EmitHalfDoneInstrRef(VReg);
814 
815  DefMI = &*MRI->def_instr_begin(VReg);
816  } else {
817  assert(DbgOperand.getKind() == SDDbgOperand::SDNODE);
818  // Look up the corresponding VReg for the given SDNode, if any.
819  SDNode *Node = DbgOperand.getSDNode();
820  SDValue Op = SDValue(Node, DbgOperand.getResNo());
822  // No VReg -> produce a DBG_VALUE $noreg instead.
823  if (I==VRBaseMap.end())
824  return EmitDbgNoLocation(SD);
825 
826  // Try to pick out a defining instruction at this point.
827  VReg = getVR(Op, VRBaseMap);
828 
829  // Again, if there's no instruction defining the VReg right now, fix it up
830  // later.
831  if (!MRI->hasOneDef(VReg))
832  return EmitHalfDoneInstrRef(VReg);
833 
834  DefMI = &*MRI->def_instr_begin(VReg);
835  }
836 
837  // Avoid copy like instructions: they don't define values, only move them.
838  // Leave a virtual-register reference until it can be fixed up later, to find
839  // the underlying value definition.
840  if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
841  return EmitHalfDoneInstrRef(VReg);
842 
843  auto MIB = BuildMI(*MF, DL, RefII);
844 
845  // Find the operand number which defines the specified VReg.
846  unsigned OperandIdx = 0;
847  for (const auto &MO : DefMI->operands()) {
848  if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
849  break;
850  ++OperandIdx;
851  }
852  assert(OperandIdx < DefMI->getNumOperands());
853 
854  // Make the DBG_INSTR_REF refer to that instruction, and that operand.
855  unsigned InstrNum = DefMI->getDebugInstrNum();
856  MIB.addImm(InstrNum);
857  MIB.addImm(OperandIdx);
858  MIB.addMetadata(Var);
859  MIB.addMetadata(Expr);
860  return &*MIB;
861 }
862 
864  // An invalidated SDNode must generate an undef DBG_VALUE: although the
865  // original value is no longer computed, earlier DBG_VALUEs live ranges
866  // must not leak into later code.
867  MDNode *Var = SD->getVariable();
868  MDNode *Expr = SD->getExpression();
869  DebugLoc DL = SD->getDebugLoc();
870  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
871  MIB.addReg(0U);
872  MIB.addReg(0U);
873  MIB.addMetadata(Var);
874  MIB.addMetadata(Expr);
875  return &*MIB;
876 }
877 
878 MachineInstr *
880  DenseMap<SDValue, Register> &VRBaseMap) {
881  MDNode *Var = SD->getVariable();
882  DIExpression *Expr = SD->getExpression();
883  DebugLoc DL = SD->getDebugLoc();
884  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
885 
886  assert(SD->getLocationOps().size() == 1 &&
887  "Non variadic dbg_value should have only one location op");
888 
889  // See about constant-folding the expression.
890  // Copy the location operand in case we replace it.
891  SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
892  if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
893  const Value *V = LocationOps[0].getConst();
894  if (auto *C = dyn_cast<ConstantInt>(V)) {
895  std::tie(Expr, C) = Expr->constantFold(C);
896  LocationOps[0] = SDDbgOperand::fromConst(C);
897  }
898  }
899 
900  // Emit non-variadic dbg_value nodes as DBG_VALUE.
901  // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
902  auto MIB = BuildMI(*MF, DL, II);
903  AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
904 
905  if (SD->isIndirect())
906  MIB.addImm(0U);
907  else
908  MIB.addReg(0U);
909 
910  return MIB.addMetadata(Var).addMetadata(Expr);
911 }
912 
913 MachineInstr *
915  MDNode *Label = SD->getLabel();
916  DebugLoc DL = SD->getDebugLoc();
917  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
918  "Expected inlined-at fields to agree");
919 
920  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
921  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
922  MIB.addMetadata(Label);
923 
924  return &*MIB;
925 }
926 
927 /// EmitMachineNode - Generate machine code for a target-specific node and
928 /// needed dependencies.
929 ///
930 void InstrEmitter::
931 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
932  DenseMap<SDValue, Register> &VRBaseMap) {
933  unsigned Opc = Node->getMachineOpcode();
934 
935  // Handle subreg insert/extract specially
936  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
937  Opc == TargetOpcode::INSERT_SUBREG ||
938  Opc == TargetOpcode::SUBREG_TO_REG) {
939  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
940  return;
941  }
942 
943  // Handle COPY_TO_REGCLASS specially.
944  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
945  EmitCopyToRegClassNode(Node, VRBaseMap);
946  return;
947  }
948 
949  // Handle REG_SEQUENCE specially.
950  if (Opc == TargetOpcode::REG_SEQUENCE) {
951  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
952  return;
953  }
954 
955  if (Opc == TargetOpcode::IMPLICIT_DEF)
956  // We want a unique VR for each IMPLICIT_DEF use.
957  return;
958 
959  const MCInstrDesc &II = TII->get(Opc);
960  unsigned NumResults = CountResults(Node);
961  unsigned NumDefs = II.getNumDefs();
962  const MCPhysReg *ScratchRegs = nullptr;
963 
964  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
965  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
966  // Stackmaps do not have arguments and do not preserve their calling
967  // convention. However, to simplify runtime support, they clobber the same
968  // scratch registers as AnyRegCC.
969  unsigned CC = CallingConv::AnyReg;
970  if (Opc == TargetOpcode::PATCHPOINT) {
971  CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
972  NumDefs = NumResults;
973  }
974  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
975  } else if (Opc == TargetOpcode::STATEPOINT) {
976  NumDefs = NumResults;
977  }
978 
979  unsigned NumImpUses = 0;
980  unsigned NodeOperands =
981  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
982  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
983  II.isVariadic() && II.variadicOpsAreDefs();
984  bool HasPhysRegOuts = NumResults > NumDefs &&
985  II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
986 #ifndef NDEBUG
987  unsigned NumMIOperands = NodeOperands + NumResults;
988  if (II.isVariadic())
989  assert(NumMIOperands >= II.getNumOperands() &&
990  "Too few operands for a variadic node!");
991  else
992  assert(NumMIOperands >= II.getNumOperands() &&
993  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
994  NumImpUses &&
995  "#operands for dag node doesn't match .td file!");
996 #endif
997 
998  // Create the new machine instruction.
999  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
1000 
1001  // Add result register values for things that are defined by this
1002  // instruction.
1003  if (NumResults) {
1004  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1005 
1006  // Transfer any IR flags from the SDNode to the MachineInstr
1007  MachineInstr *MI = MIB.getInstr();
1008  const SDNodeFlags Flags = Node->getFlags();
1009  if (Flags.hasNoSignedZeros())
1010  MI->setFlag(MachineInstr::MIFlag::FmNsz);
1011 
1012  if (Flags.hasAllowReciprocal())
1013  MI->setFlag(MachineInstr::MIFlag::FmArcp);
1014 
1015  if (Flags.hasNoNaNs())
1016  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1017 
1018  if (Flags.hasNoInfs())
1019  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1020 
1021  if (Flags.hasAllowContract())
1022  MI->setFlag(MachineInstr::MIFlag::FmContract);
1023 
1024  if (Flags.hasApproximateFuncs())
1025  MI->setFlag(MachineInstr::MIFlag::FmAfn);
1026 
1027  if (Flags.hasAllowReassociation())
1028  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1029 
1030  if (Flags.hasNoUnsignedWrap())
1031  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1032 
1033  if (Flags.hasNoSignedWrap())
1034  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1035 
1036  if (Flags.hasExact())
1037  MI->setFlag(MachineInstr::MIFlag::IsExact);
1038 
1039  if (Flags.hasNoFPExcept())
1040  MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1041  }
1042 
1043  // Emit all of the actual operands of this instruction, adding them to the
1044  // instruction as appropriate.
1045  bool HasOptPRefs = NumDefs > NumResults;
1046  assert((!HasOptPRefs || !HasPhysRegOuts) &&
1047  "Unable to cope with optional defs and phys regs defs!");
1048  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1049  for (unsigned i = NumSkip; i != NodeOperands; ++i)
1050  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1051  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1052 
1053  // Add scratch registers as implicit def and early clobber
1054  if (ScratchRegs)
1055  for (unsigned i = 0; ScratchRegs[i]; ++i)
1056  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1058 
1059  // Set the memory reference descriptions of this instruction now that it is
1060  // part of the function.
1061  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1062 
1063  // Insert the instruction into position in the block. This needs to
1064  // happen before any custom inserter hook is called so that the
1065  // hook knows where in the block to insert the replacement code.
1066  MBB->insert(InsertPos, MIB);
1067 
1068  // The MachineInstr may also define physregs instead of virtregs. These
1069  // physreg values can reach other instructions in different ways:
1070  //
1071  // 1. When there is a use of a Node value beyond the explicitly defined
1072  // virtual registers, we emit a CopyFromReg for one of the implicitly
1073  // defined physregs. This only happens when HasPhysRegOuts is true.
1074  //
1075  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1076  //
1077  // 3. A glued instruction may implicitly use a physreg.
1078  //
1079  // 4. A glued instruction may use a RegisterSDNode operand.
1080  //
1081  // Collect all the used physreg defs, and make sure that any unused physreg
1082  // defs are marked as dead.
1083  SmallVector<Register, 8> UsedRegs;
1084 
1085  // Additional results must be physical register defs.
1086  if (HasPhysRegOuts) {
1087  for (unsigned i = NumDefs; i < NumResults; ++i) {
1088  Register Reg = II.getImplicitDefs()[i - NumDefs];
1089  if (!Node->hasAnyUseOfValue(i))
1090  continue;
1091  // This implicitly defined physreg has a use.
1092  UsedRegs.push_back(Reg);
1093  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
1094  }
1095  }
1096 
1097  // Scan the glue chain for any used physregs.
1098  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1099  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1100  if (F->getOpcode() == ISD::CopyFromReg) {
1101  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1102  continue;
1103  } else if (F->getOpcode() == ISD::CopyToReg) {
1104  // Skip CopyToReg nodes that are internal to the glue chain.
1105  continue;
1106  }
1107  // Collect declared implicit uses.
1108  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1109  UsedRegs.append(MCID.getImplicitUses(),
1110  MCID.getImplicitUses() + MCID.getNumImplicitUses());
1111  // In addition to declared implicit uses, we must also check for
1112  // direct RegisterSDNode operands.
1113  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1114  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1115  Register Reg = R->getReg();
1116  if (Reg.isPhysical())
1117  UsedRegs.push_back(Reg);
1118  }
1119  }
1120  }
1121 
1122  // Finally mark unused registers as dead.
1123  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
1124  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1125 
1126  // STATEPOINT is too 'dynamic' to have meaningful machine description.
1127  // We have to manually tie operands.
1128  if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1129  assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1130  MachineInstr *MI = MIB;
1131  unsigned Def = 0;
1133  assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1134  unsigned Use = (unsigned)First;
1135  while (Def < NumDefs) {
1136  if (MI->getOperand(Use).isReg())
1137  MI->tieOperands(Def++, Use);
1139  }
1140  }
1141 
1142  // Run post-isel target hook to adjust this instruction if needed.
1143  if (II.hasPostISelHook())
1144  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1145 }
1146 
1147 /// EmitSpecialNode - Generate machine code for a target-independent node and
1148 /// needed dependencies.
1149 void InstrEmitter::
1150 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1151  DenseMap<SDValue, Register> &VRBaseMap) {
1152  switch (Node->getOpcode()) {
1153  default:
1154 #ifndef NDEBUG
1155  Node->dump();
1156 #endif
1157  llvm_unreachable("This target-independent node should have been selected!");
1158  case ISD::EntryToken:
1159  llvm_unreachable("EntryToken should have been excluded from the schedule!");
1160  case ISD::MERGE_VALUES:
1161  case ISD::TokenFactor: // fall thru
1162  break;
1163  case ISD::CopyToReg: {
1164  Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1165  SDValue SrcVal = Node->getOperand(2);
1166  if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1167  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1168  // Instead building a COPY to that vreg destination, build an
1169  // IMPLICIT_DEF instruction instead.
1170  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1171  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1172  break;
1173  }
1174  Register SrcReg;
1175  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1176  SrcReg = R->getReg();
1177  else
1178  SrcReg = getVR(SrcVal, VRBaseMap);
1179 
1180  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1181  break;
1182 
1183  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1184  DestReg).addReg(SrcReg);
1185  break;
1186  }
1187  case ISD::CopyFromReg: {
1188  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1189  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1190  break;
1191  }
1192  case ISD::EH_LABEL:
1193  case ISD::ANNOTATION_LABEL: {
1194  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1197  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1198  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1199  TII->get(Opc)).addSym(S);
1200  break;
1201  }
1202 
1203  case ISD::LIFETIME_START:
1204  case ISD::LIFETIME_END: {
1205  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1208  auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1209  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1210  .addFrameIndex(FI->getIndex());
1211  break;
1212  }
1213 
1214  case ISD::PSEUDO_PROBE: {
1215  unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1216  auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1217  auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1218  auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1219 
1220  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1221  .addImm(Guid)
1222  .addImm(Index)
1223  .addImm((uint8_t)PseudoProbeType::Block)
1224  .addImm(Attr);
1225  break;
1226  }
1227 
1228  case ISD::INLINEASM:
1229  case ISD::INLINEASM_BR: {
1230  unsigned NumOps = Node->getNumOperands();
1231  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1232  --NumOps; // Ignore the glue operand.
1233 
1234  // Create the inline asm machine instruction.
1235  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1238  MachineInstrBuilder MIB =
1239  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1240 
1241  // Add the asm string as an external symbol operand.
1242  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1243  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1244  MIB.addExternalSymbol(AsmStr);
1245 
1246  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1247  // bits.
1248  int64_t ExtraInfo =
1249  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1250  getZExtValue();
1251  MIB.addImm(ExtraInfo);
1252 
1253  // Remember to operand index of the group flags.
1254  SmallVector<unsigned, 8> GroupIdx;
1255 
1256  // Remember registers that are part of early-clobber defs.
1257  SmallVector<unsigned, 8> ECRegs;
1258 
1259  // Add all of the operand registers to the instruction.
1260  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1261  unsigned Flags =
1262  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1263  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1264 
1265  GroupIdx.push_back(MIB->getNumOperands());
1266  MIB.addImm(Flags);
1267  ++i; // Skip the ID value.
1268 
1269  switch (InlineAsm::getKind(Flags)) {
1270  default: llvm_unreachable("Bad flags!");
1272  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1273  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1274  // FIXME: Add dead flags for physical and virtual registers defined.
1275  // For now, mark physical register defs as implicit to help fast
1276  // regalloc. This makes inline asm look a lot like calls.
1277  MIB.addReg(Reg,
1280  }
1281  break;
1284  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1285  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1286  MIB.addReg(Reg,
1289  ECRegs.push_back(Reg);
1290  }
1291  break;
1292  case InlineAsm::Kind_RegUse: // Use of register.
1293  case InlineAsm::Kind_Imm: // Immediate.
1294  case InlineAsm::Kind_Mem: // Addressing mode.
1295  // The addressing mode has been selected, just add all of the
1296  // operands to the machine instruction.
1297  for (unsigned j = 0; j != NumVals; ++j, ++i)
1298  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1299  /*IsDebug=*/false, IsClone, IsCloned);
1300 
1301  // Manually set isTied bits.
1303  unsigned DefGroup = 0;
1304  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1305  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1306  unsigned UseIdx = GroupIdx.back() + 1;
1307  for (unsigned j = 0; j != NumVals; ++j)
1308  MIB->tieOperands(DefIdx + j, UseIdx + j);
1309  }
1310  }
1311  break;
1312  }
1313  }
1314 
1315  // GCC inline assembly allows input operands to also be early-clobber
1316  // output operands (so long as the operand is written only after it's
1317  // used), but this does not match the semantics of our early-clobber flag.
1318  // If an early-clobber operand register is also an input operand register,
1319  // then remove the early-clobber flag.
1320  for (unsigned Reg : ECRegs) {
1321  if (MIB->readsRegister(Reg, TRI)) {
1322  MachineOperand *MO =
1323  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1324  assert(MO && "No def operand for clobbered register?");
1325  MO->setIsEarlyClobber(false);
1326  }
1327  }
1328 
1329  // Get the mdnode from the asm if it exists and add it to the instruction.
1330  SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1331  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1332  if (MD)
1333  MIB.addMetadata(MD);
1334 
1335  MBB->insert(InsertPos, MIB);
1336  break;
1337  }
1338  }
1339 }
1340 
1341 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1342 /// at the given position in the given block.
1344  MachineBasicBlock::iterator insertpos)
1345  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1346  TII(MF->getSubtarget().getInstrInfo()),
1347  TRI(MF->getSubtarget().getRegisterInfo()),
1348  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1349  InsertPos(insertpos) {
1350  EmitDebugInstrRefs = MF->useDebugInstrRef();
1351 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::SDNodeFlags::hasAllowReciprocal
bool hasAllowReciprocal() const
Definition: SelectionDAGNodes.h:429
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::SDDbgValue::getExpression
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Definition: SDNodeDbgValue.h:182
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:132
llvm::SDDbgOperand::fromConst
static SDDbgOperand fromConst(const Value *Const)
Definition: SDNodeDbgValue.h:79
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1555
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2114
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2025
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2353
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Definition: MachineFunction.cpp:1466
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::TargetLowering::getScratchRegisters
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: TargetLowering.h:4123
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1178
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:117
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1177
llvm::LLVMTargetMachine::usesPhysRegsForValues
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
Definition: TargetMachine.h:481
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:397
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
llvm::SDNodeFlags::hasNoNaNs
bool hasNoNaNs() const
Definition: SelectionDAGNodes.h:426
llvm::MachineFunction::useDebugInstrRef
bool useDebugInstrRef() const
Returns true if the function's variable locations should be tracked with instruction referencing.
Definition: MachineFunction.cpp:1230
llvm::SDDbgOperand::getResNo
unsigned getResNo() const
Returns the ResNo for a register ref.
Definition: SDNodeDbgValue.h:47
ErrorHandling.h
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:988
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:302
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:113
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::DenseMapIterator
Definition: DenseMap.h:56
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:345
llvm::InstrEmitter::InstrEmitter
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
Definition: InstrEmitter.cpp:1343
TargetInstrInfo.h
llvm::InlineAsm::Op_AsmString
@ Op_AsmString
Definition: InlineAsm.h:212
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1010
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
llvm::InstrEmitter::CountResults
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Definition: InstrEmitter.cpp:47
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::SDDbgOperand
Holds the information for a single machine location through SDISel; either an SDNode,...
Definition: SDNodeDbgValue.h:30
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:233
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
SDNodeDbgValue.h
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2148
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::SDDbgValue::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:214
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:207
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:508
MachineRegisterInfo.h
llvm::InstrEmitter::AddDbgValueLocationOps
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
Definition: InstrEmitter.cpp:715
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:980
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1197
llvm::SDDbgOperand::getVReg
unsigned getVReg() const
Returns the Virtual Register for a VReg.
Definition: SDNodeDbgValue.h:65
llvm::TargetLowering::AdjustInstrPostInstrSelection
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: SelectionDAGISel.cpp:305
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::InstrEmitter::EmitDbgNoLocation
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Definition: InstrEmitter.cpp:863
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2190
TargetMachine.h
llvm::SDDbgLabel
Holds the information from a dbg_label node through SDISel.
Definition: SDNodeDbgValue.h:241
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:238
countOperands
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
Definition: InstrEmitter.cpp:63
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:648
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:562
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1820
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SDDbgValue::isIndirect
bool isIndirect() const
Returns whether this is an indirect value.
Definition: SDNodeDbgValue.h:209
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:581
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:235
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:584
llvm::SDDbgOperand::VREG
@ VREG
Value is a virtual register.
Definition: SDNodeDbgValue.h:36
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1743
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::InlineAsm::Op_ExtraInfo
@ Op_ExtraInfo
Definition: InlineAsm.h:214
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::InlineAsm::Op_MDNode
@ Op_MDNode
Definition: InlineAsm.h:213
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RegisterMaskSDNode
Definition: SelectionDAGNodes.h:2130
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:252
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:111
llvm::DIExpression::append
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
Definition: DebugInfoMetadata.cpp:1400
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:429
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:1124
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SDDbgLabel::getLabel
MDNode * getLabel() const
Returns the MDNode pointer for the label.
Definition: SDNodeDbgValue.h:251
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1604
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:912
llvm::InstrEmitter::EmitDbgLabel
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
Definition: InstrEmitter.cpp:914
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
DebugInfo.h
llvm::SDDbgOperand::getKind
Kind getKind() const
Definition: SDNodeDbgValue.h:38
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MachineConstantPool.h
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:236
llvm::BasicBlockSDNode
Definition: SelectionDAGNodes.h:1925
llvm::SDDbgValue::isInvalidated
bool isInvalidated() const
Definition: SDNodeDbgValue.h:224
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:673
llvm::SDNodeFlags::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Definition: SelectionDAGNodes.h:423
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1570
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:215
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:444
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:237
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1363
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:994
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:478
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1841
DataLayout.h
llvm::InstrEmitter::EmitDbgInstrRef
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
Definition: InstrEmitter.cpp:763
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::SDNodeFlags::hasApproximateFuncs
bool hasApproximateFuncs() const
Definition: SelectionDAGNodes.h:431
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:523
llvm::SDValue::getMachineOpcode
unsigned getMachineOpcode() const
Definition: SelectionDAGNodes.h:1152
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::SDDbgOperand::getSDNode
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
Definition: SDNodeDbgValue.h:41
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:293
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:870
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
InstrEmitter.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SDNodeFlags::hasNoInfs
bool hasNoInfs() const
Definition: SelectionDAGNodes.h:427
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:409
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
j
return j(j<< 16)
llvm::SDDbgValue::isVariadic
bool isVariadic() const
Definition: SDNodeDbgValue.h:211
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::SDDbgLabel::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:254
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1717
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:520
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1299
llvm::SDNodeFlags::hasNoSignedWrap
bool hasNoSignedWrap() const
Definition: SelectionDAGNodes.h:424
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:83
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:260
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1311
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::TargetIndexSDNode
Completely target-dependent object reference.
Definition: SelectionDAGNodes.h:1904
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:551
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:983
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1500
llvm::SDDbgOperand::SDNODE
@ SDNODE
Value is the result of an expression.
Definition: SDNodeDbgValue.h:33
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:256
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
StackMaps.h
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
PseudoProbe.h
MinRCSize
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
Definition: InstrEmitter.cpp:42
llvm::SDNodeFlags
These are IR-level optimization flags that may be propagated to SDNodes.
Definition: SelectionDAGNodes.h:370
llvm::SDNodeFlags::hasExact
bool hasExact() const
Definition: SelectionDAGNodes.h:425
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:234
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::SDDbgValue::getVariable
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
Definition: SDNodeDbgValue.h:179
llvm::SDNodeFlags::hasAllowReassociation
bool hasAllowReassociation() const
Definition: SelectionDAGNodes.h:432
llvm::SDDbgValue::getLocationOps
ArrayRef< SDDbgOperand > getLocationOps() const
Definition: SDNodeDbgValue.h:184
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::PseudoProbeType::Block
@ Block
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:339
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::SDDbgOperand::FRAMEIX
@ FRAMEIX
Value is contents of a stack location.
Definition: SDNodeDbgValue.h:35
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:869
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::SDDbgOperand::CONST
@ CONST
Value is a constant.
Definition: SDNodeDbgValue.h:34
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:126
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::SDNodeFlags::hasNoFPExcept
bool hasNoFPExcept() const
Definition: SelectionDAGNodes.h:433
RN
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
Definition: README_P9.txt:262
llvm::InstrEmitter::EmitDbgValueFromSingleOp
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
Definition: InstrEmitter.cpp:879
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SDDbgValue::setIsEmitted
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Definition: SDNodeDbgValue.h:228
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::SDNodeFlags::hasNoSignedZeros
bool hasNoSignedZeros() const
Definition: SelectionDAGNodes.h:428
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1082
llvm::SDValue::isMachineOpcode
bool isMachineOpcode() const
Definition: SelectionDAGNodes.h:1148
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1452
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:505
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:559
llvm::SDNodeFlags::hasAllowContract
bool hasAllowContract() const
Definition: SelectionDAGNodes.h:430
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::InstrEmitter::EmitDbgValue
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
Definition: InstrEmitter.cpp:676