32#define DEBUG_TYPE "instr-emitter"
44 unsigned N = Node->getNumValues();
45 while (
N && Node->getValueType(
N - 1) == MVT::Glue)
47 if (
N && Node->getValueType(
N - 1) == MVT::Other)
60 unsigned &NumImpUses) {
61 unsigned N =
Node->getNumOperands();
62 while (
N &&
Node->getOperand(
N - 1).getValueType() == MVT::Glue)
64 if (
N &&
Node->getOperand(
N - 1).getValueType() == MVT::Other)
68 NumImpUses =
N - NumExpUses;
69 for (
unsigned I =
N;
I > NumExpUses; --
I) {
70 if (isa<RegisterMaskSDNode>(
Node->getOperand(
I - 1)))
73 if (RN->getReg().isPhysical())
84void InstrEmitter::EmitCopyFromReg(
SDNode *
Node,
unsigned ResNo,
bool IsClone,
93 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, SrcReg)).second;
95 assert(isNew &&
"Node emitted out of order - early");
101 bool MatchReg =
true;
103 MVT VT =
Node->getSimpleValueType(ResNo);
118 }
else if (DestReg != SrcReg)
123 if (
Op.getNode() !=
Node ||
Op.getResNo() != ResNo)
125 MVT VT =
Node->getSimpleValueType(
Op.getResNo());
126 if (VT == MVT::Other || VT == MVT::Glue)
129 if (
User->isMachineOpcode()) {
132 if (i +
II.getNumDefs() <
II.getNumOperands()) {
162 "Incompatible phys register def and uses!");
174 BuildMI(*MBB, InsertPos,
Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
181 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
183 assert(isNew &&
"Node emitted out of order - early");
186void InstrEmitter::CreateVirtualRegisters(
SDNode *
Node,
189 bool IsClone,
bool IsCloned,
191 assert(
Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
192 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
196 II.isVariadic() &&
II.variadicOpsAreDefs();
197 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults :
II.getNumDefs();
198 if (
Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
199 NumVRegs = NumResults;
200 for (
unsigned i = 0; i < NumVRegs; ++i) {
211 if (i < NumResults && TLI->isTypeLegal(
Node->getSimpleValueType(i))) {
213 Node->getSimpleValueType(i),
221 if (!
II.operands().empty() &&
II.operands()[i].isOptionalDef()) {
223 VRBase = cast<RegisterSDNode>(
Node->getOperand(i-NumResults))->getReg();
228 if (!VRBase && !IsClone && !IsCloned)
234 if (
Reg.isVirtual()) {
248 assert(RC &&
"Isn't a register operand!");
255 if (i < NumResults) {
259 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
261 assert(isNew &&
"Node emitted out of order - early");
270 if (
Op.isMachineOpcode() &&
271 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
276 Op.getSimpleValueType(),
Op.getNode()->isDivergent());
278 BuildMI(*MBB, InsertPos,
Op.getDebugLoc(),
279 TII->
get(TargetOpcode::IMPLICIT_DEF), VReg);
284 assert(
I != VRBaseMap.
end() &&
"Node emitted out of order - late");
289 if (
Op->isMachineOpcode()) {
290 switch (
Op->getMachineOpcode()) {
291 case TargetOpcode::CONVERGENCECTRL_ANCHOR:
292 case TargetOpcode::CONVERGENCECTRL_ENTRY:
293 case TargetOpcode::CONVERGENCECTRL_LOOP:
294 case TargetOpcode::CONVERGENCECTRL_GLUE:
303 switch (
Op->getOpcode()) {
322 bool IsDebug,
bool IsClone,
bool IsCloned) {
323 assert(
Op.getValueType() != MVT::Other &&
324 Op.getValueType() != MVT::Glue &&
325 "Chain and glue operands should occur at end of operand list!");
331 MCID.
operands()[IIOpNum].isOptionalDef();
339 if (IIOpNum < II->getNumOperands())
346 if (
Op.isMachineOpcode() &&
347 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
352 if (!ConstrainedRC) {
354 assert(OpRC &&
"Constraints cannot be fulfilled for allocation");
356 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
357 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
361 "Constraining an allocatable VReg produced an unallocatable class?");
379 !(IsClone || IsCloned);
403 bool IsDebug,
bool IsClone,
bool IsCloned) {
404 if (
Op.isMachineOpcode()) {
405 AddRegisterOperand(MIB,
Op, IIOpNum,
II, VRBaseMap,
406 IsDebug, IsClone, IsCloned);
413 MVT OpVT =
Op.getSimpleValueType();
420 Op.getNode()->isDivergent() ||
424 if (OpRC && IIRC && OpRC != IIRC && VReg.
isVirtual()) {
426 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
427 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
433 bool Imp =
II && (IIOpNum >=
II->getNumOperands() && !
II->isVariadic());
439 TGA->getTargetFlags());
441 MIB.
addMBB(BBNode->getBasicBlock());
448 Align Alignment =
CP->getAlign();
452 if (
CP->isMachineConstantPoolEntry())
459 }
else if (
auto *SymNode = dyn_cast<MCSymbolSDNode>(
Op)) {
460 MIB.
addSym(SymNode->getMCSymbol());
464 BA->getTargetFlags());
466 MIB.
addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
468 assert(
Op.getValueType() != MVT::Other &&
469 Op.getValueType() != MVT::Glue &&
470 "Chain and glue operands should occur at end of operand list!");
471 AddRegisterOperand(MIB,
Op, IIOpNum,
II, VRBaseMap,
472 IsDebug, IsClone, IsCloned);
493 assert(RC &&
"No legal register class for VT supports that SubIdx");
495 BuildMI(*MBB, InsertPos,
DL, TII->
get(TargetOpcode::COPY), NewReg)
502void InstrEmitter::EmitSubregNode(
SDNode *
Node,
504 bool IsClone,
bool IsCloned) {
506 unsigned Opc =
Node->getMachineOpcode();
521 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
525 unsigned SubIdx =
Node->getConstantOperandVal(1);
532 if (R &&
R->getReg().isPhysical()) {
536 Reg =
R ?
R->getReg() : getVR(
Node->getOperand(0), VRBaseMap);
544 SubIdx == DefSubIdx &&
553 TII->
get(TargetOpcode::COPY), VRBase).
addReg(SrcReg);
560 Reg = ConstrainForSubReg(Reg, SubIdx,
561 Node->getOperand(0).getSimpleValueType(),
562 Node->isDivergent(),
Node->getDebugLoc());
570 TII->
get(TargetOpcode::COPY), VRBase);
572 CopyMI.
addReg(Reg, 0, SubIdx);
576 }
else if (Opc == TargetOpcode::INSERT_SUBREG ||
577 Opc == TargetOpcode::SUBREG_TO_REG) {
600 assert(SRC &&
"No register class supports VT and SubIdx for INSERT_SUBREG");
611 if (Opc == TargetOpcode::SUBREG_TO_REG) {
615 AddOperand(MIB, N0, 0,
nullptr, VRBaseMap,
false,
618 AddOperand(MIB, N1, 0,
nullptr, VRBaseMap,
false,
621 MBB->
insert(InsertPos, MIB);
623 llvm_unreachable(
"Node is not insert_subreg, extract_subreg, or subreg_to_reg");
626 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
628 assert(isNew &&
"Node emitted out of order - early");
636InstrEmitter::EmitCopyToRegClassNode(
SDNode *
Node,
638 unsigned VReg = getVR(
Node->getOperand(0), VRBaseMap);
641 unsigned DstRCIdx =
Node->getConstantOperandVal(1);
645 BuildMI(*MBB, InsertPos,
Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
649 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
651 assert(isNew &&
"Node emitted out of order - early");
656void InstrEmitter::EmitRegSequence(
SDNode *
Node,
658 bool IsClone,
bool IsCloned) {
659 unsigned DstRCIdx =
Node->getConstantOperandVal(0);
664 unsigned NumOps =
Node->getNumOperands();
668 if (NumOps &&
Node->getOperand(NumOps-1).getValueType() == MVT::Other)
671 assert((NumOps & 1) == 1 &&
672 "REG_SEQUENCE must have an odd number of operands!");
673 for (
unsigned i = 1; i != NumOps; ++i) {
679 if (!R || !
R->getReg().isPhysical()) {
680 unsigned SubIdx =
Op->getAsZExtVal();
681 unsigned SubReg = getVR(
Node->getOperand(i-1), VRBaseMap);
685 if (SRC && SRC != RC) {
691 AddOperand(MIB,
Op, i+1, &
II, VRBaseMap,
false,
695 MBB->
insert(InsertPos, MIB);
697 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
699 assert(isNew &&
"Node emitted out of order - early");
709 ->isValidLocationForIntrinsic(
DL) &&
710 "Expected inlined-at fields to agree");
715 "dbg_value with no location operands?");
721 if (EmitDebugInstrRefs)
736 const Value *V =
Op.getConst();
737 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
738 if (CI->getBitWidth() > 64)
742 if (
const ConstantFP *CF = dyn_cast<ConstantFP>(V))
745 if (isa<ConstantPointerNull>(V))
760 switch (
Op.getKind()) {
774 if (VRBaseMap.
count(V) == 0)
777 AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
835 auto AddVRegOp = [&](
unsigned VReg) {
843 for (
unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
867 if (
I == VRBaseMap.
end())
871 VReg = getVR(
Op, VRBaseMap);
896 unsigned OperandIdx = 0;
898 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
902 assert(OperandIdx < DefMI->getNumOperands());
911 if (MOs.
size() != OpCount)
914 return BuildMI(*MF,
DL, RefII,
false, MOs, Var, Expr);
936 const MCInstrDesc &DbgValDesc = TII->
get(TargetOpcode::DBG_VALUE_LIST);
954 "Non variadic dbg_value should have only one location op");
960 const Value *V = LocationOps[0].getConst();
961 if (
auto *
C = dyn_cast<ConstantInt>(V)) {
984 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
985 "Expected inlined-at fields to agree");
998EmitMachineNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
1000 unsigned Opc = Node->getMachineOpcode();
1003 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1004 Opc == TargetOpcode::INSERT_SUBREG ||
1005 Opc == TargetOpcode::SUBREG_TO_REG) {
1006 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
1011 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
1012 EmitCopyToRegClassNode(
Node, VRBaseMap);
1017 if (Opc == TargetOpcode::REG_SEQUENCE) {
1018 EmitRegSequence(
Node, VRBaseMap, IsClone, IsCloned);
1022 if (Opc == TargetOpcode::IMPLICIT_DEF)
1028 unsigned NumDefs =
II.getNumDefs();
1032 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
1037 if (Opc == TargetOpcode::PATCHPOINT) {
1039 NumDefs = NumResults;
1042 }
else if (Opc == TargetOpcode::STATEPOINT) {
1043 NumDefs = NumResults;
1046 unsigned NumImpUses = 0;
1047 unsigned NodeOperands =
1050 II.isVariadic() &&
II.variadicOpsAreDefs();
1051 bool HasPhysRegOuts = NumResults > NumDefs && !
II.implicit_defs().empty() &&
1052 !HasVRegVariadicDefs;
1054 unsigned NumMIOperands = NodeOperands + NumResults;
1055 if (
II.isVariadic())
1056 assert(NumMIOperands >=
II.getNumOperands() &&
1057 "Too few operands for a variadic node!");
1059 assert(NumMIOperands >=
II.getNumOperands() &&
1061 II.getNumOperands() +
II.implicit_defs().size() + NumImpUses &&
1062 "#operands for dag node doesn't match .td file!");
1071 CreateVirtualRegisters(
Node, MIB,
II, IsClone, IsCloned, VRBaseMap);
1076 if (
Flags.hasNoSignedZeros())
1079 if (
Flags.hasAllowReciprocal())
1082 if (
Flags.hasNoNaNs())
1085 if (
Flags.hasNoInfs())
1088 if (
Flags.hasAllowContract())
1091 if (
Flags.hasApproximateFuncs())
1094 if (
Flags.hasAllowReassociation())
1097 if (
Flags.hasNoUnsignedWrap())
1100 if (
Flags.hasNoSignedWrap())
1103 if (
Flags.hasExact())
1106 if (
Flags.hasNoFPExcept())
1109 if (
Flags.hasUnpredictable())
1115 bool HasOptPRefs = NumDefs > NumResults;
1116 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1117 "Unable to cope with optional defs and phys regs defs!");
1118 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1119 for (
unsigned i = NumSkip; i != NodeOperands; ++i)
1120 AddOperand(MIB,
Node->getOperand(i), i-NumSkip+NumDefs, &
II,
1121 VRBaseMap,
false, IsClone, IsCloned);
1125 for (
unsigned i = 0; ScratchRegs[i]; ++i)
1139 MBB->
insert(InsertPos, MIB);
1159 if (HasPhysRegOuts) {
1160 for (
unsigned i = NumDefs; i < NumResults; ++i) {
1162 if (!
Node->hasAnyUseOfValue(i))
1166 EmitCopyFromReg(
Node, i, IsClone, Reg, VRBaseMap);
1171 if (
Node->getValueType(
Node->getNumValues()-1) == MVT::Glue) {
1172 for (
SDNode *
F =
Node->getGluedUser();
F;
F =
F->getGluedUser()) {
1174 UsedRegs.
push_back(cast<RegisterSDNode>(
F->getOperand(1))->getReg());
1188 if (
Reg.isPhysical())
1202 if (!UsedRegs.
empty() || !
II.implicit_defs().empty() ||
II.hasOptionalDef())
1207 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1208 assert(!HasPhysRegOuts &&
"STATEPOINT mishandled");
1212 assert(
First > 0 &&
"Statepoint has Defs but no GC ptr list");
1214 while (Def < NumDefs) {
1215 if (
MI->getOperand(
Use).isReg())
1216 MI->tieOperands(Def++,
Use);
1221 if (
SDNode *GluedNode =
Node->getGluedNode()) {
1223 if (GluedNode->getOpcode() ==
1224 ~(
unsigned)TargetOpcode::CONVERGENCECTRL_GLUE) {
1225 Register VReg = getVR(GluedNode->getOperand(0), VRBaseMap);
1233 if (
II.hasPostISelHook())
1240EmitSpecialNode(
SDNode *
Node,
bool IsClone,
bool IsCloned,
1242 switch (
Node->getOpcode()) {
1247 llvm_unreachable(
"This target-independent node should have been selected!");
1253 Register DestReg = cast<RegisterSDNode>(
Node->getOperand(1))->getReg();
1260 TII->
get(TargetOpcode::IMPLICIT_DEF), DestReg);
1265 SrcReg =
R->getReg();
1267 SrcReg = getVR(SrcVal, VRBaseMap);
1269 if (SrcReg == DestReg)
1272 BuildMI(*MBB, InsertPos,
Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
1277 unsigned SrcReg = cast<RegisterSDNode>(
Node->getOperand(1))->getReg();
1278 EmitCopyFromReg(
Node, 0, IsClone, SrcReg, VRBaseMap);
1284 ? TargetOpcode::EH_LABEL
1285 : TargetOpcode::ANNOTATION_LABEL;
1295 ? TargetOpcode::LIFETIME_START
1296 : TargetOpcode::LIFETIME_END;
1297 auto *FI = cast<FrameIndexSDNode>(
Node->getOperand(1));
1304 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1305 auto Guid = cast<PseudoProbeSDNode>(
Node)->getGuid();
1306 auto Index = cast<PseudoProbeSDNode>(
Node)->getIndex();
1307 auto Attr = cast<PseudoProbeSDNode>(
Node)->getAttributes();
1319 unsigned NumOps =
Node->getNumOperands();
1320 if (
Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1325 ? TargetOpcode::INLINEASM_BR
1326 : TargetOpcode::INLINEASM;
1332 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1350 unsigned Flags =
Node->getConstantOperandVal(i);
1352 const unsigned NumVals =
F.getNumOperandRegisters();
1358 switch (
F.getKind()) {
1360 for (
unsigned j = 0;
j != NumVals; ++
j, ++i) {
1370 for (
unsigned j = 0;
j != NumVals; ++
j, ++i) {
1382 for (
unsigned j = 0;
j != NumVals; ++
j, ++i)
1383 AddOperand(MIB,
Node->getOperand(i), 0,
nullptr, VRBaseMap,
1384 false, IsClone, IsCloned);
1387 if (
F.isRegUseKind()) {
1389 if (
F.isUseOperandTiedToDef(DefGroup)) {
1390 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1391 unsigned UseIdx = GroupIdx.
back() + 1;
1392 for (
unsigned j = 0;
j != NumVals; ++
j)
1398 for (
unsigned j = 0;
j != NumVals; ++
j, ++i) {
1400 AddOperand(MIB,
Op, 0,
nullptr, VRBaseMap,
1401 false, IsClone, IsCloned);
1404 if (
auto *TGA = dyn_cast<GlobalAddressSDNode>(
Op)) {
1427 for (
unsigned Reg : ECRegs) {
1431 assert(MO &&
"No def operand for clobbered register?");
1438 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1442 MBB->
insert(InsertPos, MIB);
1453 TII(MF->getSubtarget().getInstrInfo()),
1454 TRI(MF->getSubtarget().getRegisterInfo()),
1455 TLI(MF->getSubtarget().getTargetLowering()),
MBB(mbb),
1456 InsertPos(insertpos) {
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
static bool isConvergenceCtrlMachineOp(SDValue Op)
MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op)
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
DEMANGLE_DUMP_METHOD void dump() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
uint64_t getZExtValue() const
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
Base class for variables.
This class represents an Operation in the Expression.
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
MachineInstr * EmitDbgValueList(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
iterator_range< mop_iterator > operands()
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
void setIsEarlyClobber(bool Val=true)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
void setTargetFlags(unsigned F)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Holds the information from a dbg_label node through SDISel.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Holds the information for a single machine location through SDISel; either an SDNode,...
unsigned getResNo() const
Returns the ResNo for a register ref.
unsigned getVReg() const
Returns the Virtual Register for a VReg.
static SDDbgOperand fromConst(const Value *Const)
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
@ VREG
Value is a virtual register.
@ FRAMEIX
Value is contents of a stack location.
@ SDNODE
Value is the result of an expression.
@ CONST
Value is a constant.
Holds the information from a dbg_value node through SDISel.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
bool isInvalidated() const
ArrayRef< SDDbgOperand > getLocationOps() const
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
bool isIndirect() const
Returns whether this is an indirect value.
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Represents one node in the SelectionDAG.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isMachineOpcode() const
unsigned getMachineOpcode() const
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
MI-level Statepoint operands.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Completely target-dependent object reference.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Primary interface to the complete machine description for the target machine.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
unsigned getNumOperands() const
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ C
The default llvm calling convention, compatible with C.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ Define
Register definition.
@ EarlyClobber
Register definition happens before uses.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
unsigned getImplRegState(bool B)
unsigned getDebugRegState(bool B)
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
DWARFExpression::Operation Op
TODO: Might pack better if we changed this to a Struct of Arrays, since MachineOperand is width 32,...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
These are IR-level optimization flags that may be propagated to SDNodes.