LLVM  15.0.0git
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
22 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/PseudoProbe.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "instr-emitter"
33 
34 /// MinRCSize - Smallest register class we allow when constraining virtual
35 /// registers. If satisfying all register class constraints would require
36 /// using a smaller register class, emit a COPY to a new virtual register
37 /// instead.
38 const unsigned MinRCSize = 4;
39 
40 /// CountResults - The results of target nodes have register or immediate
41 /// operands first, then an optional chain, and optional glue operands (which do
42 /// not go into the resulting MachineInstr).
44  unsigned N = Node->getNumValues();
45  while (N && Node->getValueType(N - 1) == MVT::Glue)
46  --N;
47  if (N && Node->getValueType(N - 1) == MVT::Other)
48  --N; // Skip over chain result.
49  return N;
50 }
51 
52 /// countOperands - The inputs to target nodes have any actual inputs first,
53 /// followed by an optional chain operand, then an optional glue operand.
54 /// Compute the number of actual operands that will go into the resulting
55 /// MachineInstr.
56 ///
57 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58 /// the chain and glue. These operands may be implicit on the machine instr.
59 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60  unsigned &NumImpUses) {
61  unsigned N = Node->getNumOperands();
62  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63  --N;
64  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65  --N; // Ignore chain if it exists.
66 
67  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68  NumImpUses = N - NumExpUses;
69  for (unsigned I = N; I > NumExpUses; --I) {
70  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71  continue;
72  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73  if (Register::isPhysicalRegister(RN->getReg()))
74  continue;
75  NumImpUses = N - I;
76  break;
77  }
78 
79  return N;
80 }
81 
82 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83 /// implicit physical register output.
84 void InstrEmitter::
85 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
86  Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
87  Register VRBase;
88  if (SrcReg.isVirtual()) {
89  // Just use the input register directly!
90  SDValue Op(Node, ResNo);
91  if (IsClone)
92  VRBaseMap.erase(Op);
93  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
94  (void)isNew; // Silence compiler warning.
95  assert(isNew && "Node emitted out of order - early");
96  return;
97  }
98 
99  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
100  // the CopyToReg'd destination register instead of creating a new vreg.
101  bool MatchReg = true;
102  const TargetRegisterClass *UseRC = nullptr;
103  MVT VT = Node->getSimpleValueType(ResNo);
104 
105  // Stick to the preferred register classes for legal types.
106  if (TLI->isTypeLegal(VT))
107  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
108 
109  if (!IsClone && !IsCloned)
110  for (SDNode *User : Node->uses()) {
111  bool Match = true;
112  if (User->getOpcode() == ISD::CopyToReg &&
113  User->getOperand(2).getNode() == Node &&
114  User->getOperand(2).getResNo() == ResNo) {
115  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
116  if (DestReg.isVirtual()) {
117  VRBase = DestReg;
118  Match = false;
119  } else if (DestReg != SrcReg)
120  Match = false;
121  } else {
122  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
123  SDValue Op = User->getOperand(i);
124  if (Op.getNode() != Node || Op.getResNo() != ResNo)
125  continue;
126  MVT VT = Node->getSimpleValueType(Op.getResNo());
127  if (VT == MVT::Other || VT == MVT::Glue)
128  continue;
129  Match = false;
130  if (User->isMachineOpcode()) {
131  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
132  const TargetRegisterClass *RC = nullptr;
133  if (i+II.getNumDefs() < II.getNumOperands()) {
134  RC = TRI->getAllocatableClass(
135  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
136  }
137  if (!UseRC)
138  UseRC = RC;
139  else if (RC) {
140  const TargetRegisterClass *ComRC =
141  TRI->getCommonSubClass(UseRC, RC);
142  // If multiple uses expect disjoint register classes, we emit
143  // copies in AddRegisterOperand.
144  if (ComRC)
145  UseRC = ComRC;
146  }
147  }
148  }
149  }
150  MatchReg &= Match;
151  if (VRBase)
152  break;
153  }
154 
155  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
156  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
157 
158  // Figure out the register class to create for the destreg.
159  if (VRBase) {
160  DstRC = MRI->getRegClass(VRBase);
161  } else if (UseRC) {
162  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
163  "Incompatible phys register def and uses!");
164  DstRC = UseRC;
165  } else
166  DstRC = SrcRC;
167 
168  // If all uses are reading from the src physical register and copying the
169  // register is either impossible or very expensive, then don't create a copy.
170  if (MatchReg && SrcRC->getCopyCost() < 0) {
171  VRBase = SrcReg;
172  } else {
173  // Create the reg, emit the copy.
174  VRBase = MRI->createVirtualRegister(DstRC);
175  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
176  VRBase).addReg(SrcReg);
177  }
178 
179  SDValue Op(Node, ResNo);
180  if (IsClone)
181  VRBaseMap.erase(Op);
182  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
183  (void)isNew; // Silence compiler warning.
184  assert(isNew && "Node emitted out of order - early");
185 }
186 
187 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
188  MachineInstrBuilder &MIB,
189  const MCInstrDesc &II,
190  bool IsClone, bool IsCloned,
191  DenseMap<SDValue, Register> &VRBaseMap) {
192  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
193  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
194 
195  unsigned NumResults = CountResults(Node);
196  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
197  II.isVariadic() && II.variadicOpsAreDefs();
198  unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
199  if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
200  NumVRegs = NumResults;
201  for (unsigned i = 0; i < NumVRegs; ++i) {
202  // If the specific node value is only used by a CopyToReg and the dest reg
203  // is a vreg in the same register class, use the CopyToReg'd destination
204  // register instead of creating a new vreg.
205  Register VRBase;
206  const TargetRegisterClass *RC =
207  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
208  // Always let the value type influence the used register class. The
209  // constraints on the instruction may be too lax to represent the value
210  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
211  // the 32-bit float super-class (X86::FR32).
212  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
213  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
214  Node->getSimpleValueType(i),
215  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
216  if (RC)
217  VTRC = TRI->getCommonSubClass(RC, VTRC);
218  if (VTRC)
219  RC = VTRC;
220  }
221 
222  if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
223  // Optional def must be a physical register.
224  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
225  assert(VRBase.isPhysical());
226  MIB.addReg(VRBase, RegState::Define);
227  }
228 
229  if (!VRBase && !IsClone && !IsCloned)
230  for (SDNode *User : Node->uses()) {
231  if (User->getOpcode() == ISD::CopyToReg &&
232  User->getOperand(2).getNode() == Node &&
233  User->getOperand(2).getResNo() == i) {
234  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
236  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
237  if (RegRC == RC) {
238  VRBase = Reg;
239  MIB.addReg(VRBase, RegState::Define);
240  break;
241  }
242  }
243  }
244  }
245 
246  // Create the result registers for this node and add the result regs to
247  // the machine instruction.
248  if (VRBase == 0) {
249  assert(RC && "Isn't a register operand!");
250  VRBase = MRI->createVirtualRegister(RC);
251  MIB.addReg(VRBase, RegState::Define);
252  }
253 
254  // If this def corresponds to a result of the SDNode insert the VRBase into
255  // the lookup map.
256  if (i < NumResults) {
257  SDValue Op(Node, i);
258  if (IsClone)
259  VRBaseMap.erase(Op);
260  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
261  (void)isNew; // Silence compiler warning.
262  assert(isNew && "Node emitted out of order - early");
263  }
264  }
265 }
266 
267 /// getVR - Return the virtual register corresponding to the specified result
268 /// of the specified node.
269 Register InstrEmitter::getVR(SDValue Op,
270  DenseMap<SDValue, Register> &VRBaseMap) {
271  if (Op.isMachineOpcode() &&
272  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
273  // Add an IMPLICIT_DEF instruction before every use.
274  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
275  // does not include operand register class info.
276  const TargetRegisterClass *RC = TLI->getRegClassFor(
277  Op.getSimpleValueType(), Op.getNode()->isDivergent());
278  Register VReg = MRI->createVirtualRegister(RC);
279  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
280  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
281  return VReg;
282  }
283 
285  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
286  return I->second;
287 }
288 
289 
290 /// AddRegisterOperand - Add the specified register as an operand to the
291 /// specified machine instr. Insert register copies if the register is
292 /// not in the required register class.
293 void
294 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
295  SDValue Op,
296  unsigned IIOpNum,
297  const MCInstrDesc *II,
298  DenseMap<SDValue, Register> &VRBaseMap,
299  bool IsDebug, bool IsClone, bool IsCloned) {
300  assert(Op.getValueType() != MVT::Other &&
301  Op.getValueType() != MVT::Glue &&
302  "Chain and glue operands should occur at end of operand list!");
303  // Get/emit the operand.
304  Register VReg = getVR(Op, VRBaseMap);
305 
306  const MCInstrDesc &MCID = MIB->getDesc();
307  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
308  MCID.OpInfo[IIOpNum].isOptionalDef();
309 
310  // If the instruction requires a register in a different class, create
311  // a new virtual register and copy the value into it, but first attempt to
312  // shrink VReg's register class within reason. For example, if VReg == GR32
313  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
314  if (II) {
315  const TargetRegisterClass *OpRC = nullptr;
316  if (IIOpNum < II->getNumOperands())
317  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
318 
319  if (OpRC) {
320  const TargetRegisterClass *ConstrainedRC
321  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
322  if (!ConstrainedRC) {
323  OpRC = TRI->getAllocatableClass(OpRC);
324  assert(OpRC && "Constraints cannot be fulfilled for allocation");
325  Register NewVReg = MRI->createVirtualRegister(OpRC);
326  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
327  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
328  VReg = NewVReg;
329  } else {
330  assert(ConstrainedRC->isAllocatable() &&
331  "Constraining an allocatable VReg produced an unallocatable class?");
332  }
333  }
334  }
335 
336  // If this value has only one use, that use is a kill. This is a
337  // conservative approximation. InstrEmitter does trivial coalescing
338  // with CopyFromReg nodes, so don't emit kill flags for them.
339  // Avoid kill flags on Schedule cloned nodes, since there will be
340  // multiple uses.
341  // Tied operands are never killed, so we need to check that. And that
342  // means we need to determine the index of the operand.
343  bool isKill = Op.hasOneUse() &&
344  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
345  !IsDebug &&
346  !(IsClone || IsCloned);
347  if (isKill) {
348  unsigned Idx = MIB->getNumOperands();
349  while (Idx > 0 &&
350  MIB->getOperand(Idx-1).isReg() &&
351  MIB->getOperand(Idx-1).isImplicit())
352  --Idx;
353  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
354  if (isTied)
355  isKill = false;
356  }
357 
358  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
359  getDebugRegState(IsDebug));
360 }
361 
362 /// AddOperand - Add the specified operand to the specified machine instr. II
363 /// specifies the instruction information for the node, and IIOpNum is the
364 /// operand number (in the II) that we are adding.
365 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
366  SDValue Op,
367  unsigned IIOpNum,
368  const MCInstrDesc *II,
369  DenseMap<SDValue, Register> &VRBaseMap,
370  bool IsDebug, bool IsClone, bool IsCloned) {
371  if (Op.isMachineOpcode()) {
372  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
373  IsDebug, IsClone, IsCloned);
374  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
375  MIB.addImm(C->getSExtValue());
376  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
377  MIB.addFPImm(F->getConstantFPValue());
378  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
379  Register VReg = R->getReg();
380  MVT OpVT = Op.getSimpleValueType();
381  const TargetRegisterClass *IIRC =
382  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
383  : nullptr;
384  const TargetRegisterClass *OpRC =
385  TLI->isTypeLegal(OpVT)
386  ? TLI->getRegClassFor(OpVT,
387  Op.getNode()->isDivergent() ||
388  (IIRC && TRI->isDivergentRegClass(IIRC)))
389  : nullptr;
390 
391  if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
392  Register NewVReg = MRI->createVirtualRegister(IIRC);
393  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
394  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
395  VReg = NewVReg;
396  }
397  // Turn additional physreg operands into implicit uses on non-variadic
398  // instructions. This is used by call and return instructions passing
399  // arguments in registers.
400  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
401  MIB.addReg(VReg, getImplRegState(Imp));
402  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
403  MIB.addRegMask(RM->getRegMask());
404  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
405  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
406  TGA->getTargetFlags());
407  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
408  MIB.addMBB(BBNode->getBasicBlock());
409  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
410  MIB.addFrameIndex(FI->getIndex());
411  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
412  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
413  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
414  int Offset = CP->getOffset();
415  Align Alignment = CP->getAlign();
416 
417  unsigned Idx;
419  if (CP->isMachineConstantPoolEntry())
420  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
421  else
422  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
423  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
424  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
425  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
426  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
427  MIB.addSym(SymNode->getMCSymbol());
428  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
429  MIB.addBlockAddress(BA->getBlockAddress(),
430  BA->getOffset(),
431  BA->getTargetFlags());
432  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
433  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
434  } else {
435  assert(Op.getValueType() != MVT::Other &&
436  Op.getValueType() != MVT::Glue &&
437  "Chain and glue operands should occur at end of operand list!");
438  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
439  IsDebug, IsClone, IsCloned);
440  }
441 }
442 
443 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
444  MVT VT, bool isDivergent, const DebugLoc &DL) {
445  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
446  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
447 
448  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
449  // within reason.
450  if (RC && RC != VRC)
451  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
452 
453  // VReg has been adjusted. It can be used with SubIdx operands now.
454  if (RC)
455  return VReg;
456 
457  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
458  // register instead.
459  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
460  assert(RC && "No legal register class for VT supports that SubIdx");
461  Register NewReg = MRI->createVirtualRegister(RC);
462  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
463  .addReg(VReg);
464  return NewReg;
465 }
466 
467 /// EmitSubregNode - Generate machine code for subreg nodes.
468 ///
469 void InstrEmitter::EmitSubregNode(SDNode *Node,
470  DenseMap<SDValue, Register> &VRBaseMap,
471  bool IsClone, bool IsCloned) {
472  Register VRBase;
473  unsigned Opc = Node->getMachineOpcode();
474 
475  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
476  // the CopyToReg'd destination register instead of creating a new vreg.
477  for (SDNode *User : Node->uses()) {
478  if (User->getOpcode() == ISD::CopyToReg &&
479  User->getOperand(2).getNode() == Node) {
480  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
481  if (DestReg.isVirtual()) {
482  VRBase = DestReg;
483  break;
484  }
485  }
486  }
487 
488  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
489  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
490  // constraints on the %dst register, COPY can target all legal register
491  // classes.
492  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
493  const TargetRegisterClass *TRC =
494  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
495 
496  Register Reg;
498  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
499  if (R && Register::isPhysicalRegister(R->getReg())) {
500  Reg = R->getReg();
501  DefMI = nullptr;
502  } else {
503  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
504  DefMI = MRI->getVRegDef(Reg);
505  }
506 
507  Register SrcReg, DstReg;
508  unsigned DefSubIdx;
509  if (DefMI &&
510  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
511  SubIdx == DefSubIdx &&
512  TRC == MRI->getRegClass(SrcReg)) {
513  // Optimize these:
514  // r1025 = s/zext r1024, 4
515  // r1026 = extract_subreg r1025, 4
516  // to a copy
517  // r1026 = copy r1024
518  VRBase = MRI->createVirtualRegister(TRC);
519  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
520  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
521  MRI->clearKillFlags(SrcReg);
522  } else {
523  // Reg may not support a SubIdx sub-register, and we may need to
524  // constrain its register class or issue a COPY to a compatible register
525  // class.
526  if (Reg.isVirtual())
527  Reg = ConstrainForSubReg(Reg, SubIdx,
528  Node->getOperand(0).getSimpleValueType(),
529  Node->isDivergent(), Node->getDebugLoc());
530  // Create the destreg if it is missing.
531  if (!VRBase)
532  VRBase = MRI->createVirtualRegister(TRC);
533 
534  // Create the extract_subreg machine instruction.
535  MachineInstrBuilder CopyMI =
536  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
537  TII->get(TargetOpcode::COPY), VRBase);
538  if (Reg.isVirtual())
539  CopyMI.addReg(Reg, 0, SubIdx);
540  else
541  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
542  }
543  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
544  Opc == TargetOpcode::SUBREG_TO_REG) {
545  SDValue N0 = Node->getOperand(0);
546  SDValue N1 = Node->getOperand(1);
547  SDValue N2 = Node->getOperand(2);
548  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
549 
550  // Figure out the register class to create for the destreg. It should be
551  // the largest legal register class supporting SubIdx sub-registers.
552  // RegisterCoalescer will constrain it further if it decides to eliminate
553  // the INSERT_SUBREG instruction.
554  //
555  // %dst = INSERT_SUBREG %src, %sub, SubIdx
556  //
557  // is lowered by TwoAddressInstructionPass to:
558  //
559  // %dst = COPY %src
560  // %dst:SubIdx = COPY %sub
561  //
562  // There is no constraint on the %src register class.
563  //
564  const TargetRegisterClass *SRC =
565  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
566  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
567  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
568 
569  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
570  VRBase = MRI->createVirtualRegister(SRC);
571 
572  // Create the insert_subreg or subreg_to_reg machine instruction.
573  MachineInstrBuilder MIB =
574  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
575 
576  // If creating a subreg_to_reg, then the first input operand
577  // is an implicit value immediate, otherwise it's a register
578  if (Opc == TargetOpcode::SUBREG_TO_REG) {
579  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
580  MIB.addImm(SD->getZExtValue());
581  } else
582  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
583  IsClone, IsCloned);
584  // Add the subregister being inserted
585  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
586  IsClone, IsCloned);
587  MIB.addImm(SubIdx);
588  MBB->insert(InsertPos, MIB);
589  } else
590  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
591 
592  SDValue Op(Node, 0);
593  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
594  (void)isNew; // Silence compiler warning.
595  assert(isNew && "Node emitted out of order - early");
596 }
597 
598 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
599 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
600 /// register is constrained to be in a particular register class.
601 ///
602 void
603 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
604  DenseMap<SDValue, Register> &VRBaseMap) {
605  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
606 
607  // Create the new VReg in the destination class and emit a copy.
608  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
609  const TargetRegisterClass *DstRC =
610  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
611  Register NewVReg = MRI->createVirtualRegister(DstRC);
612  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
613  NewVReg).addReg(VReg);
614 
615  SDValue Op(Node, 0);
616  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
617  (void)isNew; // Silence compiler warning.
618  assert(isNew && "Node emitted out of order - early");
619 }
620 
621 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
622 ///
623 void InstrEmitter::EmitRegSequence(SDNode *Node,
624  DenseMap<SDValue, Register> &VRBaseMap,
625  bool IsClone, bool IsCloned) {
626  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
627  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
628  Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
629  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
630  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
631  unsigned NumOps = Node->getNumOperands();
632  // If the input pattern has a chain, then the root of the corresponding
633  // output pattern will get a chain as well. This can happen to be a
634  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
635  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
636  --NumOps; // Ignore chain if it exists.
637 
638  assert((NumOps & 1) == 1 &&
639  "REG_SEQUENCE must have an odd number of operands!");
640  for (unsigned i = 1; i != NumOps; ++i) {
641  SDValue Op = Node->getOperand(i);
642  if ((i & 1) == 0) {
643  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
644  // Skip physical registers as they don't have a vreg to get and we'll
645  // insert copies for them in TwoAddressInstructionPass anyway.
646  if (!R || !Register::isPhysicalRegister(R->getReg())) {
647  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
648  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
649  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
650  const TargetRegisterClass *SRC =
651  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
652  if (SRC && SRC != RC) {
653  MRI->setRegClass(NewVReg, SRC);
654  RC = SRC;
655  }
656  }
657  }
658  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
659  IsClone, IsCloned);
660  }
661 
662  MBB->insert(InsertPos, MIB);
663  SDValue Op(Node, 0);
664  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
665  (void)isNew; // Silence compiler warning.
666  assert(isNew && "Node emitted out of order - early");
667 }
668 
669 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
670 ///
671 MachineInstr *
673  DenseMap<SDValue, Register> &VRBaseMap) {
674  MDNode *Var = SD->getVariable();
675  MDNode *Expr = SD->getExpression();
676  DebugLoc DL = SD->getDebugLoc();
677  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
678  "Expected inlined-at fields to agree");
679 
680  SD->setIsEmitted();
681 
682  ArrayRef<SDDbgOperand> LocationOps = SD->getLocationOps();
683  assert(!LocationOps.empty() && "dbg_value with no location operands?");
684 
685  if (SD->isInvalidated())
686  return EmitDbgNoLocation(SD);
687 
688  // Emit variadic dbg_value nodes as DBG_VALUE_LIST.
689  if (SD->isVariadic()) {
690  // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
691  const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
692  // Build the DBG_VALUE_LIST instruction base.
693  auto MIB = BuildMI(*MF, DL, DbgValDesc);
694  MIB.addMetadata(Var);
695  MIB.addMetadata(Expr);
696  AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps, VRBaseMap);
697  return &*MIB;
698  }
699 
700  // Attempt to produce a DBG_INSTR_REF if we've been asked to.
701  // We currently exclude the possibility of instruction references for
702  // variadic nodes; if at some point we enable them, this should be moved
703  // above the variadic block.
704  if (EmitDebugInstrRefs)
705  if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
706  return InstrRef;
707 
708  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
709 }
710 
712  MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
713  ArrayRef<SDDbgOperand> LocationOps,
714  DenseMap<SDValue, Register> &VRBaseMap) {
715  for (const SDDbgOperand &Op : LocationOps) {
716  switch (Op.getKind()) {
718  MIB.addFrameIndex(Op.getFrameIx());
719  break;
720  case SDDbgOperand::VREG:
721  MIB.addReg(Op.getVReg());
722  break;
723  case SDDbgOperand::SDNODE: {
724  SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
725  // It's possible we replaced this SDNode with other(s) and therefore
726  // didn't generate code for it. It's better to catch these cases where
727  // they happen and transfer the debug info, but trying to guarantee that
728  // in all cases would be very fragile; this is a safeguard for any
729  // that were missed.
730  if (VRBaseMap.count(V) == 0)
731  MIB.addReg(0U); // undef
732  else
733  AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
734  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
735  } break;
736  case SDDbgOperand::CONST: {
737  const Value *V = Op.getConst();
738  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
739  if (CI->getBitWidth() > 64)
740  MIB.addCImm(CI);
741  else
742  MIB.addImm(CI->getSExtValue());
743  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
744  MIB.addFPImm(CF);
745  } else if (isa<ConstantPointerNull>(V)) {
746  // Note: This assumes that all nullptr constants are zero-valued.
747  MIB.addImm(0);
748  } else {
749  // Could be an Undef. In any case insert an Undef so we can see what we
750  // dropped.
751  MIB.addReg(0U);
752  }
753  } break;
754  }
755  }
756 }
757 
758 MachineInstr *
760  DenseMap<SDValue, Register> &VRBaseMap) {
761  assert(!SD->isVariadic());
762  SDDbgOperand DbgOperand = SD->getLocationOps()[0];
763  MDNode *Var = SD->getVariable();
764  DIExpression *Expr = (DIExpression*)SD->getExpression();
765  DebugLoc DL = SD->getDebugLoc();
766  const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
767 
768  // Handle variable locations that don't actually depend on the instructions
769  // in the program: constants and stack locations.
770  if (DbgOperand.getKind() == SDDbgOperand::FRAMEIX ||
771  DbgOperand.getKind() == SDDbgOperand::CONST)
772  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
773 
774  // Immediately fold any indirectness from the LLVM-IR intrinsic into the
775  // expression:
776  if (SD->isIndirect()) {
777  std::vector<uint64_t> Elts = {dwarf::DW_OP_deref};
778  Expr = DIExpression::append(Expr, Elts);
779  }
780 
781  // It may not be immediately possible to identify the MachineInstr that
782  // defines a VReg, it can depend for example on the order blocks are
783  // emitted in. When this happens, or when further analysis is needed later,
784  // produce an instruction like this:
785  //
786  // DBG_INSTR_REF %0:gr64, 0, !123, !456
787  //
788  // i.e., point the instruction at the vreg, and patch it up later in
789  // MachineFunction::finalizeDebugInstrRefs.
790  auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
791  auto MIB = BuildMI(*MF, DL, RefII);
792  MIB.addReg(VReg);
793  MIB.addImm(0);
794  MIB.addMetadata(Var);
795  MIB.addMetadata(Expr);
796  return MIB;
797  };
798 
799  // Try to find both the defined register and the instruction defining it.
800  MachineInstr *DefMI = nullptr;
801  unsigned VReg;
802 
803  if (DbgOperand.getKind() == SDDbgOperand::VREG) {
804  VReg = DbgOperand.getVReg();
805 
806  // No definition means that block hasn't been emitted yet. Leave a vreg
807  // reference to be fixed later.
808  if (!MRI->hasOneDef(VReg))
809  return EmitHalfDoneInstrRef(VReg);
810 
811  DefMI = &*MRI->def_instr_begin(VReg);
812  } else {
813  assert(DbgOperand.getKind() == SDDbgOperand::SDNODE);
814  // Look up the corresponding VReg for the given SDNode, if any.
815  SDNode *Node = DbgOperand.getSDNode();
816  SDValue Op = SDValue(Node, DbgOperand.getResNo());
818  // No VReg -> produce a DBG_VALUE $noreg instead.
819  if (I==VRBaseMap.end())
820  return EmitDbgNoLocation(SD);
821 
822  // Try to pick out a defining instruction at this point.
823  VReg = getVR(Op, VRBaseMap);
824 
825  // Again, if there's no instruction defining the VReg right now, fix it up
826  // later.
827  if (!MRI->hasOneDef(VReg))
828  return EmitHalfDoneInstrRef(VReg);
829 
830  DefMI = &*MRI->def_instr_begin(VReg);
831  }
832 
833  // Avoid copy like instructions: they don't define values, only move them.
834  // Leave a virtual-register reference until it can be fixed up later, to find
835  // the underlying value definition.
836  if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
837  return EmitHalfDoneInstrRef(VReg);
838 
839  auto MIB = BuildMI(*MF, DL, RefII);
840 
841  // Find the operand number which defines the specified VReg.
842  unsigned OperandIdx = 0;
843  for (const auto &MO : DefMI->operands()) {
844  if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
845  break;
846  ++OperandIdx;
847  }
848  assert(OperandIdx < DefMI->getNumOperands());
849 
850  // Make the DBG_INSTR_REF refer to that instruction, and that operand.
851  unsigned InstrNum = DefMI->getDebugInstrNum();
852  MIB.addImm(InstrNum);
853  MIB.addImm(OperandIdx);
854  MIB.addMetadata(Var);
855  MIB.addMetadata(Expr);
856  return &*MIB;
857 }
858 
860  // An invalidated SDNode must generate an undef DBG_VALUE: although the
861  // original value is no longer computed, earlier DBG_VALUEs live ranges
862  // must not leak into later code.
863  MDNode *Var = SD->getVariable();
864  MDNode *Expr = SD->getExpression();
865  DebugLoc DL = SD->getDebugLoc();
866  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
867  MIB.addReg(0U);
868  MIB.addReg(0U);
869  MIB.addMetadata(Var);
870  MIB.addMetadata(Expr);
871  return &*MIB;
872 }
873 
874 MachineInstr *
876  DenseMap<SDValue, Register> &VRBaseMap) {
877  MDNode *Var = SD->getVariable();
878  DIExpression *Expr = SD->getExpression();
879  DebugLoc DL = SD->getDebugLoc();
880  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
881 
882  assert(SD->getLocationOps().size() == 1 &&
883  "Non variadic dbg_value should have only one location op");
884 
885  // See about constant-folding the expression.
886  // Copy the location operand in case we replace it.
887  SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
888  if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
889  const Value *V = LocationOps[0].getConst();
890  if (auto *C = dyn_cast<ConstantInt>(V)) {
891  std::tie(Expr, C) = Expr->constantFold(C);
892  LocationOps[0] = SDDbgOperand::fromConst(C);
893  }
894  }
895 
896  // Emit non-variadic dbg_value nodes as DBG_VALUE.
897  // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
898  auto MIB = BuildMI(*MF, DL, II);
899  AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
900 
901  if (SD->isIndirect())
902  MIB.addImm(0U);
903  else
904  MIB.addReg(0U);
905 
906  return MIB.addMetadata(Var).addMetadata(Expr);
907 }
908 
909 MachineInstr *
911  MDNode *Label = SD->getLabel();
912  DebugLoc DL = SD->getDebugLoc();
913  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
914  "Expected inlined-at fields to agree");
915 
916  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
917  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
918  MIB.addMetadata(Label);
919 
920  return &*MIB;
921 }
922 
923 /// EmitMachineNode - Generate machine code for a target-specific node and
924 /// needed dependencies.
925 ///
926 void InstrEmitter::
927 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
928  DenseMap<SDValue, Register> &VRBaseMap) {
929  unsigned Opc = Node->getMachineOpcode();
930 
931  // Handle subreg insert/extract specially
932  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
933  Opc == TargetOpcode::INSERT_SUBREG ||
934  Opc == TargetOpcode::SUBREG_TO_REG) {
935  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
936  return;
937  }
938 
939  // Handle COPY_TO_REGCLASS specially.
940  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
941  EmitCopyToRegClassNode(Node, VRBaseMap);
942  return;
943  }
944 
945  // Handle REG_SEQUENCE specially.
946  if (Opc == TargetOpcode::REG_SEQUENCE) {
947  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
948  return;
949  }
950 
951  if (Opc == TargetOpcode::IMPLICIT_DEF)
952  // We want a unique VR for each IMPLICIT_DEF use.
953  return;
954 
955  const MCInstrDesc &II = TII->get(Opc);
956  unsigned NumResults = CountResults(Node);
957  unsigned NumDefs = II.getNumDefs();
958  const MCPhysReg *ScratchRegs = nullptr;
959 
960  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
961  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
962  // Stackmaps do not have arguments and do not preserve their calling
963  // convention. However, to simplify runtime support, they clobber the same
964  // scratch registers as AnyRegCC.
965  unsigned CC = CallingConv::AnyReg;
966  if (Opc == TargetOpcode::PATCHPOINT) {
967  CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
968  NumDefs = NumResults;
969  }
970  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
971  } else if (Opc == TargetOpcode::STATEPOINT) {
972  NumDefs = NumResults;
973  }
974 
975  unsigned NumImpUses = 0;
976  unsigned NodeOperands =
977  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
978  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
979  II.isVariadic() && II.variadicOpsAreDefs();
980  bool HasPhysRegOuts = NumResults > NumDefs &&
981  II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
982 #ifndef NDEBUG
983  unsigned NumMIOperands = NodeOperands + NumResults;
984  if (II.isVariadic())
985  assert(NumMIOperands >= II.getNumOperands() &&
986  "Too few operands for a variadic node!");
987  else
988  assert(NumMIOperands >= II.getNumOperands() &&
989  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
990  NumImpUses &&
991  "#operands for dag node doesn't match .td file!");
992 #endif
993 
994  // Create the new machine instruction.
995  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
996 
997  // Add result register values for things that are defined by this
998  // instruction.
999  if (NumResults) {
1000  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1001 
1002  // Transfer any IR flags from the SDNode to the MachineInstr
1003  MachineInstr *MI = MIB.getInstr();
1004  const SDNodeFlags Flags = Node->getFlags();
1005  if (Flags.hasNoSignedZeros())
1006  MI->setFlag(MachineInstr::MIFlag::FmNsz);
1007 
1008  if (Flags.hasAllowReciprocal())
1009  MI->setFlag(MachineInstr::MIFlag::FmArcp);
1010 
1011  if (Flags.hasNoNaNs())
1012  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1013 
1014  if (Flags.hasNoInfs())
1015  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1016 
1017  if (Flags.hasAllowContract())
1018  MI->setFlag(MachineInstr::MIFlag::FmContract);
1019 
1020  if (Flags.hasApproximateFuncs())
1021  MI->setFlag(MachineInstr::MIFlag::FmAfn);
1022 
1023  if (Flags.hasAllowReassociation())
1024  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1025 
1026  if (Flags.hasNoUnsignedWrap())
1027  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1028 
1029  if (Flags.hasNoSignedWrap())
1030  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1031 
1032  if (Flags.hasExact())
1033  MI->setFlag(MachineInstr::MIFlag::IsExact);
1034 
1035  if (Flags.hasNoFPExcept())
1036  MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1037  }
1038 
1039  // Emit all of the actual operands of this instruction, adding them to the
1040  // instruction as appropriate.
1041  bool HasOptPRefs = NumDefs > NumResults;
1042  assert((!HasOptPRefs || !HasPhysRegOuts) &&
1043  "Unable to cope with optional defs and phys regs defs!");
1044  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1045  for (unsigned i = NumSkip; i != NodeOperands; ++i)
1046  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1047  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1048 
1049  // Add scratch registers as implicit def and early clobber
1050  if (ScratchRegs)
1051  for (unsigned i = 0; ScratchRegs[i]; ++i)
1052  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1054 
1055  // Set the memory reference descriptions of this instruction now that it is
1056  // part of the function.
1057  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1058 
1059  // Insert the instruction into position in the block. This needs to
1060  // happen before any custom inserter hook is called so that the
1061  // hook knows where in the block to insert the replacement code.
1062  MBB->insert(InsertPos, MIB);
1063 
1064  // The MachineInstr may also define physregs instead of virtregs. These
1065  // physreg values can reach other instructions in different ways:
1066  //
1067  // 1. When there is a use of a Node value beyond the explicitly defined
1068  // virtual registers, we emit a CopyFromReg for one of the implicitly
1069  // defined physregs. This only happens when HasPhysRegOuts is true.
1070  //
1071  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1072  //
1073  // 3. A glued instruction may implicitly use a physreg.
1074  //
1075  // 4. A glued instruction may use a RegisterSDNode operand.
1076  //
1077  // Collect all the used physreg defs, and make sure that any unused physreg
1078  // defs are marked as dead.
1079  SmallVector<Register, 8> UsedRegs;
1080 
1081  // Additional results must be physical register defs.
1082  if (HasPhysRegOuts) {
1083  for (unsigned i = NumDefs; i < NumResults; ++i) {
1084  Register Reg = II.getImplicitDefs()[i - NumDefs];
1085  if (!Node->hasAnyUseOfValue(i))
1086  continue;
1087  // This implicitly defined physreg has a use.
1088  UsedRegs.push_back(Reg);
1089  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
1090  }
1091  }
1092 
1093  // Scan the glue chain for any used physregs.
1094  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1095  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1096  if (F->getOpcode() == ISD::CopyFromReg) {
1097  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1098  continue;
1099  } else if (F->getOpcode() == ISD::CopyToReg) {
1100  // Skip CopyToReg nodes that are internal to the glue chain.
1101  continue;
1102  }
1103  // Collect declared implicit uses.
1104  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1105  UsedRegs.append(MCID.getImplicitUses(),
1106  MCID.getImplicitUses() + MCID.getNumImplicitUses());
1107  // In addition to declared implicit uses, we must also check for
1108  // direct RegisterSDNode operands.
1109  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1110  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1111  Register Reg = R->getReg();
1112  if (Reg.isPhysical())
1113  UsedRegs.push_back(Reg);
1114  }
1115  }
1116  }
1117 
1118  // Finally mark unused registers as dead.
1119  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
1120  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1121 
1122  // STATEPOINT is too 'dynamic' to have meaningful machine description.
1123  // We have to manually tie operands.
1124  if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1125  assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1126  MachineInstr *MI = MIB;
1127  unsigned Def = 0;
1129  assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1130  unsigned Use = (unsigned)First;
1131  while (Def < NumDefs) {
1132  if (MI->getOperand(Use).isReg())
1133  MI->tieOperands(Def++, Use);
1135  }
1136  }
1137 
1138  // Run post-isel target hook to adjust this instruction if needed.
1139  if (II.hasPostISelHook())
1140  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1141 }
1142 
1143 /// EmitSpecialNode - Generate machine code for a target-independent node and
1144 /// needed dependencies.
1145 void InstrEmitter::
1146 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1147  DenseMap<SDValue, Register> &VRBaseMap) {
1148  switch (Node->getOpcode()) {
1149  default:
1150 #ifndef NDEBUG
1151  Node->dump();
1152 #endif
1153  llvm_unreachable("This target-independent node should have been selected!");
1154  case ISD::EntryToken:
1155  llvm_unreachable("EntryToken should have been excluded from the schedule!");
1156  case ISD::MERGE_VALUES:
1157  case ISD::TokenFactor: // fall thru
1158  break;
1159  case ISD::CopyToReg: {
1160  Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1161  SDValue SrcVal = Node->getOperand(2);
1162  if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1163  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1164  // Instead building a COPY to that vreg destination, build an
1165  // IMPLICIT_DEF instruction instead.
1166  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1167  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1168  break;
1169  }
1170  Register SrcReg;
1171  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1172  SrcReg = R->getReg();
1173  else
1174  SrcReg = getVR(SrcVal, VRBaseMap);
1175 
1176  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1177  break;
1178 
1179  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1180  DestReg).addReg(SrcReg);
1181  break;
1182  }
1183  case ISD::CopyFromReg: {
1184  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1185  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1186  break;
1187  }
1188  case ISD::EH_LABEL:
1189  case ISD::ANNOTATION_LABEL: {
1190  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1193  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1194  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1195  TII->get(Opc)).addSym(S);
1196  break;
1197  }
1198 
1199  case ISD::LIFETIME_START:
1200  case ISD::LIFETIME_END: {
1201  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1204  auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1205  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1206  .addFrameIndex(FI->getIndex());
1207  break;
1208  }
1209 
1210  case ISD::PSEUDO_PROBE: {
1211  unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1212  auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1213  auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1214  auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1215 
1216  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1217  .addImm(Guid)
1218  .addImm(Index)
1219  .addImm((uint8_t)PseudoProbeType::Block)
1220  .addImm(Attr);
1221  break;
1222  }
1223 
1224  case ISD::INLINEASM:
1225  case ISD::INLINEASM_BR: {
1226  unsigned NumOps = Node->getNumOperands();
1227  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1228  --NumOps; // Ignore the glue operand.
1229 
1230  // Create the inline asm machine instruction.
1231  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1234  MachineInstrBuilder MIB =
1235  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1236 
1237  // Add the asm string as an external symbol operand.
1238  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1239  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1240  MIB.addExternalSymbol(AsmStr);
1241 
1242  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1243  // bits.
1244  int64_t ExtraInfo =
1245  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1246  getZExtValue();
1247  MIB.addImm(ExtraInfo);
1248 
1249  // Remember to operand index of the group flags.
1250  SmallVector<unsigned, 8> GroupIdx;
1251 
1252  // Remember registers that are part of early-clobber defs.
1253  SmallVector<unsigned, 8> ECRegs;
1254 
1255  // Add all of the operand registers to the instruction.
1256  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1257  unsigned Flags =
1258  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1259  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1260 
1261  GroupIdx.push_back(MIB->getNumOperands());
1262  MIB.addImm(Flags);
1263  ++i; // Skip the ID value.
1264 
1265  switch (InlineAsm::getKind(Flags)) {
1266  default: llvm_unreachable("Bad flags!");
1268  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1269  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1270  // FIXME: Add dead flags for physical and virtual registers defined.
1271  // For now, mark physical register defs as implicit to help fast
1272  // regalloc. This makes inline asm look a lot like calls.
1273  MIB.addReg(Reg,
1276  }
1277  break;
1280  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1281  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1282  MIB.addReg(Reg,
1285  ECRegs.push_back(Reg);
1286  }
1287  break;
1288  case InlineAsm::Kind_RegUse: // Use of register.
1289  case InlineAsm::Kind_Imm: // Immediate.
1290  case InlineAsm::Kind_Mem: // Addressing mode.
1291  // The addressing mode has been selected, just add all of the
1292  // operands to the machine instruction.
1293  for (unsigned j = 0; j != NumVals; ++j, ++i)
1294  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1295  /*IsDebug=*/false, IsClone, IsCloned);
1296 
1297  // Manually set isTied bits.
1299  unsigned DefGroup = 0;
1300  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1301  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1302  unsigned UseIdx = GroupIdx.back() + 1;
1303  for (unsigned j = 0; j != NumVals; ++j)
1304  MIB->tieOperands(DefIdx + j, UseIdx + j);
1305  }
1306  }
1307  break;
1308  }
1309  }
1310 
1311  // GCC inline assembly allows input operands to also be early-clobber
1312  // output operands (so long as the operand is written only after it's
1313  // used), but this does not match the semantics of our early-clobber flag.
1314  // If an early-clobber operand register is also an input operand register,
1315  // then remove the early-clobber flag.
1316  for (unsigned Reg : ECRegs) {
1317  if (MIB->readsRegister(Reg, TRI)) {
1318  MachineOperand *MO =
1319  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1320  assert(MO && "No def operand for clobbered register?");
1321  MO->setIsEarlyClobber(false);
1322  }
1323  }
1324 
1325  // Get the mdnode from the asm if it exists and add it to the instruction.
1326  SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1327  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1328  if (MD)
1329  MIB.addMetadata(MD);
1330 
1331  MBB->insert(InsertPos, MIB);
1332  break;
1333  }
1334  }
1335 }
1336 
1337 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1338 /// at the given position in the given block.
1340  MachineBasicBlock::iterator insertpos,
1341  bool UseInstrRefDebugInfo)
1342  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1343  TII(MF->getSubtarget().getInstrInfo()),
1344  TRI(MF->getSubtarget().getRegisterInfo()),
1345  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1346  InsertPos(insertpos) {
1347  EmitDebugInstrRefs = UseInstrRefDebugInfo;
1348 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:624
llvm::SDNodeFlags::hasAllowReciprocal
bool hasAllowReciprocal() const
Definition: SelectionDAGNodes.h:429
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::SDDbgValue::getExpression
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Definition: SDNodeDbgValue.h:183
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:133
llvm::SDDbgOperand::fromConst
static SDDbgOperand fromConst(const Value *Const)
Definition: SDNodeDbgValue.h:80
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2131
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:1995
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2323
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Definition: MachineFunction.cpp:1498
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::TargetLowering::getScratchRegisters
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: TargetLowering.h:4296
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1216
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::InlineAsm::Op_AsmString
@ Op_AsmString
Definition: InlineAsm.h:217
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:118
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1215
llvm::LLVMTargetMachine::usesPhysRegsForValues
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
Definition: TargetMachine.h:480
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:239
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:405
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::SDNodeFlags::hasNoNaNs
bool hasNoNaNs() const
Definition: SelectionDAGNodes.h:426
llvm::SDDbgOperand::getResNo
unsigned getResNo() const
Returns the ResNo for a register ref.
Definition: SDNodeDbgValue.h:48
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1026
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:304
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:114
llvm::DenseMapIterator
Definition: DenseMap.h:57
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:488
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:361
TargetInstrInfo.h
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1025
llvm::InstrEmitter::CountResults
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Definition: InstrEmitter.cpp:43
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::SDDbgOperand
Holds the information for a single machine location through SDISel; either an SDNode,...
Definition: SDNodeDbgValue.h:31
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2548
SDNodeDbgValue.h
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:242
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::SDDbgValue::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:215
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:240
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:514
MachineRegisterInfo.h
llvm::InstrEmitter::AddDbgValueLocationOps
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
Definition: InstrEmitter.cpp:711
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1018
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1235
llvm::SDDbgOperand::getVReg
unsigned getVReg() const
Returns the Virtual Register for a VReg.
Definition: SDNodeDbgValue.h:66
llvm::TargetLowering::AdjustInstrPostInstrSelection
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: SelectionDAGISel.cpp:302
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:45
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::InstrEmitter::EmitDbgNoLocation
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Definition: InstrEmitter.cpp:859
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
TargetMachine.h
llvm::SDDbgLabel
Holds the information from a dbg_label node through SDISel.
Definition: SDNodeDbgValue.h:242
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
countOperands
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
Definition: InstrEmitter.cpp:59
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:667
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:568
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SDDbgValue::isIndirect
bool isIndirect() const
Returns whether this is an indirect value.
Definition: SDNodeDbgValue.h:210
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::SDDbgOperand::VREG
@ VREG
Value is a virtual register.
Definition: SDNodeDbgValue.h:37
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:238
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1760
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:344
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RegisterMaskSDNode
Definition: SelectionDAGNodes.h:2147
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:252
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::DIExpression::append
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
Definition: DebugInfoMetadata.cpp:1546
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:427
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SPIRV::Decoration::Alignment
@ Alignment
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:1129
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:412
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SDDbgLabel::getLabel
MDNode * getLabel() const
Returns the MDNode pointer for the label.
Definition: SDNodeDbgValue.h:252
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1613
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:934
llvm::InstrEmitter::EmitDbgLabel
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
Definition: InstrEmitter.cpp:910
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:716
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::SDDbgOperand::getKind
Kind getKind() const
Definition: SDNodeDbgValue.h:39
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MachineConstantPool.h
llvm::BasicBlockSDNode
Definition: SelectionDAGNodes.h:1942
llvm::SDDbgValue::isInvalidated
bool isInvalidated() const
Definition: SDNodeDbgValue.h:225
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:672
llvm::SDNodeFlags::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Definition: SelectionDAGNodes.h:423
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1579
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:452
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:937
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1347
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1032
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::InlineAsm::Op_MDNode
@ Op_MDNode
Definition: InlineAsm.h:218
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:240
Dwarf.h
llvm::InstrEmitter::EmitDbgInstrRef
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
Definition: InstrEmitter.cpp:759
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::SDNodeFlags::hasApproximateFuncs
bool hasApproximateFuncs() const
Definition: SelectionDAGNodes.h:431
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:532
llvm::SDValue::getMachineOpcode
unsigned getMachineOpcode() const
Definition: SelectionDAGNodes.h:1157
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SDDbgOperand::getSDNode
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
Definition: SDNodeDbgValue.h:42
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:294
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:868
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
InstrEmitter.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SDNodeFlags::hasNoInfs
bool hasNoInfs() const
Definition: SelectionDAGNodes.h:427
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:243
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:209
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
j
return j(j<< 16)
llvm::SDDbgValue::isVariadic
bool isVariadic() const
Definition: SDNodeDbgValue.h:212
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::SDDbgLabel::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:255
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:520
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1307
llvm::SDNodeFlags::hasNoSignedWrap
bool hasNoSignedWrap() const
Definition: SelectionDAGNodes.h:424
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:344
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:262
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1308
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::TargetIndexSDNode
Completely target-dependent object reference.
Definition: SelectionDAGNodes.h:1921
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:544
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1021
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1646
llvm::SDDbgOperand::SDNODE
@ SDNODE
Value is the result of an expression.
Definition: SDNodeDbgValue.h:34
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
StackMaps.h
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
PseudoProbe.h
MinRCSize
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
Definition: InstrEmitter.cpp:38
llvm::SDNodeFlags
These are IR-level optimization flags that may be propagated to SDNodes.
Definition: SelectionDAGNodes.h:370
llvm::SDNodeFlags::hasExact
bool hasExact() const
Definition: SelectionDAGNodes.h:425
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::SDDbgValue::getVariable
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
Definition: SDNodeDbgValue.h:180
llvm::SDNodeFlags::hasAllowReassociation
bool hasAllowReassociation() const
Definition: SelectionDAGNodes.h:432
llvm::SDDbgValue::getLocationOps
ArrayRef< SDDbgOperand > getLocationOps() const
Definition: SDNodeDbgValue.h:185
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::PseudoProbeType::Block
@ Block
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:355
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::SDDbgOperand::FRAMEIX
@ FRAMEIX
Value is contents of a stack location.
Definition: SDNodeDbgValue.h:36
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:891
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::InstrEmitter::InstrEmitter
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos, bool UseInstrRefDebugInfo)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
Definition: InstrEmitter.cpp:1339
llvm::SDDbgOperand::CONST
@ CONST
Value is a constant.
Definition: SDNodeDbgValue.h:35
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:127
llvm::InlineAsm::Op_ExtraInfo
@ Op_ExtraInfo
Definition: InlineAsm.h:219
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::SDNodeFlags::hasNoFPExcept
bool hasNoFPExcept() const
Definition: SelectionDAGNodes.h:433
RN
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
Definition: README_P9.txt:262
llvm::InstrEmitter::EmitDbgValueFromSingleOp
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
Definition: InstrEmitter.cpp:875
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SDDbgValue::setIsEmitted
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Definition: SDNodeDbgValue.h:229
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::SDNodeFlags::hasNoSignedZeros
bool hasNoSignedZeros() const
Definition: SelectionDAGNodes.h:428
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1052
llvm::SDValue::isMachineOpcode
bool isMachineOpcode() const
Definition: SelectionDAGNodes.h:1153
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1436
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:505
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:220
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:620
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:241
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::SDNodeFlags::hasAllowContract
bool hasAllowContract() const
Definition: SelectionDAGNodes.h:430
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::InstrEmitter::EmitDbgValue
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
Definition: InstrEmitter.cpp:672