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32 #define DEBUG_TYPE "instr-emitter"
44 unsigned N = Node->getNumValues();
60 unsigned &NumImpUses) {
61 unsigned N = Node->getNumOperands();
62 while (
N && Node->getOperand(
N - 1).getValueType() ==
MVT::Glue)
64 if (
N && Node->getOperand(
N - 1).getValueType() ==
MVT::Other)
68 NumImpUses =
N - NumExpUses;
69 for (
unsigned I =
N;
I > NumExpUses; --
I) {
70 if (isa<RegisterMaskSDNode>(Node->getOperand(
I - 1)))
85 EmitCopyFromReg(
SDNode *Node,
unsigned ResNo,
bool IsClone,
bool IsCloned,
93 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, SrcReg)).second;
95 assert(isNew &&
"Node emitted out of order - early");
101 bool MatchReg =
true;
103 MVT VT = Node->getSimpleValueType(ResNo);
109 if (!IsClone && !IsCloned)
119 }
else if (DestReg != SrcReg)
124 if (
Op.getNode() != Node ||
Op.getResNo() != ResNo)
126 MVT VT = Node->getSimpleValueType(
Op.getResNo());
130 if (
User->isMachineOpcode()) {
163 "Incompatible phys register def and uses!");
175 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
182 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
184 assert(isNew &&
"Node emitted out of order - early");
187 void InstrEmitter::CreateVirtualRegisters(
SDNode *Node,
190 bool IsClone,
bool IsCloned,
192 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
193 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
198 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.
getNumDefs();
199 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
200 NumVRegs = NumResults;
201 for (
unsigned i = 0;
i < NumVRegs; ++
i) {
212 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(
i))) {
214 Node->getSimpleValueType(
i),
224 VRBase = cast<RegisterSDNode>(Node->getOperand(
i-NumResults))->getReg();
229 if (!VRBase && !IsClone && !IsCloned)
249 assert(RC &&
"Isn't a register operand!");
256 if (
i < NumResults) {
260 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
262 assert(isNew &&
"Node emitted out of order - early");
271 if (
Op.isMachineOpcode() &&
272 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
277 Op.getSimpleValueType(),
Op.getNode()->isDivergent());
279 BuildMI(*MBB, InsertPos,
Op.getDebugLoc(),
280 TII->
get(TargetOpcode::IMPLICIT_DEF), VReg);
285 assert(
I != VRBaseMap.
end() &&
"Node emitted out of order - late");
299 bool IsDebug,
bool IsClone,
bool IsCloned) {
302 "Chain and glue operands should occur at end of operand list!");
316 if (IIOpNum < II->getNumOperands())
322 if (!ConstrainedRC) {
324 assert(OpRC &&
"Constraints cannot be fulfilled for allocation");
326 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
327 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
331 "Constraining an allocatable VReg produced an unallocatable class?");
343 bool isKill =
Op.hasOneUse() &&
346 !(IsClone || IsCloned);
370 bool IsDebug,
bool IsClone,
bool IsCloned) {
371 if (
Op.isMachineOpcode()) {
372 AddRegisterOperand(MIB,
Op, IIOpNum, II, VRBaseMap,
373 IsDebug, IsClone, IsCloned);
380 MVT OpVT =
Op.getSimpleValueType();
387 Op.getNode()->isDivergent() ||
393 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
394 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
406 TGA->getTargetFlags());
408 MIB.
addMBB(BBNode->getBasicBlock());
419 if (
CP->isMachineConstantPoolEntry())
426 }
else if (
auto *SymNode = dyn_cast<MCSymbolSDNode>(
Op)) {
427 MIB.
addSym(SymNode->getMCSymbol());
431 BA->getTargetFlags());
433 MIB.
addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
437 "Chain and glue operands should occur at end of operand list!");
438 AddRegisterOperand(MIB,
Op, IIOpNum, II, VRBaseMap,
439 IsDebug, IsClone, IsCloned);
460 assert(RC &&
"No legal register class for VT supports that SubIdx");
462 BuildMI(*MBB, InsertPos,
DL, TII->
get(TargetOpcode::COPY), NewReg)
469 void InstrEmitter::EmitSubregNode(
SDNode *Node,
471 bool IsClone,
bool IsCloned) {
473 unsigned Opc = Node->getMachineOpcode();
488 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
492 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
494 TLI->
getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
503 Reg =
R ?
R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
511 SubIdx == DefSubIdx &&
519 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
520 TII->
get(TargetOpcode::COPY), VRBase).
addReg(SrcReg);
527 Reg = ConstrainForSubReg(
Reg, SubIdx,
528 Node->getOperand(0).getSimpleValueType(),
529 Node->isDivergent(), Node->getDebugLoc());
536 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
537 TII->
get(TargetOpcode::COPY), VRBase);
543 }
else if (Opc == TargetOpcode::INSERT_SUBREG ||
544 Opc == TargetOpcode::SUBREG_TO_REG) {
545 SDValue N0 = Node->getOperand(0);
546 SDValue N1 = Node->getOperand(1);
547 SDValue N2 = Node->getOperand(2);
548 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
565 TLI->
getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
567 assert(SRC &&
"No register class supports VT and SubIdx for INSERT_SUBREG");
574 BuildMI(*MF, Node->getDebugLoc(), TII->
get(Opc), VRBase);
578 if (Opc == TargetOpcode::SUBREG_TO_REG) {
582 AddOperand(MIB, N0, 0,
nullptr, VRBaseMap,
false,
585 AddOperand(MIB, N1, 0,
nullptr, VRBaseMap,
false,
588 MBB->
insert(InsertPos, MIB);
590 llvm_unreachable(
"Node is not insert_subreg, extract_subreg, or subreg_to_reg");
593 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
595 assert(isNew &&
"Node emitted out of order - early");
603 InstrEmitter::EmitCopyToRegClassNode(
SDNode *Node,
605 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
608 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
612 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
616 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
618 assert(isNew &&
"Node emitted out of order - early");
623 void InstrEmitter::EmitRegSequence(
SDNode *Node,
625 bool IsClone,
bool IsCloned) {
626 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
631 unsigned NumOps = Node->getNumOperands();
635 if (NumOps && Node->getOperand(NumOps-1).getValueType() ==
MVT::Other)
638 assert((NumOps & 1) == 1 &&
639 "REG_SEQUENCE must have an odd number of operands!");
640 for (
unsigned i = 1;
i != NumOps; ++
i) {
647 unsigned SubIdx = cast<ConstantSDNode>(
Op)->getZExtValue();
648 unsigned SubReg = getVR(Node->getOperand(
i-1), VRBaseMap);
652 if (SRC && SRC != RC) {
658 AddOperand(MIB,
Op,
i+1, &II, VRBaseMap,
false,
662 MBB->
insert(InsertPos, MIB);
664 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
666 assert(isNew &&
"Node emitted out of order - early");
677 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
678 "Expected inlined-at fields to agree");
683 assert(!LocationOps.
empty() &&
"dbg_value with no location operands?");
691 const MCInstrDesc &DbgValDesc = TII->
get(TargetOpcode::DBG_VALUE_LIST);
704 if (EmitDebugInstrRefs)
716 switch (
Op.getKind()) {
730 if (VRBaseMap.
count(V) == 0)
733 AddOperand(MIB, V, (*MIB).
getNumOperands(), &DbgValDesc, VRBaseMap,
737 const Value *V =
Op.getConst();
738 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
739 if (CI->getBitWidth() > 64)
742 MIB.
addImm(CI->getSExtValue());
743 }
else if (
const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
745 }
else if (isa<ConstantPointerNull>(V)) {
777 std::vector<uint64_t> Elts = {dwarf::DW_OP_deref};
790 auto EmitHalfDoneInstrRef = [&](
unsigned VReg) ->
MachineInstr * {
809 return EmitHalfDoneInstrRef(VReg);
819 if (
I==VRBaseMap.
end())
823 VReg = getVR(
Op, VRBaseMap);
828 return EmitHalfDoneInstrRef(VReg);
837 return EmitHalfDoneInstrRef(VReg);
842 unsigned OperandIdx = 0;
844 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
848 assert(OperandIdx < DefMI->getNumOperands());
866 auto MIB =
BuildMI(*MF,
DL, TII->
get(TargetOpcode::DBG_VALUE));
883 "Non variadic dbg_value should have only one location op");
889 const Value *V = LocationOps[0].getConst();
890 if (
auto *
C = dyn_cast<ConstantInt>(V)) {
913 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
914 "Expected inlined-at fields to agree");
927 EmitMachineNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
929 unsigned Opc = Node->getMachineOpcode();
932 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
933 Opc == TargetOpcode::INSERT_SUBREG ||
934 Opc == TargetOpcode::SUBREG_TO_REG) {
935 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
940 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
941 EmitCopyToRegClassNode(Node, VRBaseMap);
946 if (Opc == TargetOpcode::REG_SEQUENCE) {
947 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
951 if (Opc == TargetOpcode::IMPLICIT_DEF)
961 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
966 if (Opc == TargetOpcode::PATCHPOINT) {
968 NumDefs = NumResults;
971 }
else if (Opc == TargetOpcode::STATEPOINT) {
972 NumDefs = NumResults;
975 unsigned NumImpUses = 0;
976 unsigned NodeOperands =
980 bool HasPhysRegOuts = NumResults > NumDefs &&
983 unsigned NumMIOperands = NodeOperands + NumResults;
986 "Too few operands for a variadic node!");
991 "#operands for dag node doesn't match .td file!");
1000 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1006 MI->setFlag(MachineInstr::MIFlag::FmNsz);
1009 MI->setFlag(MachineInstr::MIFlag::FmArcp);
1012 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1015 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1018 MI->setFlag(MachineInstr::MIFlag::FmContract);
1021 MI->setFlag(MachineInstr::MIFlag::FmAfn);
1024 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1027 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1030 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1033 MI->setFlag(MachineInstr::MIFlag::IsExact);
1036 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1041 bool HasOptPRefs = NumDefs > NumResults;
1042 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1043 "Unable to cope with optional defs and phys regs defs!");
1044 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1045 for (
unsigned i = NumSkip;
i != NodeOperands; ++
i)
1046 AddOperand(MIB, Node->getOperand(
i),
i-NumSkip+NumDefs, &II,
1047 VRBaseMap,
false, IsClone, IsCloned);
1051 for (
unsigned i = 0; ScratchRegs[
i]; ++
i)
1057 MIB.
setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1062 MBB->
insert(InsertPos, MIB);
1082 if (HasPhysRegOuts) {
1083 for (
unsigned i = NumDefs;
i < NumResults; ++
i) {
1085 if (!Node->hasAnyUseOfValue(
i))
1088 UsedRegs.push_back(
Reg);
1089 EmitCopyFromReg(Node,
i, IsClone, IsCloned,
Reg, VRBaseMap);
1094 if (Node->getValueType(Node->getNumValues()-1) ==
MVT::Glue) {
1095 for (
SDNode *
F = Node->getGluedUser();
F;
F =
F->getGluedUser()) {
1097 UsedRegs.push_back(cast<RegisterSDNode>(
F->getOperand(1))->getReg());
1109 for (
unsigned i = 0,
e =
F->getNumOperands();
i !=
e; ++
i)
1112 if (
Reg.isPhysical())
1113 UsedRegs.push_back(
Reg);
1124 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1125 assert(!HasPhysRegOuts &&
"STATEPOINT mishandled");
1129 assert(First > 0 &&
"Statepoint has Defs but no GC ptr list");
1130 unsigned Use = (unsigned)First;
1131 while (
Def < NumDefs) {
1132 if (
MI->getOperand(
Use).isReg())
1146 EmitSpecialNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
1148 switch (Node->getOpcode()) {
1153 llvm_unreachable(
"This target-independent node should have been selected!");
1155 llvm_unreachable(
"EntryToken should have been excluded from the schedule!");
1160 Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1161 SDValue SrcVal = Node->getOperand(2);
1166 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1167 TII->
get(TargetOpcode::IMPLICIT_DEF), DestReg);
1172 SrcReg =
R->getReg();
1174 SrcReg = getVR(SrcVal, VRBaseMap);
1176 if (SrcReg == DestReg)
1179 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
1184 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1185 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1193 MCSymbol *
S = cast<LabelSDNode>(Node)->getLabel();
1194 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1204 auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1205 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TarOp))
1212 auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1213 auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1214 auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1216 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TarOp))
1226 unsigned NumOps = Node->getNumOperands();
1227 if (Node->getOperand(NumOps-1).getValueType() ==
MVT::Glue)
1235 BuildMI(*MF, Node->getDebugLoc(), TII->
get(TgtOpc));
1239 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1258 cast<ConstantSDNode>(Node->getOperand(
i))->getZExtValue();
1268 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i) {
1269 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(
i))->getReg();
1280 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i) {
1281 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(
i))->getReg();
1285 ECRegs.push_back(
Reg);
1293 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i)
1294 AddOperand(MIB, Node->getOperand(
i), 0,
nullptr, VRBaseMap,
1295 false, IsClone, IsCloned);
1299 unsigned DefGroup = 0;
1301 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1302 unsigned UseIdx = GroupIdx.back() + 1;
1303 for (
unsigned j = 0;
j != NumVals; ++
j)
1316 for (
unsigned Reg : ECRegs) {
1320 assert(MO &&
"No def operand for clobbered register?");
1327 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1331 MBB->
insert(InsertPos, MIB);
1341 bool UseInstrRefDebugInfo)
1343 TII(MF->getSubtarget().getInstrInfo()),
1344 TRI(MF->getSubtarget().getRegisterInfo()),
1345 TLI(MF->getSubtarget().getTargetLowering()),
MBB(mbb),
1346 InsertPos(insertpos) {
1347 EmitDebugInstrRefs = UseInstrRefDebugInfo;
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
bool hasAllowReciprocal() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Holds the information from a dbg_value node through SDISel.
static SDDbgOperand fromConst(const Value *Const)
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
This is an optimization pass for GlobalISel generic memory operations.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
def_instr_iterator def_instr_begin(Register RegNo) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getResNo() const
Returns the ResNo for a register ref.
Reg
All possible values of the reg field in the ModR/M byte.
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Represents one node in the SelectionDAG.
bool erase(const KeyT &Val)
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Holds the information for a single machine location through SDISel; either an SDNode,...
unsigned const TargetRegisterInfo * TRI
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
bool empty() const
empty - Check if the array is empty.
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
@ EarlyClobber
Register definition happens before uses.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
unsigned getVReg() const
Returns the Virtual Register for a VReg.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
This is the shared class of boolean and integer constants.
unsigned getDefRegState(bool B)
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Holds the information from a dbg_label node through SDISel.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool isIndirect() const
Returns whether this is an indirect value.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
into llvm powi allowing the code generator to produce balanced multiplication trees First
MachineOperand class - Representation of each machine instruction operand.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
@ VREG
Value is a virtual register.
ConstantFP - Floating Point Values [float, double].
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
static unsigned getKind(unsigned Flags)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isOptionalDef() const
Set if this operand is a optional def.
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned getNumOperands() const
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isInvalidated() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool hasNoUnsignedWrap() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
uint64_t getZExtValue() const
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const MCOperandInfo * OpInfo
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
@ Kind_RegDefEarlyClobber
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
bool hasApproximateFuncs() const
void setIsEarlyClobber(bool Val=true)
unsigned getMachineOpcode() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
static const Function * getParent(const Value *V)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
MI-level Statepoint operands.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
unsigned getDebugRegState(bool B)
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool hasNoSignedWrap() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Completely target-dependent object reference.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ Define
Register definition.
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
@ SDNODE
Value is the result of an expression.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
These are IR-level optimization flags that may be propagated to SDNodes.
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
bool hasAllowReassociation() const
ArrayRef< SDDbgOperand > getLocationOps() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
unsigned getKillRegState(bool B)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumOperands() const
Retuns the total number of operands.
@ FRAMEIX
Value is contents of a stack location.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos, bool UseInstrRefDebugInfo)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
@ CONST
Value is a constant.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const char LLVMTargetMachineRef TM
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool hasNoFPExcept() const
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Value * getOperand(unsigned i) const
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool hasNoSignedZeros() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool isMachineOpcode() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getImplRegState(bool B)
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
iterator_range< mop_iterator > operands()
LLVM Value Representation.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
bool hasAllowContract() const
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
A Use represents the edge between a Value definition and its users.
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.