LLVM  16.0.0git
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
22 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/PseudoProbe.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "instr-emitter"
33 
34 /// MinRCSize - Smallest register class we allow when constraining virtual
35 /// registers. If satisfying all register class constraints would require
36 /// using a smaller register class, emit a COPY to a new virtual register
37 /// instead.
38 const unsigned MinRCSize = 4;
39 
40 /// CountResults - The results of target nodes have register or immediate
41 /// operands first, then an optional chain, and optional glue operands (which do
42 /// not go into the resulting MachineInstr).
44  unsigned N = Node->getNumValues();
45  while (N && Node->getValueType(N - 1) == MVT::Glue)
46  --N;
47  if (N && Node->getValueType(N - 1) == MVT::Other)
48  --N; // Skip over chain result.
49  return N;
50 }
51 
52 /// countOperands - The inputs to target nodes have any actual inputs first,
53 /// followed by an optional chain operand, then an optional glue operand.
54 /// Compute the number of actual operands that will go into the resulting
55 /// MachineInstr.
56 ///
57 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58 /// the chain and glue. These operands may be implicit on the machine instr.
59 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60  unsigned &NumImpUses) {
61  unsigned N = Node->getNumOperands();
62  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63  --N;
64  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65  --N; // Ignore chain if it exists.
66 
67  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68  NumImpUses = N - NumExpUses;
69  for (unsigned I = N; I > NumExpUses; --I) {
70  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71  continue;
72  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73  if (Register::isPhysicalRegister(RN->getReg()))
74  continue;
75  NumImpUses = N - I;
76  break;
77  }
78 
79  return N;
80 }
81 
82 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83 /// implicit physical register output.
84 void InstrEmitter::
85 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
86  Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
87  Register VRBase;
88  if (SrcReg.isVirtual()) {
89  // Just use the input register directly!
90  SDValue Op(Node, ResNo);
91  if (IsClone)
92  VRBaseMap.erase(Op);
93  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
94  (void)isNew; // Silence compiler warning.
95  assert(isNew && "Node emitted out of order - early");
96  return;
97  }
98 
99  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
100  // the CopyToReg'd destination register instead of creating a new vreg.
101  bool MatchReg = true;
102  const TargetRegisterClass *UseRC = nullptr;
103  MVT VT = Node->getSimpleValueType(ResNo);
104 
105  // Stick to the preferred register classes for legal types.
106  if (TLI->isTypeLegal(VT))
107  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
108 
109  if (!IsClone && !IsCloned)
110  for (SDNode *User : Node->uses()) {
111  bool Match = true;
112  if (User->getOpcode() == ISD::CopyToReg &&
113  User->getOperand(2).getNode() == Node &&
114  User->getOperand(2).getResNo() == ResNo) {
115  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
116  if (DestReg.isVirtual()) {
117  VRBase = DestReg;
118  Match = false;
119  } else if (DestReg != SrcReg)
120  Match = false;
121  } else {
122  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
123  SDValue Op = User->getOperand(i);
124  if (Op.getNode() != Node || Op.getResNo() != ResNo)
125  continue;
126  MVT VT = Node->getSimpleValueType(Op.getResNo());
127  if (VT == MVT::Other || VT == MVT::Glue)
128  continue;
129  Match = false;
130  if (User->isMachineOpcode()) {
131  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
132  const TargetRegisterClass *RC = nullptr;
133  if (i+II.getNumDefs() < II.getNumOperands()) {
134  RC = TRI->getAllocatableClass(
135  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
136  }
137  if (!UseRC)
138  UseRC = RC;
139  else if (RC) {
140  const TargetRegisterClass *ComRC =
141  TRI->getCommonSubClass(UseRC, RC);
142  // If multiple uses expect disjoint register classes, we emit
143  // copies in AddRegisterOperand.
144  if (ComRC)
145  UseRC = ComRC;
146  }
147  }
148  }
149  }
150  MatchReg &= Match;
151  if (VRBase)
152  break;
153  }
154 
155  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
156  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
157 
158  // Figure out the register class to create for the destreg.
159  if (VRBase) {
160  DstRC = MRI->getRegClass(VRBase);
161  } else if (UseRC) {
162  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
163  "Incompatible phys register def and uses!");
164  DstRC = UseRC;
165  } else
166  DstRC = SrcRC;
167 
168  // If all uses are reading from the src physical register and copying the
169  // register is either impossible or very expensive, then don't create a copy.
170  if (MatchReg && SrcRC->getCopyCost() < 0) {
171  VRBase = SrcReg;
172  } else {
173  // Create the reg, emit the copy.
174  VRBase = MRI->createVirtualRegister(DstRC);
175  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
176  VRBase).addReg(SrcReg);
177  }
178 
179  SDValue Op(Node, ResNo);
180  if (IsClone)
181  VRBaseMap.erase(Op);
182  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
183  (void)isNew; // Silence compiler warning.
184  assert(isNew && "Node emitted out of order - early");
185 }
186 
187 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
188  MachineInstrBuilder &MIB,
189  const MCInstrDesc &II,
190  bool IsClone, bool IsCloned,
191  DenseMap<SDValue, Register> &VRBaseMap) {
192  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
193  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
194 
195  unsigned NumResults = CountResults(Node);
196  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
197  II.isVariadic() && II.variadicOpsAreDefs();
198  unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
199  if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
200  NumVRegs = NumResults;
201  for (unsigned i = 0; i < NumVRegs; ++i) {
202  // If the specific node value is only used by a CopyToReg and the dest reg
203  // is a vreg in the same register class, use the CopyToReg'd destination
204  // register instead of creating a new vreg.
205  Register VRBase;
206  const TargetRegisterClass *RC =
207  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
208  // Always let the value type influence the used register class. The
209  // constraints on the instruction may be too lax to represent the value
210  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
211  // the 32-bit float super-class (X86::FR32).
212  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
213  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
214  Node->getSimpleValueType(i),
215  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
216  if (RC)
217  VTRC = TRI->getCommonSubClass(RC, VTRC);
218  if (VTRC)
219  RC = VTRC;
220  }
221 
222  if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
223  // Optional def must be a physical register.
224  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
225  assert(VRBase.isPhysical());
226  MIB.addReg(VRBase, RegState::Define);
227  }
228 
229  if (!VRBase && !IsClone && !IsCloned)
230  for (SDNode *User : Node->uses()) {
231  if (User->getOpcode() == ISD::CopyToReg &&
232  User->getOperand(2).getNode() == Node &&
233  User->getOperand(2).getResNo() == i) {
234  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
236  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
237  if (RegRC == RC) {
238  VRBase = Reg;
239  MIB.addReg(VRBase, RegState::Define);
240  break;
241  }
242  }
243  }
244  }
245 
246  // Create the result registers for this node and add the result regs to
247  // the machine instruction.
248  if (VRBase == 0) {
249  assert(RC && "Isn't a register operand!");
250  VRBase = MRI->createVirtualRegister(RC);
251  MIB.addReg(VRBase, RegState::Define);
252  }
253 
254  // If this def corresponds to a result of the SDNode insert the VRBase into
255  // the lookup map.
256  if (i < NumResults) {
257  SDValue Op(Node, i);
258  if (IsClone)
259  VRBaseMap.erase(Op);
260  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
261  (void)isNew; // Silence compiler warning.
262  assert(isNew && "Node emitted out of order - early");
263  }
264  }
265 }
266 
267 /// getVR - Return the virtual register corresponding to the specified result
268 /// of the specified node.
269 Register InstrEmitter::getVR(SDValue Op,
270  DenseMap<SDValue, Register> &VRBaseMap) {
271  if (Op.isMachineOpcode() &&
272  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
273  // Add an IMPLICIT_DEF instruction before every use.
274  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
275  // does not include operand register class info.
276  const TargetRegisterClass *RC = TLI->getRegClassFor(
277  Op.getSimpleValueType(), Op.getNode()->isDivergent());
278  Register VReg = MRI->createVirtualRegister(RC);
279  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
280  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
281  return VReg;
282  }
283 
285  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
286  return I->second;
287 }
288 
289 
290 /// AddRegisterOperand - Add the specified register as an operand to the
291 /// specified machine instr. Insert register copies if the register is
292 /// not in the required register class.
293 void
294 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
295  SDValue Op,
296  unsigned IIOpNum,
297  const MCInstrDesc *II,
298  DenseMap<SDValue, Register> &VRBaseMap,
299  bool IsDebug, bool IsClone, bool IsCloned) {
300  assert(Op.getValueType() != MVT::Other &&
301  Op.getValueType() != MVT::Glue &&
302  "Chain and glue operands should occur at end of operand list!");
303  // Get/emit the operand.
304  Register VReg = getVR(Op, VRBaseMap);
305 
306  const MCInstrDesc &MCID = MIB->getDesc();
307  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
308  MCID.OpInfo[IIOpNum].isOptionalDef();
309 
310  // If the instruction requires a register in a different class, create
311  // a new virtual register and copy the value into it, but first attempt to
312  // shrink VReg's register class within reason. For example, if VReg == GR32
313  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
314  if (II) {
315  const TargetRegisterClass *OpRC = nullptr;
316  if (IIOpNum < II->getNumOperands())
317  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
318 
319  if (OpRC) {
320  unsigned MinNumRegs = MinRCSize;
321  // Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
322  // virtual register.
323  if (Op.isMachineOpcode() &&
324  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
325  MinNumRegs = 0;
326 
327  const TargetRegisterClass *ConstrainedRC
328  = MRI->constrainRegClass(VReg, OpRC, MinNumRegs);
329  if (!ConstrainedRC) {
330  OpRC = TRI->getAllocatableClass(OpRC);
331  assert(OpRC && "Constraints cannot be fulfilled for allocation");
332  Register NewVReg = MRI->createVirtualRegister(OpRC);
333  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
334  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
335  VReg = NewVReg;
336  } else {
337  assert(ConstrainedRC->isAllocatable() &&
338  "Constraining an allocatable VReg produced an unallocatable class?");
339  }
340  }
341  }
342 
343  // If this value has only one use, that use is a kill. This is a
344  // conservative approximation. InstrEmitter does trivial coalescing
345  // with CopyFromReg nodes, so don't emit kill flags for them.
346  // Avoid kill flags on Schedule cloned nodes, since there will be
347  // multiple uses.
348  // Tied operands are never killed, so we need to check that. And that
349  // means we need to determine the index of the operand.
350  bool isKill = Op.hasOneUse() &&
351  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
352  !IsDebug &&
353  !(IsClone || IsCloned);
354  if (isKill) {
355  unsigned Idx = MIB->getNumOperands();
356  while (Idx > 0 &&
357  MIB->getOperand(Idx-1).isReg() &&
358  MIB->getOperand(Idx-1).isImplicit())
359  --Idx;
360  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
361  if (isTied)
362  isKill = false;
363  }
364 
365  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
366  getDebugRegState(IsDebug));
367 }
368 
369 /// AddOperand - Add the specified operand to the specified machine instr. II
370 /// specifies the instruction information for the node, and IIOpNum is the
371 /// operand number (in the II) that we are adding.
372 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
373  SDValue Op,
374  unsigned IIOpNum,
375  const MCInstrDesc *II,
376  DenseMap<SDValue, Register> &VRBaseMap,
377  bool IsDebug, bool IsClone, bool IsCloned) {
378  if (Op.isMachineOpcode()) {
379  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
380  IsDebug, IsClone, IsCloned);
381  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
382  MIB.addImm(C->getSExtValue());
383  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
384  MIB.addFPImm(F->getConstantFPValue());
385  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
386  Register VReg = R->getReg();
387  MVT OpVT = Op.getSimpleValueType();
388  const TargetRegisterClass *IIRC =
389  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
390  : nullptr;
391  const TargetRegisterClass *OpRC =
392  TLI->isTypeLegal(OpVT)
393  ? TLI->getRegClassFor(OpVT,
394  Op.getNode()->isDivergent() ||
395  (IIRC && TRI->isDivergentRegClass(IIRC)))
396  : nullptr;
397 
398  if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
399  Register NewVReg = MRI->createVirtualRegister(IIRC);
400  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
401  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
402  VReg = NewVReg;
403  }
404  // Turn additional physreg operands into implicit uses on non-variadic
405  // instructions. This is used by call and return instructions passing
406  // arguments in registers.
407  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
408  MIB.addReg(VReg, getImplRegState(Imp));
409  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
410  MIB.addRegMask(RM->getRegMask());
411  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
412  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
413  TGA->getTargetFlags());
414  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
415  MIB.addMBB(BBNode->getBasicBlock());
416  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
417  MIB.addFrameIndex(FI->getIndex());
418  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
419  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
420  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
421  int Offset = CP->getOffset();
422  Align Alignment = CP->getAlign();
423 
424  unsigned Idx;
426  if (CP->isMachineConstantPoolEntry())
427  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
428  else
429  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
430  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
431  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
432  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
433  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
434  MIB.addSym(SymNode->getMCSymbol());
435  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
436  MIB.addBlockAddress(BA->getBlockAddress(),
437  BA->getOffset(),
438  BA->getTargetFlags());
439  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
440  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
441  } else {
442  assert(Op.getValueType() != MVT::Other &&
443  Op.getValueType() != MVT::Glue &&
444  "Chain and glue operands should occur at end of operand list!");
445  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
446  IsDebug, IsClone, IsCloned);
447  }
448 }
449 
450 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
451  MVT VT, bool isDivergent, const DebugLoc &DL) {
452  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
453  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
454 
455  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
456  // within reason.
457  if (RC && RC != VRC)
458  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
459 
460  // VReg has been adjusted. It can be used with SubIdx operands now.
461  if (RC)
462  return VReg;
463 
464  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
465  // register instead.
466  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
467  assert(RC && "No legal register class for VT supports that SubIdx");
468  Register NewReg = MRI->createVirtualRegister(RC);
469  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
470  .addReg(VReg);
471  return NewReg;
472 }
473 
474 /// EmitSubregNode - Generate machine code for subreg nodes.
475 ///
476 void InstrEmitter::EmitSubregNode(SDNode *Node,
477  DenseMap<SDValue, Register> &VRBaseMap,
478  bool IsClone, bool IsCloned) {
479  Register VRBase;
480  unsigned Opc = Node->getMachineOpcode();
481 
482  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
483  // the CopyToReg'd destination register instead of creating a new vreg.
484  for (SDNode *User : Node->uses()) {
485  if (User->getOpcode() == ISD::CopyToReg &&
486  User->getOperand(2).getNode() == Node) {
487  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
488  if (DestReg.isVirtual()) {
489  VRBase = DestReg;
490  break;
491  }
492  }
493  }
494 
495  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
496  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
497  // constraints on the %dst register, COPY can target all legal register
498  // classes.
499  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
500  const TargetRegisterClass *TRC =
501  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
502 
503  Register Reg;
505  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
506  if (R && Register::isPhysicalRegister(R->getReg())) {
507  Reg = R->getReg();
508  DefMI = nullptr;
509  } else {
510  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
511  DefMI = MRI->getVRegDef(Reg);
512  }
513 
514  Register SrcReg, DstReg;
515  unsigned DefSubIdx;
516  if (DefMI &&
517  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
518  SubIdx == DefSubIdx &&
519  TRC == MRI->getRegClass(SrcReg)) {
520  // Optimize these:
521  // r1025 = s/zext r1024, 4
522  // r1026 = extract_subreg r1025, 4
523  // to a copy
524  // r1026 = copy r1024
525  VRBase = MRI->createVirtualRegister(TRC);
526  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
527  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
528  MRI->clearKillFlags(SrcReg);
529  } else {
530  // Reg may not support a SubIdx sub-register, and we may need to
531  // constrain its register class or issue a COPY to a compatible register
532  // class.
533  if (Reg.isVirtual())
534  Reg = ConstrainForSubReg(Reg, SubIdx,
535  Node->getOperand(0).getSimpleValueType(),
536  Node->isDivergent(), Node->getDebugLoc());
537  // Create the destreg if it is missing.
538  if (!VRBase)
539  VRBase = MRI->createVirtualRegister(TRC);
540 
541  // Create the extract_subreg machine instruction.
542  MachineInstrBuilder CopyMI =
543  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
544  TII->get(TargetOpcode::COPY), VRBase);
545  if (Reg.isVirtual())
546  CopyMI.addReg(Reg, 0, SubIdx);
547  else
548  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
549  }
550  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
551  Opc == TargetOpcode::SUBREG_TO_REG) {
552  SDValue N0 = Node->getOperand(0);
553  SDValue N1 = Node->getOperand(1);
554  SDValue N2 = Node->getOperand(2);
555  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
556 
557  // Figure out the register class to create for the destreg. It should be
558  // the largest legal register class supporting SubIdx sub-registers.
559  // RegisterCoalescer will constrain it further if it decides to eliminate
560  // the INSERT_SUBREG instruction.
561  //
562  // %dst = INSERT_SUBREG %src, %sub, SubIdx
563  //
564  // is lowered by TwoAddressInstructionPass to:
565  //
566  // %dst = COPY %src
567  // %dst:SubIdx = COPY %sub
568  //
569  // There is no constraint on the %src register class.
570  //
571  const TargetRegisterClass *SRC =
572  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
573  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
574  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
575 
576  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
577  VRBase = MRI->createVirtualRegister(SRC);
578 
579  // Create the insert_subreg or subreg_to_reg machine instruction.
580  MachineInstrBuilder MIB =
581  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
582 
583  // If creating a subreg_to_reg, then the first input operand
584  // is an implicit value immediate, otherwise it's a register
585  if (Opc == TargetOpcode::SUBREG_TO_REG) {
586  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
587  MIB.addImm(SD->getZExtValue());
588  } else
589  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
590  IsClone, IsCloned);
591  // Add the subregister being inserted
592  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
593  IsClone, IsCloned);
594  MIB.addImm(SubIdx);
595  MBB->insert(InsertPos, MIB);
596  } else
597  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
598 
599  SDValue Op(Node, 0);
600  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
601  (void)isNew; // Silence compiler warning.
602  assert(isNew && "Node emitted out of order - early");
603 }
604 
605 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
606 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
607 /// register is constrained to be in a particular register class.
608 ///
609 void
610 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
611  DenseMap<SDValue, Register> &VRBaseMap) {
612  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
613 
614  // Create the new VReg in the destination class and emit a copy.
615  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
616  const TargetRegisterClass *DstRC =
617  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
618  Register NewVReg = MRI->createVirtualRegister(DstRC);
619  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
620  NewVReg).addReg(VReg);
621 
622  SDValue Op(Node, 0);
623  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
624  (void)isNew; // Silence compiler warning.
625  assert(isNew && "Node emitted out of order - early");
626 }
627 
628 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
629 ///
630 void InstrEmitter::EmitRegSequence(SDNode *Node,
631  DenseMap<SDValue, Register> &VRBaseMap,
632  bool IsClone, bool IsCloned) {
633  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
634  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
635  Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
636  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
637  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
638  unsigned NumOps = Node->getNumOperands();
639  // If the input pattern has a chain, then the root of the corresponding
640  // output pattern will get a chain as well. This can happen to be a
641  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
642  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
643  --NumOps; // Ignore chain if it exists.
644 
645  assert((NumOps & 1) == 1 &&
646  "REG_SEQUENCE must have an odd number of operands!");
647  for (unsigned i = 1; i != NumOps; ++i) {
648  SDValue Op = Node->getOperand(i);
649  if ((i & 1) == 0) {
650  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
651  // Skip physical registers as they don't have a vreg to get and we'll
652  // insert copies for them in TwoAddressInstructionPass anyway.
653  if (!R || !Register::isPhysicalRegister(R->getReg())) {
654  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
655  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
656  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
657  const TargetRegisterClass *SRC =
658  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
659  if (SRC && SRC != RC) {
660  MRI->setRegClass(NewVReg, SRC);
661  RC = SRC;
662  }
663  }
664  }
665  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
666  IsClone, IsCloned);
667  }
668 
669  MBB->insert(InsertPos, MIB);
670  SDValue Op(Node, 0);
671  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
672  (void)isNew; // Silence compiler warning.
673  assert(isNew && "Node emitted out of order - early");
674 }
675 
676 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
677 ///
678 MachineInstr *
680  DenseMap<SDValue, Register> &VRBaseMap) {
681  MDNode *Var = SD->getVariable();
682  MDNode *Expr = SD->getExpression();
683  DebugLoc DL = SD->getDebugLoc();
684  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
685  "Expected inlined-at fields to agree");
686 
687  SD->setIsEmitted();
688 
689  ArrayRef<SDDbgOperand> LocationOps = SD->getLocationOps();
690  assert(!LocationOps.empty() && "dbg_value with no location operands?");
691 
692  if (SD->isInvalidated())
693  return EmitDbgNoLocation(SD);
694 
695  // Emit variadic dbg_value nodes as DBG_VALUE_LIST.
696  if (SD->isVariadic()) {
697  // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
698  const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
699  // Build the DBG_VALUE_LIST instruction base.
700  auto MIB = BuildMI(*MF, DL, DbgValDesc);
701  MIB.addMetadata(Var);
702  MIB.addMetadata(Expr);
703  AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps, VRBaseMap);
704  return &*MIB;
705  }
706 
707  // Attempt to produce a DBG_INSTR_REF if we've been asked to.
708  // We currently exclude the possibility of instruction references for
709  // variadic nodes; if at some point we enable them, this should be moved
710  // above the variadic block.
711  if (EmitDebugInstrRefs)
712  if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
713  return InstrRef;
714 
715  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
716 }
717 
719  MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
720  ArrayRef<SDDbgOperand> LocationOps,
721  DenseMap<SDValue, Register> &VRBaseMap) {
722  for (const SDDbgOperand &Op : LocationOps) {
723  switch (Op.getKind()) {
725  MIB.addFrameIndex(Op.getFrameIx());
726  break;
727  case SDDbgOperand::VREG:
728  MIB.addReg(Op.getVReg());
729  break;
730  case SDDbgOperand::SDNODE: {
731  SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
732  // It's possible we replaced this SDNode with other(s) and therefore
733  // didn't generate code for it. It's better to catch these cases where
734  // they happen and transfer the debug info, but trying to guarantee that
735  // in all cases would be very fragile; this is a safeguard for any
736  // that were missed.
737  if (VRBaseMap.count(V) == 0)
738  MIB.addReg(0U); // undef
739  else
740  AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
741  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
742  } break;
743  case SDDbgOperand::CONST: {
744  const Value *V = Op.getConst();
745  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
746  if (CI->getBitWidth() > 64)
747  MIB.addCImm(CI);
748  else
749  MIB.addImm(CI->getSExtValue());
750  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
751  MIB.addFPImm(CF);
752  } else if (isa<ConstantPointerNull>(V)) {
753  // Note: This assumes that all nullptr constants are zero-valued.
754  MIB.addImm(0);
755  } else {
756  // Could be an Undef. In any case insert an Undef so we can see what we
757  // dropped.
758  MIB.addReg(0U);
759  }
760  } break;
761  }
762  }
763 }
764 
765 MachineInstr *
767  DenseMap<SDValue, Register> &VRBaseMap) {
768  assert(!SD->isVariadic());
769  SDDbgOperand DbgOperand = SD->getLocationOps()[0];
770  MDNode *Var = SD->getVariable();
771  DIExpression *Expr = (DIExpression*)SD->getExpression();
772  DebugLoc DL = SD->getDebugLoc();
773  const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
774 
775  // Handle variable locations that don't actually depend on the instructions
776  // in the program: constants and stack locations.
777  if (DbgOperand.getKind() == SDDbgOperand::FRAMEIX ||
778  DbgOperand.getKind() == SDDbgOperand::CONST)
779  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
780 
781  // Immediately fold any indirectness from the LLVM-IR intrinsic into the
782  // expression:
783  if (SD->isIndirect()) {
784  std::vector<uint64_t> Elts = {dwarf::DW_OP_deref};
785  Expr = DIExpression::append(Expr, Elts);
786  }
787 
788  // It may not be immediately possible to identify the MachineInstr that
789  // defines a VReg, it can depend for example on the order blocks are
790  // emitted in. When this happens, or when further analysis is needed later,
791  // produce an instruction like this:
792  //
793  // DBG_INSTR_REF %0:gr64, 0, !123, !456
794  //
795  // i.e., point the instruction at the vreg, and patch it up later in
796  // MachineFunction::finalizeDebugInstrRefs.
797  auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
798  auto MIB = BuildMI(*MF, DL, RefII);
799  MIB.addReg(VReg);
800  MIB.addImm(0);
801  MIB.addMetadata(Var);
802  MIB.addMetadata(Expr);
803  return MIB;
804  };
805 
806  // Try to find both the defined register and the instruction defining it.
807  MachineInstr *DefMI = nullptr;
808  unsigned VReg;
809 
810  if (DbgOperand.getKind() == SDDbgOperand::VREG) {
811  VReg = DbgOperand.getVReg();
812 
813  // No definition means that block hasn't been emitted yet. Leave a vreg
814  // reference to be fixed later.
815  if (!MRI->hasOneDef(VReg))
816  return EmitHalfDoneInstrRef(VReg);
817 
818  DefMI = &*MRI->def_instr_begin(VReg);
819  } else {
820  assert(DbgOperand.getKind() == SDDbgOperand::SDNODE);
821  // Look up the corresponding VReg for the given SDNode, if any.
822  SDNode *Node = DbgOperand.getSDNode();
823  SDValue Op = SDValue(Node, DbgOperand.getResNo());
825  // No VReg -> produce a DBG_VALUE $noreg instead.
826  if (I==VRBaseMap.end())
827  return EmitDbgNoLocation(SD);
828 
829  // Try to pick out a defining instruction at this point.
830  VReg = getVR(Op, VRBaseMap);
831 
832  // Again, if there's no instruction defining the VReg right now, fix it up
833  // later.
834  if (!MRI->hasOneDef(VReg))
835  return EmitHalfDoneInstrRef(VReg);
836 
837  DefMI = &*MRI->def_instr_begin(VReg);
838  }
839 
840  // Avoid copy like instructions: they don't define values, only move them.
841  // Leave a virtual-register reference until it can be fixed up later, to find
842  // the underlying value definition.
843  if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
844  return EmitHalfDoneInstrRef(VReg);
845 
846  auto MIB = BuildMI(*MF, DL, RefII);
847 
848  // Find the operand number which defines the specified VReg.
849  unsigned OperandIdx = 0;
850  for (const auto &MO : DefMI->operands()) {
851  if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
852  break;
853  ++OperandIdx;
854  }
855  assert(OperandIdx < DefMI->getNumOperands());
856 
857  // Make the DBG_INSTR_REF refer to that instruction, and that operand.
858  unsigned InstrNum = DefMI->getDebugInstrNum();
859  MIB.addImm(InstrNum);
860  MIB.addImm(OperandIdx);
861  MIB.addMetadata(Var);
862  MIB.addMetadata(Expr);
863  return &*MIB;
864 }
865 
867  // An invalidated SDNode must generate an undef DBG_VALUE: although the
868  // original value is no longer computed, earlier DBG_VALUEs live ranges
869  // must not leak into later code.
870  MDNode *Var = SD->getVariable();
871  MDNode *Expr = SD->getExpression();
872  DebugLoc DL = SD->getDebugLoc();
873  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
874  MIB.addReg(0U);
875  MIB.addReg(0U);
876  MIB.addMetadata(Var);
877  MIB.addMetadata(Expr);
878  return &*MIB;
879 }
880 
881 MachineInstr *
883  DenseMap<SDValue, Register> &VRBaseMap) {
884  MDNode *Var = SD->getVariable();
885  DIExpression *Expr = SD->getExpression();
886  DebugLoc DL = SD->getDebugLoc();
887  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
888 
889  assert(SD->getLocationOps().size() == 1 &&
890  "Non variadic dbg_value should have only one location op");
891 
892  // See about constant-folding the expression.
893  // Copy the location operand in case we replace it.
894  SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
895  if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
896  const Value *V = LocationOps[0].getConst();
897  if (auto *C = dyn_cast<ConstantInt>(V)) {
898  std::tie(Expr, C) = Expr->constantFold(C);
899  LocationOps[0] = SDDbgOperand::fromConst(C);
900  }
901  }
902 
903  // Emit non-variadic dbg_value nodes as DBG_VALUE.
904  // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
905  auto MIB = BuildMI(*MF, DL, II);
906  AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
907 
908  if (SD->isIndirect())
909  MIB.addImm(0U);
910  else
911  MIB.addReg(0U);
912 
913  return MIB.addMetadata(Var).addMetadata(Expr);
914 }
915 
916 MachineInstr *
918  MDNode *Label = SD->getLabel();
919  DebugLoc DL = SD->getDebugLoc();
920  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
921  "Expected inlined-at fields to agree");
922 
923  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
924  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
925  MIB.addMetadata(Label);
926 
927  return &*MIB;
928 }
929 
930 /// EmitMachineNode - Generate machine code for a target-specific node and
931 /// needed dependencies.
932 ///
933 void InstrEmitter::
934 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
935  DenseMap<SDValue, Register> &VRBaseMap) {
936  unsigned Opc = Node->getMachineOpcode();
937 
938  // Handle subreg insert/extract specially
939  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
940  Opc == TargetOpcode::INSERT_SUBREG ||
941  Opc == TargetOpcode::SUBREG_TO_REG) {
942  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
943  return;
944  }
945 
946  // Handle COPY_TO_REGCLASS specially.
947  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
948  EmitCopyToRegClassNode(Node, VRBaseMap);
949  return;
950  }
951 
952  // Handle REG_SEQUENCE specially.
953  if (Opc == TargetOpcode::REG_SEQUENCE) {
954  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
955  return;
956  }
957 
958  if (Opc == TargetOpcode::IMPLICIT_DEF)
959  // We want a unique VR for each IMPLICIT_DEF use.
960  return;
961 
962  const MCInstrDesc &II = TII->get(Opc);
963  unsigned NumResults = CountResults(Node);
964  unsigned NumDefs = II.getNumDefs();
965  const MCPhysReg *ScratchRegs = nullptr;
966 
967  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
968  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
969  // Stackmaps do not have arguments and do not preserve their calling
970  // convention. However, to simplify runtime support, they clobber the same
971  // scratch registers as AnyRegCC.
972  unsigned CC = CallingConv::AnyReg;
973  if (Opc == TargetOpcode::PATCHPOINT) {
974  CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
975  NumDefs = NumResults;
976  }
977  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
978  } else if (Opc == TargetOpcode::STATEPOINT) {
979  NumDefs = NumResults;
980  }
981 
982  unsigned NumImpUses = 0;
983  unsigned NodeOperands =
984  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
985  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
986  II.isVariadic() && II.variadicOpsAreDefs();
987  bool HasPhysRegOuts = NumResults > NumDefs &&
988  II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
989 #ifndef NDEBUG
990  unsigned NumMIOperands = NodeOperands + NumResults;
991  if (II.isVariadic())
992  assert(NumMIOperands >= II.getNumOperands() &&
993  "Too few operands for a variadic node!");
994  else
995  assert(NumMIOperands >= II.getNumOperands() &&
996  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
997  NumImpUses &&
998  "#operands for dag node doesn't match .td file!");
999 #endif
1000 
1001  // Create the new machine instruction.
1002  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
1003 
1004  // Add result register values for things that are defined by this
1005  // instruction.
1006  if (NumResults) {
1007  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1008 
1009  // Transfer any IR flags from the SDNode to the MachineInstr
1010  MachineInstr *MI = MIB.getInstr();
1011  const SDNodeFlags Flags = Node->getFlags();
1012  if (Flags.hasNoSignedZeros())
1013  MI->setFlag(MachineInstr::MIFlag::FmNsz);
1014 
1015  if (Flags.hasAllowReciprocal())
1016  MI->setFlag(MachineInstr::MIFlag::FmArcp);
1017 
1018  if (Flags.hasNoNaNs())
1019  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1020 
1021  if (Flags.hasNoInfs())
1022  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1023 
1024  if (Flags.hasAllowContract())
1025  MI->setFlag(MachineInstr::MIFlag::FmContract);
1026 
1027  if (Flags.hasApproximateFuncs())
1028  MI->setFlag(MachineInstr::MIFlag::FmAfn);
1029 
1030  if (Flags.hasAllowReassociation())
1031  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1032 
1033  if (Flags.hasNoUnsignedWrap())
1034  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1035 
1036  if (Flags.hasNoSignedWrap())
1037  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1038 
1039  if (Flags.hasExact())
1040  MI->setFlag(MachineInstr::MIFlag::IsExact);
1041 
1042  if (Flags.hasNoFPExcept())
1043  MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1044  }
1045 
1046  // Emit all of the actual operands of this instruction, adding them to the
1047  // instruction as appropriate.
1048  bool HasOptPRefs = NumDefs > NumResults;
1049  assert((!HasOptPRefs || !HasPhysRegOuts) &&
1050  "Unable to cope with optional defs and phys regs defs!");
1051  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1052  for (unsigned i = NumSkip; i != NodeOperands; ++i)
1053  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1054  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1055 
1056  // Add scratch registers as implicit def and early clobber
1057  if (ScratchRegs)
1058  for (unsigned i = 0; ScratchRegs[i]; ++i)
1059  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1061 
1062  // Set the memory reference descriptions of this instruction now that it is
1063  // part of the function.
1064  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1065 
1066  // Set the CFI type.
1067  MIB->setCFIType(*MF, Node->getCFIType());
1068 
1069  // Insert the instruction into position in the block. This needs to
1070  // happen before any custom inserter hook is called so that the
1071  // hook knows where in the block to insert the replacement code.
1072  MBB->insert(InsertPos, MIB);
1073 
1074  // The MachineInstr may also define physregs instead of virtregs. These
1075  // physreg values can reach other instructions in different ways:
1076  //
1077  // 1. When there is a use of a Node value beyond the explicitly defined
1078  // virtual registers, we emit a CopyFromReg for one of the implicitly
1079  // defined physregs. This only happens when HasPhysRegOuts is true.
1080  //
1081  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1082  //
1083  // 3. A glued instruction may implicitly use a physreg.
1084  //
1085  // 4. A glued instruction may use a RegisterSDNode operand.
1086  //
1087  // Collect all the used physreg defs, and make sure that any unused physreg
1088  // defs are marked as dead.
1089  SmallVector<Register, 8> UsedRegs;
1090 
1091  // Additional results must be physical register defs.
1092  if (HasPhysRegOuts) {
1093  for (unsigned i = NumDefs; i < NumResults; ++i) {
1094  Register Reg = II.getImplicitDefs()[i - NumDefs];
1095  if (!Node->hasAnyUseOfValue(i))
1096  continue;
1097  // This implicitly defined physreg has a use.
1098  UsedRegs.push_back(Reg);
1099  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
1100  }
1101  }
1102 
1103  // Scan the glue chain for any used physregs.
1104  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1105  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1106  if (F->getOpcode() == ISD::CopyFromReg) {
1107  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1108  continue;
1109  } else if (F->getOpcode() == ISD::CopyToReg) {
1110  // Skip CopyToReg nodes that are internal to the glue chain.
1111  continue;
1112  }
1113  // Collect declared implicit uses.
1114  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1115  UsedRegs.append(MCID.getImplicitUses(),
1116  MCID.getImplicitUses() + MCID.getNumImplicitUses());
1117  // In addition to declared implicit uses, we must also check for
1118  // direct RegisterSDNode operands.
1119  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1120  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1121  Register Reg = R->getReg();
1122  if (Reg.isPhysical())
1123  UsedRegs.push_back(Reg);
1124  }
1125  }
1126  }
1127 
1128  // Finally mark unused registers as dead.
1129  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
1130  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1131 
1132  // STATEPOINT is too 'dynamic' to have meaningful machine description.
1133  // We have to manually tie operands.
1134  if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1135  assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1136  MachineInstr *MI = MIB;
1137  unsigned Def = 0;
1139  assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1140  unsigned Use = (unsigned)First;
1141  while (Def < NumDefs) {
1142  if (MI->getOperand(Use).isReg())
1143  MI->tieOperands(Def++, Use);
1145  }
1146  }
1147 
1148  // Run post-isel target hook to adjust this instruction if needed.
1149  if (II.hasPostISelHook())
1150  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1151 }
1152 
1153 /// EmitSpecialNode - Generate machine code for a target-independent node and
1154 /// needed dependencies.
1155 void InstrEmitter::
1156 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1157  DenseMap<SDValue, Register> &VRBaseMap) {
1158  switch (Node->getOpcode()) {
1159  default:
1160 #ifndef NDEBUG
1161  Node->dump();
1162 #endif
1163  llvm_unreachable("This target-independent node should have been selected!");
1164  case ISD::EntryToken:
1165  case ISD::MERGE_VALUES:
1166  case ISD::TokenFactor: // fall thru
1167  break;
1168  case ISD::CopyToReg: {
1169  Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1170  SDValue SrcVal = Node->getOperand(2);
1171  if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1172  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1173  // Instead building a COPY to that vreg destination, build an
1174  // IMPLICIT_DEF instruction instead.
1175  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1176  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1177  break;
1178  }
1179  Register SrcReg;
1180  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1181  SrcReg = R->getReg();
1182  else
1183  SrcReg = getVR(SrcVal, VRBaseMap);
1184 
1185  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1186  break;
1187 
1188  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1189  DestReg).addReg(SrcReg);
1190  break;
1191  }
1192  case ISD::CopyFromReg: {
1193  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1194  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1195  break;
1196  }
1197  case ISD::EH_LABEL:
1198  case ISD::ANNOTATION_LABEL: {
1199  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1202  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1203  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1204  TII->get(Opc)).addSym(S);
1205  break;
1206  }
1207 
1208  case ISD::LIFETIME_START:
1209  case ISD::LIFETIME_END: {
1210  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1213  auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1214  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1215  .addFrameIndex(FI->getIndex());
1216  break;
1217  }
1218 
1219  case ISD::PSEUDO_PROBE: {
1220  unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1221  auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1222  auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1223  auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1224 
1225  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1226  .addImm(Guid)
1227  .addImm(Index)
1228  .addImm((uint8_t)PseudoProbeType::Block)
1229  .addImm(Attr);
1230  break;
1231  }
1232 
1233  case ISD::INLINEASM:
1234  case ISD::INLINEASM_BR: {
1235  unsigned NumOps = Node->getNumOperands();
1236  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1237  --NumOps; // Ignore the glue operand.
1238 
1239  // Create the inline asm machine instruction.
1240  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1243  MachineInstrBuilder MIB =
1244  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1245 
1246  // Add the asm string as an external symbol operand.
1247  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1248  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1249  MIB.addExternalSymbol(AsmStr);
1250 
1251  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1252  // bits.
1253  int64_t ExtraInfo =
1254  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1255  getZExtValue();
1256  MIB.addImm(ExtraInfo);
1257 
1258  // Remember to operand index of the group flags.
1259  SmallVector<unsigned, 8> GroupIdx;
1260 
1261  // Remember registers that are part of early-clobber defs.
1262  SmallVector<unsigned, 8> ECRegs;
1263 
1264  // Add all of the operand registers to the instruction.
1265  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1266  unsigned Flags =
1267  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1268  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1269 
1270  GroupIdx.push_back(MIB->getNumOperands());
1271  MIB.addImm(Flags);
1272  ++i; // Skip the ID value.
1273 
1274  switch (InlineAsm::getKind(Flags)) {
1275  default: llvm_unreachable("Bad flags!");
1277  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1278  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1279  // FIXME: Add dead flags for physical and virtual registers defined.
1280  // For now, mark physical register defs as implicit to help fast
1281  // regalloc. This makes inline asm look a lot like calls.
1282  MIB.addReg(Reg,
1285  }
1286  break;
1289  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1290  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1291  MIB.addReg(Reg,
1294  ECRegs.push_back(Reg);
1295  }
1296  break;
1297  case InlineAsm::Kind_RegUse: // Use of register.
1298  case InlineAsm::Kind_Imm: // Immediate.
1299  case InlineAsm::Kind_Mem: // Non-function addressing mode.
1300  // The addressing mode has been selected, just add all of the
1301  // operands to the machine instruction.
1302  for (unsigned j = 0; j != NumVals; ++j, ++i)
1303  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1304  /*IsDebug=*/false, IsClone, IsCloned);
1305 
1306  // Manually set isTied bits.
1308  unsigned DefGroup = 0;
1309  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1310  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1311  unsigned UseIdx = GroupIdx.back() + 1;
1312  for (unsigned j = 0; j != NumVals; ++j)
1313  MIB->tieOperands(DefIdx + j, UseIdx + j);
1314  }
1315  }
1316  break;
1317  case InlineAsm::Kind_Func: // Function addressing mode.
1318  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1319  SDValue Op = Node->getOperand(i);
1320  AddOperand(MIB, Op, 0, nullptr, VRBaseMap,
1321  /*IsDebug=*/false, IsClone, IsCloned);
1322 
1323  // Adjust Target Flags for function reference.
1324  if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
1325  unsigned NewFlags =
1327  TGA->getGlobal());
1328  unsigned LastIdx = MIB.getInstr()->getNumOperands() - 1;
1329  MIB.getInstr()->getOperand(LastIdx).setTargetFlags(NewFlags);
1330  }
1331  }
1332  }
1333  }
1334 
1335  // GCC inline assembly allows input operands to also be early-clobber
1336  // output operands (so long as the operand is written only after it's
1337  // used), but this does not match the semantics of our early-clobber flag.
1338  // If an early-clobber operand register is also an input operand register,
1339  // then remove the early-clobber flag.
1340  for (unsigned Reg : ECRegs) {
1341  if (MIB->readsRegister(Reg, TRI)) {
1342  MachineOperand *MO =
1343  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1344  assert(MO && "No def operand for clobbered register?");
1345  MO->setIsEarlyClobber(false);
1346  }
1347  }
1348 
1349  // Get the mdnode from the asm if it exists and add it to the instruction.
1350  SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1351  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1352  if (MD)
1353  MIB.addMetadata(MD);
1354 
1355  MBB->insert(InsertPos, MIB);
1356  break;
1357  }
1358  }
1359 }
1360 
1361 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1362 /// at the given position in the given block.
1364  MachineBasicBlock::iterator insertpos,
1365  bool UseInstrRefDebugInfo)
1366  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1367  TII(MF->getSubtarget().getInstrInfo()),
1368  TRI(MF->getSubtarget().getRegisterInfo()),
1369  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1370  InsertPos(insertpos) {
1371  EmitDebugInstrRefs = UseInstrRefDebugInfo;
1372 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:637
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::SDDbgValue::getExpression
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Definition: SDNodeDbgValue.h:183
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:133
llvm::SDDbgOperand::fromConst
static SDDbgOperand fromConst(const Value *Const)
Definition: SDNodeDbgValue.h:80
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2161
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2043
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2371
llvm::InlineAsm::Op_ExtraInfo
@ Op_ExtraInfo
Definition: InlineAsm.h:221
llvm::CallingConv::AnyReg
@ AnyReg
Used for dynamic register based calls (e.g.
Definition: CallingConv.h:60
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Definition: MachineFunction.cpp:1479
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::TargetLowering::getScratchRegisters
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: TargetLowering.h:4470
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1225
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:121
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1224
llvm::LLVMTargetMachine::usesPhysRegsForValues
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
Definition: TargetMachine.h:483
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:405
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::SDDbgOperand::getResNo
unsigned getResNo() const
Returns the ResNo for a register ref.
Definition: SDNodeDbgValue.h:48
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:282
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:302
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:117
llvm::DenseMapIterator
Definition: DenseMap.h:57
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:369
TargetInstrInfo.h
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1035
llvm::InstrEmitter::CountResults
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Definition: InstrEmitter.cpp:43
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::SDDbgOperand
Holds the information for a single machine location through SDISel; either an SDNode,...
Definition: SDNodeDbgValue.h:31
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
SDNodeDbgValue.h
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2195
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SDDbgValue::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:215
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:514
MachineRegisterInfo.h
llvm::InstrEmitter::AddDbgValueLocationOps
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
Definition: InstrEmitter.cpp:718
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:245
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1244
llvm::SDDbgOperand::getVReg
unsigned getVReg() const
Returns the Virtual Register for a VReg.
Definition: SDNodeDbgValue.h:66
llvm::TargetLowering::AdjustInstrPostInstrSelection
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: SelectionDAGISel.cpp:303
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:46
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:540
llvm::InstrEmitter::EmitDbgNoLocation
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Definition: InstrEmitter.cpp:866
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2237
TargetMachine.h
llvm::SDDbgLabel
Holds the information from a dbg_label node through SDISel.
Definition: SDNodeDbgValue.h:242
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
countOperands
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
Definition: InstrEmitter.cpp:59
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:244
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::MCInstrDesc::getNumImplicitUses
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:568
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1862
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SDDbgValue::isIndirect
bool isIndirect() const
Returns whether this is an indirect value.
Definition: SDNodeDbgValue.h:210
llvm::MCInstrDesc::getImplicitDefs
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:587
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:240
llvm::MCInstrDesc::getNumImplicitDefs
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:590
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:222
llvm::SDDbgOperand::VREG
@ VREG
Value is a virtual register.
Definition: SDNodeDbgValue.h:37
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1785
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
llvm::SmallVectorImpl::append
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
llvm::InlineAsm::Op_AsmString
@ Op_AsmString
Definition: InlineAsm.h:219
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:351
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RegisterMaskSDNode
Definition: SelectionDAGNodes.h:2177
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:255
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::DIExpression::append
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
Definition: DebugInfoMetadata.cpp:1587
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:433
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:1145
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:243
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:771
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SDDbgLabel::getLabel
MDNode * getLabel() const
Returns the MDNode pointer for the label.
Definition: SDNodeDbgValue.h:252
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1631
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:939
llvm::InstrEmitter::EmitDbgLabel
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
Definition: InstrEmitter.cpp:917
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::SDDbgOperand::getKind
Kind getKind() const
Definition: SDNodeDbgValue.h:39
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MachineConstantPool.h
llvm::BasicBlockSDNode
Definition: SelectionDAGNodes.h:1967
llvm::SDDbgValue::isInvalidated
bool isInvalidated() const
Definition: SDNodeDbgValue.h:225
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::TargetSubtargetInfo::classifyGlobalFunctionReference
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
Definition: TargetSubtargetInfo.h:318
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:689
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1597
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:452
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1390
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1039
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1883
Dwarf.h
llvm::InstrEmitter::EmitDbgInstrRef
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
Definition: InstrEmitter.cpp:766
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:532
llvm::SDValue::getMachineOpcode
unsigned getMachineOpcode() const
Definition: SelectionDAGNodes.h:1173
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SDDbgOperand::getSDNode
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
Definition: SDNodeDbgValue.h:42
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:297
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:805
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
InstrEmitter.h
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
j
return j(j<< 16)
llvm::SDDbgValue::isVariadic
bool isVariadic() const
Definition: SDNodeDbgValue.h:212
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::SDDbgLabel::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:255
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:558
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1350
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:262
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1327
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::TargetIndexSDNode
Completely target-dependent object reference.
Definition: SelectionDAGNodes.h:1946
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:557
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1707
llvm::SDDbgOperand::SDNODE
@ SDNODE
Value is the result of an expression.
Definition: SDNodeDbgValue.h:34
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:258
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:242
StackMaps.h
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
PseudoProbe.h
MinRCSize
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
Definition: InstrEmitter.cpp:38
llvm::SDNodeFlags
These are IR-level optimization flags that may be propagated to SDNodes.
Definition: SelectionDAGNodes.h:379
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::SDDbgValue::getVariable
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
Definition: SDNodeDbgValue.h:180
llvm::SDDbgValue::getLocationOps
ArrayRef< SDDbgOperand > getLocationOps() const
Definition: SDNodeDbgValue.h:185
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::PseudoProbeType::Block
@ Block
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:241
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:363
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::SDDbgOperand::FRAMEIX
@ FRAMEIX
Value is contents of a stack location.
Definition: SDNodeDbgValue.h:36
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:896
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::InstrEmitter::InstrEmitter
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos, bool UseInstrRefDebugInfo)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
Definition: InstrEmitter.cpp:1363
llvm::MachineInstr::setCFIType
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
Definition: MachineInstr.cpp:510
llvm::SDDbgOperand::CONST
@ CONST
Value is a constant.
Definition: SDNodeDbgValue.h:35
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:82
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:130
llvm::omp::RTLDependInfoFields::Flags
@ Flags
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
RN
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
Definition: README_P9.txt:262
llvm::InstrEmitter::EmitDbgValueFromSingleOp
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
Definition: InstrEmitter.cpp:882
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SDDbgValue::setIsEmitted
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Definition: SDNodeDbgValue.h:229
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1094
llvm::SDValue::isMachineOpcode
bool isMachineOpcode() const
Definition: SelectionDAGNodes.h:1169
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1479
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:543
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MCInstrDesc::getImplicitUses
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::InstrEmitter::EmitDbgValue
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
Definition: InstrEmitter.cpp:679
llvm::InlineAsm::Op_MDNode
@ Op_MDNode
Definition: InlineAsm.h:220
llvm::InlineAsm::Kind_Func
@ Kind_Func
Definition: InlineAsm.h:246