Go to the documentation of this file.
35 #define DEBUG_TYPE "lrshrink"
37 STATISTIC(NumInstrsHoistedToShrinkLiveRange,
38 "Number of insructions hoisted to shrink live range.");
55 StringRef getPassName()
const override {
return "Live Range Shrink"; }
66 INITIALIZE_PASS(LiveRangeShrink,
"lrshrink",
"Live Range Shrink Pass",
false,
78 const InstOrderMap &M) {
79 auto NewIter =
M.find(&New);
80 if (NewIter ==
M.end())
84 unsigned OrderOld =
M.find(Old)->second;
85 unsigned OrderNew = NewIter->second;
86 if (OrderOld != OrderNew)
87 return OrderOld < OrderNew ? &New : Old;
90 for (
MachineInstr *
I = Old->getNextNode();
M.find(
I)->second == OrderNew;
125 bool SawStore =
false;
132 if (
MI.isPHI() ||
MI.isDebugOrPseudoInstr())
137 unsigned CurrentOrder = IOM[&
MI];
141 if (!MO.isReg() || MO.isDebug())
144 UseMap[MO.getReg()] = std::make_pair(CurrentOrder, &
MI);
145 else if (MO.isDead() && UseMap.
count(MO.getReg()))
148 if (
Barrier < UseMap[MO.getReg()].first) {
149 Barrier = UseMap[MO.getReg()].first;
150 BarrierMI = UseMap[MO.getReg()].second;
154 if (!
MI.isSafeToMove(
nullptr, SawStore)) {
158 if (
MI.hasUnmodeledSideEffects() && !
MI.isPseudoProbe() &&
171 unsigned NumEligibleUse = 0;
174 if (!MO.isReg() || MO.isDead() || MO.isDebug())
212 I =
I->getNextNode())
213 if (
I == BarrierMI) {
218 if (DefMO && Insert && NumEligibleUse > 1 &&
Barrier <= IOM[Insert]) {
221 while (
I !=
MBB.
end() && (
I->isPHI() ||
I->isDebugOrPseudoInstr()))
223 if (
I ==
MI.getIterator())
229 unsigned NewOrder = IOM[&*
I];
231 NumInstrsHoistedToShrinkLiveRange++;
235 if (
MI.getOperand(0).isReg())
236 for (; EndIter !=
MBB.
end() && EndIter->isDebugValue() &&
237 EndIter->hasDebugOperandForReg(
MI.getOperand(0).getReg());
239 IOM[&*EndIter] = NewOrder;
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Vector Rotate Left Mask Mask Insert
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
def_instr_iterator def_instr_begin(Register RegNo) const
void initializeLiveRangeShrinkPass(PassRegistry &)
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Represent the analysis usage information of a pass.
MachineOperand class - Representation of each machine instruction operand.
STATISTIC(NumFunctions, "Total number of functions")
static void BuildInstOrderMap(MachineBasicBlock::iterator Start, InstOrderMap &M)
Builds Instruction to its dominating order number map M by traversing from instruction Start.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Representation of each machine instruction.
char & LiveRangeShrinkID
LiveRangeShrink pass.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Register getReg() const
getReg - Returns the register number.
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
StringRef - Represent a constant reference to a string, i.e.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Function & getFunction()
Return the LLVM function that this machine code represents.
static MachineInstr * FindDominatedInstruction(MachineInstr &New, MachineInstr *Old, const InstOrderMap &M)
Returns New if it's dominated by Old, otherwise return Old.
INITIALIZE_PASS(LiveRangeShrink, "lrshrink", "Live Range Shrink Pass", false, false) using InstOrderMap