33 if (Preheader ==
Loop)
34 Preheader = *std::next(
Loop->pred_begin());
37 Exit = *std::next(
Loop->succ_begin());
43 MF.
insert(std::next(
Loop->getIterator()), NewBB);
46 auto InsertPt = NewBB->
end();
49 NewBB->
insert(InsertPt, NewMI);
64 if (
Use.getParent()->getParent() !=
Loop)
69 assert(ConstrainRegClass &&
70 "Expected a valid constrained register class!");
71 (void)ConstrainRegClass;
81 if (
auto It = Remaps.
find(MO.getReg()); It != Remaps.
end())
82 MO.setReg(It->second);
84 for (
auto I = NewBB->
begin();
I->isPHI(); ++
I) {
86 unsigned LoopRegIdx = 3, InitRegIdx = 1;
87 if (
MI.getOperand(2).getMBB() != Preheader)
94 Register R =
MI.getOperand(LoopRegIdx).getReg();
95 if (
auto It = Remaps.
find(R); It != Remaps.
end())
98 MI.removeOperand(LoopRegIdx + 1);
99 MI.removeOperand(LoopRegIdx + 0);
104 MI.getOperand(LoopRegIdx).setReg(LoopReg);
105 MI.removeOperand(InitRegIdx + 1);
106 MI.removeOperand(InitRegIdx + 0);
114 Loop->replacePhiUsesWith(Preheader, NewBB);
115 if (
auto PreheaderLayoutSuccessor = std::next(Preheader->
getIterator());
116 PreheaderLayoutSuccessor != Preheader->
getParent()->
end())
118 TII->removeBranch(*NewBB);
119 TII->insertBranch(*NewBB,
Loop,
nullptr, {},
DL);
121 Loop->replaceSuccessor(Exit, NewBB);
122 Exit->replacePhiUsesWith(
Loop, NewBB);
129 assert(CanAnalyzeBr &&
"Must be able to analyze the loop branch!");
132 FBB == Exit ? NewBB : FBB,
Cond,
DL);
133 if (
TII->removeBranch(*NewBB) > 0)
134 TII->insertBranch(*NewBB, Exit,
nullptr, {},
DL);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Remove Loads Into Fake Uses
iterator find(const_arg_type_t< KeyT > Val)
Represents a single loop in the control flow graph.
instr_iterator instr_begin()
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LLVM_ABI void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
LLVM_ABI iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Instructions::iterator instr_iterator
LLVM_ABI void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Representation of each machine instruction.
mop_range defs()
Returns all explicit operands that are register definitions.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
iterator_range< use_iterator > use_operands(Register Reg) const
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
A Use represents the edge between a Value definition and its users.
self_iterator getIterator()
This is an optimization pass for GlobalISel generic memory operations.
MachineBasicBlock * PeelSingleBlockLoop(LoopPeelDirection Direction, MachineBasicBlock *Loop, MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Peels a single block loop.
@ LPD_Back
Peel the last iteration of the loop.
@ LPD_Front
Peel the first iteration of the loop.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.