21 #define GET_TARGET_REGBANK_IMPL
23 #include "MipsGenRegisterBank.inc"
85 case Mips::GPR32RegClassID:
86 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
87 case Mips::GPRMM16MovePPairFirstRegClassID:
88 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
89 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
90 case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
91 case Mips::SP32RegClassID:
92 case Mips::GP32RegClassID:
94 case Mips::FGRCCRegClassID:
95 case Mips::FGR32RegClassID:
96 case Mips::FGR64RegClassID:
97 case Mips::AFGR64RegClassID:
98 case Mips::MSA128BRegClassID:
99 case Mips::MSA128HRegClassID:
100 case Mips::MSA128WRegClassID:
101 case Mips::MSA128DRegClassID:
111 case TargetOpcode::G_FCONSTANT:
112 case TargetOpcode::G_FADD:
113 case TargetOpcode::G_FSUB:
114 case TargetOpcode::G_FMUL:
115 case TargetOpcode::G_FDIV:
116 case TargetOpcode::G_FABS:
117 case TargetOpcode::G_FSQRT:
118 case TargetOpcode::G_FCEIL:
119 case TargetOpcode::G_FFLOOR:
120 case TargetOpcode::G_FPEXT:
121 case TargetOpcode::G_FPTRUNC:
132 case TargetOpcode::G_FPTOSI:
133 case TargetOpcode::G_FPTOUI:
134 case TargetOpcode::G_FCMP:
145 case TargetOpcode::G_SITOFP:
146 case TargetOpcode::G_UITOFP:
154 if (
MI->getOpcode() == TargetOpcode::G_LOAD ||
155 MI->getOpcode() == TargetOpcode::G_STORE) {
156 auto MMO = *
MI->memoperands_begin();
160 MMO->getAlign() < MMO->getSize()))
168 case TargetOpcode::G_LOAD:
169 case TargetOpcode::G_STORE:
170 case TargetOpcode::G_PHI:
171 case TargetOpcode::G_SELECT:
172 case TargetOpcode::G_IMPLICIT_DEF:
173 case TargetOpcode::G_UNMERGE_VALUES:
174 case TargetOpcode::G_MERGE_VALUES:
181 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
184 "Pointers are gprb, they should not be considered as ambiguous.\n");
188 if (NonCopyInstr->
getOpcode() == TargetOpcode::COPY &&
192 DefUses.push_back(skipCopiesOutgoing(&
UseMI));
196 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(
199 "Pointers are gprb, they should not be considered as ambiguous.\n");
201 UseDefs.push_back(skipCopiesIncoming(
DefMI));
205 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(
210 while (
Ret->getOpcode() == TargetOpcode::COPY &&
219 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(
224 while (
Ret->getOpcode() == TargetOpcode::COPY &&
230 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
233 "Not implemented for non Ambiguous opcode.\n");
237 if (
MI->getOpcode() == TargetOpcode::G_LOAD)
238 addDefUses(
MI->getOperand(0).getReg(),
MRI);
240 if (
MI->getOpcode() == TargetOpcode::G_STORE)
241 addUseDef(
MI->getOperand(0).getReg(),
MRI);
243 if (
MI->getOpcode() == TargetOpcode::G_PHI) {
244 addDefUses(
MI->getOperand(0).getReg(),
MRI);
246 for (
unsigned i = 1;
i <
MI->getNumOperands();
i += 2)
247 addUseDef(
MI->getOperand(
i).getReg(),
MRI);
250 if (
MI->getOpcode() == TargetOpcode::G_SELECT) {
251 addDefUses(
MI->getOperand(0).getReg(),
MRI);
253 addUseDef(
MI->getOperand(2).getReg(),
MRI);
254 addUseDef(
MI->getOperand(3).getReg(),
MRI);
257 if (
MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
258 addDefUses(
MI->getOperand(0).getReg(),
MRI);
260 if (
MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)
261 addUseDef(
MI->getOperand(
MI->getNumOperands() - 1).getReg(),
MRI);
263 if (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES)
264 addDefUses(
MI->getOperand(0).getReg(),
MRI);
267 bool MipsRegisterBankInfo::TypeInfoForMF::visit(
269 InstType &AmbiguousTy) {
275 AmbiguousRegDefUseContainer DefUseContainer(
MI);
278 setTypes(
MI, Integer);
282 if (AmbiguousTy == InstType::Ambiguous &&
283 (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||
284 MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))
285 AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge;
288 if (visitAdjacentInstrs(
MI, DefUseContainer.getDefUses(),
true, AmbiguousTy))
292 if (visitAdjacentInstrs(
MI, DefUseContainer.getUseDefs(),
false, AmbiguousTy))
296 if (!WaitingForTypeOfMI) {
298 setTypes(
MI, AmbiguousTy);
309 addToWaitingQueue(WaitingForTypeOfMI,
MI);
313 bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(
315 bool isDefUse, InstType &AmbiguousTy) {
316 while (!AdjacentInstrs.empty()) {
321 setTypes(
MI, InstType::FloatingPoint);
327 if (AdjMI->
getOpcode() == TargetOpcode::COPY) {
328 setTypesAccordingToPhysicalRegister(
MI, AdjMI, isDefUse ? 0 : 1);
334 if ((!isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_UNMERGE_VALUES) ||
335 (isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES) ||
343 if (!wasVisited(AdjMI) ||
344 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) {
345 if (visit(AdjMI,
MI, AmbiguousTy)) {
347 setTypes(
MI, getRecordedTypeForInstr(AdjMI));
355 void MipsRegisterBankInfo::TypeInfoForMF::setTypes(
const MachineInstr *
MI,
357 changeRecordedTypeForInstr(
MI, InstTy);
359 setTypes(WaitingInstr, InstTy);
363 void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
366 "Copies of non physical registers should not be considered here.\n");
376 if (Bank == &Mips::FPRBRegBank)
377 setTypes(
MI, InstType::FloatingPoint);
378 else if (Bank == &Mips::GPRBRegBank)
384 MipsRegisterBankInfo::InstType
385 MipsRegisterBankInfo::TypeInfoForMF::determineInstType(
const MachineInstr *
MI) {
386 InstType DefaultAmbiguousType = InstType::Ambiguous;
387 visit(
MI,
nullptr, DefaultAmbiguousType);
388 return getRecordedTypeForInstr(
MI);
391 void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(
393 if (MFName != FunctionName) {
394 MFName = std::string(FunctionName);
395 WaitingQueues.clear();
400 static const MipsRegisterBankInfo::ValueMapping *
403 "MSA mapping not available on target without MSA.");
416 static const MipsRegisterBankInfo::ValueMapping *
428 static TypeInfoForMF TI;
431 TI.cleanupIfNewFunction(
MI.getMF()->getName());
433 unsigned Opc =
MI.getOpcode();
437 if (
MI.getOpcode() != TargetOpcode::G_PHI) {
444 using namespace TargetOpcode;
446 unsigned NumOperands =
MI.getNumOperands();
501 if (Op0Size == 128) {
508 InstTy = TI.determineInstType(&
MI);
510 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
511 isAmbiguous_64(InstTy, Op0Size)) {
515 assert((isInteger_32(InstTy, Op0Size) ||
516 isAmbiguous_32(InstTy, Op0Size) ||
517 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
518 "Unexpected Inst type");
528 InstTy = TI.determineInstType(&
MI);
531 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) {
534 TI.clearTypeInfoData(&
MI);
538 assert((isInteger_32(InstTy, Op0Size) ||
539 isFloatingPoint_32or64(InstTy, Op0Size) ||
540 isAmbiguous_32or64(InstTy, Op0Size)) &&
541 "Unexpected Inst type");
548 InstTy = TI.determineInstType(&
MI);
549 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
550 isAmbiguous_64(InstTy, Op0Size)) {
556 assert((isInteger_32(InstTy, Op0Size) ||
557 isAmbiguous_32(InstTy, Op0Size) ||
558 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
559 "Unexpected Inst type");
567 case G_IMPLICIT_DEF: {
569 InstTy = TI.determineInstType(&
MI);
571 if (isFloatingPoint_32or64(InstTy, Op0Size))
574 assert((isInteger_32(InstTy, Op0Size) ||
575 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
576 "Unexpected Inst type");
580 case G_UNMERGE_VALUES: {
581 assert(
MI.getNumOperands() == 3 &&
"Unsupported G_UNMERGE_VALUES");
583 InstTy = TI.determineInstType(&
MI);
584 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size) ||
585 isFloatingPoint_64(InstTy, Op3Size)) &&
586 "Unexpected Inst type");
590 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size))
594 case G_MERGE_VALUES: {
595 InstTy = TI.determineInstType(&
MI);
596 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size) ||
597 isFloatingPoint_64(InstTy, Op0Size)) &&
598 "Unexpected Inst type");
602 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size))
635 assert((Op0Size == 32) &&
"Unsupported integer size");
643 "Unsupported integer size");
671 TI.clearTypeInfoData(&
MI);
682 InstManager(
InstListTy &Insts) : InstList(Insts) {}
694 switch (
MI.getOpcode()) {
695 case TargetOpcode::G_STORE:
698 case TargetOpcode::G_CONSTANT:
699 case TargetOpcode::G_LOAD:
700 case TargetOpcode::G_SELECT:
701 case TargetOpcode::G_PHI:
702 case TargetOpcode::G_IMPLICIT_DEF: {
707 case TargetOpcode::G_PTR_ADD: {
724 DeadMI->eraseFromParent();
735 InstManager NewInstrObserver(NewInstrs);
740 switch (
MI.getOpcode()) {
741 case TargetOpcode::G_LOAD:
742 case TargetOpcode::G_STORE:
743 case TargetOpcode::G_PHI:
744 case TargetOpcode::G_SELECT:
745 case TargetOpcode::G_IMPLICIT_DEF: {
748 while (!NewInstrs.
empty()) {
753 if (NewMI->
getOpcode() == TargetOpcode::G_UNMERGE_VALUES)
757 else if (NewMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES)
765 case TargetOpcode::G_UNMERGE_VALUES: