21 #define GET_TARGET_REGBANK_IMPL
23 #include "MipsGenRegisterBank.inc"
84 case Mips::GPR32RegClassID:
85 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
86 case Mips::GPRMM16MovePPairFirstRegClassID:
87 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
88 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
89 case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
90 case Mips::SP32RegClassID:
91 case Mips::GP32RegClassID:
93 case Mips::FGRCCRegClassID:
94 case Mips::FGR32RegClassID:
95 case Mips::FGR64RegClassID:
96 case Mips::AFGR64RegClassID:
97 case Mips::MSA128BRegClassID:
98 case Mips::MSA128HRegClassID:
99 case Mips::MSA128WRegClassID:
100 case Mips::MSA128DRegClassID:
110 case TargetOpcode::G_FCONSTANT:
111 case TargetOpcode::G_FADD:
112 case TargetOpcode::G_FSUB:
113 case TargetOpcode::G_FMUL:
114 case TargetOpcode::G_FDIV:
115 case TargetOpcode::G_FABS:
116 case TargetOpcode::G_FSQRT:
117 case TargetOpcode::G_FCEIL:
118 case TargetOpcode::G_FFLOOR:
119 case TargetOpcode::G_FPEXT:
120 case TargetOpcode::G_FPTRUNC:
131 case TargetOpcode::G_FPTOSI:
132 case TargetOpcode::G_FPTOUI:
133 case TargetOpcode::G_FCMP:
144 case TargetOpcode::G_SITOFP:
145 case TargetOpcode::G_UITOFP:
153 if (
MI->getOpcode() == TargetOpcode::G_LOAD ||
154 MI->getOpcode() == TargetOpcode::G_STORE) {
155 auto MMO = *
MI->memoperands_begin();
159 MMO->getAlign() < MMO->getSize()))
167 case TargetOpcode::G_LOAD:
168 case TargetOpcode::G_STORE:
169 case TargetOpcode::G_PHI:
170 case TargetOpcode::G_SELECT:
171 case TargetOpcode::G_IMPLICIT_DEF:
172 case TargetOpcode::G_UNMERGE_VALUES:
173 case TargetOpcode::G_MERGE_VALUES:
180 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
183 "Pointers are gprb, they should not be considered as ambiguous.\n");
187 if (NonCopyInstr->
getOpcode() == TargetOpcode::COPY &&
191 DefUses.push_back(skipCopiesOutgoing(&
UseMI));
195 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(
198 "Pointers are gprb, they should not be considered as ambiguous.\n");
200 UseDefs.push_back(skipCopiesIncoming(
DefMI));
204 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(
209 while (
Ret->getOpcode() == TargetOpcode::COPY &&
218 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(
223 while (
Ret->getOpcode() == TargetOpcode::COPY &&
229 MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
232 "Not implemented for non Ambiguous opcode.\n");
236 if (
MI->getOpcode() == TargetOpcode::G_LOAD)
237 addDefUses(
MI->getOperand(0).getReg(),
MRI);
239 if (
MI->getOpcode() == TargetOpcode::G_STORE)
240 addUseDef(
MI->getOperand(0).getReg(),
MRI);
242 if (
MI->getOpcode() == TargetOpcode::G_PHI) {
243 addDefUses(
MI->getOperand(0).getReg(),
MRI);
245 for (
unsigned i = 1;
i <
MI->getNumOperands();
i += 2)
246 addUseDef(
MI->getOperand(
i).getReg(),
MRI);
249 if (
MI->getOpcode() == TargetOpcode::G_SELECT) {
250 addDefUses(
MI->getOperand(0).getReg(),
MRI);
252 addUseDef(
MI->getOperand(2).getReg(),
MRI);
253 addUseDef(
MI->getOperand(3).getReg(),
MRI);
256 if (
MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
257 addDefUses(
MI->getOperand(0).getReg(),
MRI);
259 if (
MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)
260 addUseDef(
MI->getOperand(
MI->getNumOperands() - 1).getReg(),
MRI);
262 if (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES)
263 addDefUses(
MI->getOperand(0).getReg(),
MRI);
266 bool MipsRegisterBankInfo::TypeInfoForMF::visit(
268 InstType &AmbiguousTy) {
274 AmbiguousRegDefUseContainer DefUseContainer(
MI);
277 setTypes(
MI, Integer);
281 if (AmbiguousTy == InstType::Ambiguous &&
282 (
MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||
283 MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))
284 AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge;
287 if (visitAdjacentInstrs(
MI, DefUseContainer.getDefUses(),
true, AmbiguousTy))
291 if (visitAdjacentInstrs(
MI, DefUseContainer.getUseDefs(),
false, AmbiguousTy))
295 if (!WaitingForTypeOfMI) {
297 setTypes(
MI, AmbiguousTy);
308 addToWaitingQueue(WaitingForTypeOfMI,
MI);
312 bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(
314 bool isDefUse, InstType &AmbiguousTy) {
315 while (!AdjacentInstrs.empty()) {
320 setTypes(
MI, InstType::FloatingPoint);
326 if (AdjMI->
getOpcode() == TargetOpcode::COPY) {
327 setTypesAccordingToPhysicalRegister(
MI, AdjMI, isDefUse ? 0 : 1);
333 if ((!isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_UNMERGE_VALUES) ||
334 (isDefUse && AdjMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES) ||
342 if (!wasVisited(AdjMI) ||
343 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) {
344 if (visit(AdjMI,
MI, AmbiguousTy)) {
346 setTypes(
MI, getRecordedTypeForInstr(AdjMI));
354 void MipsRegisterBankInfo::TypeInfoForMF::setTypes(
const MachineInstr *
MI,
356 changeRecordedTypeForInstr(
MI, InstTy);
358 setTypes(WaitingInstr, InstTy);
362 void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
365 "Copies of non physical registers should not be considered here.\n");
375 if (Bank == &Mips::FPRBRegBank)
376 setTypes(
MI, InstType::FloatingPoint);
377 else if (Bank == &Mips::GPRBRegBank)
383 MipsRegisterBankInfo::InstType
384 MipsRegisterBankInfo::TypeInfoForMF::determineInstType(
const MachineInstr *
MI) {
385 InstType DefaultAmbiguousType = InstType::Ambiguous;
386 visit(
MI,
nullptr, DefaultAmbiguousType);
387 return getRecordedTypeForInstr(
MI);
390 void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(
392 if (MFName != FunctionName) {
393 MFName = std::string(FunctionName);
394 WaitingQueues.clear();
399 static const MipsRegisterBankInfo::ValueMapping *
402 "MSA mapping not available on target without MSA.");
415 static const MipsRegisterBankInfo::ValueMapping *
427 static TypeInfoForMF TI;
430 TI.cleanupIfNewFunction(
MI.getMF()->getName());
432 unsigned Opc =
MI.getOpcode();
436 if (
MI.getOpcode() != TargetOpcode::G_PHI) {
443 using namespace TargetOpcode;
445 unsigned NumOperands =
MI.getNumOperands();
500 if (Op0Size == 128) {
507 InstTy = TI.determineInstType(&
MI);
509 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
510 isAmbiguous_64(InstTy, Op0Size)) {
514 assert((isInteger_32(InstTy, Op0Size) ||
515 isAmbiguous_32(InstTy, Op0Size) ||
516 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
517 "Unexpected Inst type");
527 InstTy = TI.determineInstType(&
MI);
530 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) {
533 TI.clearTypeInfoData(&
MI);
537 assert((isInteger_32(InstTy, Op0Size) ||
538 isFloatingPoint_32or64(InstTy, Op0Size) ||
539 isAmbiguous_32or64(InstTy, Op0Size)) &&
540 "Unexpected Inst type");
547 InstTy = TI.determineInstType(&
MI);
548 if (isFloatingPoint_32or64(InstTy, Op0Size) ||
549 isAmbiguous_64(InstTy, Op0Size)) {
555 assert((isInteger_32(InstTy, Op0Size) ||
556 isAmbiguous_32(InstTy, Op0Size) ||
557 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
558 "Unexpected Inst type");
566 case G_IMPLICIT_DEF: {
568 InstTy = TI.determineInstType(&
MI);
570 if (isFloatingPoint_32or64(InstTy, Op0Size))
573 assert((isInteger_32(InstTy, Op0Size) ||
574 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&
575 "Unexpected Inst type");
579 case G_UNMERGE_VALUES: {
580 assert(
MI.getNumOperands() == 3 &&
"Unsupported G_UNMERGE_VALUES");
582 InstTy = TI.determineInstType(&
MI);
583 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size) ||
584 isFloatingPoint_64(InstTy, Op3Size)) &&
585 "Unexpected Inst type");
589 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size))
593 case G_MERGE_VALUES: {
594 InstTy = TI.determineInstType(&
MI);
595 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size) ||
596 isFloatingPoint_64(InstTy, Op0Size)) &&
597 "Unexpected Inst type");
601 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size))
634 assert((Op0Size == 32) &&
"Unsupported integer size");
642 "Unsupported integer size");
670 TI.clearTypeInfoData(&
MI);
681 InstManager(
InstListTy &Insts) : InstList(Insts) {}
693 switch (
MI.getOpcode()) {
694 case TargetOpcode::G_STORE:
697 case TargetOpcode::G_CONSTANT:
698 case TargetOpcode::G_LOAD:
699 case TargetOpcode::G_SELECT:
700 case TargetOpcode::G_PHI:
701 case TargetOpcode::G_IMPLICIT_DEF: {
706 case TargetOpcode::G_PTR_ADD: {
722 UpdatedDefs, Observer);
724 DeadMI->eraseFromParent();
735 InstManager NewInstrObserver(NewInstrs);
740 switch (
MI.getOpcode()) {
741 case TargetOpcode::G_LOAD:
742 case TargetOpcode::G_STORE:
743 case TargetOpcode::G_PHI:
744 case TargetOpcode::G_SELECT:
745 case TargetOpcode::G_IMPLICIT_DEF: {
748 while (!NewInstrs.
empty()) {
753 if (
auto *Unmerge = dyn_cast<GUnmerge>(NewMI))
757 else if (NewMI->
getOpcode() == TargetOpcode::G_MERGE_VALUES)
765 case TargetOpcode::G_UNMERGE_VALUES: