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60 #ifndef LLVM_CODEGEN_MODULOSCHEDULE_H
61 #define LLVM_CODEGEN_MODULOSCHEDULE_H
71 class MachineBasicBlock;
73 class MachineRegisterInfo;
87 std::vector<MachineInstr *> ScheduledInstrs;
107 std::vector<MachineInstr *> ScheduledInstrs,
113 for (
auto &KV : this->Stage)
114 NumStages =
std::max(NumStages, KV.second);
136 return I == Stage.
end() ? -1 :
I->second;
142 return I ==
Cycle.end() ? -1 :
I->second;
179 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
LoopInfo;
185 std::map<unsigned, std::pair<unsigned, bool>> RegToStageDiff;
190 void generatePipelinedLoop();
199 unsigned LastStageNum,
unsigned CurStageNum,
204 unsigned LastStageNum,
unsigned CurStageNum,
bool IsLast);
215 unsigned InstStageNum);
217 unsigned InstStageNum);
218 void updateInstruction(
MachineInstr *NewMI,
bool LastDef,
219 unsigned CurStageNum,
unsigned InstrStageNum,
222 unsigned getPrevMapVal(
unsigned StageNum,
unsigned PhiStage,
unsigned LoopVal,
228 unsigned CurStageNum,
unsigned PhiNum,
230 unsigned NewReg,
unsigned PrevReg = 0);
235 unsigned getStagesForReg(
int Reg,
unsigned CurStage) {
236 std::pair<unsigned, bool> Stages = RegToStageDiff[
Reg];
237 if ((
int)CurStage > Schedule.
getNumStages() - 1 && Stages.first == 0 &&
249 unsigned getStagesForPhi(
int Reg) {
250 std::pair<unsigned, bool> Stages = RegToStageDiff[
Reg];
253 return Stages.first - 1;
264 : Schedule(
S), MF(MF), ST(MF.getSubtarget()),
MRI(MF.getRegInfo()),
265 TII(ST.getInstrInfo()), LIS(LIS),
266 InstrChanges(
std::
move(InstrChanges)) {}
367 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
LoopInfo;
390 #endif // LLVM_CODEGEN_MODULOSCHEDULE_H
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > LoopInfo
Target loop info before kernel peeling.
This is an optimization pass for GlobalISel generic memory operations.
void rewriteKernel()
Converts BB from the original loop body to the rewritten, pipelined steady-state.
void cleanup()
Performs final cleanup after expansion.
Represents a schedule for a single-block loop.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a single loop in the control flow graph.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
ModuloSchedule(MachineFunction &MF, MachineLoop *Loop, std::vector< MachineInstr * > ScheduledInstrs, DenseMap< MachineInstr *, int > Cycle, DenseMap< MachineInstr *, int > Stage)
Create a new ModuloSchedule.
SmallVector< MachineBasicBlock *, 4 > Epilogs
unsigned getStage(MachineInstr *MI)
Helper to get the stage of an instruction in the schedule.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
const TargetInstrInfo * TII
A reimplementation of ModuloScheduleExpander.
void expand()
Performs the actual expansion.
std::deque< MachineBasicBlock * > PeeledFront
State passed from peelKernel to peelPrologAndEpilogs().
void moveStageBetweenBlocks(MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
DenseMap< MachineBasicBlock *, BitVector > AvailableStages
For every block, the stages that are available.
TargetInstrInfo - Interface to description of machine instruction set.
ModuloSchedule & Schedule
std::deque< MachineBasicBlock * > PeeledBack
DenseMap< MachineInstr *, unsigned > PhiNodeLoopIteration
When peeling the epilogue keep track of the distance between the phi nodes and the kernel.
ModuloScheduleExpander(MachineFunction &MF, ModuloSchedule &S, LiveIntervals &LIS, InstrChangesTy InstrChanges)
Create a new ModuloScheduleExpander.
DenseMap< std::pair< MachineBasicBlock *, MachineInstr * >, MachineInstr * > BlockMIs
MachineBasicBlock * BB
The original loop block that gets rewritten in-place.
const HexagonInstrInfo * TII
SmallVector< MachineBasicBlock *, 4 > Prologs
All prolog and epilog blocks.
A possibly irreducible generalization of a Loop.
void filterInstructions(MachineBasicBlock *MB, int MinStage)
void setStage(MachineInstr *MI, int MIStage)
Set the stage of a newly created instruction.
This class implements an extremely fast bulk output stream that can only output to a stream.
ArrayRef< MachineInstr * > getInstructions()
Return the rescheduled instructions in order.
MachineBasicBlock * peelKernel(LoopPeelDirection LPD)
Peels one iteration of the rewritten kernel (BB) in the specified direction.
int getFinalCycle()
Return the final cycle in the schedule, which is the cycle index of the last instruction.
MachineBasicBlock * Preheader
The original loop preheader.
void fixupBranches()
Insert branches between prologs, kernel and epilogs.
const TargetSubtargetInfo & ST
MachineBasicBlock * getRewrittenKernel()
Returns the newly rewritten kernel block, or nullptr if this was optimized away.
void rewriteUsesOf(MachineInstr *MI)
Change all users of MI, if MI is predicated out (LiveStages[MI->getParent()] == false).
Representation of each machine instruction.
void annotate()
Performs the annotation.
int getFirstCycle()
Return the first cycle in the schedule, which is the cycle index of the first instruction.
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
MachineBasicBlock * CreateLCSSAExitingBlock()
Create a poor-man's LCSSA by cloning only the PHIs from the kernel block to a block dominated by all ...
Register getEquivalentRegisterIn(Register Reg, MachineBasicBlock *BB)
All prolog and epilog blocks are clones of the kernel, so any produced register in one block has an c...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expander that simply annotates each scheduled instruction with a post-instr symbol that can be consum...
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
PeelingModuloScheduleExpander(MachineFunction &MF, ModuloSchedule &S, LiveIntervals *LIS)
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
MachineRegisterInfo & MRI
int getCycle(MachineInstr *MI)
Return the cycle that MI is scheduled at, or -1.
int getNumStages() const
Return the number of stages contained in this schedule, which is the largest stage index + 1.
SmallVector< MachineInstr *, 4 > IllegalPhisToDelete
Illegal phis that need to be deleted once we re-link stages.
MachineLoop * getLoop() const
Return the single-block loop being scheduled.
void peelPrologAndEpilogs()
Peel the kernel forwards and backwards to produce prologs and epilogs, and stitch them together.
void validateAgainstModuloScheduleExpander()
Runs ModuloScheduleExpander and treats it as a golden input to validate aspects of the code generated...
void print(raw_ostream &OS)
DenseMap< MachineBasicBlock *, BitVector > LiveStages
For every block, the stages that are produced.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
The ModuloScheduleExpander takes a ModuloSchedule and expands it in-place, rewriting the old loop and...
int getStage(MachineInstr *MI)
Return the stage that MI is scheduled in, or -1.
Register getPhiCanonicalReg(MachineInstr *CanonicalPhi, MachineInstr *Phi)
Helper function to find the right canonical register for a phi instruction coming from a peeled out p...
ModuloScheduleTestAnnotater(MachineFunction &MF, ModuloSchedule &S)
DenseMap< MachineInstr *, MachineInstr * > CanonicalMIs
CanonicalMIs and BlockMIs form a bidirectional map between any of the loop kernel clones.