RISCVInstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for RISC-V. More...

#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVRegisterBankInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
#include "RISCVGenGlobalISel.inc"

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE   "riscv-isel"
#define	GET_GLOBALISEL_PREDICATE_BITSET
#define	GET_GLOBALISEL_PREDICATES_DECL
#define	GET_GLOBALISEL_TEMPORARIES_DECL
#define	GET_GLOBALISEL_IMPL
#define	GET_GLOBALISEL_PREDICATES_INIT
#define	GET_GLOBALISEL_TEMPORARIES_INIT

Functions
static void	getOperandsForBranch (Register CondReg, RISCVCC::CondCode &CC, Register &LHS, Register &RHS, MachineRegisterInfo &MRI)
static unsigned	selectZalasrLoadStoreOp (unsigned GenericOpc, unsigned OpSize)
	Select the RISC-V Zalasr opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the GPR register bank and of memory access size OpSize.
static unsigned	selectRegImmLoadStoreOp (const RISCVSubtarget &STI, unsigned GenericOpc, unsigned OpSize)
	Select the RISC-V regimm opcode for the G_LOAD or G_STORE operation GenericOpc on STI, appropriate for the GPR register bank and of memory access size OpSize.
static unsigned	getFCmpOpcode (CmpInst::Predicate Pred, unsigned Size)
static bool	legalizeFCmpPredicate (Register &LHS, Register &RHS, CmpInst::Predicate &Pred, bool &NeedInvert)
InstructionSelector *	llvm::createRISCVInstructionSelector (const RISCVTargetMachine &TM, const RISCVSubtarget &Subtarget, const RISCVRegisterBankInfo &RBI)

Detailed Description

This file implements the targeting of the InstructionSelector class for RISC-V.

Todo

This should be generated by TableGen.

Definition in file RISCVInstructionSelector.cpp.

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-isel"

Definition at line 28 of file RISCVInstructionSelector.cpp.

GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 207 of file RISCVInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

Definition at line 33 of file RISCVInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

Definition at line 196 of file RISCVInstructionSelector.cpp.

GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

Definition at line 200 of file RISCVInstructionSelector.cpp.

GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

getFCmpOpcode()

unsigned getFCmpOpcode ( CmpInst::Predicate Pred, unsigned Size )

static

Definition at line 2157 of file RISCVInstructionSelector.cpp.

References assert(), llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm_unreachable, and Size.

getOperandsForBranch()

void getOperandsForBranch ( Register CondReg, RISCVCC::CondCode & CC, Register & LHS, Register & RHS, MachineRegisterInfo & MRI )

static

Definition at line 763 of file RISCVInstructionSelector.cpp.

References llvm::CmpInst::BAD_ICMP_PREDICATE, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_NE, llvm::getIConstantVRegSExtVal(), llvm::CmpInst::getSwappedPredicate(), llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, LHS, llvm_unreachable, llvm::MIPatternMatch::m_GICmp(), llvm::MIPatternMatch::m_Pred(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), RHS, and std::swap().

legalizeFCmpPredicate()

bool legalizeFCmpPredicate ( Register & LHS, Register & RHS, CmpInst::Predicate & Pred, bool & NeedInvert )

static

Definition at line 2173 of file RISCVInstructionSelector.cpp.

References assert(), llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::getInversePredicate(), llvm::CmpInst::getSwappedPredicate(), LHS, RHS, and std::swap().

selectRegImmLoadStoreOp()

unsigned selectRegImmLoadStoreOp ( const RISCVSubtarget & STI, unsigned GenericOpc, unsigned OpSize )

static

Select the RISC-V regimm opcode for the G_LOAD or G_STORE operation GenericOpc on STI, appropriate for the GPR register bank and of memory access size OpSize.

Returns

GenericOpc if the combination is unsupported.

Definition at line 850 of file RISCVInstructionSelector.cpp.

References llvm::RISCVSubtarget::is64Bit().

selectZalasrLoadStoreOp()

unsigned selectZalasrLoadStoreOp ( unsigned GenericOpc, unsigned OpSize )

static

Select the RISC-V Zalasr opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the GPR register bank and of memory access size OpSize.

Definition at line 830 of file RISCVInstructionSelector.cpp.

References llvm_unreachable.