LLVM  15.0.0git
RISCVMCTargetDesc.cpp
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1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVMCObjectFileInfo.h"
19 #include "RISCVTargetStreamer.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/MC/MCAsmBackend.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCObjectWriter.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/TargetRegistry.h"
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "RISCVGenInstrInfo.inc"
37 
38 #define GET_REGINFO_MC_DESC
39 #include "RISCVGenRegisterInfo.inc"
40 
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "RISCVGenSubtargetInfo.inc"
43 
44 using namespace llvm;
45 
47  MCInstrInfo *X = new MCInstrInfo();
48  InitRISCVMCInstrInfo(X);
49  return X;
50 }
51 
54  InitRISCVMCRegisterInfo(X, RISCV::X1);
55  return X;
56 }
57 
59  const Triple &TT,
60  const MCTargetOptions &Options) {
61  MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
62 
63  MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
64  MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
65  MAI->addInitialFrameState(Inst);
66 
67  return MAI;
68 }
69 
70 static MCObjectFileInfo *
72  bool LargeCodeModel = false) {
74  MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
75  return MOFI;
76 }
77 
79  StringRef CPU, StringRef FS) {
80  if (CPU.empty() || CPU == "generic")
81  CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
82 
83  return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
84 }
85 
87  unsigned SyntaxVariant,
88  const MCAsmInfo &MAI,
89  const MCInstrInfo &MII,
90  const MCRegisterInfo &MRI) {
91  return new RISCVInstPrinter(MAI, MII, MRI);
92 }
93 
94 static MCTargetStreamer *
96  const Triple &TT = STI.getTargetTriple();
97  if (TT.isOSBinFormatELF())
98  return new RISCVTargetELFStreamer(S, STI);
99  return nullptr;
100 }
101 
104  MCInstPrinter *InstPrint,
105  bool isVerboseAsm) {
106  return new RISCVTargetAsmStreamer(S, OS);
107 }
108 
110  return new RISCVTargetStreamer(S);
111 }
112 
113 namespace {
114 
115 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
116 public:
117  explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
118  : MCInstrAnalysis(Info) {}
119 
120  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
121  uint64_t &Target) const override {
122  if (isConditionalBranch(Inst)) {
123  int64_t Imm;
124  if (Size == 2)
125  Imm = Inst.getOperand(1).getImm();
126  else
127  Imm = Inst.getOperand(2).getImm();
128  Target = Addr + Imm;
129  return true;
130  }
131 
132  if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
133  Target = Addr + Inst.getOperand(0).getImm();
134  return true;
135  }
136 
137  if (Inst.getOpcode() == RISCV::JAL) {
138  Target = Addr + Inst.getOperand(1).getImm();
139  return true;
140  }
141 
142  return false;
143  }
144 };
145 
146 } // end anonymous namespace
147 
149  return new RISCVMCInstrAnalysis(Info);
150 }
151 
152 namespace {
154  std::unique_ptr<MCAsmBackend> &&MAB,
155  std::unique_ptr<MCObjectWriter> &&MOW,
156  std::unique_ptr<MCCodeEmitter> &&MCE,
157  bool RelaxAll) {
159  std::move(MCE), RelaxAll);
160 }
161 } // end anonymous namespace
162 
164  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
177 
178  // Register the asm target streamer.
180  // Register the null target streamer.
183  }
184 }
llvm::createRISCVELFStreamer
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE, bool RelaxAll)
Definition: RISCVELFStreamer.cpp:260
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
RISCVELFStreamer.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
MCCodeEmitter.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createRISCVNullTargetStreamer
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
Definition: RISCVMCTargetDesc.cpp:109
ErrorHandling.h
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:993
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:840
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCObjectFileInfo.h
PIC
PassInstrumentationCallbacks PIC
Definition: PassBuilderBindings.cpp:55
RISCVMCObjectFileInfo.h
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::TargetRegistry::RegisterMCObjectFileInfo
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
Definition: TargetRegistry.h:820
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: RISCVMCCodeEmitter.cpp:96
createRISCVMCSubtargetInfo
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: RISCVMCTargetDesc.cpp:78
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:947
createRISCVObjectTargetStreamer
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: RISCVMCTargetDesc.cpp:95
RISCVInstPrinter.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
createRISCVAsmTargetStreamer
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: RISCVMCTargetDesc.cpp:102
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:201
llvm::createRISCVAsmBackend
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: RISCVAsmBackend.cpp:640
MCAsmBackend.h
llvm::RISCVInstPrinter
Definition: RISCVInstPrinter.h:21
LLVMInitializeRISCVTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
Definition: RISCVMCTargetDesc.cpp:163
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
llvm::RISCVMCAsmInfo
Definition: RISCVMCAsmInfo.h:21
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
RISCVMCTargetDesc.h
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCCFIInstruction
Definition: MCDwarf.h:472
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
RISCVTargetStreamer.h
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:894
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
uint64_t
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
createRISCVMCObjectFileInfo
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
Definition: RISCVMCTargetDesc.cpp:71
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:999
MCRegisterInfo.h
RISCVMCAsmInfo.h
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
llvm::TargetRegistry::RegisterMCAsmInfo
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
Definition: TargetRegistry.h:808
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:526
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
createRISCVInstrAnalysis
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
Definition: RISCVMCTargetDesc.cpp:148
createRISCVMCInstrInfo
static MCInstrInfo * createRISCVMCInstrInfo()
Definition: RISCVMCTargetDesc.cpp:46
createRISCVMCInstPrinter
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: RISCVMCTargetDesc.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:867
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::MCObjectFileInfo::initMCObjectFileInfo
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
Definition: MCObjectFileInfo.cpp:1008
llvm::RISCVTargetAsmStreamer
Definition: RISCVTargetStreamer.h:47
MCInstrAnalysis.h
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:834
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:960
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
createRISCVMCRegisterInfo
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
Definition: RISCVMCTargetDesc.cpp:52
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:854
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
RISCVBaseInfo.h
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:988
llvm::RISCVTargetELFStreamer
Definition: RISCVELFStreamer.h:17
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
RISCVTargetInfo.h
llvm::RISCVTargetStreamer
Definition: RISCVTargetStreamer.h:20
llvm::RISCVMCObjectFileInfo
Definition: RISCVMCObjectFileInfo.h:20
llvm::X86AS::FS
@ FS
Definition: X86.h:188
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
createRISCVMCAsmInfo
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: RISCVMCTargetDesc.cpp:58
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::MCObjectFileInfo
Definition: MCObjectFileInfo.h:27
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24