LLVM 19.0.0git
RISCVMCTargetDesc.cpp
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1//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISC-V specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVELFStreamer.h"
16#include "RISCVInstPrinter.h"
17#include "RISCVMCAsmInfo.h"
19#include "RISCVTargetStreamer.h"
21#include "llvm/ADT/STLExtras.h"
23#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCInstrInfo.h"
30#include "llvm/MC/MCStreamer.h"
34#include <bitset>
35
36#define GET_INSTRINFO_MC_DESC
37#define ENABLE_INSTR_PREDICATE_VERIFIER
38#include "RISCVGenInstrInfo.inc"
39
40#define GET_REGINFO_MC_DESC
41#include "RISCVGenRegisterInfo.inc"
42
43#define GET_SUBTARGETINFO_MC_DESC
44#include "RISCVGenSubtargetInfo.inc"
45
46using namespace llvm;
47
49 MCInstrInfo *X = new MCInstrInfo();
50 InitRISCVMCInstrInfo(X);
51 return X;
52}
53
56 InitRISCVMCRegisterInfo(X, RISCV::X1);
57 return X;
58}
59
61 const Triple &TT,
62 const MCTargetOptions &Options) {
63 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
64
65 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
66 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
67 MAI->addInitialFrameState(Inst);
68
69 return MAI;
70}
71
72static MCObjectFileInfo *
74 bool LargeCodeModel = false) {
76 MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
77 return MOFI;
78}
79
81 StringRef CPU, StringRef FS) {
82 if (CPU.empty() || CPU == "generic")
83 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
84
85 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
86}
87
89 unsigned SyntaxVariant,
90 const MCAsmInfo &MAI,
91 const MCInstrInfo &MII,
92 const MCRegisterInfo &MRI) {
93 return new RISCVInstPrinter(MAI, MII, MRI);
94}
95
96static MCTargetStreamer *
98 const Triple &TT = STI.getTargetTriple();
99 if (TT.isOSBinFormatELF())
100 return new RISCVTargetELFStreamer(S, STI);
101 return nullptr;
102}
103
106 MCInstPrinter *InstPrint,
107 bool isVerboseAsm) {
108 return new RISCVTargetAsmStreamer(S, OS);
109}
110
112 return new RISCVTargetStreamer(S);
113}
114
115namespace {
116
117class RISCVMCInstrAnalysis : public MCInstrAnalysis {
118 int64_t GPRState[31] = {};
119 std::bitset<31> GPRValidMask;
120
121 static bool isGPR(unsigned Reg) {
122 return Reg >= RISCV::X0 && Reg <= RISCV::X31;
123 }
124
125 static unsigned getRegIndex(unsigned Reg) {
126 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
127 return Reg - RISCV::X1;
128 }
129
130 void setGPRState(unsigned Reg, std::optional<int64_t> Value) {
131 if (Reg == RISCV::X0)
132 return;
133
134 auto Index = getRegIndex(Reg);
135
136 if (Value) {
137 GPRState[Index] = *Value;
138 GPRValidMask.set(Index);
139 } else {
140 GPRValidMask.reset(Index);
141 }
142 }
143
144 std::optional<int64_t> getGPRState(unsigned Reg) const {
145 if (Reg == RISCV::X0)
146 return 0;
147
148 auto Index = getRegIndex(Reg);
149
150 if (GPRValidMask.test(Index))
151 return GPRState[Index];
152 return std::nullopt;
153 }
154
155public:
156 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
158
159 void resetState() override { GPRValidMask.reset(); }
160
161 void updateState(const MCInst &Inst, uint64_t Addr) override {
162 // Terminators mark the end of a basic block which means the sequentially
163 // next instruction will be the first of another basic block and the current
164 // state will typically not be valid anymore. For calls, we assume all
165 // registers may be clobbered by the callee (TODO: should we take the
166 // calling convention into account?).
167 if (isTerminator(Inst) || isCall(Inst)) {
168 resetState();
169 return;
170 }
171
172 switch (Inst.getOpcode()) {
173 default: {
174 // Clear the state of all defined registers for instructions that we don't
175 // explicitly support.
176 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
177 for (unsigned I = 0; I < NumDefs; ++I) {
178 auto DefReg = Inst.getOperand(I).getReg();
179 if (isGPR(DefReg))
180 setGPRState(DefReg, std::nullopt);
181 }
182 break;
183 }
184 case RISCV::AUIPC:
185 setGPRState(Inst.getOperand(0).getReg(),
186 Addr + (Inst.getOperand(1).getImm() << 12));
187 break;
188 }
189 }
190
191 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
192 uint64_t &Target) const override {
193 if (isConditionalBranch(Inst)) {
194 int64_t Imm;
195 if (Size == 2)
196 Imm = Inst.getOperand(1).getImm();
197 else
198 Imm = Inst.getOperand(2).getImm();
199 Target = Addr + Imm;
200 return true;
201 }
202
203 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
204 Target = Addr + Inst.getOperand(0).getImm();
205 return true;
206 }
207
208 if (Inst.getOpcode() == RISCV::JAL) {
209 Target = Addr + Inst.getOperand(1).getImm();
210 return true;
211 }
212
213 if (Inst.getOpcode() == RISCV::JALR) {
214 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
215 Target = *TargetRegState + Inst.getOperand(2).getImm();
216 return true;
217 }
218
219 return false;
220 }
221
222 return false;
223 }
224
225 bool isTerminator(const MCInst &Inst) const override {
227 return true;
228
229 switch (Inst.getOpcode()) {
230 default:
231 return false;
232 case RISCV::JAL:
233 case RISCV::JALR:
234 return Inst.getOperand(0).getReg() == RISCV::X0;
235 }
236 }
237
238 bool isCall(const MCInst &Inst) const override {
239 if (MCInstrAnalysis::isCall(Inst))
240 return true;
241
242 switch (Inst.getOpcode()) {
243 default:
244 return false;
245 case RISCV::JAL:
246 case RISCV::JALR:
247 return Inst.getOperand(0).getReg() != RISCV::X0;
248 }
249 }
250
251 bool isReturn(const MCInst &Inst) const override {
253 return true;
254
255 switch (Inst.getOpcode()) {
256 default:
257 return false;
258 case RISCV::JALR:
259 return Inst.getOperand(0).getReg() == RISCV::X0 &&
260 maybeReturnAddress(Inst.getOperand(1).getReg());
261 case RISCV::C_JR:
262 return maybeReturnAddress(Inst.getOperand(0).getReg());
263 }
264 }
265
266 bool isBranch(const MCInst &Inst) const override {
268 return true;
269
270 return isBranchImpl(Inst);
271 }
272
273 bool isUnconditionalBranch(const MCInst &Inst) const override {
275 return true;
276
277 return isBranchImpl(Inst);
278 }
279
280 bool isIndirectBranch(const MCInst &Inst) const override {
282 return true;
283
284 switch (Inst.getOpcode()) {
285 default:
286 return false;
287 case RISCV::JALR:
288 return Inst.getOperand(0).getReg() == RISCV::X0 &&
289 !maybeReturnAddress(Inst.getOperand(1).getReg());
290 case RISCV::C_JR:
291 return !maybeReturnAddress(Inst.getOperand(0).getReg());
292 }
293 }
294
295private:
296 static bool maybeReturnAddress(unsigned Reg) {
297 // X1 is used for normal returns, X5 for returns from outlined functions.
298 return Reg == RISCV::X1 || Reg == RISCV::X5;
299 }
300
301 static bool isBranchImpl(const MCInst &Inst) {
302 switch (Inst.getOpcode()) {
303 default:
304 return false;
305 case RISCV::JAL:
306 return Inst.getOperand(0).getReg() == RISCV::X0;
307 case RISCV::JALR:
308 return Inst.getOperand(0).getReg() == RISCV::X0 &&
309 !maybeReturnAddress(Inst.getOperand(1).getReg());
310 case RISCV::C_JR:
311 return !maybeReturnAddress(Inst.getOperand(0).getReg());
312 }
313 }
314};
315
316} // end anonymous namespace
317
319 return new RISCVMCInstrAnalysis(Info);
320}
321
322namespace {
324 std::unique_ptr<MCAsmBackend> &&MAB,
325 std::unique_ptr<MCObjectWriter> &&MOW,
326 std::unique_ptr<MCCodeEmitter> &&MCE,
327 bool RelaxAll) {
328 return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
329 std::move(MCE), RelaxAll);
330}
331} // end anonymous namespace
332
347
348 // Register the asm target streamer.
350 // Register the null target streamer.
353 }
354}
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PassInstrumentationCallbacks PIC
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
static MCInstrInfo * createRISCVMCInstrInfo()
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:75
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:541
Context object for machine code objects.
Definition: MCContext.h:76
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual void resetState()
Clear the internal state. See updateState for more information.
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual void updateState(const MCInst &Inst, uint64_t Addr)
Update internal state with Inst at Addr.
virtual bool isIndirectBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
int64_t getImm() const
Definition: MCInst.h:80
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Target specific streamer interface.
Definition: MCStreamer.h:93
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheRISCV32Target()
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheRISCV64Target()
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE, bool RelaxAll)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)