LLVM 18.0.0git
RISCVMCTargetDesc.cpp
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1//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file provides RISC-V specific target descriptions.
10///
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMCTargetDesc.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVELFStreamer.h"
16#include "RISCVInstPrinter.h"
17#include "RISCVMCAsmInfo.h"
19#include "RISCVTargetStreamer.h"
21#include "llvm/ADT/STLExtras.h"
23#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCInstrInfo.h"
30#include "llvm/MC/MCStreamer.h"
34
35#define GET_INSTRINFO_MC_DESC
36#define ENABLE_INSTR_PREDICATE_VERIFIER
37#include "RISCVGenInstrInfo.inc"
38
39#define GET_REGINFO_MC_DESC
40#include "RISCVGenRegisterInfo.inc"
41
42#define GET_SUBTARGETINFO_MC_DESC
43#include "RISCVGenSubtargetInfo.inc"
44
45using namespace llvm;
46
48 MCInstrInfo *X = new MCInstrInfo();
49 InitRISCVMCInstrInfo(X);
50 return X;
51}
52
55 InitRISCVMCRegisterInfo(X, RISCV::X1);
56 return X;
57}
58
60 const Triple &TT,
61 const MCTargetOptions &Options) {
62 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
63
64 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
65 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
66 MAI->addInitialFrameState(Inst);
67
68 return MAI;
69}
70
71static MCObjectFileInfo *
73 bool LargeCodeModel = false) {
75 MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
76 return MOFI;
77}
78
80 StringRef CPU, StringRef FS) {
81 if (CPU.empty() || CPU == "generic")
82 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
83
84 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
85}
86
88 unsigned SyntaxVariant,
89 const MCAsmInfo &MAI,
90 const MCInstrInfo &MII,
91 const MCRegisterInfo &MRI) {
92 return new RISCVInstPrinter(MAI, MII, MRI);
93}
94
95static MCTargetStreamer *
97 const Triple &TT = STI.getTargetTriple();
98 if (TT.isOSBinFormatELF())
99 return new RISCVTargetELFStreamer(S, STI);
100 return nullptr;
101}
102
105 MCInstPrinter *InstPrint,
106 bool isVerboseAsm) {
107 return new RISCVTargetAsmStreamer(S, OS);
108}
109
111 return new RISCVTargetStreamer(S);
112}
113
114namespace {
115
116class RISCVMCInstrAnalysis : public MCInstrAnalysis {
117public:
118 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
120
121 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
122 uint64_t &Target) const override {
123 if (isConditionalBranch(Inst)) {
124 int64_t Imm;
125 if (Size == 2)
126 Imm = Inst.getOperand(1).getImm();
127 else
128 Imm = Inst.getOperand(2).getImm();
129 Target = Addr + Imm;
130 return true;
131 }
132
133 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
134 Target = Addr + Inst.getOperand(0).getImm();
135 return true;
136 }
137
138 if (Inst.getOpcode() == RISCV::JAL) {
139 Target = Addr + Inst.getOperand(1).getImm();
140 return true;
141 }
142
143 return false;
144 }
145
146 bool isTerminator(const MCInst &Inst) const override {
148 return true;
149
150 switch (Inst.getOpcode()) {
151 default:
152 return false;
153 case RISCV::JAL:
154 case RISCV::JALR:
155 return Inst.getOperand(0).getReg() == RISCV::X0;
156 }
157 }
158
159 bool isCall(const MCInst &Inst) const override {
160 if (MCInstrAnalysis::isCall(Inst))
161 return true;
162
163 switch (Inst.getOpcode()) {
164 default:
165 return false;
166 case RISCV::JAL:
167 case RISCV::JALR:
168 return Inst.getOperand(0).getReg() != RISCV::X0;
169 }
170 }
171
172 bool isReturn(const MCInst &Inst) const override {
174 return true;
175
176 switch (Inst.getOpcode()) {
177 default:
178 return false;
179 case RISCV::JALR:
180 return Inst.getOperand(0).getReg() == RISCV::X0 &&
181 maybeReturnAddress(Inst.getOperand(1).getReg());
182 case RISCV::C_JR:
183 return maybeReturnAddress(Inst.getOperand(0).getReg());
184 }
185 }
186
187 bool isBranch(const MCInst &Inst) const override {
189 return true;
190
191 return isBranchImpl(Inst);
192 }
193
194 bool isUnconditionalBranch(const MCInst &Inst) const override {
196 return true;
197
198 return isBranchImpl(Inst);
199 }
200
201 bool isIndirectBranch(const MCInst &Inst) const override {
203 return true;
204
205 switch (Inst.getOpcode()) {
206 default:
207 return false;
208 case RISCV::JALR:
209 return Inst.getOperand(0).getReg() == RISCV::X0 &&
210 !maybeReturnAddress(Inst.getOperand(1).getReg());
211 case RISCV::C_JR:
212 return !maybeReturnAddress(Inst.getOperand(0).getReg());
213 }
214 }
215
216private:
217 static bool maybeReturnAddress(unsigned Reg) {
218 // X1 is used for normal returns, X5 for returns from outlined functions.
219 return Reg == RISCV::X1 || Reg == RISCV::X5;
220 }
221
222 static bool isBranchImpl(const MCInst &Inst) {
223 switch (Inst.getOpcode()) {
224 default:
225 return false;
226 case RISCV::JAL:
227 return Inst.getOperand(0).getReg() == RISCV::X0;
228 case RISCV::JALR:
229 return Inst.getOperand(0).getReg() == RISCV::X0 &&
230 !maybeReturnAddress(Inst.getOperand(1).getReg());
231 case RISCV::C_JR:
232 return !maybeReturnAddress(Inst.getOperand(0).getReg());
233 }
234 }
235};
236
237} // end anonymous namespace
238
240 return new RISCVMCInstrAnalysis(Info);
241}
242
243namespace {
245 std::unique_ptr<MCAsmBackend> &&MAB,
246 std::unique_ptr<MCObjectWriter> &&MOW,
247 std::unique_ptr<MCCodeEmitter> &&MCE,
248 bool RelaxAll) {
249 return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
250 std::move(MCE), RelaxAll);
251}
252} // end anonymous namespace
253
268
269 // Register the asm target streamer.
271 // Register the null target streamer.
274 }
275}
unsigned const MachineRegisterInfo * MRI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
PassInstrumentationCallbacks PIC
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
static MCInstrInfo * createRISCVMCInstrInfo()
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:74
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:540
Context object for machine code objects.
Definition: MCContext.h:76
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual bool isIndirectBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
int64_t getImm() const
Definition: MCInst.h:80
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Target specific streamer interface.
Definition: MCStreamer.h:93
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheRISCV32Target()
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheRISCV64Target()
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE, bool RelaxAll)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)