LLVM  13.0.0git
RISCVMCTargetDesc.cpp
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1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVTargetStreamer.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
29 
30 #define GET_INSTRINFO_MC_DESC
31 #include "RISCVGenInstrInfo.inc"
32 
33 #define GET_REGINFO_MC_DESC
34 #include "RISCVGenRegisterInfo.inc"
35 
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "RISCVGenSubtargetInfo.inc"
38 
39 using namespace llvm;
40 
42  MCInstrInfo *X = new MCInstrInfo();
43  InitRISCVMCInstrInfo(X);
44  return X;
45 }
46 
49  InitRISCVMCRegisterInfo(X, RISCV::X1);
50  return X;
51 }
52 
54  const Triple &TT,
55  const MCTargetOptions &Options) {
56  MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
57 
58  MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
59  MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
60  MAI->addInitialFrameState(Inst);
61 
62  return MAI;
63 }
64 
66  StringRef CPU, StringRef FS) {
67  if (CPU.empty())
68  CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
69  if (CPU == "generic")
70  report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
71  (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"));
72  return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
73 }
74 
76  unsigned SyntaxVariant,
77  const MCAsmInfo &MAI,
78  const MCInstrInfo &MII,
79  const MCRegisterInfo &MRI) {
80  return new RISCVInstPrinter(MAI, MII, MRI);
81 }
82 
83 static MCTargetStreamer *
85  const Triple &TT = STI.getTargetTriple();
86  if (TT.isOSBinFormatELF())
87  return new RISCVTargetELFStreamer(S, STI);
88  return nullptr;
89 }
90 
93  MCInstPrinter *InstPrint,
94  bool isVerboseAsm) {
95  return new RISCVTargetAsmStreamer(S, OS);
96 }
97 
99  return new RISCVTargetStreamer(S);
100 }
101 
102 namespace {
103 
104 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
105 public:
106  explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
107  : MCInstrAnalysis(Info) {}
108 
109  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
110  uint64_t &Target) const override {
111  if (isConditionalBranch(Inst)) {
112  int64_t Imm;
113  if (Size == 2)
114  Imm = Inst.getOperand(1).getImm();
115  else
116  Imm = Inst.getOperand(2).getImm();
117  Target = Addr + Imm;
118  return true;
119  }
120 
121  if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
122  Target = Addr + Inst.getOperand(0).getImm();
123  return true;
124  }
125 
126  if (Inst.getOpcode() == RISCV::JAL) {
127  Target = Addr + Inst.getOperand(1).getImm();
128  return true;
129  }
130 
131  return false;
132  }
133 };
134 
135 } // end anonymous namespace
136 
138  return new RISCVMCInstrAnalysis(Info);
139 }
140 
142  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
153 
154  // Register the asm target streamer.
156  // Register the null target streamer.
159  }
160 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm
Definition: AllocatorList.h:23
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
RISCVELFStreamer.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createRISCVNullTargetStreamer
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
Definition: RISCVMCTargetDesc.cpp:98
ErrorHandling.h
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:876
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:731
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
T
#define T
Definition: Mips16ISelLowering.cpp:341
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
createRISCVMCSubtargetInfo
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: RISCVMCTargetDesc.cpp:65
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:838
createRISCVObjectTargetStreamer
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: RISCVMCTargetDesc.cpp:84
RISCVInstPrinter.h
createRISCVAsmTargetStreamer
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: RISCVMCTargetDesc.cpp:91
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
llvm::createRISCVAsmBackend
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: RISCVAsmBackend.cpp:472
llvm::X86AS::FS
@ FS
Definition: X86.h:183
llvm::RISCVInstPrinter
Definition: RISCVInstPrinter.h:21
LLVMInitializeRISCVTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
Definition: RISCVMCTargetDesc.cpp:141
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::RISCVMCAsmInfo
Definition: RISCVMCAsmInfo.h:21
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:79
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
RISCVMCTargetDesc.h
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:91
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::MCCFIInstruction
Definition: MCDwarf.h:441
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
RISCVTargetStreamer.h
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:785
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: RISCVMCCodeEmitter.cpp:95
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:882
MCRegisterInfo.h
RISCVMCAsmInfo.h
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
llvm::TargetRegistry::RegisterMCAsmInfo
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
Definition: TargetRegistry.h:712
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:81
createRISCVInstrAnalysis
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
Definition: RISCVMCTargetDesc.cpp:137
createRISCVMCInstrInfo
static MCInstrInfo * createRISCVMCInstrInfo()
Definition: RISCVMCTargetDesc.cpp:41
createRISCVMCInstPrinter
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: RISCVMCTargetDesc.cpp:75
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:758
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::RISCVTargetAsmStreamer
Definition: RISCVTargetStreamer.h:42
MCInstrAnalysis.h
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:725
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:851
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
createRISCVMCRegisterInfo
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
Definition: RISCVMCTargetDesc.cpp:47
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:745
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:197
RISCVBaseInfo.h
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:871
llvm::RISCVTargetELFStreamer
Definition: RISCVELFStreamer.h:17
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:205
RISCVTargetInfo.h
llvm::RISCVTargetStreamer
Definition: RISCVTargetStreamer.h:19
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
createRISCVMCAsmInfo
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: RISCVMCTargetDesc.cpp:53
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22