LLVM  15.0.0git
RegAllocEvictionAdvisor.cpp
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1 //===- RegAllocEvictionAdvisor.cpp - eviction advisor ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the default eviction advisor and of the Analysis pass.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "AllocationOrder.h"
15 #include "RegAllocGreedy.h"
20 #include "llvm/InitializePasses.h"
21 #include "llvm/Pass.h"
25 
26 using namespace llvm;
27 
29  "regalloc-enable-advisor", cl::Hidden, cl::ZeroOrMore,
31  cl::desc("Enable regalloc advisor mode"),
32  cl::values(
34  "default", "Default"),
36  "release", "precompiled"),
38  "development", "for training")));
39 
41  "enable-local-reassign", cl::Hidden,
42  cl::desc("Local reassignment can yield better allocation decisions, but "
43  "may be compile time intensive"),
44  cl::init(false));
45 
47  "regalloc-eviction-max-interference-cutoff", cl::Hidden,
48  cl::desc("Number of interferences after which we declare "
49  "an interference unevictable and bail out. This "
50  "is a compilation cost-saving consideration. To "
51  "disable, pass a very large number."),
52  cl::init(10));
53 
54 #define DEBUG_TYPE "regalloc"
55 #ifdef LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL
56 #define LLVM_HAVE_TF_AOT
57 #endif
58 
61  "Regalloc eviction policy", false, true)
62 
63 namespace {
64 class DefaultEvictionAdvisorAnalysis final
66 public:
67  DefaultEvictionAdvisorAnalysis(bool NotAsRequested)
69  NotAsRequested(NotAsRequested) {}
70 
71  // support for isa<> and dyn_cast.
72  static bool classof(const RegAllocEvictionAdvisorAnalysis *R) {
73  return R->getAdvisorMode() == AdvisorMode::Default;
74  }
75 
76 private:
77  std::unique_ptr<RegAllocEvictionAdvisor>
78  getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
79  return std::make_unique<DefaultEvictionAdvisor>(MF, RA);
80  }
81  bool doInitialization(Module &M) override {
82  if (NotAsRequested)
83  M.getContext().emitError("Requested regalloc eviction advisor analysis "
84  "could be created. Using default");
86  }
87  const bool NotAsRequested;
88 };
89 } // namespace
90 
92  Pass *Ret = nullptr;
93  switch (Mode) {
95  Ret = new DefaultEvictionAdvisorAnalysis(/*NotAsRequested*/ false);
96  break;
98 #if defined(LLVM_HAVE_TF_API)
100 #endif
101  break;
103 #if defined(LLVM_HAVE_TF_AOT)
105 #endif
106  break;
107  }
108  if (Ret)
109  return Ret;
110  return new DefaultEvictionAdvisorAnalysis(/*NotAsRequested*/ true);
111 }
112 
113 StringRef RegAllocEvictionAdvisorAnalysis::getPassName() const {
114  switch (getAdvisorMode()) {
116  return "Default Regalloc Eviction Advisor";
118  return "Release mode Regalloc Eviction Advisor";
120  return "Development mode Regalloc Eviction Advisor";
121  }
122  llvm_unreachable("Unknown advisor kind");
123 }
124 
126  const RAGreedy &RA)
127  : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()),
128  LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()),
129  MRI(&VRM->getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()),
130  RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)),
131  EnableLocalReassign(EnableLocalReassignment ||
132  MF.getSubtarget().enableRALocalReassignment(
133  MF.getTarget().getOptLevel())) {}
134 
135 /// shouldEvict - determine if A should evict the assigned live range B. The
136 /// eviction policy defined by this function together with the allocation order
137 /// defined by enqueue() decides which registers ultimately end up being split
138 /// and spilled.
139 ///
140 /// Cascade numbers are used to prevent infinite loops if this function is a
141 /// cyclic relation.
142 ///
143 /// @param A The live range to be assigned.
144 /// @param IsHint True when A is about to be assigned to its preferred
145 /// register.
146 /// @param B The live range to be evicted.
147 /// @param BreaksHint True when B is already assigned to its preferred register.
148 bool DefaultEvictionAdvisor::shouldEvict(const LiveInterval &A, bool IsHint,
149  const LiveInterval &B,
150  bool BreaksHint) const {
151  bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill;
152 
153  // Be fairly aggressive about following hints as long as the evictee can be
154  // split.
155  if (CanSplit && IsHint && !BreaksHint)
156  return true;
157 
158  if (A.weight() > B.weight()) {
159  LLVM_DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight() << '\n');
160  return true;
161  }
162  return false;
163 }
164 
165 /// canEvictHintInterference - return true if the interference for VirtReg
166 /// on the PhysReg, which is VirtReg's hint, can be evicted in favor of VirtReg.
167 bool DefaultEvictionAdvisor::canEvictHintInterference(
168  const LiveInterval &VirtReg, MCRegister PhysReg,
169  const SmallVirtRegSet &FixedRegisters) const {
170  EvictionCost MaxCost;
171  MaxCost.setBrokenHints(1);
172  return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost,
173  FixedRegisters);
174 }
175 
176 /// canEvictInterferenceBasedOnCost - Return true if all interferences between
177 /// VirtReg and PhysReg can be evicted.
178 ///
179 /// @param VirtReg Live range that is about to be assigned.
180 /// @param PhysReg Desired register for assignment.
181 /// @param IsHint True when PhysReg is VirtReg's preferred register.
182 /// @param MaxCost Only look for cheaper candidates and update with new cost
183 /// when returning true.
184 /// @returns True when interference can be evicted cheaper than MaxCost.
185 bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
186  const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint,
187  EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) const {
188  // It is only possible to evict virtual register interference.
189  if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
190  return false;
191 
192  bool IsLocal = VirtReg.empty() || LIS->intervalIsInOneMBB(VirtReg);
193 
194  // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
195  // involved in an eviction before. If a cascade number was assigned, deny
196  // evicting anything with the same or a newer cascade number. This prevents
197  // infinite eviction loops.
198  //
199  // This works out so a register without a cascade number is allowed to evict
200  // anything, and it can be evicted by anything.
201  unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
202 
203  EvictionCost Cost;
204  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
205  LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
206  // If there is 10 or more interferences, chances are one is heavier.
207  const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
208  if (Interferences.size() >= EvictInterferenceCutoff)
209  return false;
210 
211  // Check if any interfering live range is heavier than MaxWeight.
212  for (const LiveInterval *Intf : reverse(Interferences)) {
213  assert(Register::isVirtualRegister(Intf->reg()) &&
214  "Only expecting virtual register interference from query");
215 
216  // Do not allow eviction of a virtual register if we are in the middle
217  // of last-chance recoloring and this virtual register is one that we
218  // have scavenged a physical register for.
219  if (FixedRegisters.count(Intf->reg()))
220  return false;
221 
222  // Never evict spill products. They cannot split or spill.
223  if (RA.getExtraInfo().getStage(*Intf) == RS_Done)
224  return false;
225  // Once a live range becomes small enough, it is urgent that we find a
226  // register for it. This is indicated by an infinite spill weight. These
227  // urgent live ranges get to evict almost anything.
228  //
229  // Also allow urgent evictions of unspillable ranges from a strictly
230  // larger allocation order.
231  bool Urgent =
232  !VirtReg.isSpillable() &&
233  (Intf->isSpillable() ||
236  MRI->getRegClass(Intf->reg())));
237  // Only evict older cascades or live ranges without a cascade.
238  unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg());
239  if (Cascade == IntfCascade)
240  return false;
241 
242  if (Cascade < IntfCascade) {
243  if (!Urgent)
244  return false;
245  // We permit breaking cascades for urgent evictions. It should be the
246  // last resort, though, so make it really expensive.
247  Cost.BrokenHints += 10;
248  }
249  // Would this break a satisfied hint?
250  bool BreaksHint = VRM->hasPreferredPhys(Intf->reg());
251  // Update eviction cost.
252  Cost.BrokenHints += BreaksHint;
253  Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight());
254  // Abort if this would be too expensive.
255  if (!(Cost < MaxCost))
256  return false;
257  if (Urgent)
258  continue;
259  // Apply the eviction policy for non-urgent evictions.
260  if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
261  return false;
262  // If !MaxCost.isMax(), then we're just looking for a cheap register.
263  // Evicting another local live range in this case could lead to suboptimal
264  // coloring.
265  if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
266  (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
267  return false;
268  }
269  }
270  }
271  MaxCost = Cost;
272  return true;
273 }
274 
275 MCRegister DefaultEvictionAdvisor::tryFindEvictionCandidate(
276  const LiveInterval &VirtReg, const AllocationOrder &Order,
277  uint8_t CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) const {
278  // Keep track of the cheapest interference seen so far.
279  EvictionCost BestCost;
280  BestCost.setMax();
281  MCRegister BestPhys;
282  auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit);
283  if (!MaybeOrderLimit)
284  return MCRegister::NoRegister;
285  unsigned OrderLimit = *MaybeOrderLimit;
286 
287  // When we are just looking for a reduced cost per use, don't break any
288  // hints, and only evict smaller spill weights.
289  if (CostPerUseLimit < uint8_t(~0u)) {
290  BestCost.BrokenHints = 0;
291  BestCost.MaxWeight = VirtReg.weight();
292  }
293 
294  for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E;
295  ++I) {
296  MCRegister PhysReg = *I;
297  assert(PhysReg);
298  if (!canAllocatePhysReg(CostPerUseLimit, PhysReg) ||
299  !canEvictInterferenceBasedOnCost(VirtReg, PhysReg, false, BestCost,
300  FixedRegisters))
301  continue;
302 
303  // Best so far.
304  BestPhys = PhysReg;
305 
306  // Stop if the hint can be used.
307  if (I.isHint())
308  break;
309  }
310  return BestPhys;
311 }
LiveRegMatrix.h
EvictInterferenceCutoff
cl::opt< unsigned > EvictInterferenceCutoff("regalloc-eviction-max-interference-cutoff", cl::Hidden, cl::desc("Number of interferences after which we declare " "an interference unevictable and bail out. This " "is a compilation cost-saving consideration. To " "disable, pass a very large number."), cl::init(10))
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:382
llvm::RegAllocEvictionAdvisorAnalysis
ImmutableAnalysis abstraction for fetching the Eviction Advisor.
Definition: RegAllocEvictionAdvisor.h:171
AllocationOrder.h
llvm::VirtRegMap::hasPreferredPhys
bool hasPreferredPhys(Register VirtReg) const
returns true if VirtReg is assigned to its preferred physreg.
Definition: VirtRegMap.cpp:109
Pass.h
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:819
llvm::LiveInterval::weight
float weight() const
Definition: LiveInterval.h:718
ErrorHandling.h
llvm::LiveIntervals::intervalIsInOneMBB
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
Definition: LiveIntervals.cpp:827
llvm::RAGreedy
Definition: RegAllocGreedy.h:62
llvm::RegAllocEvictionAdvisor::canAllocatePhysReg
bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const
Definition: RegAllocGreedy.cpp:612
RegisterClassInfo.h
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::RegAllocEvictionAdvisor::EnableLocalReassign
const bool EnableLocalReassign
Run or not the local reassignment heuristic.
Definition: RegAllocEvictionAdvisor.h:150
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MCRegister::NoRegister
static constexpr unsigned NoRegister
Definition: MCRegister.h:43
llvm::RS_Spill
@ RS_Spill
Live range will be spilled. No more splitting will be attempted.
Definition: RegAllocEvictionAdvisor.h:63
llvm::AllocationOrder::begin
Iterator begin() const
Definition: AllocationOrder.h:95
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::callDefaultCtor< RegAllocEvictionAdvisorAnalysis >
Pass * callDefaultCtor< RegAllocEvictionAdvisorAnalysis >()
Specialization for the API used by the analysis infrastructure to create an instance of the eviction ...
Definition: RegAllocEvictionAdvisor.cpp:91
llvm::RegAllocEvictionAdvisor::VRM
VirtRegMap *const VRM
Definition: RegAllocEvictionAdvisor.h:142
llvm::RegAllocEvictionAdvisorAnalysis::getAdvisorMode
AdvisorMode getAdvisorMode() const
Definition: RegAllocEvictionAdvisor.h:182
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development
@ Development
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::RegAllocEvictionAdvisor::RegAllocEvictionAdvisor
RegAllocEvictionAdvisor(const RegAllocEvictionAdvisor &)=delete
CommandLine.h
TargetMachine.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::RS_Done
@ RS_Done
There is nothing more we can do to this live range.
Definition: RegAllocEvictionAdvisor.h:71
EnableLocalReassignment
static cl::opt< bool > EnableLocalReassignment("enable-local-reassign", cl::Hidden, cl::desc("Local reassignment can yield better allocation decisions, but " "may be compile time intensive"), cl::init(false))
llvm::EvictionCost::MaxWeight
float MaxWeight
Maximum spill weight evicted.
Definition: RegAllocEvictionAdvisor.h:80
llvm::EvictionCost
Cost of evicting interference - used by default advisor, and the eviction chain heuristic in RegAlloc...
Definition: RegAllocEvictionAdvisor.h:78
llvm::createDevelopmentModeAdvisor
RegAllocEvictionAdvisorAnalysis * createDevelopmentModeAdvisor()
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::RegAllocEvictionAdvisor::LIS
LiveIntervals *const LIS
Definition: RegAllocEvictionAdvisor.h:141
llvm::RegisterClassInfo::getNumAllocatableRegs
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
Definition: RegisterClassInfo.h:91
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:116
llvm::LiveRegMatrix::query
LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegister RegUnit)
Query a line of the assigned virtual register matrix directly.
Definition: LiveRegMatrix.cpp:178
llvm::RegAllocEvictionAdvisor::TRI
const TargetRegisterInfo *const TRI
Definition: RegAllocEvictionAdvisor.h:144
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::AllocationOrder
Definition: AllocationOrder.h:30
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:685
VirtRegMap.h
llvm::AllocationOrder::getOrderLimitEnd
Iterator getOrderLimitEnd(unsigned OrderLimit) const
Definition: AllocationOrder.h:101
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INITIALIZE_PASS
INITIALIZE_PASS(RegAllocEvictionAdvisorAnalysis, "regalloc-evict", "Regalloc eviction policy", false, true) namespace
Definition: RegAllocEvictionAdvisor.cpp:60
llvm::RegAllocEvictionAdvisor::MRI
MachineRegisterInfo *const MRI
Definition: RegAllocEvictionAdvisor.h:143
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::EvictionCost::isMax
bool isMax() const
Definition: RegAllocEvictionAdvisor.h:84
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::LiveRegMatrix::IK_VirtReg
@ IK_VirtReg
Virtual register interference.
Definition: LiveRegMatrix.h:90
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::Pass::doInitialization
virtual bool doInitialization(Module &)
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
Definition: Pass.h:116
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default
@ Default
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::LiveRegMatrix::checkInterference
InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for interference before assigning VirtReg to PhysReg.
Definition: LiveRegMatrix.cpp:186
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:660
llvm::EvictionCost::BrokenHints
unsigned BrokenHints
Total number of broken hints.
Definition: RegAllocEvictionAdvisor.h:79
llvm::LiveIntervalUnion::Query::interferingVRegs
const SmallVectorImpl< const LiveInterval * > & interferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
Definition: LiveIntervalUnion.h:162
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::createReleaseModeAdvisor
RegAllocEvictionAdvisorAnalysis * createReleaseModeAdvisor()
Definition: MLRegallocEvictAdvisor.cpp:903
llvm::RegAllocEvictionAdvisor::getOrderLimit
Optional< unsigned > getOrderLimit(const LiveInterval &VirtReg, const AllocationOrder &Order, unsigned CostPerUseLimit) const
Definition: RegAllocGreedy.cpp:586
llvm::RegAllocEvictionAdvisorAnalysis::ID
static char ID
Definition: RegAllocEvictionAdvisor.h:176
llvm::RAGreedy::ExtraRegInfo::getCascade
unsigned getCascade(Register Reg) const
Definition: RegAllocGreedy.h:109
llvm::EvictionCost::setMax
void setMax()
Definition: RegAllocEvictionAdvisor.h:86
llvm::RegAllocEvictionAdvisor::RA
const RAGreedy & RA
Definition: RegAllocEvictionAdvisor.h:139
RegAllocGreedy.h
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::RegAllocEvictionAdvisor::RegClassInfo
const RegisterClassInfo & RegClassInfo
Definition: RegAllocEvictionAdvisor.h:145
llvm::RAGreedy::ExtraRegInfo::getCascadeOrCurrentNext
unsigned getCascadeOrCurrentNext(Register Reg) const
Definition: RegAllocGreedy.h:125
RegAllocEvictionAdvisor.h
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::RAGreedy::ExtraRegInfo::getStage
LiveRangeStage getStage(Register Reg) const
Definition: RegAllocGreedy.h:87
llvm::LiveIntervalUnion::Query
Query interferences between a single live virtual register and a live interval union.
Definition: LiveIntervalUnion.h:112
llvm::RegAllocEvictionAdvisor::canReassign
Register canReassign(const LiveInterval &VirtReg, Register PrevReg) const
Definition: RegAllocGreedy.cpp:423
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
Mode
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::ZeroOrMore, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
llvm::RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release
@ Release
llvm::EvictionCost::setBrokenHints
void setBrokenHints(unsigned NHints)
Definition: RegAllocEvictionAdvisor.h:88
llvm::RegAllocEvictionAdvisor::Matrix
LiveRegMatrix *const Matrix
Definition: RegAllocEvictionAdvisor.h:140
llvm::cl::desc
Definition: CommandLine.h:405
MachineFunction.h
InitializePasses.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::RAGreedy::getExtraInfo
const ExtraRegInfo & getExtraInfo() const
Definition: RegAllocGreedy.h:148