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31 cl::desc(
"Enable regalloc advisor mode"),
34 "default",
"Default"),
36 "release",
"precompiled"),
38 "development",
"for training")));
42 cl::desc(
"Local reassignment can yield better allocation decisions, but "
43 "may be compile time intensive"),
47 "regalloc-eviction-max-interference-cutoff",
cl::Hidden,
48 cl::desc(
"Number of interferences after which we declare "
49 "an interference unevictable and bail out. This "
50 "is a compilation cost-saving consideration. To "
51 "disable, pass a very large number."),
54 #define DEBUG_TYPE "regalloc"
55 #ifdef LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL
56 #define LLVM_HAVE_TF_AOT
61 "Regalloc eviction policy",
false,
true)
64 class DefaultEvictionAdvisorAnalysis final
67 DefaultEvictionAdvisorAnalysis(
bool NotAsRequested)
69 NotAsRequested(NotAsRequested) {}
77 std::unique_ptr<RegAllocEvictionAdvisor>
79 return std::make_unique<DefaultEvictionAdvisor>(MF,
RA);
81 bool doInitialization(
Module &
M)
override {
83 M.getContext().emitError(
"Requested regalloc eviction advisor analysis "
84 "could be created. Using default");
87 const bool NotAsRequested;
95 Ret =
new DefaultEvictionAdvisorAnalysis(
false);
98 #if defined(LLVM_HAVE_TF_API)
103 #if defined(LLVM_HAVE_TF_AOT)
110 return new DefaultEvictionAdvisorAnalysis(
true);
113 StringRef RegAllocEvictionAdvisorAnalysis::getPassName()
const {
116 return "Default Regalloc Eviction Advisor";
118 return "Release mode Regalloc Eviction Advisor";
120 return "Development mode Regalloc Eviction Advisor";
128 LIS(
RA.getLiveIntervals()), VRM(
RA.getVirtRegMap()),
129 MRI(&VRM->getRegInfo()),
TRI(MF.getSubtarget().getRegisterInfo()),
130 RegClassInfo(
RA.getRegClassInfo()), RegCosts(
TRI->getRegisterCosts(MF)),
132 MF.getSubtarget().enableRALocalReassignment(
133 MF.getTarget().getOptLevel())) {}
148 bool DefaultEvictionAdvisor::shouldEvict(
const LiveInterval &A,
bool IsHint,
150 bool BreaksHint)
const {
155 if (CanSplit && IsHint && !BreaksHint)
158 if (A.weight() >
B.weight()) {
159 LLVM_DEBUG(
dbgs() <<
"should evict: " <<
B <<
" w= " <<
B.weight() <<
'\n');
167 bool DefaultEvictionAdvisor::canEvictHintInterference(
172 return canEvictInterferenceBasedOnCost(VirtReg, PhysReg,
true, MaxCost,
185 bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
214 "Only expecting virtual register interference from query");
219 if (FixedRegisters.
count(Intf->reg()))
233 (Intf->isSpillable() ||
239 if (Cascade == IntfCascade)
242 if (Cascade < IntfCascade) {
255 if (!(Cost < MaxCost))
260 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
275 MCRegister DefaultEvictionAdvisor::tryFindEvictionCandidate(
277 uint8_t CostPerUseLimit,
const SmallVirtRegSet &FixedRegisters)
const {
282 auto MaybeOrderLimit =
getOrderLimit(VirtReg, Order, CostPerUseLimit);
283 if (!MaybeOrderLimit)
285 unsigned OrderLimit = *MaybeOrderLimit;
289 if (CostPerUseLimit < uint8_t(~0u)) {
299 !canEvictInterferenceBasedOnCost(VirtReg, PhysReg,
false, BestCost,
cl::opt< unsigned > EvictInterferenceCutoff("regalloc-eviction-max-interference-cutoff", cl::Hidden, cl::desc("Number of interferences after which we declare " "an interference unevictable and bail out. This " "is a compilation cost-saving consideration. To " "disable, pass a very large number."), cl::init(10))
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
ImmutableAnalysis abstraction for fetching the Eviction Advisor.
bool hasPreferredPhys(Register VirtReg) const
returns true if VirtReg is assigned to its preferred physreg.
bool isSpillable() const
isSpillable - Can this interval be spilled?
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const
const bool EnableLocalReassign
Run or not the local reassignment heuristic.
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
static constexpr unsigned NoRegister
@ RS_Spill
Live range will be spilled. No more splitting will be attempted.
Pass * callDefaultCtor< RegAllocEvictionAdvisorAnalysis >()
Specialization for the API used by the analysis infrastructure to create an instance of the eviction ...
AdvisorMode getAdvisorMode() const
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
RegAllocEvictionAdvisor(const RegAllocEvictionAdvisor &)=delete
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
@ RS_Done
There is nothing more we can do to this live range.
static cl::opt< bool > EnableLocalReassignment("enable-local-reassign", cl::Hidden, cl::desc("Local reassignment can yield better allocation decisions, but " "may be compile time intensive"), cl::init(false))
float MaxWeight
Maximum spill weight evicted.
Cost of evicting interference - used by default advisor, and the eviction chain heuristic in RegAlloc...
RegAllocEvictionAdvisorAnalysis * createDevelopmentModeAdvisor()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
LiveInterval - This class represents the liveness of a register, or stack slot.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegister RegUnit)
Query a line of the assigned virtual register matrix directly.
const TargetRegisterInfo *const TRI
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Iterator getOrderLimitEnd(unsigned OrderLimit) const
initializer< Ty > init(const Ty &Val)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INITIALIZE_PASS(RegAllocEvictionAdvisorAnalysis, "regalloc-evict", "Regalloc eviction policy", false, true) namespace
MachineRegisterInfo *const MRI
A Module instance is used to store all the information related to an LLVM module.
SI optimize exec mask operations pre RA
@ IK_VirtReg
Virtual register interference.
virtual bool doInitialization(Module &)
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for interference before assigning VirtReg to PhysReg.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
unsigned BrokenHints
Total number of broken hints.
const SmallVectorImpl< const LiveInterval * > & interferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
unsigned const MachineRegisterInfo * MRI
RegAllocEvictionAdvisorAnalysis * createReleaseModeAdvisor()
Optional< unsigned > getOrderLimit(const LiveInterval &VirtReg, const AllocationOrder &Order, unsigned CostPerUseLimit) const
const RegisterClassInfo & RegClassInfo
Pass interface - Implemented by all 'passes'.
Query interferences between a single live virtual register and a live interval union.
Register canReassign(const LiveInterval &VirtReg, Register PrevReg) const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Align max(MaybeAlign Lhs, Align Rhs)
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::ZeroOrMore, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
void setBrokenHints(unsigned NHints)
LiveRegMatrix *const Matrix
Wrapper class representing physical registers. Should be passed by value.
const ExtraRegInfo & getExtraInfo() const