LLVM  14.0.0git
LiveIntervals.cpp
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1 //===- LiveIntervals.cpp - Live Interval Analysis -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LiveInterval analysis pass which is used
10 /// by the Linear Scan Register allocator. This pass linearizes the
11 /// basic blocks of the function in DFS order and computes live intervals for
12 /// each virtual and physical register.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/Config/llvm-config.h"
40 #include "llvm/IR/InstrTypes.h"
41 #include "llvm/IR/Statepoint.h"
42 #include "llvm/MC/LaneBitmask.h"
43 #include "llvm/MC/MCRegisterInfo.h"
44 #include "llvm/Pass.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
51 #include "llvm/CodeGen/StackMaps.h"
52 #include <algorithm>
53 #include <cassert>
54 #include <cstdint>
55 #include <iterator>
56 #include <tuple>
57 #include <utility>
58 
59 using namespace llvm;
60 
61 #define DEBUG_TYPE "regalloc"
62 
63 char LiveIntervals::ID = 0;
65 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
66  "Live Interval Analysis", false, false)
71  "Live Interval Analysis", false, false)
72 
73 #ifndef NDEBUG
75  "precompute-phys-liveness", cl::Hidden,
76  cl::desc("Eagerly compute live intervals for all physreg units."));
77 #else
78 static bool EnablePrecomputePhysRegs = false;
79 #endif // NDEBUG
80 
81 namespace llvm {
82 
84  "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
85  cl::desc(
86  "Use segment set for the computation of the live ranges of physregs."));
87 
88 } // end namespace llvm
89 
91  AU.setPreservesCFG();
101 }
102 
105 }
106 
107 LiveIntervals::~LiveIntervals() { delete LICalc; }
108 
110  // Free the live intervals themselves.
111  for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
112  delete VirtRegIntervals[Register::index2VirtReg(i)];
113  VirtRegIntervals.clear();
114  RegMaskSlots.clear();
115  RegMaskBits.clear();
116  RegMaskBlocks.clear();
117 
118  for (LiveRange *LR : RegUnitRanges)
119  delete LR;
120  RegUnitRanges.clear();
121 
122  // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
123  VNInfoAllocator.Reset();
124 }
125 
127  MF = &fn;
128  MRI = &MF->getRegInfo();
129  TRI = MF->getSubtarget().getRegisterInfo();
130  TII = MF->getSubtarget().getInstrInfo();
131  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
132  Indexes = &getAnalysis<SlotIndexes>();
133  DomTree = &getAnalysis<MachineDominatorTree>();
134 
135  if (!LICalc)
136  LICalc = new LiveIntervalCalc();
137 
138  // Allocate space for all virtual registers.
139  VirtRegIntervals.resize(MRI->getNumVirtRegs());
140 
141  computeVirtRegs();
142  computeRegMasks();
143  computeLiveInRegUnits();
144 
146  // For stress testing, precompute live ranges of all physical register
147  // units, including reserved registers.
148  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
149  getRegUnit(i);
150  }
151  LLVM_DEBUG(dump());
152  return true;
153 }
154 
155 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
156  OS << "********** INTERVALS **********\n";
157 
158  // Dump the regunits.
159  for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)
160  if (LiveRange *LR = RegUnitRanges[Unit])
161  OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n';
162 
163  // Dump the virtregs.
164  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
166  if (hasInterval(Reg))
167  OS << getInterval(Reg) << '\n';
168  }
169 
170  OS << "RegMasks:";
171  for (SlotIndex Idx : RegMaskSlots)
172  OS << ' ' << Idx;
173  OS << '\n';
174 
175  printInstrs(OS);
176 }
177 
178 void LiveIntervals::printInstrs(raw_ostream &OS) const {
179  OS << "********** MACHINEINSTRS **********\n";
180  MF->print(OS, Indexes);
181 }
182 
183 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
184 LLVM_DUMP_METHOD void LiveIntervals::dumpInstrs() const {
185  printInstrs(dbgs());
186 }
187 #endif
188 
189 LiveInterval *LiveIntervals::createInterval(Register reg) {
190  float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F;
191  return new LiveInterval(reg, Weight);
192 }
193 
194 /// Compute the live interval of a virtual register, based on defs and uses.
195 bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
196  assert(LICalc && "LICalc not initialized.");
197  assert(LI.empty() && "Should only compute empty intervals.");
198  LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
199  LICalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg()));
200  return computeDeadValues(LI, nullptr);
201 }
202 
203 void LiveIntervals::computeVirtRegs() {
204  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
206  if (MRI->reg_nodbg_empty(Reg))
207  continue;
209  bool NeedSplit = computeVirtRegInterval(LI);
210  if (NeedSplit) {
212  splitSeparateComponents(LI, SplitLIs);
213  }
214  }
215 }
216 
217 void LiveIntervals::computeRegMasks() {
218  RegMaskBlocks.resize(MF->getNumBlockIDs());
219 
220  // Find all instructions with regmask operands.
221  for (const MachineBasicBlock &MBB : *MF) {
222  std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];
223  RMB.first = RegMaskSlots.size();
224 
225  // Some block starts, such as EH funclets, create masks.
226  if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
227  RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
228  RegMaskBits.push_back(Mask);
229  }
230 
231  // Unwinders may clobber additional registers.
232  // FIXME: This functionality can possibly be merged into
233  // MachineBasicBlock::getBeginClobberMask().
234  if (MBB.isEHPad())
235  if (auto *Mask = TRI->getCustomEHPadPreservedMask(*MBB.getParent())) {
236  RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
237  RegMaskBits.push_back(Mask);
238  }
239 
240  for (const MachineInstr &MI : MBB) {
241  for (const MachineOperand &MO : MI.operands()) {
242  if (!MO.isRegMask())
243  continue;
244  RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
245  RegMaskBits.push_back(MO.getRegMask());
246  }
247  }
248 
249  // Some block ends, such as funclet returns, create masks. Put the mask on
250  // the last instruction of the block, because MBB slot index intervals are
251  // half-open.
252  if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
253  assert(!MBB.empty() && "empty return block?");
254  RegMaskSlots.push_back(
255  Indexes->getInstructionIndex(MBB.back()).getRegSlot());
256  RegMaskBits.push_back(Mask);
257  }
258 
259  // Compute the number of register mask instructions in this block.
260  RMB.second = RegMaskSlots.size() - RMB.first;
261  }
262 }
263 
264 //===----------------------------------------------------------------------===//
265 // Register Unit Liveness
266 //===----------------------------------------------------------------------===//
267 //
268 // Fixed interference typically comes from ABI boundaries: Function arguments
269 // and return values are passed in fixed registers, and so are exception
270 // pointers entering landing pads. Certain instructions require values to be
271 // present in specific registers. That is also represented through fixed
272 // interference.
273 //
274 
275 /// Compute the live range of a register unit, based on the uses and defs of
276 /// aliasing registers. The range should be empty, or contain only dead
277 /// phi-defs from ABI blocks.
278 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
279  assert(LICalc && "LICalc not initialized.");
280  LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
281 
282  // The physregs aliasing Unit are the roots and their super-registers.
283  // Create all values as dead defs before extending to uses. Note that roots
284  // may share super-registers. That's OK because createDeadDefs() is
285  // idempotent. It is very rare for a register unit to have multiple roots, so
286  // uniquing super-registers is probably not worthwhile.
287  bool IsReserved = false;
288  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
289  bool IsRootReserved = true;
290  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
291  Super.isValid(); ++Super) {
292  MCRegister Reg = *Super;
293  if (!MRI->reg_empty(Reg))
294  LICalc->createDeadDefs(LR, Reg);
295  // A register unit is considered reserved if all its roots and all their
296  // super registers are reserved.
297  if (!MRI->isReserved(Reg))
298  IsRootReserved = false;
299  }
300  IsReserved |= IsRootReserved;
301  }
302  assert(IsReserved == MRI->isReservedRegUnit(Unit) &&
303  "reserved computation mismatch");
304 
305  // Now extend LR to reach all uses.
306  // Ignore uses of reserved registers. We only track defs of those.
307  if (!IsReserved) {
308  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
309  for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
310  Super.isValid(); ++Super) {
311  MCRegister Reg = *Super;
312  if (!MRI->reg_empty(Reg))
313  LICalc->extendToUses(LR, Reg);
314  }
315  }
316  }
317 
318  // Flush the segment set to the segment vector.
320  LR.flushSegmentSet();
321 }
322 
323 /// Precompute the live ranges of any register units that are live-in to an ABI
324 /// block somewhere. Register values can appear without a corresponding def when
325 /// entering the entry block or a landing pad.
326 void LiveIntervals::computeLiveInRegUnits() {
327  RegUnitRanges.resize(TRI->getNumRegUnits());
328  LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
329 
330  // Keep track of the live range sets allocated.
331  SmallVector<unsigned, 8> NewRanges;
332 
333  // Check all basic blocks for live-ins.
334  for (const MachineBasicBlock &MBB : *MF) {
335  // We only care about ABI blocks: Entry + landing pads.
336  if ((&MBB != &MF->front() && !MBB.isEHPad()) || MBB.livein_empty())
337  continue;
338 
339  // Create phi-defs at Begin for all live-in registers.
340  SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
341  LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
342  for (const auto &LI : MBB.liveins()) {
343  for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
344  unsigned Unit = *Units;
345  LiveRange *LR = RegUnitRanges[Unit];
346  if (!LR) {
347  // Use segment set to speed-up initial computation of the live range.
348  LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
349  NewRanges.push_back(Unit);
350  }
351  VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
352  (void)VNI;
353  LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
354  }
355  }
356  LLVM_DEBUG(dbgs() << '\n');
357  }
358  LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
359 
360  // Compute the 'normal' part of the ranges.
361  for (unsigned Unit : NewRanges)
362  computeRegUnitRange(*RegUnitRanges[Unit], Unit);
363 }
364 
367  for (VNInfo *VNI : VNIs) {
368  if (VNI->isUnused())
369  continue;
370  SlotIndex Def = VNI->def;
371  LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
372  }
373 }
374 
375 void LiveIntervals::extendSegmentsToUses(LiveRange &Segments,
376  ShrinkToUsesWorkList &WorkList,
377  Register Reg, LaneBitmask LaneMask) {
378  // Keep track of the PHIs that are in use.
379  SmallPtrSet<VNInfo*, 8> UsedPHIs;
380  // Blocks that have already been added to WorkList as live-out.
382 
383  auto getSubRange = [](const LiveInterval &I, LaneBitmask M)
384  -> const LiveRange& {
385  if (M.none())
386  return I;
387  for (const LiveInterval::SubRange &SR : I.subranges()) {
388  if ((SR.LaneMask & M).any()) {
389  assert(SR.LaneMask == M && "Expecting lane masks to match exactly");
390  return SR;
391  }
392  }
393  llvm_unreachable("Subrange for mask not found");
394  };
395 
396  const LiveInterval &LI = getInterval(Reg);
397  const LiveRange &OldRange = getSubRange(LI, LaneMask);
398 
399  // Extend intervals to reach all uses in WorkList.
400  while (!WorkList.empty()) {
401  SlotIndex Idx = WorkList.back().first;
402  VNInfo *VNI = WorkList.back().second;
403  WorkList.pop_back();
404  const MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Idx.getPrevSlot());
405  SlotIndex BlockStart = Indexes->getMBBStartIdx(MBB);
406 
407  // Extend the live range for VNI to be live at Idx.
408  if (VNInfo *ExtVNI = Segments.extendInBlock(BlockStart, Idx)) {
409  assert(ExtVNI == VNI && "Unexpected existing value number");
410  (void)ExtVNI;
411  // Is this a PHIDef we haven't seen before?
412  if (!VNI->isPHIDef() || VNI->def != BlockStart ||
413  !UsedPHIs.insert(VNI).second)
414  continue;
415  // The PHI is live, make sure the predecessors are live-out.
416  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
417  if (!LiveOut.insert(Pred).second)
418  continue;
419  SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
420  // A predecessor is not required to have a live-out value for a PHI.
421  if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
422  WorkList.push_back(std::make_pair(Stop, PVNI));
423  }
424  continue;
425  }
426 
427  // VNI is live-in to MBB.
428  LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
429  Segments.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
430 
431  // Make sure VNI is live-out from the predecessors.
432  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
433  if (!LiveOut.insert(Pred).second)
434  continue;
435  SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
436  if (VNInfo *OldVNI = OldRange.getVNInfoBefore(Stop)) {
437  assert(OldVNI == VNI && "Wrong value out of predecessor");
438  (void)OldVNI;
439  WorkList.push_back(std::make_pair(Stop, VNI));
440  } else {
441 #ifndef NDEBUG
442  // There was no old VNI. Verify that Stop is jointly dominated
443  // by <undef>s for this live range.
444  assert(LaneMask.any() &&
445  "Missing value out of predecessor for main range");
447  LI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
448  assert(LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes) &&
449  "Missing value out of predecessor for subrange");
450 #endif
451  }
452  }
453  }
454 }
455 
458  LLVM_DEBUG(dbgs() << "Shrink: " << *li << '\n');
460  "Can only shrink virtual registers");
461 
462  // Shrink subregister live ranges.
463  bool NeedsCleanup = false;
464  for (LiveInterval::SubRange &S : li->subranges()) {
465  shrinkToUses(S, li->reg());
466  if (S.empty())
467  NeedsCleanup = true;
468  }
469  if (NeedsCleanup)
470  li->removeEmptySubRanges();
471 
472  // Find all the values used, including PHI kills.
473  ShrinkToUsesWorkList WorkList;
474 
475  // Visit all instructions reading li->reg().
476  Register Reg = li->reg();
477  for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
478  if (UseMI.isDebugInstr() || !UseMI.readsVirtualRegister(Reg))
479  continue;
481  LiveQueryResult LRQ = li->Query(Idx);
482  VNInfo *VNI = LRQ.valueIn();
483  if (!VNI) {
484  // This shouldn't happen: readsVirtualRegister returns true, but there is
485  // no live value. It is likely caused by a target getting <undef> flags
486  // wrong.
487  LLVM_DEBUG(
488  dbgs() << Idx << '\t' << UseMI
489  << "Warning: Instr claims to read non-existent value in "
490  << *li << '\n');
491  continue;
492  }
493  // Special case: An early-clobber tied operand reads and writes the
494  // register one slot early.
495  if (VNInfo *DefVNI = LRQ.valueDefined())
496  Idx = DefVNI->def;
497 
498  WorkList.push_back(std::make_pair(Idx, VNI));
499  }
500 
501  // Create new live ranges with only minimal live segments per def.
502  LiveRange NewLR;
503  createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
504  extendSegmentsToUses(NewLR, WorkList, Reg, LaneBitmask::getNone());
505 
506  // Move the trimmed segments back.
507  li->segments.swap(NewLR.segments);
508 
509  // Handle dead values.
510  bool CanSeparate = computeDeadValues(*li, dead);
511  LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n');
512  return CanSeparate;
513 }
514 
515 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
517  bool MayHaveSplitComponents = false;
518  bool HaveDeadDef = false;
519 
520  for (VNInfo *VNI : LI.valnos) {
521  if (VNI->isUnused())
522  continue;
523  SlotIndex Def = VNI->def;
525  assert(I != LI.end() && "Missing segment for VNI");
526 
527  // Is the register live before? Otherwise we may have to add a read-undef
528  // flag for subregister defs.
529  Register VReg = LI.reg();
530  if (MRI->shouldTrackSubRegLiveness(VReg)) {
531  if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
533  MI->setRegisterDefReadUndef(VReg);
534  }
535  }
536 
537  if (I->end != Def.getDeadSlot())
538  continue;
539  if (VNI->isPHIDef()) {
540  // This is a dead PHI. Remove it.
541  VNI->markUnused();
542  LI.removeSegment(I);
543  LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
544  MayHaveSplitComponents = true;
545  } else {
546  // This is a dead def. Make sure the instruction knows.
548  assert(MI && "No instruction defining live value");
549  MI->addRegisterDead(LI.reg(), TRI);
550  if (HaveDeadDef)
551  MayHaveSplitComponents = true;
552  HaveDeadDef = true;
553 
554  if (dead && MI->allDefsAreDead()) {
555  LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
556  dead->push_back(MI);
557  }
558  }
559  }
560  return MayHaveSplitComponents;
561 }
562 
564  LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n');
566  "Can only shrink virtual registers");
567  // Find all the values used, including PHI kills.
568  ShrinkToUsesWorkList WorkList;
569 
570  // Visit all instructions reading Reg.
571  SlotIndex LastIdx;
572  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
573  // Skip "undef" uses.
574  if (!MO.readsReg())
575  continue;
576  // Maybe the operand is for a subregister we don't care about.
577  unsigned SubReg = MO.getSubReg();
578  if (SubReg != 0) {
579  LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
580  if ((LaneMask & SR.LaneMask).none())
581  continue;
582  }
583  // We only need to visit each instruction once.
584  MachineInstr *UseMI = MO.getParent();
585  SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
586  if (Idx == LastIdx)
587  continue;
588  LastIdx = Idx;
589 
590  LiveQueryResult LRQ = SR.Query(Idx);
591  VNInfo *VNI = LRQ.valueIn();
592  // For Subranges it is possible that only undef values are left in that
593  // part of the subregister, so there is no real liverange at the use
594  if (!VNI)
595  continue;
596 
597  // Special case: An early-clobber tied operand reads and writes the
598  // register one slot early.
599  if (VNInfo *DefVNI = LRQ.valueDefined())
600  Idx = DefVNI->def;
601 
602  WorkList.push_back(std::make_pair(Idx, VNI));
603  }
604 
605  // Create a new live ranges with only minimal live segments per def.
606  LiveRange NewLR;
608  extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);
609 
610  // Move the trimmed ranges back.
611  SR.segments.swap(NewLR.segments);
612 
613  // Remove dead PHI value numbers
614  for (VNInfo *VNI : SR.valnos) {
615  if (VNI->isUnused())
616  continue;
617  const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
618  assert(Segment != nullptr && "Missing segment for VNI");
619  if (Segment->end != VNI->def.getDeadSlot())
620  continue;
621  if (VNI->isPHIDef()) {
622  // This is a dead PHI. Remove it.
623  LLVM_DEBUG(dbgs() << "Dead PHI at " << VNI->def
624  << " may separate interval\n");
625  VNI->markUnused();
626  SR.removeSegment(*Segment);
627  }
628  }
629 
630  LLVM_DEBUG(dbgs() << "Shrunk: " << SR << '\n');
631 }
632 
634  ArrayRef<SlotIndex> Indices,
635  ArrayRef<SlotIndex> Undefs) {
636  assert(LICalc && "LICalc not initialized.");
637  LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
638  for (SlotIndex Idx : Indices)
639  LICalc->extend(LR, Idx, /*PhysReg=*/0, Undefs);
640 }
641 
643  SmallVectorImpl<SlotIndex> *EndPoints) {
644  LiveQueryResult LRQ = LR.Query(Kill);
645  VNInfo *VNI = LRQ.valueOutOrDead();
646  if (!VNI)
647  return;
648 
649  MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
650  SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
651 
652  // If VNI isn't live out from KillMBB, the value is trivially pruned.
653  if (LRQ.endPoint() < MBBEnd) {
654  LR.removeSegment(Kill, LRQ.endPoint());
655  if (EndPoints) EndPoints->push_back(LRQ.endPoint());
656  return;
657  }
658 
659  // VNI is live out of KillMBB.
660  LR.removeSegment(Kill, MBBEnd);
661  if (EndPoints) EndPoints->push_back(MBBEnd);
662 
663  // Find all blocks that are reachable from KillMBB without leaving VNI's live
664  // range. It is possible that KillMBB itself is reachable, so start a DFS
665  // from each successor.
667  VisitedTy Visited;
668  for (MachineBasicBlock *Succ : KillMBB->successors()) {
670  I = df_ext_begin(Succ, Visited), E = df_ext_end(Succ, Visited);
671  I != E;) {
672  MachineBasicBlock *MBB = *I;
673 
674  // Check if VNI is live in to MBB.
675  SlotIndex MBBStart, MBBEnd;
676  std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
677  LiveQueryResult LRQ = LR.Query(MBBStart);
678  if (LRQ.valueIn() != VNI) {
679  // This block isn't part of the VNI segment. Prune the search.
680  I.skipChildren();
681  continue;
682  }
683 
684  // Prune the search if VNI is killed in MBB.
685  if (LRQ.endPoint() < MBBEnd) {
686  LR.removeSegment(MBBStart, LRQ.endPoint());
687  if (EndPoints) EndPoints->push_back(LRQ.endPoint());
688  I.skipChildren();
689  continue;
690  }
691 
692  // VNI is live through MBB.
693  LR.removeSegment(MBBStart, MBBEnd);
694  if (EndPoints) EndPoints->push_back(MBBEnd);
695  ++I;
696  }
697  }
698 }
699 
700 //===----------------------------------------------------------------------===//
701 // Register allocator hooks.
702 //
703 
705  // Keep track of regunit ranges.
707 
708  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
710  if (MRI->reg_nodbg_empty(Reg))
711  continue;
712  const LiveInterval &LI = getInterval(Reg);
713  if (LI.empty())
714  continue;
715 
716  // Target may have not allocated this yet.
717  Register PhysReg = VRM->getPhys(Reg);
718  if (!PhysReg)
719  continue;
720 
721  // Find the regunit intervals for the assigned register. They may overlap
722  // the virtual register live range, cancelling any kills.
723  RU.clear();
724  for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid();
725  ++Unit) {
726  const LiveRange &RURange = getRegUnit(*Unit);
727  if (RURange.empty())
728  continue;
729  RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
730  }
731  // Every instruction that kills Reg corresponds to a segment range end
732  // point.
733  for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
734  ++RI) {
735  // A block index indicates an MBB edge.
736  if (RI->end.isBlock())
737  continue;
739  if (!MI)
740  continue;
741 
742  // Check if any of the regunits are live beyond the end of RI. That could
743  // happen when a physreg is defined as a copy of a virtreg:
744  //
745  // %eax = COPY %5
746  // FOO %5 <--- MI, cancel kill because %eax is live.
747  // BAR killed %eax
748  //
749  // There should be no kill flag on FOO when %5 is rewritten as %eax.
750  for (auto &RUP : RU) {
751  const LiveRange &RURange = *RUP.first;
752  LiveRange::const_iterator &I = RUP.second;
753  if (I == RURange.end())
754  continue;
755  I = RURange.advanceTo(I, RI->end);
756  if (I == RURange.end() || I->start >= RI->end)
757  continue;
758  // I is overlapping RI.
759  goto CancelKill;
760  }
761 
762  if (MRI->subRegLivenessEnabled()) {
763  // When reading a partial undefined value we must not add a kill flag.
764  // The regalloc might have used the undef lane for something else.
765  // Example:
766  // %1 = ... ; R32: %1
767  // %2:high16 = ... ; R64: %2
768  // = read killed %2 ; R64: %2
769  // = read %1 ; R32: %1
770  // The <kill> flag is correct for %2, but the register allocator may
771  // assign R0L to %1, and R0 to %2 because the low 32bits of R0
772  // are actually never written by %2. After assignment the <kill>
773  // flag at the read instruction is invalid.
774  LaneBitmask DefinedLanesMask;
775  if (LI.hasSubRanges()) {
776  // Compute a mask of lanes that are defined.
777  DefinedLanesMask = LaneBitmask::getNone();
778  for (const LiveInterval::SubRange &SR : LI.subranges())
779  for (const LiveRange::Segment &Segment : SR.segments) {
780  if (Segment.start >= RI->end)
781  break;
782  if (Segment.end == RI->end) {
783  DefinedLanesMask |= SR.LaneMask;
784  break;
785  }
786  }
787  } else
788  DefinedLanesMask = LaneBitmask::getAll();
789 
790  bool IsFullWrite = false;
791  for (const MachineOperand &MO : MI->operands()) {
792  if (!MO.isReg() || MO.getReg() != Reg)
793  continue;
794  if (MO.isUse()) {
795  // Reading any undefined lanes?
796  unsigned SubReg = MO.getSubReg();
798  : MRI->getMaxLaneMaskForVReg(Reg);
799  if ((UseMask & ~DefinedLanesMask).any())
800  goto CancelKill;
801  } else if (MO.getSubReg() == 0) {
802  // Writing to the full register?
803  assert(MO.isDef());
804  IsFullWrite = true;
805  }
806  }
807 
808  // If an instruction writes to a subregister, a new segment starts in
809  // the LiveInterval. But as this is only overriding part of the register
810  // adding kill-flags is not correct here after registers have been
811  // assigned.
812  if (!IsFullWrite) {
813  // Next segment has to be adjacent in the subregister write case.
814  LiveRange::const_iterator N = std::next(RI);
815  if (N != LI.end() && N->start == RI->end)
816  goto CancelKill;
817  }
818  }
819 
820  MI->addRegisterKilled(Reg, nullptr);
821  continue;
822 CancelKill:
823  MI->clearRegisterKills(Reg, nullptr);
824  }
825  }
826 }
827 
830  // A local live range must be fully contained inside the block, meaning it is
831  // defined and killed at instructions, not at block boundaries. It is not
832  // live in or out of any block.
833  //
834  // It is technically possible to have a PHI-defined live range identical to a
835  // single block, but we are going to return false in that case.
836 
837  SlotIndex Start = LI.beginIndex();
838  if (Start.isBlock())
839  return nullptr;
840 
841  SlotIndex Stop = LI.endIndex();
842  if (Stop.isBlock())
843  return nullptr;
844 
845  // getMBBFromIndex doesn't need to search the MBB table when both indexes
846  // belong to proper instructions.
847  MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
848  MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
849  return MBB1 == MBB2 ? MBB1 : nullptr;
850 }
851 
852 bool
853 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
854  for (const VNInfo *PHI : LI.valnos) {
855  if (PHI->isUnused() || !PHI->isPHIDef())
856  continue;
857  const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
858  // Conservatively return true instead of scanning huge predecessor lists.
859  if (PHIMBB->pred_size() > 100)
860  return true;
861  for (const MachineBasicBlock *Pred : PHIMBB->predecessors())
862  if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(Pred)))
863  return true;
864  }
865  return false;
866 }
867 
868 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
869  const MachineBlockFrequencyInfo *MBFI,
870  const MachineInstr &MI) {
871  return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
872 }
873 
874 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
875  const MachineBlockFrequencyInfo *MBFI,
876  const MachineBasicBlock *MBB) {
877  return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB);
878 }
879 
883  VNInfo *VN = Interval.getNextValue(
884  SlotIndex(getInstructionIndex(startInst).getRegSlot()),
886  LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
887  getMBBEndIdx(startInst.getParent()), VN);
888  Interval.addSegment(S);
889 
890  return S;
891 }
892 
893 //===----------------------------------------------------------------------===//
894 // Register mask functions
895 //===----------------------------------------------------------------------===//
896 /// Check whether use of reg in MI is live-through. Live-through means that
897 /// the value is alive on exit from Machine instruction. The example of such
898 /// use is a deopt value in statepoint instruction.
900  if (MI->getOpcode() != TargetOpcode::STATEPOINT)
901  return false;
902  StatepointOpers SO(MI);
904  return false;
905  for (unsigned Idx = SO.getNumDeoptArgsIdx(), E = SO.getNumGCPtrIdx(); Idx < E;
906  ++Idx) {
907  const MachineOperand &MO = MI->getOperand(Idx);
908  if (MO.isReg() && MO.getReg() == Reg)
909  return true;
910  }
911  return false;
912 }
913 
915  BitVector &UsableRegs) {
916  if (LI.empty())
917  return false;
918  LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
919 
920  // Use a smaller arrays for local live ranges.
921  ArrayRef<SlotIndex> Slots;
926  } else {
927  Slots = getRegMaskSlots();
928  Bits = getRegMaskBits();
929  }
930 
931  // We are going to enumerate all the register mask slots contained in LI.
932  // Start with a binary search of RegMaskSlots to find a starting point.
933  ArrayRef<SlotIndex>::iterator SlotI = llvm::lower_bound(Slots, LiveI->start);
934  ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
935 
936  // No slots in range, LI begins after the last call.
937  if (SlotI == SlotE)
938  return false;
939 
940  bool Found = false;
941  // Utility to union regmasks.
942  auto unionBitMask = [&](unsigned Idx) {
943  if (!Found) {
944  // This is the first overlap. Initialize UsableRegs to all ones.
945  UsableRegs.clear();
946  UsableRegs.resize(TRI->getNumRegs(), true);
947  Found = true;
948  }
949  // Remove usable registers clobbered by this mask.
950  UsableRegs.clearBitsNotInMask(Bits[Idx]);
951  };
952  while (true) {
953  assert(*SlotI >= LiveI->start);
954  // Loop over all slots overlapping this segment.
955  while (*SlotI < LiveI->end) {
956  // *SlotI overlaps LI. Collect mask bits.
957  unionBitMask(SlotI - Slots.begin());
958  if (++SlotI == SlotE)
959  return Found;
960  }
961  // If segment ends with live-through use we need to collect its regmask.
962  if (*SlotI == LiveI->end)
963  if (MachineInstr *MI = getInstructionFromIndex(*SlotI))
964  if (hasLiveThroughUse(MI, LI.reg()))
965  unionBitMask(SlotI++ - Slots.begin());
966  // *SlotI is beyond the current LI segment.
967  // Special advance implementation to not miss next LiveI->end.
968  if (++LiveI == LiveE || SlotI == SlotE || *SlotI > LI.endIndex())
969  return Found;
970  while (LiveI->end < *SlotI)
971  ++LiveI;
972  // Advance SlotI until it overlaps.
973  while (*SlotI < LiveI->start)
974  if (++SlotI == SlotE)
975  return Found;
976  }
977 }
978 
979 //===----------------------------------------------------------------------===//
980 // IntervalUpdate class.
981 //===----------------------------------------------------------------------===//
982 
983 /// Toolkit used by handleMove to trim or extend live intervals.
985 private:
986  LiveIntervals& LIS;
987  const MachineRegisterInfo& MRI;
988  const TargetRegisterInfo& TRI;
989  SlotIndex OldIdx;
990  SlotIndex NewIdx;
992  bool UpdateFlags;
993 
994 public:
996  const TargetRegisterInfo& TRI,
997  SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
998  : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
999  UpdateFlags(UpdateFlags) {}
1000 
1001  // FIXME: UpdateFlags is a workaround that creates live intervals for all
1002  // physregs, even those that aren't needed for regalloc, in order to update
1003  // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
1004  // flags, and postRA passes will use a live register utility instead.
1005  LiveRange *getRegUnitLI(unsigned Unit) {
1006  if (UpdateFlags && !MRI.isReservedRegUnit(Unit))
1007  return &LIS.getRegUnit(Unit);
1008  return LIS.getCachedRegUnit(Unit);
1009  }
1010 
1011  /// Update all live ranges touched by MI, assuming a move from OldIdx to
1012  /// NewIdx.
1014  LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "
1015  << *MI);
1016  bool hasRegMask = false;
1017  for (MachineOperand &MO : MI->operands()) {
1018  if (MO.isRegMask())
1019  hasRegMask = true;
1020  if (!MO.isReg())
1021  continue;
1022  if (MO.isUse()) {
1023  if (!MO.readsReg())
1024  continue;
1025  // Aggressively clear all kill flags.
1026  // They are reinserted by VirtRegRewriter.
1027  MO.setIsKill(false);
1028  }
1029 
1030  Register Reg = MO.getReg();
1031  if (!Reg)
1032  continue;
1034  LiveInterval &LI = LIS.getInterval(Reg);
1035  if (LI.hasSubRanges()) {
1036  unsigned SubReg = MO.getSubReg();
1039  for (LiveInterval::SubRange &S : LI.subranges()) {
1040  if ((S.LaneMask & LaneMask).none())
1041  continue;
1042  updateRange(S, Reg, S.LaneMask);
1043  }
1044  }
1045  updateRange(LI, Reg, LaneBitmask::getNone());
1046  // If main range has a hole and we are moving a subrange use across
1047  // the hole updateRange() cannot properly handle it since it only
1048  // gets the LiveRange and not the whole LiveInterval. As a result
1049  // we may end up with a main range not covering all subranges.
1050  // This is extremely rare case, so let's check and reconstruct the
1051  // main range.
1052  for (LiveInterval::SubRange &S : LI.subranges()) {
1053  if (LI.covers(S))
1054  continue;
1055  LI.clear();
1057  break;
1058  }
1059 
1060  continue;
1061  }
1062 
1063  // For physregs, only update the regunits that actually have a
1064  // precomputed live range.
1065  for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
1066  ++Units)
1067  if (LiveRange *LR = getRegUnitLI(*Units))
1068  updateRange(*LR, *Units, LaneBitmask::getNone());
1069  }
1070  if (hasRegMask)
1071  updateRegMaskSlots();
1072  }
1073 
1074 private:
1075  /// Update a single live range, assuming an instruction has been moved from
1076  /// OldIdx to NewIdx.
1077  void updateRange(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
1078  if (!Updated.insert(&LR).second)
1079  return;
1080  LLVM_DEBUG({
1081  dbgs() << " ";
1083  dbgs() << printReg(Reg);
1084  if (LaneMask.any())
1085  dbgs() << " L" << PrintLaneMask(LaneMask);
1086  } else {
1087  dbgs() << printRegUnit(Reg, &TRI);
1088  }
1089  dbgs() << ":\t" << LR << '\n';
1090  });
1091  if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
1092  handleMoveDown(LR);
1093  else
1094  handleMoveUp(LR, Reg, LaneMask);
1095  LLVM_DEBUG(dbgs() << " -->\t" << LR << '\n');
1096  LR.verify();
1097  }
1098 
1099  /// Update LR to reflect an instruction has been moved downwards from OldIdx
1100  /// to NewIdx (OldIdx < NewIdx).
1101  void handleMoveDown(LiveRange &LR) {
1102  LiveRange::iterator E = LR.end();
1103  // Segment going into OldIdx.
1104  LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
1105 
1106  // No value live before or after OldIdx? Nothing to do.
1107  if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1108  return;
1109 
1110  LiveRange::iterator OldIdxOut;
1111  // Do we have a value live-in to OldIdx?
1112  if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1113  // If the live-in value already extends to NewIdx, there is nothing to do.
1114  if (SlotIndex::isEarlierEqualInstr(NewIdx, OldIdxIn->end))
1115  return;
1116  // Aggressively remove all kill flags from the old kill point.
1117  // Kill flags shouldn't be used while live intervals exist, they will be
1118  // reinserted by VirtRegRewriter.
1119  if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
1120  for (MachineOperand &MOP : mi_bundle_ops(*KillMI))
1121  if (MOP.isReg() && MOP.isUse())
1122  MOP.setIsKill(false);
1123 
1124  // Is there a def before NewIdx which is not OldIdx?
1125  LiveRange::iterator Next = std::next(OldIdxIn);
1126  if (Next != E && !SlotIndex::isSameInstr(OldIdx, Next->start) &&
1127  SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1128  // If we are here then OldIdx was just a use but not a def. We only have
1129  // to ensure liveness extends to NewIdx.
1130  LiveRange::iterator NewIdxIn =
1131  LR.advanceTo(Next, NewIdx.getBaseIndex());
1132  // Extend the segment before NewIdx if necessary.
1133  if (NewIdxIn == E ||
1134  !SlotIndex::isEarlierInstr(NewIdxIn->start, NewIdx)) {
1135  LiveRange::iterator Prev = std::prev(NewIdxIn);
1136  Prev->end = NewIdx.getRegSlot();
1137  }
1138  // Extend OldIdxIn.
1139  OldIdxIn->end = Next->start;
1140  return;
1141  }
1142 
1143  // Adjust OldIdxIn->end to reach NewIdx. This may temporarily make LR
1144  // invalid by overlapping ranges.
1145  bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1146  OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1147  // If this was not a kill, then there was no def and we're done.
1148  if (!isKill)
1149  return;
1150 
1151  // Did we have a Def at OldIdx?
1152  OldIdxOut = Next;
1153  if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1154  return;
1155  } else {
1156  OldIdxOut = OldIdxIn;
1157  }
1158 
1159  // If we are here then there is a Definition at OldIdx. OldIdxOut points
1160  // to the segment starting there.
1161  assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1162  "No def?");
1163  VNInfo *OldIdxVNI = OldIdxOut->valno;
1164  assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1165 
1166  // If the defined value extends beyond NewIdx, just move the beginning
1167  // of the segment to NewIdx.
1168  SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1169  if (SlotIndex::isEarlierInstr(NewIdxDef, OldIdxOut->end)) {
1170  OldIdxVNI->def = NewIdxDef;
1171  OldIdxOut->start = OldIdxVNI->def;
1172  return;
1173  }
1174 
1175  // If we are here then we have a Definition at OldIdx which ends before
1176  // NewIdx.
1177 
1178  // Is there an existing Def at NewIdx?
1179  LiveRange::iterator AfterNewIdx
1180  = LR.advanceTo(OldIdxOut, NewIdx.getRegSlot());
1181  bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1182  if (!OldIdxDefIsDead &&
1183  SlotIndex::isEarlierInstr(OldIdxOut->end, NewIdxDef)) {
1184  // OldIdx is not a dead def, and NewIdxDef is inside a new interval.
1185  VNInfo *DefVNI;
1186  if (OldIdxOut != LR.begin() &&
1187  !SlotIndex::isEarlierInstr(std::prev(OldIdxOut)->end,
1188  OldIdxOut->start)) {
1189  // There is no gap between OldIdxOut and its predecessor anymore,
1190  // merge them.
1191  LiveRange::iterator IPrev = std::prev(OldIdxOut);
1192  DefVNI = OldIdxVNI;
1193  IPrev->end = OldIdxOut->end;
1194  } else {
1195  // The value is live in to OldIdx
1196  LiveRange::iterator INext = std::next(OldIdxOut);
1197  assert(INext != E && "Must have following segment");
1198  // We merge OldIdxOut and its successor. As we're dealing with subreg
1199  // reordering, there is always a successor to OldIdxOut in the same BB
1200  // We don't need INext->valno anymore and will reuse for the new segment
1201  // we create later.
1202  DefVNI = OldIdxVNI;
1203  INext->start = OldIdxOut->end;
1204  INext->valno->def = INext->start;
1205  }
1206  // If NewIdx is behind the last segment, extend that and append a new one.
1207  if (AfterNewIdx == E) {
1208  // OldIdxOut is undef at this point, Slide (OldIdxOut;AfterNewIdx] up
1209  // one position.
1210  // |- ?/OldIdxOut -| |- X0 -| ... |- Xn -| end
1211  // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS -| end
1212  std::copy(std::next(OldIdxOut), E, OldIdxOut);
1213  // The last segment is undefined now, reuse it for a dead def.
1214  LiveRange::iterator NewSegment = std::prev(E);
1215  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1216  DefVNI);
1217  DefVNI->def = NewIdxDef;
1218 
1219  LiveRange::iterator Prev = std::prev(NewSegment);
1220  Prev->end = NewIdxDef;
1221  } else {
1222  // OldIdxOut is undef at this point, Slide (OldIdxOut;AfterNewIdx] up
1223  // one position.
1224  // |- ?/OldIdxOut -| |- X0 -| ... |- Xn/AfterNewIdx -| |- Next -|
1225  // => |- X0/OldIdxOut -| ... |- Xn -| |- Xn/AfterNewIdx -| |- Next -|
1226  std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);
1227  LiveRange::iterator Prev = std::prev(AfterNewIdx);
1228  // We have two cases:
1229  if (SlotIndex::isEarlierInstr(Prev->start, NewIdxDef)) {
1230  // Case 1: NewIdx is inside a liverange. Split this liverange at
1231  // NewIdxDef into the segment "Prev" followed by "NewSegment".
1232  LiveRange::iterator NewSegment = AfterNewIdx;
1233  *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);
1234  Prev->valno->def = NewIdxDef;
1235 
1236  *Prev = LiveRange::Segment(Prev->start, NewIdxDef, DefVNI);
1237  DefVNI->def = Prev->start;
1238  } else {
1239  // Case 2: NewIdx is in a lifetime hole. Keep AfterNewIdx as is and
1240  // turn Prev into a segment from NewIdx to AfterNewIdx->start.
1241  *Prev = LiveRange::Segment(NewIdxDef, AfterNewIdx->start, DefVNI);
1242  DefVNI->def = NewIdxDef;
1243  assert(DefVNI != AfterNewIdx->valno);
1244  }
1245  }
1246  return;
1247  }
1248 
1249  if (AfterNewIdx != E &&
1250  SlotIndex::isSameInstr(AfterNewIdx->start, NewIdxDef)) {
1251  // There is an existing def at NewIdx. The def at OldIdx is coalesced into
1252  // that value.
1253  assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");
1254  LR.removeValNo(OldIdxVNI);
1255  } else {
1256  // There was no existing def at NewIdx. We need to create a dead def
1257  // at NewIdx. Shift segments over the old OldIdxOut segment, this frees
1258  // a new segment at the place where we want to construct the dead def.
1259  // |- OldIdxOut -| |- X0 -| ... |- Xn -| |- AfterNewIdx -|
1260  // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS. -| |- AfterNewIdx -|
1261  assert(AfterNewIdx != OldIdxOut && "Inconsistent iterators");
1262  std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);
1263  // We can reuse OldIdxVNI now.
1264  LiveRange::iterator NewSegment = std::prev(AfterNewIdx);
1265  VNInfo *NewSegmentVNI = OldIdxVNI;
1266  NewSegmentVNI->def = NewIdxDef;
1267  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1268  NewSegmentVNI);
1269  }
1270  }
1271 
1272  /// Update LR to reflect an instruction has been moved upwards from OldIdx
1273  /// to NewIdx (NewIdx < OldIdx).
1274  void handleMoveUp(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
1275  LiveRange::iterator E = LR.end();
1276  // Segment going into OldIdx.
1277  LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
1278 
1279  // No value live before or after OldIdx? Nothing to do.
1280  if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1281  return;
1282 
1283  LiveRange::iterator OldIdxOut;
1284  // Do we have a value live-in to OldIdx?
1285  if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1286  // If the live-in value isn't killed here, then we have no Def at
1287  // OldIdx, moreover the value must be live at NewIdx so there is nothing
1288  // to do.
1289  bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1290  if (!isKill)
1291  return;
1292 
1293  // At this point we have to move OldIdxIn->end back to the nearest
1294  // previous use or (dead-)def but no further than NewIdx.
1295  SlotIndex DefBeforeOldIdx
1296  = std::max(OldIdxIn->start.getDeadSlot(),
1297  NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
1298  OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);
1299 
1300  // Did we have a Def at OldIdx? If not we are done now.
1301  OldIdxOut = std::next(OldIdxIn);
1302  if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1303  return;
1304  } else {
1305  OldIdxOut = OldIdxIn;
1306  OldIdxIn = OldIdxOut != LR.begin() ? std::prev(OldIdxOut) : E;
1307  }
1308 
1309  // If we are here then there is a Definition at OldIdx. OldIdxOut points
1310  // to the segment starting there.
1311  assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1312  "No def?");
1313  VNInfo *OldIdxVNI = OldIdxOut->valno;
1314  assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1315  bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1316 
1317  // Is there an existing def at NewIdx?
1318  SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1319  LiveRange::iterator NewIdxOut = LR.find(NewIdx.getRegSlot());
1320  if (SlotIndex::isSameInstr(NewIdxOut->start, NewIdx)) {
1321  assert(NewIdxOut->valno != OldIdxVNI &&
1322  "Same value defined more than once?");
1323  // If OldIdx was a dead def remove it.
1324  if (!OldIdxDefIsDead) {
1325  // Remove segment starting at NewIdx and move begin of OldIdxOut to
1326  // NewIdx so it can take its place.
1327  OldIdxVNI->def = NewIdxDef;
1328  OldIdxOut->start = NewIdxDef;
1329  LR.removeValNo(NewIdxOut->valno);
1330  } else {
1331  // Simply remove the dead def at OldIdx.
1332  LR.removeValNo(OldIdxVNI);
1333  }
1334  } else {
1335  // Previously nothing was live after NewIdx, so all we have to do now is
1336  // move the begin of OldIdxOut to NewIdx.
1337  if (!OldIdxDefIsDead) {
1338  // Do we have any intermediate Defs between OldIdx and NewIdx?
1339  if (OldIdxIn != E &&
1340  SlotIndex::isEarlierInstr(NewIdxDef, OldIdxIn->start)) {
1341  // OldIdx is not a dead def and NewIdx is before predecessor start.
1342  LiveRange::iterator NewIdxIn = NewIdxOut;
1343  assert(NewIdxIn == LR.find(NewIdx.getBaseIndex()));
1344  const SlotIndex SplitPos = NewIdxDef;
1345  OldIdxVNI = OldIdxIn->valno;
1346 
1347  SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;
1348  LiveRange::iterator Prev = std::prev(OldIdxIn);
1349  if (OldIdxIn != LR.begin() &&
1350  SlotIndex::isEarlierInstr(NewIdx, Prev->end)) {
1351  // If the segment before OldIdx read a value defined earlier than
1352  // NewIdx, the moved instruction also reads and forwards that
1353  // value. Extend the lifetime of the new def point.
1354 
1355  // Extend to where the previous range started, unless there is
1356  // another redef first.
1357  NewDefEndPoint = std::min(OldIdxIn->start,
1358  std::next(NewIdxOut)->start);
1359  }
1360 
1361  // Merge the OldIdxIn and OldIdxOut segments into OldIdxOut.
1362  OldIdxOut->valno->def = OldIdxIn->start;
1363  *OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
1364  OldIdxOut->valno);
1365  // OldIdxIn and OldIdxVNI are now undef and can be overridden.
1366  // We Slide [NewIdxIn, OldIdxIn) down one position.
1367  // |- X0/NewIdxIn -| ... |- Xn-1 -||- Xn/OldIdxIn -||- OldIdxOut -|
1368  // => |- undef/NexIdxIn -| |- X0 -| ... |- Xn-1 -| |- Xn/OldIdxOut -|
1369  std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);
1370  // NewIdxIn is now considered undef so we can reuse it for the moved
1371  // value.
1372  LiveRange::iterator NewSegment = NewIdxIn;
1373  LiveRange::iterator Next = std::next(NewSegment);
1374  if (SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1375  // There is no gap between NewSegment and its predecessor.
1376  *NewSegment = LiveRange::Segment(Next->start, SplitPos,
1377  Next->valno);
1378 
1379  *Next = LiveRange::Segment(SplitPos, NewDefEndPoint, OldIdxVNI);
1380  Next->valno->def = SplitPos;
1381  } else {
1382  // There is a gap between NewSegment and its predecessor
1383  // Value becomes live in.
1384  *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);
1385  NewSegment->valno->def = SplitPos;
1386  }
1387  } else {
1388  // Leave the end point of a live def.
1389  OldIdxOut->start = NewIdxDef;
1390  OldIdxVNI->def = NewIdxDef;
1391  if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdx, OldIdxIn->end))
1392  OldIdxIn->end = NewIdxDef;
1393  }
1394  } else if (OldIdxIn != E
1395  && SlotIndex::isEarlierInstr(NewIdxOut->start, NewIdx)
1396  && SlotIndex::isEarlierInstr(NewIdx, NewIdxOut->end)) {
1397  // OldIdxVNI is a dead def that has been moved into the middle of
1398  // another value in LR. That can happen when LR is a whole register,
1399  // but the dead def is a write to a subreg that is dead at NewIdx.
1400  // The dead def may have been moved across other values
1401  // in LR, so move OldIdxOut up to NewIdxOut. Slide [NewIdxOut;OldIdxOut)
1402  // down one position.
1403  // |- X0/NewIdxOut -| ... |- Xn-1 -| |- Xn/OldIdxOut -| |- next - |
1404  // => |- X0/NewIdxOut -| |- X0 -| ... |- Xn-1 -| |- next -|
1405  std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));
1406  // Modify the segment at NewIdxOut and the following segment to meet at
1407  // the point of the dead def, with the following segment getting
1408  // OldIdxVNI as its value number.
1409  *NewIdxOut = LiveRange::Segment(
1410  NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);
1411  *(NewIdxOut + 1) = LiveRange::Segment(
1412  NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);
1413  OldIdxVNI->def = NewIdxDef;
1414  // Modify subsequent segments to be defined by the moved def OldIdxVNI.
1415  for (auto Idx = NewIdxOut + 2; Idx <= OldIdxOut; ++Idx)
1416  Idx->valno = OldIdxVNI;
1417  // Aggressively remove all dead flags from the former dead definition.
1418  // Kill/dead flags shouldn't be used while live intervals exist; they
1419  // will be reinserted by VirtRegRewriter.
1420  if (MachineInstr *KillMI = LIS.getInstructionFromIndex(NewIdx))
1421  for (MIBundleOperands MO(*KillMI); MO.isValid(); ++MO)
1422  if (MO->isReg() && !MO->isUse())
1423  MO->setIsDead(false);
1424  } else {
1425  // OldIdxVNI is a dead def. It may have been moved across other values
1426  // in LR, so move OldIdxOut up to NewIdxOut. Slide [NewIdxOut;OldIdxOut)
1427  // down one position.
1428  // |- X0/NewIdxOut -| ... |- Xn-1 -| |- Xn/OldIdxOut -| |- next - |
1429  // => |- undef/NewIdxOut -| |- X0 -| ... |- Xn-1 -| |- next -|
1430  std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));
1431  // OldIdxVNI can be reused now to build a new dead def segment.
1432  LiveRange::iterator NewSegment = NewIdxOut;
1433  VNInfo *NewSegmentVNI = OldIdxVNI;
1434  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1435  NewSegmentVNI);
1436  NewSegmentVNI->def = NewIdxDef;
1437  }
1438  }
1439  }
1440 
1441  void updateRegMaskSlots() {
1443  llvm::lower_bound(LIS.RegMaskSlots, OldIdx);
1444  assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1445  "No RegMask at OldIdx.");
1446  *RI = NewIdx.getRegSlot();
1447  assert((RI == LIS.RegMaskSlots.begin() ||
1448  SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1449  "Cannot move regmask instruction above another call");
1450  assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1451  SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1452  "Cannot move regmask instruction below another call");
1453  }
1454 
1455  // Return the last use of reg between NewIdx and OldIdx.
1456  SlotIndex findLastUseBefore(SlotIndex Before, Register Reg,
1457  LaneBitmask LaneMask) {
1459  SlotIndex LastUse = Before;
1460  for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1461  if (MO.isUndef())
1462  continue;
1463  unsigned SubReg = MO.getSubReg();
1464  if (SubReg != 0 && LaneMask.any()
1465  && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
1466  continue;
1467 
1468  const MachineInstr &MI = *MO.getParent();
1469  SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1470  if (InstSlot > LastUse && InstSlot < OldIdx)
1471  LastUse = InstSlot.getRegSlot();
1472  }
1473  return LastUse;
1474  }
1475 
1476  // This is a regunit interval, so scanning the use list could be very
1477  // expensive. Scan upwards from OldIdx instead.
1478  assert(Before < OldIdx && "Expected upwards move");
1479  SlotIndexes *Indexes = LIS.getSlotIndexes();
1480  MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Before);
1481 
1482  // OldIdx may not correspond to an instruction any longer, so set MII to
1483  // point to the next instruction after OldIdx, or MBB->end().
1485  if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1486  Indexes->getNextNonNullIndex(OldIdx)))
1487  if (MI->getParent() == MBB)
1488  MII = MI;
1489 
1491  while (MII != Begin) {
1492  if ((--MII)->isDebugOrPseudoInstr())
1493  continue;
1494  SlotIndex Idx = Indexes->getInstructionIndex(*MII);
1495 
1496  // Stop searching when Before is reached.
1497  if (!SlotIndex::isEarlierInstr(Before, Idx))
1498  return Before;
1499 
1500  // Check if MII uses Reg.
1501  for (MIBundleOperands MO(*MII); MO.isValid(); ++MO)
1502  if (MO->isReg() && !MO->isUndef() &&
1503  Register::isPhysicalRegister(MO->getReg()) &&
1504  TRI.hasRegUnit(MO->getReg(), Reg))
1505  return Idx.getRegSlot();
1506  }
1507  // Didn't reach Before. It must be the first instruction in the block.
1508  return Before;
1509  }
1510 };
1511 
1512 void LiveIntervals::handleMove(MachineInstr &MI, bool UpdateFlags) {
1513  // It is fine to move a bundle as a whole, but not an individual instruction
1514  // inside it.
1515  assert((!MI.isBundled() || MI.getOpcode() == TargetOpcode::BUNDLE) &&
1516  "Cannot move instruction in bundle");
1517  SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1518  Indexes->removeMachineInstrFromMaps(MI);
1519  SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1520  assert(getMBBStartIdx(MI.getParent()) <= OldIndex &&
1521  OldIndex < getMBBEndIdx(MI.getParent()) &&
1522  "Cannot handle moves across basic block boundaries.");
1523 
1524  HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1525  HME.updateAllRanges(&MI);
1526 }
1527 
1529  bool UpdateFlags) {
1530  assert((BundleStart.getOpcode() == TargetOpcode::BUNDLE) &&
1531  "Bundle start is not a bundle");
1532  SmallVector<SlotIndex, 16> ToProcess;
1533  const SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(BundleStart);
1534  auto BundleEnd = getBundleEnd(BundleStart.getIterator());
1535 
1536  auto I = BundleStart.getIterator();
1537  I++;
1538  while (I != BundleEnd) {
1539  if (!Indexes->hasIndex(*I))
1540  continue;
1541  SlotIndex OldIndex = Indexes->getInstructionIndex(*I, true);
1542  ToProcess.push_back(OldIndex);
1543  Indexes->removeMachineInstrFromMaps(*I, true);
1544  I++;
1545  }
1546  for (SlotIndex OldIndex : ToProcess) {
1547  HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1548  HME.updateAllRanges(&BundleStart);
1549  }
1550 
1551  // Fix up dead defs
1552  const SlotIndex Index = getInstructionIndex(BundleStart);
1553  for (unsigned Idx = 0, E = BundleStart.getNumOperands(); Idx != E; ++Idx) {
1554  MachineOperand &MO = BundleStart.getOperand(Idx);
1555  if (!MO.isReg())
1556  continue;
1557  Register Reg = MO.getReg();
1558  if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) {
1559  LiveInterval &LI = getInterval(Reg);
1560  LiveQueryResult LRQ = LI.Query(Index);
1561  if (LRQ.isDeadDef())
1562  MO.setIsDead();
1563  }
1564  }
1565 }
1566 
1567 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1568  const MachineBasicBlock::iterator End,
1569  const SlotIndex EndIdx, LiveRange &LR,
1570  const Register Reg,
1571  LaneBitmask LaneMask) {
1572  LiveInterval::iterator LII = LR.find(EndIdx);
1573  SlotIndex lastUseIdx;
1574  if (LII != LR.end() && LII->start < EndIdx) {
1575  lastUseIdx = LII->end;
1576  } else if (LII == LR.begin()) {
1577  // We may not have a liverange at all if this is a subregister untouched
1578  // between \p Begin and \p End.
1579  } else {
1580  --LII;
1581  }
1582 
1583  for (MachineBasicBlock::iterator I = End; I != Begin;) {
1584  --I;
1585  MachineInstr &MI = *I;
1586  if (MI.isDebugOrPseudoInstr())
1587  continue;
1588 
1589  SlotIndex instrIdx = getInstructionIndex(MI);
1590  bool isStartValid = getInstructionFromIndex(LII->start);
1591  bool isEndValid = getInstructionFromIndex(LII->end);
1592 
1593  // FIXME: This doesn't currently handle early-clobber or multiple removed
1594  // defs inside of the region to repair.
1595  for (const MachineOperand &MO : MI.operands()) {
1596  if (!MO.isReg() || MO.getReg() != Reg)
1597  continue;
1598 
1599  unsigned SubReg = MO.getSubReg();
1601  if ((Mask & LaneMask).none())
1602  continue;
1603 
1604  if (MO.isDef()) {
1605  if (!isStartValid) {
1606  if (LII->end.isDead()) {
1607  LII = LR.removeSegment(LII, true);
1608  if (LII != LR.begin())
1609  --LII;
1610  } else {
1611  LII->start = instrIdx.getRegSlot();
1612  LII->valno->def = instrIdx.getRegSlot();
1613  if (MO.getSubReg() && !MO.isUndef())
1614  lastUseIdx = instrIdx.getRegSlot();
1615  else
1616  lastUseIdx = SlotIndex();
1617  continue;
1618  }
1619  }
1620 
1621  if (!lastUseIdx.isValid()) {
1622  VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1623  LiveRange::Segment S(instrIdx.getRegSlot(),
1624  instrIdx.getDeadSlot(), VNI);
1625  LII = LR.addSegment(S);
1626  } else if (LII->start != instrIdx.getRegSlot()) {
1627  VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1628  LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1629  LII = LR.addSegment(S);
1630  }
1631 
1632  if (MO.getSubReg() && !MO.isUndef())
1633  lastUseIdx = instrIdx.getRegSlot();
1634  else
1635  lastUseIdx = SlotIndex();
1636  } else if (MO.isUse()) {
1637  // FIXME: This should probably be handled outside of this branch,
1638  // either as part of the def case (for defs inside of the region) or
1639  // after the loop over the region.
1640  if (!isEndValid && !LII->end.isBlock())
1641  LII->end = instrIdx.getRegSlot();
1642  if (!lastUseIdx.isValid())
1643  lastUseIdx = instrIdx.getRegSlot();
1644  }
1645  }
1646  }
1647 
1648  bool isStartValid = getInstructionFromIndex(LII->start);
1649  if (!isStartValid && LII->end.isDead())
1650  LR.removeSegment(*LII, true);
1651 }
1652 
1653 void
1657  ArrayRef<Register> OrigRegs) {
1658  // Find anchor points, which are at the beginning/end of blocks or at
1659  // instructions that already have indexes.
1660  while (Begin != MBB->begin() && !Indexes->hasIndex(*Begin))
1661  --Begin;
1662  while (End != MBB->end() && !Indexes->hasIndex(*End))
1663  ++End;
1664 
1665  SlotIndex EndIdx;
1666  if (End == MBB->end())
1667  EndIdx = getMBBEndIdx(MBB).getPrevSlot();
1668  else
1669  EndIdx = getInstructionIndex(*End);
1670 
1671  Indexes->repairIndexesInRange(MBB, Begin, End);
1672 
1673  // Make sure a live interval exists for all register operands in the range.
1674  SmallVector<Register> RegsToRepair(OrigRegs.begin(), OrigRegs.end());
1675  for (MachineBasicBlock::iterator I = End; I != Begin;) {
1676  --I;
1677  MachineInstr &MI = *I;
1678  if (MI.isDebugOrPseudoInstr())
1679  continue;
1680  for (const MachineOperand &MO : MI.operands()) {
1681  if (MO.isReg() && MO.getReg().isVirtual()) {
1682  Register Reg = MO.getReg();
1683  // If the new instructions refer to subregs but the old instructions did
1684  // not, throw away any old live interval so it will be recomputed with
1685  // subranges.
1686  if (MO.getSubReg() && hasInterval(Reg) &&
1687  !getInterval(Reg).hasSubRanges() &&
1690  if (!hasInterval(Reg)) {
1692  // Don't bother to repair a freshly calculated live interval.
1693  erase_value(RegsToRepair, Reg);
1694  }
1695  }
1696  }
1697  }
1698 
1699  for (Register Reg : RegsToRepair) {
1700  if (!Reg.isVirtual())
1701  continue;
1702 
1703  LiveInterval &LI = getInterval(Reg);
1704  // FIXME: Should we support undefs that gain defs?
1705  if (!LI.hasAtLeastOneValue())
1706  continue;
1707 
1708  for (LiveInterval::SubRange &S : LI.subranges())
1709  repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask);
1710  LI.removeEmptySubRanges();
1711 
1712  repairOldRegInRange(Begin, End, EndIdx, LI, Reg);
1713  }
1714 }
1715 
1717  for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
1718  if (LiveRange *LR = getCachedRegUnit(*Unit))
1719  if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1720  LR->removeValNo(VNI);
1721  }
1722 }
1723 
1725  // LI may not have the main range computed yet, but its subranges may
1726  // be present.
1727  VNInfo *VNI = LI.getVNInfoAt(Pos);
1728  if (VNI != nullptr) {
1729  assert(VNI->def.getBaseIndex() == Pos.getBaseIndex());
1730  LI.removeValNo(VNI);
1731  }
1732 
1733  // Also remove the value defined in subranges.
1734  for (LiveInterval::SubRange &S : LI.subranges()) {
1735  if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1736  if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())
1737  S.removeValNo(SVNI);
1738  }
1739  LI.removeEmptySubRanges();
1740 }
1741 
1743  SmallVectorImpl<LiveInterval*> &SplitLIs) {
1744  ConnectedVNInfoEqClasses ConEQ(*this);
1745  unsigned NumComp = ConEQ.Classify(LI);
1746  if (NumComp <= 1)
1747  return;
1748  LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
1749  Register Reg = LI.reg();
1750  const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1751  for (unsigned I = 1; I < NumComp; ++I) {
1752  Register NewVReg = MRI->createVirtualRegister(RegClass);
1753  LiveInterval &NewLI = createEmptyInterval(NewVReg);
1754  SplitLIs.push_back(&NewLI);
1755  }
1756  ConEQ.Distribute(LI, SplitLIs.data(), *MRI);
1757 }
1758 
1760  assert(LICalc && "LICalc not initialized.");
1761  LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
1762  LICalc->constructMainRangeFromSubranges(LI);
1763 }
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iterator find(SlotIndex Pos)
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Definition: LaneBitmask.h:40
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Definition: README.txt:29
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Definition: LiveInterval.h:135
llvm::LiveIntervals::addSegmentToEndOfBlock
LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.
Definition: LiveIntervals.cpp:881
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Definition: LiveInterval.cpp:977
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Return the (start,end) range of the given basic block number.
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Definition: IRTranslator.cpp:105
MachineInstr.h
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bool subRegLivenessEnabled() const
Definition: MachineRegisterInfo.h:221
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M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
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iterator_range< T > make_range(T x, T y)
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Definition: iterator_range.h:53
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bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:214
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void flushSegmentSet()
Flush segment set into the regular segment vector.
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SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:211
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Definition: LiveIntervals.cpp:1005
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Definition: Allocator.h:125
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Definition: LiveInterval.cpp:1361
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::SlotIndex::isEarlierEqualInstr
static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)
Return true if A refers to the same instruction as B or an earlier one.
Definition: SlotIndexes.h:209
llvm::SlotIndex::isValid
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1691
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:327
llvm::ArrayRef::iterator
const_pointer iterator
Definition: ArrayRef.h:48
llvm::LiveQueryResult::valueOutOrDead
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
Definition: LiveInterval.h:129
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::LiveRange::advanceTo
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...
Definition: LiveInterval.h:263
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::LiveIntervals::getRegMaskSlotsInBlock
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...
Definition: LiveIntervals.h:355
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::LiveRangeCalc::extend
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
Definition: LiveRangeCalc.cpp:89
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::LiveQueryResult::isDeadDef
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
llvm::MachineBlockFrequencyInfo::getBlockFreqRelativeToEntryBlock
float getBlockFreqRelativeToEntryBlock(const MachineBasicBlock *MBB) const
Compute the frequency of the block, relative to the entry block.
Definition: MachineBlockFrequencyInfo.h:68
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::LiveIntervals::intervalIsInOneMBB
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
Definition: LiveIntervals.cpp:829
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::huge_valf
const float huge_valf
Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
Definition: MathExtras.cpp:28
llvm::LiveIntervals::addKillFlags
void addKillFlags(const VirtRegMap *)
Add kill flags to any instruction that kills a virtual register.
Definition: LiveIntervals.cpp:704
MachineBasicBlock.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::LiveIntervals::HMEditor::HMEditor
HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
Definition: LiveIntervals.cpp:995
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:761
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:145
BlockFrequency.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
llvm::LiveIntervals::getRegMaskSlots
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
Definition: LiveIntervals.h:351
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::LiveRange::Segment::start
SlotIndex start
Definition: LiveInterval.h:163
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::SlotIndexes::repairIndexesInRange
void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)
Repair indexes after adding and removing instructions.
Definition: SlotIndexes.cpp:179
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:476
llvm::LiveRange::vni_begin
vni_iterator vni_begin()
Definition: LiveInterval.h:224
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
llvm::mi_bundle_ops
iterator_range< MIBundleOperands > mi_bundle_ops(MachineInstr &MI)
Definition: MachineInstrBundle.h:210
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:239
llvm::LiveIntervals::createAndComputeVirtRegInterval
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
Definition: LiveIntervals.h:138
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:255
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
DepthFirstIterator.h
llvm::LiveIntervalCalc::constructMainRangeFromSubranges
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
Definition: LiveIntervalCalc.cpp:116
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
MachineRegisterInfo.h
llvm::LiveIntervals::handleMove
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
Definition: LiveIntervals.cpp:1512
llvm::LiveRange::beginIndex
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:377
llvm::LiveInterval::SubRange::LaneMask
LaneBitmask LaneMask
Definition: LiveInterval.h:690
AliasAnalysis.h
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:155
llvm::getBundleEnd
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
Definition: MachineInstrBundle.h:60
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::df_ext_begin
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:241
CommandLine.h
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
llvm::StatepointOpers::getNumDeoptArgsIdx
unsigned getNumDeoptArgsIdx() const
Get index of Number Deopt Arguments operand.
Definition: StackMaps.h:199
llvm::AnalysisUsage::addRequiredTransitiveID
AnalysisUsage & addRequiredTransitiveID(char &ID)
Definition: Pass.cpp:277
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:380
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::LiveIntervalCalc
Definition: LiveIntervalCalc.h:28
llvm::MachineBlockFrequencyInfo
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
Definition: MachineBlockFrequencyInfo.h:33
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:406
llvm::LiveRange::covers
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
Definition: LiveInterval.cpp:494
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LiveIntervals::ID
static char ID
Definition: LiveIntervals.h:99
llvm::LiveIntervals::hasPHIKill
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
Definition: LiveIntervals.cpp:853
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:928
llvm::SlotIndex::isEarlierInstr
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
Definition: SlotIndexes.h:203
InstrTypes.h
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:548
llvm::LiveRange::const_iterator
Segments::const_iterator const_iterator
Definition: LiveInterval.h:213
llvm::LiveIntervals::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &) override
Pass entry point; Calculates LiveIntervals.
Definition: LiveIntervals.cpp:126
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:435
llvm::LiveIntervalCalc::createDeadDefs
void createDeadDefs(LiveRange &LR, Register Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
Definition: LiveIntervalCalc.cpp:133
LiveVariables.h
false
Definition: StackSlotColoring.cpp:142
llvm::LiveIntervals::pruneValue
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.
Definition: LiveIntervals.cpp:642
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineRegisterInfo::reg_instructions
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:302
llvm::LiveRange::valnos
VNInfoList valnos
Definition: LiveInterval.h:204
llvm::LiveIntervals::checkRegMaskInterference
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
Definition: LiveIntervals.cpp:914
MachineInstrBundle.h
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:385
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
llvm::MIBundleOperands
MIBundleOperands - Iterate over all operands in a bundle of machine instructions.
Definition: MachineInstrBundle.h:166
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
SmallPtrSet.h
llvm::BitVector::clearBitsNotInMask
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
Definition: BitVector.h:705
llvm::BitVector
Definition: BitVector.h:74
llvm::LiveIntervals::LiveIntervals
LiveIntervals()
Definition: LiveIntervals.cpp:103
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
createSegmentsForValues
static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)
Definition: LiveIntervals.cpp:365
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::SlotIndexes::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:403
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::LiveQueryResult::endPoint
SlotIndex endPoint() const
Return the end point of the last live range segment to interact with the instruction,...
Definition: LiveInterval.h:147
Statepoint.h
llvm::erase_value
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
Definition: STLExtras.h:1770
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCRegUnitRootIterator::isValid
bool isValid() const
Check if the iterator is at the end of the list.
Definition: MCRegisterInfo.h:765
llvm::LiveIntervals::handleMoveIntoNewBundle
void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)
Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...
Definition: LiveIntervals.cpp:1528
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:535
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
Passes.h
LiveIntervalCalc.h
llvm::LiveIntervals::HMEditor
Toolkit used by handleMove to trim or extend live intervals.
Definition: LiveIntervals.cpp:984
llvm::LiveIntervals::removePhysRegDefAt
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
Definition: LiveIntervals.cpp:1716
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:44
llvm::cl::opt< bool >
llvm::SlotIndex::getBaseIndex
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:241
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::LiveRange::getVNInfoBefore
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:421
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::LiveInterval::removeEmptySubRanges
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
Definition: LiveInterval.cpp:854
llvm::LiveRange::hasAtLeastOneValue
bool hasAtLeastOneValue() const
Definition: LiveInterval.h:301
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
liveintervals
liveintervals
Definition: LiveIntervals.cpp:70
LiveIntervals.h
llvm::LiveIntervalCalc::calculate
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
Definition: LiveIntervalCalc.cpp:52
llvm::LiveIntervals::getRegMaskBitsInBlock
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).
Definition: LiveIntervals.h:366
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:241
VirtRegMap.h
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
llvm::Interval
Interval Class - An Interval is a set of nodes defined such that every node in the interval has all o...
Definition: Interval.h:36
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::LiveIntervals::releaseMemory
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Definition: LiveIntervals.cpp:109
MCRegisterInfo.h
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
llvm::LiveRange::getNextValue
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:323
ArrayRef.h
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
llvm::RISCVFPRndMode::RUP
@ RUP
Definition: RISCVBaseInfo.h:218
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ConnectedVNInfoEqClasses::Classify
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
Definition: LiveInterval.cpp:1319
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::pdb::PDB_TableType::Segments
@ Segments
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::SlotIndexes::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:514
iterator_range.h
llvm::LiveIntervals::shrinkToUses
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
Definition: LiveIntervals.cpp:456
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
LiveRange
SI Optimize VGPR LiveRange
Definition: SIOptimizeVGPRLiveRange.cpp:570
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::LiveRange::FindSegmentContaining
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none.
Definition: LiveInterval.h:428
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:69
llvm::LiveRange::createDeadDef
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
Definition: LiveInterval.cpp:370
llvm::MachineBasicBlock::getBeginClobberMask
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
Definition: MachineBasicBlock.cpp:1585
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:526
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::StatepointOpers::getFlags
uint64_t getFlags() const
Return the statepoint flags.
Definition: StackMaps.h:222
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", "Live Interval Analysis", false, false) INITIALIZE_PASS_END(LiveIntervals
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
uint32_t
Compiler.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::LiveIntervals::createEmptyInterval
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
Definition: LiveIntervals.h:131
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
hasLiveThroughUse
static bool hasLiveThroughUse(const MachineInstr *MI, Register Reg)
Check whether use of reg in MI is live-through.
Definition: LiveIntervals.cpp:899
llvm::LiveRange::Segment::end
SlotIndex end
Definition: LiveInterval.h:164
llvm::df_ext_end
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:246
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LiveRange::endIndex
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:384
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeCalc::isJointlyDominated
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
Definition: LiveRangeCalc.cpp:434
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::LiveRange::iterator
Segments::iterator iterator
Definition: LiveInterval.h:212
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:491
llvm::SmallVectorImpl::swap
void swap(SmallVectorImpl &RHS)
Definition: SmallVector.h:936
llvm::LiveIntervals::getSpillWeight
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
Definition: LiveIntervals.cpp:868
llvm::initializeLiveIntervalsPass
void initializeLiveIntervalsPass(PassRegistry &)
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::LiveIntervals::extendToIndices
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
Definition: LiveIntervals.cpp:633
llvm::SlotIndex::getPrevSlot
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
llvm::LiveIntervals::~LiveIntervals
~LiveIntervals() override
Definition: LiveIntervals.cpp:107
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:496
llvm::MachineFunction::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Definition: MachineFunction.cpp:546
llvm::MachineRegisterInfo::reg_empty
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
Definition: MachineRegisterInfo.h:323
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
StackMaps.h
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::LiveRange::verify
void verify() const
Walk the range and assert if any invariants fail to hold.
Definition: LiveInterval.cpp:1070
EnablePrecomputePhysRegs
Live Interval static false cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))
llvm::MachineBasicBlock::livein_empty
bool livein_empty() const
Definition: MachineBasicBlock.h:411
llvm::LiveIntervals::getRegMaskBits
ArrayRef< const uint32_t * > getRegMaskBits() const
Returns an array of register mask pointers corresponding to getRegMaskSlots().
Definition: LiveIntervals.h:362
llvm::LiveRange::removeSegment
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
Definition: LiveInterval.cpp:583
llvm::LiveIntervals::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: LiveIntervals.cpp:90
llvm::LiveIntervals::constructMainRangeFromSubranges
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
Definition: LiveIntervals.cpp:1759
llvm::SlotIndexes::getNextNonNullIndex
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
Definition: SlotIndexes.h:409
LiveInterval.h
llvm::MachineBasicBlock::getEndClobberMask
const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the end of the basic block.
Definition: MachineBasicBlock.cpp:1591
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:746
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::UseSegmentSetForPhysRegs
cl::opt< bool > UseSegmentSetForPhysRegs
llvm::LiveIntervals::HMEditor::updateAllRanges
void updateAllRanges(MachineInstr *MI)
Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.
Definition: LiveIntervals.cpp:1013
llvm::SmallVectorImpl::iterator
typename SuperClass::iterator iterator
Definition: SmallVector.h:562
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::LiveIntervals::splitSeparateComponents
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
Definition: LiveIntervals.cpp:1742
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:1336
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::LiveRange::segments
Segments segments
Definition: LiveInterval.h:203
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::LiveRange::getSegmentContaining
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:400
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::df_ext_iterator
Definition: DepthFirstIterator.h:235
LaneBitmask.h
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::LiveRange::clear
void clear()
Definition: LiveInterval.h:292
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::LiveRangeCalc::reset
void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
Definition: LiveRangeCalc.cpp:51
llvm::SmallVectorImpl< MachineInstr * >
MachineOperand.h
llvm::AnalysisUsage::addRequiredTransitive
AnalysisUsage & addRequiredTransitive()
Definition: PassAnalysisSupport.h:81
llvm::LiveIntervals::repairIntervalsInRange
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
Definition: LiveIntervals.cpp:1654
llvm::StatepointFlags::DeoptLiveIn
@ DeoptLiveIn
Mark the deopt arguments associated with the statepoint as only being "live-in".
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::LiveRange::removeValNo
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
Definition: LiveInterval.cpp:634
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:638
SlotIndexes.h
llvm::cl::desc
Definition: CommandLine.h:412
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
llvm::LiveRange::vni_end
vni_iterator vni_end()
Definition: LiveInterval.h:225
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::ConnectedVNInfoEqClasses
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:992
llvm::SlotIndexes::removeMachineInstrFromMaps
void removeMachineInstrFromMaps(MachineInstr &MI, bool AllowBundled=false)
Removes machine instruction (bundle) MI from the mapping.
Definition: SlotIndexes.cpp:115
llvm::LiveIntervalsID
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
Definition: LiveIntervals.cpp:64
llvm::LiveIntervals::removeVRegDefAt
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
Definition: LiveIntervals.cpp:1724
MachineBlockFrequencyInfo.h
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::LiveIntervals::getVNInfoAllocator
VNInfo::Allocator & getVNInfoAllocator()
Definition: LiveIntervals.h:284
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::VNInfo::markUnused
void markUnused()
Mark this value as unused.
Definition: LiveInterval.h:84
llvm::LiveIntervals::getRegUnit
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Definition: LiveIntervals.h:393
MachineDominators.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::StatepointOpers::getNumGCPtrIdx
unsigned getNumGCPtrIdx()
Get index of number of GC pointers.
Definition: StackMaps.cpp:114
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769