LLVM 19.0.0git
XtensaAsmBackend.cpp
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1//===-- XtensaMCAsmBackend.cpp - Xtensa assembler backend -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCInst.h"
22
23using namespace llvm;
24
25namespace llvm {
28 uint8_t OSABI;
29 bool IsLittleEndian;
30
31public:
32 XtensaMCAsmBackend(uint8_t osABI, bool isLE)
33 : MCAsmBackend(llvm::endianness::little), OSABI(osABI),
34 IsLittleEndian(isLE) {}
35
36 unsigned getNumFixupKinds() const override {
38 }
39 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
40 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
42 uint64_t Value, bool IsResolved,
43 const MCSubtargetInfo *STI) const override;
44 bool mayNeedRelaxation(const MCInst &Inst,
45 const MCSubtargetInfo &STI) const override;
47 const MCRelaxableFragment *Fragment,
48 const MCAsmLayout &Layout) const override;
49 void relaxInstruction(MCInst &Inst,
50 const MCSubtargetInfo &STI) const override;
52 const MCSubtargetInfo *STI) const override;
53
54 std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override {
55 return createXtensaObjectWriter(OSABI, IsLittleEndian);
56 }
57};
58} // namespace llvm
59
60const MCFixupKindInfo &
62 const static MCFixupKindInfo Infos[Xtensa::NumTargetFixupKinds] = {
63 // name offset bits flags
64 {"fixup_xtensa_branch_6", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_xtensa_branch_8", 16, 8, MCFixupKindInfo::FKF_IsPCRel},
66 {"fixup_xtensa_branch_12", 12, 12, MCFixupKindInfo::FKF_IsPCRel},
67 {"fixup_xtensa_jump_18", 6, 18, MCFixupKindInfo::FKF_IsPCRel},
68 {"fixup_xtensa_call_18", 6, 18,
71 {"fixup_xtensa_l32r_16", 8, 16,
74
75 if (Kind < FirstTargetFixupKind)
77 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
78 "Invalid kind!");
79 return Infos[Kind - FirstTargetFixupKind];
80}
81
83 MCContext &Ctx) {
84 unsigned Kind = Fixup.getKind();
85 switch (Kind) {
86 default:
87 llvm_unreachable("Unknown fixup kind!");
88 case FK_Data_1:
89 case FK_Data_2:
90 case FK_Data_4:
91 case FK_Data_8:
92 return Value;
94 Value -= 4;
95 if (!isInt<6>(Value))
96 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
97 unsigned Hi2 = (Value >> 4) & 0x3;
98 unsigned Lo4 = Value & 0xf;
99 return (Hi2 << 4) | (Lo4 << 12);
100 }
102 Value -= 4;
103 if (!isInt<8>(Value))
104 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
105 return (Value & 0xff);
107 Value -= 4;
108 if (!isInt<12>(Value))
109 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
110 return (Value & 0xfff);
112 Value -= 4;
113 if (!isInt<18>(Value))
114 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
115 return (Value & 0x3ffff);
117 Value -= 4;
118 if (!isInt<20>(Value))
119 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
120 if (Value & 0x3)
121 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
122 return (Value & 0xffffc) >> 2;
124 unsigned Offset = Fixup.getOffset();
125 if (Offset & 0x3)
126 Value -= 4;
127 if (!isInt<18>(Value) && (Value & 0x20000))
128 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
129 if (Value & 0x3)
130 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
131 return (Value & 0x3fffc) >> 2;
132 }
133}
134
135static unsigned getSize(unsigned Kind) {
136 switch (Kind) {
137 default:
138 return 3;
140 return 4;
142 return 2;
143 }
144}
145
147 const MCFixup &Fixup, const MCValue &Target,
149 bool IsResolved,
150 const MCSubtargetInfo *STI) const {
151 MCContext &Ctx = Asm.getContext();
153
155
156 // Shift the value into position.
157 Value <<= Info.TargetOffset;
158
159 if (!Value)
160 return; // Doesn't change encoding.
161
162 unsigned Offset = Fixup.getOffset();
163 unsigned FullSize = getSize(Fixup.getKind());
164
165 for (unsigned i = 0; i != FullSize; ++i) {
166 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
167 }
168}
169
171 const MCSubtargetInfo &STI) const {
172 return false;
173}
174
176 const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *Fragment,
177 const MCAsmLayout &Layout) const {
178 return false;
179}
180
182 const MCSubtargetInfo &STI) const {}
183
185 const MCSubtargetInfo *STI) const {
186 uint64_t NumNops24b = Count / 3;
187
188 for (uint64_t i = 0; i != NumNops24b; ++i) {
189 // Currently just little-endian machine supported,
190 // but probably big-endian will be also implemented in future
191 if (IsLittleEndian) {
192 OS.write("\xf0", 1);
193 OS.write("\x20", 1);
194 OS.write("\0x00", 1);
195 } else {
196 report_fatal_error("Big-endian mode currently is not supported!");
197 }
198 Count -= 3;
199 }
200
201 // TODO maybe function should return error if (Count > 0)
202 switch (Count) {
203 default:
204 break;
205 case 1:
206 OS.write("\0", 1);
207 break;
208 case 2:
209 // NOP.N instruction
210 OS.write("\x3d", 1);
211 OS.write("\xf0", 1);
212 break;
213 }
214
215 return true;
216}
217
219 const MCSubtargetInfo &STI,
220 const MCRegisterInfo &MRI,
221 const MCTargetOptions &Options) {
222 uint8_t OSABI =
224 return new llvm::XtensaMCAsmBackend(OSABI, true);
225}
unsigned const MachineRegisterInfo * MRI
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static LVOptions Options
Definition: LVOptions.cpp:25
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static unsigned getSize(unsigned Kind)
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Context object for machine code objects.
Definition: MCContext.h:82
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1093
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Base class for classes that define behaviour that is specific to both the target and the object forma...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:267
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
Target - Wrapper for Target specific information.
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
LLVM Value Representation.
Definition: Value.h:74
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
XtensaMCAsmBackend(uint8_t osABI, bool isLE)
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *Fragment, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write(unsigned char C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
std::unique_ptr< MCObjectTargetWriter > createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian)
endianness
Definition: bit.h:70
MCAsmBackend * createXtensaMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...