LLVM 19.0.0git
SIInstrInfo.cpp
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1//===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIInstrInfo.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "GCNHazardRecognizer.h"
18#include "GCNSubtarget.h"
31#include "llvm/IR/IntrinsicsAMDGPU.h"
32#include "llvm/MC/MCContext.h"
35
36using namespace llvm;
37
38#define DEBUG_TYPE "si-instr-info"
39
40#define GET_INSTRINFO_CTOR_DTOR
41#include "AMDGPUGenInstrInfo.inc"
42
43namespace llvm {
44namespace AMDGPU {
45#define GET_D16ImageDimIntrinsics_IMPL
46#define GET_ImageDimIntrinsicTable_IMPL
47#define GET_RsrcIntrinsics_IMPL
48#include "AMDGPUGenSearchableTables.inc"
49}
50}
51
52
53// Must be at least 4 to be able to branch over minimum unconditional branch
54// code. This is only for making it possible to write reasonably small tests for
55// long branches.
57BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
58 cl::desc("Restrict range of branch instructions (DEBUG)"));
59
61 "amdgpu-fix-16-bit-physreg-copies",
62 cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"),
63 cl::init(true),
65
67 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
68 RI(ST), ST(ST) {
69 SchedModel.init(&ST);
70}
71
72//===----------------------------------------------------------------------===//
73// TargetInstrInfo callbacks
74//===----------------------------------------------------------------------===//
75
76static unsigned getNumOperandsNoGlue(SDNode *Node) {
77 unsigned N = Node->getNumOperands();
78 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
79 --N;
80 return N;
81}
82
83/// Returns true if both nodes have the same value for the given
84/// operand \p Op, or if both nodes do not have this operand.
85static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
86 unsigned Opc0 = N0->getMachineOpcode();
87 unsigned Opc1 = N1->getMachineOpcode();
88
89 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
90 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
91
92 if (Op0Idx == -1 && Op1Idx == -1)
93 return true;
94
95
96 if ((Op0Idx == -1 && Op1Idx != -1) ||
97 (Op1Idx == -1 && Op0Idx != -1))
98 return false;
99
100 // getNamedOperandIdx returns the index for the MachineInstr's operands,
101 // which includes the result as the first operand. We are indexing into the
102 // MachineSDNode's operands, so we need to skip the result operand to get
103 // the real index.
104 --Op0Idx;
105 --Op1Idx;
106
107 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
108}
109
110static bool canRemat(const MachineInstr &MI) {
111
115 return true;
116
117 if (SIInstrInfo::isSMRD(MI)) {
118 return !MI.memoperands_empty() &&
119 llvm::all_of(MI.memoperands(), [](const MachineMemOperand *MMO) {
120 return MMO->isLoad() && MMO->isInvariant();
121 });
122 }
123
124 return false;
125}
126
128 const MachineInstr &MI) const {
129
130 if (canRemat(MI)) {
131 // Normally VALU use of exec would block the rematerialization, but that
132 // is OK in this case to have an implicit exec read as all VALU do.
133 // We really want all of the generic logic for this except for this.
134
135 // Another potential implicit use is mode register. The core logic of
136 // the RA will not attempt rematerialization if mode is set anywhere
137 // in the function, otherwise it is safe since mode is not changed.
138
139 // There is difference to generic method which does not allow
140 // rematerialization if there are virtual register uses. We allow this,
141 // therefore this method includes SOP instructions as well.
142 if (!MI.hasImplicitDef() &&
143 MI.getNumImplicitOperands() == MI.getDesc().implicit_uses().size() &&
144 !MI.mayRaiseFPException())
145 return true;
146 }
147
149}
150
151// Returns true if the scalar result of a VALU instruction depends on exec.
153 // Ignore comparisons which are only used masked with exec.
154 // This allows some hoisting/sinking of VALU comparisons.
155 if (MI.isCompare()) {
156 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
157 Register DstReg = MI.getOperand(0).getReg();
158 if (!DstReg.isVirtual())
159 return true;
160 for (MachineInstr &Use : MRI.use_nodbg_instructions(DstReg)) {
161 switch (Use.getOpcode()) {
162 case AMDGPU::S_AND_SAVEEXEC_B32:
163 case AMDGPU::S_AND_SAVEEXEC_B64:
164 break;
165 case AMDGPU::S_AND_B32:
166 case AMDGPU::S_AND_B64:
167 if (!Use.readsRegister(AMDGPU::EXEC, /*TRI=*/nullptr))
168 return true;
169 break;
170 default:
171 return true;
172 }
173 }
174 return false;
175 }
176
177 switch (MI.getOpcode()) {
178 default:
179 break;
180 case AMDGPU::V_READFIRSTLANE_B32:
181 return true;
182 }
183
184 return false;
185}
186
188 // Any implicit use of exec by VALU is not a real register read.
189 return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
191}
192
194 MachineBasicBlock *SuccToSinkTo,
195 MachineCycleInfo *CI) const {
196 // Allow sinking if MI edits lane mask (divergent i1 in sgpr).
197 if (MI.getOpcode() == AMDGPU::SI_IF_BREAK)
198 return true;
199
200 MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
201 // Check if sinking of MI would create temporal divergent use.
202 for (auto Op : MI.uses()) {
203 if (Op.isReg() && Op.getReg().isVirtual() &&
204 RI.isSGPRClass(MRI.getRegClass(Op.getReg()))) {
205 MachineInstr *SgprDef = MRI.getVRegDef(Op.getReg());
206
207 // SgprDef defined inside cycle
208 MachineCycle *FromCycle = CI->getCycle(SgprDef->getParent());
209 if (FromCycle == nullptr)
210 continue;
211
212 MachineCycle *ToCycle = CI->getCycle(SuccToSinkTo);
213 // Check if there is a FromCycle that contains SgprDef's basic block but
214 // does not contain SuccToSinkTo and also has divergent exit condition.
215 while (FromCycle && !FromCycle->contains(ToCycle)) {
217 FromCycle->getExitingBlocks(ExitingBlocks);
218
219 // FromCycle has divergent exit condition.
220 for (MachineBasicBlock *ExitingBlock : ExitingBlocks) {
221 if (hasDivergentBranch(ExitingBlock))
222 return false;
223 }
224
225 FromCycle = FromCycle->getParentCycle();
226 }
227 }
228 }
229
230 return true;
231}
232
234 int64_t &Offset0,
235 int64_t &Offset1) const {
236 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
237 return false;
238
239 unsigned Opc0 = Load0->getMachineOpcode();
240 unsigned Opc1 = Load1->getMachineOpcode();
241
242 // Make sure both are actually loads.
243 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
244 return false;
245
246 // A mayLoad instruction without a def is not a load. Likely a prefetch.
247 if (!get(Opc0).getNumDefs() || !get(Opc1).getNumDefs())
248 return false;
249
250 if (isDS(Opc0) && isDS(Opc1)) {
251
252 // FIXME: Handle this case:
253 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
254 return false;
255
256 // Check base reg.
257 if (Load0->getOperand(0) != Load1->getOperand(0))
258 return false;
259
260 // Skip read2 / write2 variants for simplicity.
261 // TODO: We should report true if the used offsets are adjacent (excluded
262 // st64 versions).
263 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
264 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
265 if (Offset0Idx == -1 || Offset1Idx == -1)
266 return false;
267
268 // XXX - be careful of dataless loads
269 // getNamedOperandIdx returns the index for MachineInstrs. Since they
270 // include the output in the operand list, but SDNodes don't, we need to
271 // subtract the index by one.
272 Offset0Idx -= get(Opc0).NumDefs;
273 Offset1Idx -= get(Opc1).NumDefs;
274 Offset0 = Load0->getConstantOperandVal(Offset0Idx);
275 Offset1 = Load1->getConstantOperandVal(Offset1Idx);
276 return true;
277 }
278
279 if (isSMRD(Opc0) && isSMRD(Opc1)) {
280 // Skip time and cache invalidation instructions.
281 if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) ||
282 !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase))
283 return false;
284
285 unsigned NumOps = getNumOperandsNoGlue(Load0);
286 if (NumOps != getNumOperandsNoGlue(Load1))
287 return false;
288
289 // Check base reg.
290 if (Load0->getOperand(0) != Load1->getOperand(0))
291 return false;
292
293 // Match register offsets, if both register and immediate offsets present.
294 assert(NumOps == 4 || NumOps == 5);
295 if (NumOps == 5 && Load0->getOperand(1) != Load1->getOperand(1))
296 return false;
297
298 const ConstantSDNode *Load0Offset =
299 dyn_cast<ConstantSDNode>(Load0->getOperand(NumOps - 3));
300 const ConstantSDNode *Load1Offset =
301 dyn_cast<ConstantSDNode>(Load1->getOperand(NumOps - 3));
302
303 if (!Load0Offset || !Load1Offset)
304 return false;
305
306 Offset0 = Load0Offset->getZExtValue();
307 Offset1 = Load1Offset->getZExtValue();
308 return true;
309 }
310
311 // MUBUF and MTBUF can access the same addresses.
312 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
313
314 // MUBUF and MTBUF have vaddr at different indices.
315 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
316 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
317 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
318 return false;
319
320 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
321 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
322
323 if (OffIdx0 == -1 || OffIdx1 == -1)
324 return false;
325
326 // getNamedOperandIdx returns the index for MachineInstrs. Since they
327 // include the output in the operand list, but SDNodes don't, we need to
328 // subtract the index by one.
329 OffIdx0 -= get(Opc0).NumDefs;
330 OffIdx1 -= get(Opc1).NumDefs;
331
332 SDValue Off0 = Load0->getOperand(OffIdx0);
333 SDValue Off1 = Load1->getOperand(OffIdx1);
334
335 // The offset might be a FrameIndexSDNode.
336 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
337 return false;
338
339 Offset0 = Off0->getAsZExtVal();
340 Offset1 = Off1->getAsZExtVal();
341 return true;
342 }
343
344 return false;
345}
346
347static bool isStride64(unsigned Opc) {
348 switch (Opc) {
349 case AMDGPU::DS_READ2ST64_B32:
350 case AMDGPU::DS_READ2ST64_B64:
351 case AMDGPU::DS_WRITE2ST64_B32:
352 case AMDGPU::DS_WRITE2ST64_B64:
353 return true;
354 default:
355 return false;
356 }
357}
358
361 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
362 const TargetRegisterInfo *TRI) const {
363 if (!LdSt.mayLoadOrStore())
364 return false;
365
366 unsigned Opc = LdSt.getOpcode();
367 OffsetIsScalable = false;
368 const MachineOperand *BaseOp, *OffsetOp;
369 int DataOpIdx;
370
371 if (isDS(LdSt)) {
372 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
373 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
374 if (OffsetOp) {
375 // Normal, single offset LDS instruction.
376 if (!BaseOp) {
377 // DS_CONSUME/DS_APPEND use M0 for the base address.
378 // TODO: find the implicit use operand for M0 and use that as BaseOp?
379 return false;
380 }
381 BaseOps.push_back(BaseOp);
382 Offset = OffsetOp->getImm();
383 // Get appropriate operand, and compute width accordingly.
384 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
385 if (DataOpIdx == -1)
386 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
387 Width = getOpSize(LdSt, DataOpIdx);
388 } else {
389 // The 2 offset instructions use offset0 and offset1 instead. We can treat
390 // these as a load with a single offset if the 2 offsets are consecutive.
391 // We will use this for some partially aligned loads.
392 const MachineOperand *Offset0Op =
393 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
394 const MachineOperand *Offset1Op =
395 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
396
397 unsigned Offset0 = Offset0Op->getImm() & 0xff;
398 unsigned Offset1 = Offset1Op->getImm() & 0xff;
399 if (Offset0 + 1 != Offset1)
400 return false;
401
402 // Each of these offsets is in element sized units, so we need to convert
403 // to bytes of the individual reads.
404
405 unsigned EltSize;
406 if (LdSt.mayLoad())
407 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
408 else {
409 assert(LdSt.mayStore());
410 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
411 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
412 }
413
414 if (isStride64(Opc))
415 EltSize *= 64;
416
417 BaseOps.push_back(BaseOp);
418 Offset = EltSize * Offset0;
419 // Get appropriate operand(s), and compute width accordingly.
420 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
421 if (DataOpIdx == -1) {
422 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
423 Width = getOpSize(LdSt, DataOpIdx);
424 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
425 Width = Width.getValue() + getOpSize(LdSt, DataOpIdx);
426 } else {
427 Width = getOpSize(LdSt, DataOpIdx);
428 }
429 }
430 return true;
431 }
432
433 if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
434 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
435 if (!RSrc) // e.g. BUFFER_WBINVL1_VOL
436 return false;
437 BaseOps.push_back(RSrc);
438 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
439 if (BaseOp && !BaseOp->isFI())
440 BaseOps.push_back(BaseOp);
441 const MachineOperand *OffsetImm =
442 getNamedOperand(LdSt, AMDGPU::OpName::offset);
443 Offset = OffsetImm->getImm();
444 const MachineOperand *SOffset =
445 getNamedOperand(LdSt, AMDGPU::OpName::soffset);
446 if (SOffset) {
447 if (SOffset->isReg())
448 BaseOps.push_back(SOffset);
449 else
450 Offset += SOffset->getImm();
451 }
452 // Get appropriate operand, and compute width accordingly.
453 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
454 if (DataOpIdx == -1)
455 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
456 if (DataOpIdx == -1) // LDS DMA
457 return false;
458 Width = getOpSize(LdSt, DataOpIdx);
459 return true;
460 }
461
462 if (isImage(LdSt)) {
463 auto RsrcOpName =
464 isMIMG(LdSt) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc;
465 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RsrcOpName);
466 BaseOps.push_back(&LdSt.getOperand(SRsrcIdx));
467 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
468 if (VAddr0Idx >= 0) {
469 // GFX10 possible NSA encoding.
470 for (int I = VAddr0Idx; I < SRsrcIdx; ++I)
471 BaseOps.push_back(&LdSt.getOperand(I));
472 } else {
473 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr));
474 }
475 Offset = 0;
476 // Get appropriate operand, and compute width accordingly.
477 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
478 Width = getOpSize(LdSt, DataOpIdx);
479 return true;
480 }
481
482 if (isSMRD(LdSt)) {
483 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
484 if (!BaseOp) // e.g. S_MEMTIME
485 return false;
486 BaseOps.push_back(BaseOp);
487 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
488 Offset = OffsetOp ? OffsetOp->getImm() : 0;
489 // Get appropriate operand, and compute width accordingly.
490 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
491 if (DataOpIdx == -1)
492 return false;
493 Width = getOpSize(LdSt, DataOpIdx);
494 return true;
495 }
496
497 if (isFLAT(LdSt)) {
498 // Instructions have either vaddr or saddr or both or none.
499 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
500 if (BaseOp)
501 BaseOps.push_back(BaseOp);
502 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
503 if (BaseOp)
504 BaseOps.push_back(BaseOp);
505 Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
506 // Get appropriate operand, and compute width accordingly.
507 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
508 if (DataOpIdx == -1)
509 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
510 if (DataOpIdx == -1) // LDS DMA
511 return false;
512 Width = getOpSize(LdSt, DataOpIdx);
513 return true;
514 }
515
516 return false;
517}
518
519static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
521 const MachineInstr &MI2,
523 // Only examine the first "base" operand of each instruction, on the
524 // assumption that it represents the real base address of the memory access.
525 // Other operands are typically offsets or indices from this base address.
526 if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front()))
527 return true;
528
529 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
530 return false;
531
532 auto MO1 = *MI1.memoperands_begin();
533 auto MO2 = *MI2.memoperands_begin();
534 if (MO1->getAddrSpace() != MO2->getAddrSpace())
535 return false;
536
537 auto Base1 = MO1->getValue();
538 auto Base2 = MO2->getValue();
539 if (!Base1 || !Base2)
540 return false;
541 Base1 = getUnderlyingObject(Base1);
542 Base2 = getUnderlyingObject(Base2);
543
544 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
545 return false;
546
547 return Base1 == Base2;
548}
549
551 int64_t Offset1, bool OffsetIsScalable1,
553 int64_t Offset2, bool OffsetIsScalable2,
554 unsigned ClusterSize,
555 unsigned NumBytes) const {
556 // If the mem ops (to be clustered) do not have the same base ptr, then they
557 // should not be clustered
558 if (!BaseOps1.empty() && !BaseOps2.empty()) {
559 const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
560 const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
561 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
562 return false;
563 } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
564 // If only one base op is empty, they do not have the same base ptr
565 return false;
566 }
567
568 // In order to avoid register pressure, on an average, the number of DWORDS
569 // loaded together by all clustered mem ops should not exceed 8. This is an
570 // empirical value based on certain observations and performance related
571 // experiments.
572 // The good thing about this heuristic is - it avoids clustering of too many
573 // sub-word loads, and also avoids clustering of wide loads. Below is the
574 // brief summary of how the heuristic behaves for various `LoadSize`.
575 // (1) 1 <= LoadSize <= 4: cluster at max 8 mem ops
576 // (2) 5 <= LoadSize <= 8: cluster at max 4 mem ops
577 // (3) 9 <= LoadSize <= 12: cluster at max 2 mem ops
578 // (4) 13 <= LoadSize <= 16: cluster at max 2 mem ops
579 // (5) LoadSize >= 17: do not cluster
580 const unsigned LoadSize = NumBytes / ClusterSize;
581 const unsigned NumDWORDs = ((LoadSize + 3) / 4) * ClusterSize;
582 return NumDWORDs <= 8;
583}
584
585// FIXME: This behaves strangely. If, for example, you have 32 load + stores,
586// the first 16 loads will be interleaved with the stores, and the next 16 will
587// be clustered as expected. It should really split into 2 16 store batches.
588//
589// Loads are clustered until this returns false, rather than trying to schedule
590// groups of stores. This also means we have to deal with saying different
591// address space loads should be clustered, and ones which might cause bank
592// conflicts.
593//
594// This might be deprecated so it might not be worth that much effort to fix.
596 int64_t Offset0, int64_t Offset1,
597 unsigned NumLoads) const {
598 assert(Offset1 > Offset0 &&
599 "Second offset should be larger than first offset!");
600 // If we have less than 16 loads in a row, and the offsets are within 64
601 // bytes, then schedule together.
602
603 // A cacheline is 64 bytes (for global memory).
604 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
605}
606
609 const DebugLoc &DL, MCRegister DestReg,
610 MCRegister SrcReg, bool KillSrc,
611 const char *Msg = "illegal VGPR to SGPR copy") {
613 DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(), Msg, DL, DS_Error);
615 C.diagnose(IllegalCopy);
616
617 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
618 .addReg(SrcReg, getKillRegState(KillSrc));
619}
620
621/// Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. It is not
622/// possible to have a direct copy in these cases on GFX908, so an intermediate
623/// VGPR copy is required.
627 const DebugLoc &DL, MCRegister DestReg,
628 MCRegister SrcReg, bool KillSrc,
629 RegScavenger &RS, bool RegsOverlap,
630 Register ImpDefSuperReg = Register(),
631 Register ImpUseSuperReg = Register()) {
632 assert((TII.getSubtarget().hasMAIInsts() &&
633 !TII.getSubtarget().hasGFX90AInsts()) &&
634 "Expected GFX908 subtarget.");
635
636 assert((AMDGPU::SReg_32RegClass.contains(SrcReg) ||
637 AMDGPU::AGPR_32RegClass.contains(SrcReg)) &&
638 "Source register of the copy should be either an SGPR or an AGPR.");
639
640 assert(AMDGPU::AGPR_32RegClass.contains(DestReg) &&
641 "Destination register of the copy should be an AGPR.");
642
643 const SIRegisterInfo &RI = TII.getRegisterInfo();
644
645 // First try to find defining accvgpr_write to avoid temporary registers.
646 // In the case of copies of overlapping AGPRs, we conservatively do not
647 // reuse previous accvgpr_writes. Otherwise, we may incorrectly pick up
648 // an accvgpr_write used for this same copy due to implicit-defs
649 if (!RegsOverlap) {
650 for (auto Def = MI, E = MBB.begin(); Def != E; ) {
651 --Def;
652
653 if (!Def->modifiesRegister(SrcReg, &RI))
654 continue;
655
656 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
657 Def->getOperand(0).getReg() != SrcReg)
658 break;
659
660 MachineOperand &DefOp = Def->getOperand(1);
661 assert(DefOp.isReg() || DefOp.isImm());
662
663 if (DefOp.isReg()) {
664 bool SafeToPropagate = true;
665 // Check that register source operand is not clobbered before MI.
666 // Immediate operands are always safe to propagate.
667 for (auto I = Def; I != MI && SafeToPropagate; ++I)
668 if (I->modifiesRegister(DefOp.getReg(), &RI))
669 SafeToPropagate = false;
670
671 if (!SafeToPropagate)
672 break;
673
674 DefOp.setIsKill(false);
675 }
676
677 MachineInstrBuilder Builder =
678 BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
679 .add(DefOp);
680 if (ImpDefSuperReg)
681 Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
682
683 if (ImpUseSuperReg) {
684 Builder.addReg(ImpUseSuperReg,
686 }
687
688 return;
689 }
690 }
691
693 RS.backward(std::next(MI));
694
695 // Ideally we want to have three registers for a long reg_sequence copy
696 // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
697 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
698 *MBB.getParent());
699
700 // Registers in the sequence are allocated contiguously so we can just
701 // use register number to pick one of three round-robin temps.
702 unsigned RegNo = (DestReg - AMDGPU::AGPR0) % 3;
703 Register Tmp =
704 MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getVGPRForAGPRCopy();
706 "VGPR used for an intermediate copy should have been reserved.");
707
708 // Only loop through if there are any free registers left. We don't want to
709 // spill.
710 while (RegNo--) {
711 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI,
712 /* RestoreAfter */ false, 0,
713 /* AllowSpill */ false);
714 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
715 break;
716 Tmp = Tmp2;
717 RS.setRegUsed(Tmp);
718 }
719
720 // Insert copy to temporary VGPR.
721 unsigned TmpCopyOp = AMDGPU::V_MOV_B32_e32;
722 if (AMDGPU::AGPR_32RegClass.contains(SrcReg)) {
723 TmpCopyOp = AMDGPU::V_ACCVGPR_READ_B32_e64;
724 } else {
725 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
726 }
727
728 MachineInstrBuilder UseBuilder = BuildMI(MBB, MI, DL, TII.get(TmpCopyOp), Tmp)
729 .addReg(SrcReg, getKillRegState(KillSrc));
730 if (ImpUseSuperReg) {
731 UseBuilder.addReg(ImpUseSuperReg,
733 }
734
735 MachineInstrBuilder DefBuilder
736 = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
737 .addReg(Tmp, RegState::Kill);
738
739 if (ImpDefSuperReg)
740 DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
741}
742
745 MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
746 const TargetRegisterClass *RC, bool Forward) {
747 const SIRegisterInfo &RI = TII.getRegisterInfo();
748 ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4);
750 MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
751
752 for (unsigned Idx = 0; Idx < BaseIndices.size(); ++Idx) {
753 int16_t SubIdx = BaseIndices[Idx];
754 Register DestSubReg = RI.getSubReg(DestReg, SubIdx);
755 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
756 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
757 unsigned Opcode = AMDGPU::S_MOV_B32;
758
759 // Is SGPR aligned? If so try to combine with next.
760 bool AlignedDest = ((DestSubReg - AMDGPU::SGPR0) % 2) == 0;
761 bool AlignedSrc = ((SrcSubReg - AMDGPU::SGPR0) % 2) == 0;
762 if (AlignedDest && AlignedSrc && (Idx + 1 < BaseIndices.size())) {
763 // Can use SGPR64 copy
764 unsigned Channel = RI.getChannelFromSubReg(SubIdx);
765 SubIdx = RI.getSubRegFromChannel(Channel, 2);
766 DestSubReg = RI.getSubReg(DestReg, SubIdx);
767 SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
768 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
769 Opcode = AMDGPU::S_MOV_B64;
770 Idx++;
771 }
772
773 LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), DestSubReg)
774 .addReg(SrcSubReg)
775 .addReg(SrcReg, RegState::Implicit);
776
777 if (!FirstMI)
778 FirstMI = LastMI;
779
780 if (!Forward)
781 I--;
782 }
783
784 assert(FirstMI && LastMI);
785 if (!Forward)
786 std::swap(FirstMI, LastMI);
787
788 FirstMI->addOperand(
789 MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
790
791 if (KillSrc)
792 LastMI->addRegisterKilled(SrcReg, &RI);
793}
794
797 const DebugLoc &DL, MCRegister DestReg,
798 MCRegister SrcReg, bool KillSrc) const {
799 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
800 unsigned Size = RI.getRegSizeInBits(*RC);
801 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
802 unsigned SrcSize = RI.getRegSizeInBits(*SrcRC);
803
804 // The rest of copyPhysReg assumes Src and Dst size are the same size.
805 // TODO-GFX11_16BIT If all true 16 bit instruction patterns are completed can
806 // we remove Fix16BitCopies and this code block?
807 if (Fix16BitCopies) {
808 if (((Size == 16) != (SrcSize == 16))) {
809 // Non-VGPR Src and Dst will later be expanded back to 32 bits.
811 MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
812 MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
813 RegToFix = SubReg;
814
815 if (DestReg == SrcReg) {
816 // Identity copy. Insert empty bundle since ExpandPostRA expects an
817 // instruction here.
818 BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
819 return;
820 }
821 RC = RI.getPhysRegBaseClass(DestReg);
822 Size = RI.getRegSizeInBits(*RC);
823 SrcRC = RI.getPhysRegBaseClass(SrcReg);
824 SrcSize = RI.getRegSizeInBits(*SrcRC);
825 }
826 }
827
828 if (RC == &AMDGPU::VGPR_32RegClass) {
829 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
830 AMDGPU::SReg_32RegClass.contains(SrcReg) ||
831 AMDGPU::AGPR_32RegClass.contains(SrcReg));
832 unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
833 AMDGPU::V_ACCVGPR_READ_B32_e64 : AMDGPU::V_MOV_B32_e32;
834 BuildMI(MBB, MI, DL, get(Opc), DestReg)
835 .addReg(SrcReg, getKillRegState(KillSrc));
836 return;
837 }
838
839 if (RC == &AMDGPU::SReg_32_XM0RegClass ||
840 RC == &AMDGPU::SReg_32RegClass) {
841 if (SrcReg == AMDGPU::SCC) {
842 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
843 .addImm(1)
844 .addImm(0);
845 return;
846 }
847
848 if (DestReg == AMDGPU::VCC_LO) {
849 if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
850 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
851 .addReg(SrcReg, getKillRegState(KillSrc));
852 } else {
853 // FIXME: Hack until VReg_1 removed.
854 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
855 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
856 .addImm(0)
857 .addReg(SrcReg, getKillRegState(KillSrc));
858 }
859
860 return;
861 }
862
863 if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
864 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
865 return;
866 }
867
868 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
869 .addReg(SrcReg, getKillRegState(KillSrc));
870 return;
871 }
872
873 if (RC == &AMDGPU::SReg_64RegClass) {
874 if (SrcReg == AMDGPU::SCC) {
875 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg)
876 .addImm(1)
877 .addImm(0);
878 return;
879 }
880
881 if (DestReg == AMDGPU::VCC) {
882 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
883 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
884 .addReg(SrcReg, getKillRegState(KillSrc));
885 } else {
886 // FIXME: Hack until VReg_1 removed.
887 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
888 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
889 .addImm(0)
890 .addReg(SrcReg, getKillRegState(KillSrc));
891 }
892
893 return;
894 }
895
896 if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
897 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
898 return;
899 }
900
901 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
902 .addReg(SrcReg, getKillRegState(KillSrc));
903 return;
904 }
905
906 if (DestReg == AMDGPU::SCC) {
907 // Copying 64-bit or 32-bit sources to SCC barely makes sense,
908 // but SelectionDAG emits such copies for i1 sources.
909 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
910 // This copy can only be produced by patterns
911 // with explicit SCC, which are known to be enabled
912 // only for subtargets with S_CMP_LG_U64 present.
914 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U64))
915 .addReg(SrcReg, getKillRegState(KillSrc))
916 .addImm(0);
917 } else {
918 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
919 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
920 .addReg(SrcReg, getKillRegState(KillSrc))
921 .addImm(0);
922 }
923
924 return;
925 }
926
927 if (RC == &AMDGPU::AGPR_32RegClass) {
928 if (AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
929 (ST.hasGFX90AInsts() && AMDGPU::SReg_32RegClass.contains(SrcReg))) {
930 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
931 .addReg(SrcReg, getKillRegState(KillSrc));
932 return;
933 }
934
935 if (AMDGPU::AGPR_32RegClass.contains(SrcReg) && ST.hasGFX90AInsts()) {
936 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_MOV_B32), DestReg)
937 .addReg(SrcReg, getKillRegState(KillSrc));
938 return;
939 }
940
941 // FIXME: Pass should maintain scavenger to avoid scan through the block on
942 // every AGPR spill.
943 RegScavenger RS;
944 const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
945 indirectCopyToAGPR(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RS, Overlap);
946 return;
947 }
948
949 if (Size == 16) {
950 assert(AMDGPU::VGPR_16RegClass.contains(SrcReg) ||
951 AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
952 AMDGPU::AGPR_LO16RegClass.contains(SrcReg));
953
954 bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
955 bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
956 bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
957 bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
958 bool DstLow = !AMDGPU::isHi(DestReg, RI);
959 bool SrcLow = !AMDGPU::isHi(SrcReg, RI);
960 MCRegister NewDestReg = RI.get32BitRegister(DestReg);
961 MCRegister NewSrcReg = RI.get32BitRegister(SrcReg);
962
963 if (IsSGPRDst) {
964 if (!IsSGPRSrc) {
965 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
966 return;
967 }
968
969 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
970 .addReg(NewSrcReg, getKillRegState(KillSrc));
971 return;
972 }
973
974 if (IsAGPRDst || IsAGPRSrc) {
975 if (!DstLow || !SrcLow) {
976 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
977 "Cannot use hi16 subreg with an AGPR!");
978 }
979
980 copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
981 return;
982 }
983
984 if (ST.hasTrue16BitInsts()) {
985 if (IsSGPRSrc) {
986 assert(SrcLow);
987 SrcReg = NewSrcReg;
988 }
989 // Use the smaller instruction encoding if possible.
990 if (AMDGPU::VGPR_16_Lo128RegClass.contains(DestReg) &&
991 (IsSGPRSrc || AMDGPU::VGPR_16_Lo128RegClass.contains(SrcReg))) {
992 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B16_t16_e32), DestReg)
993 .addReg(SrcReg);
994 } else {
995 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B16_t16_e64), DestReg)
996 .addImm(0) // src0_modifiers
997 .addReg(SrcReg)
998 .addImm(0); // op_sel
999 }
1000 return;
1001 }
1002
1003 if (IsSGPRSrc && !ST.hasSDWAScalar()) {
1004 if (!DstLow || !SrcLow) {
1005 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
1006 "Cannot use hi16 subreg on VI!");
1007 }
1008
1009 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
1010 .addReg(NewSrcReg, getKillRegState(KillSrc));
1011 return;
1012 }
1013
1014 auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
1015 .addImm(0) // src0_modifiers
1016 .addReg(NewSrcReg)
1017 .addImm(0) // clamp
1024 // First implicit operand is $exec.
1025 MIB->tieOperands(0, MIB->getNumOperands() - 1);
1026 return;
1027 }
1028
1029 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
1030 if (ST.hasMovB64()) {
1031 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_e32), DestReg)
1032 .addReg(SrcReg, getKillRegState(KillSrc));
1033 return;
1034 }
1035 if (ST.hasPkMovB32()) {
1036 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestReg)
1038 .addReg(SrcReg)
1040 .addReg(SrcReg)
1041 .addImm(0) // op_sel_lo
1042 .addImm(0) // op_sel_hi
1043 .addImm(0) // neg_lo
1044 .addImm(0) // neg_hi
1045 .addImm(0) // clamp
1046 .addReg(SrcReg, getKillRegState(KillSrc) | RegState::Implicit);
1047 return;
1048 }
1049 }
1050
1051 const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
1052 if (RI.isSGPRClass(RC)) {
1053 if (!RI.isSGPRClass(SrcRC)) {
1054 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
1055 return;
1056 }
1057 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg);
1058 expandSGPRCopy(*this, MBB, MI, DL, DestReg, SrcReg, CanKillSuperReg, RC,
1059 Forward);
1060 return;
1061 }
1062
1063 unsigned EltSize = 4;
1064 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1065 if (RI.isAGPRClass(RC)) {
1066 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC))
1067 Opcode = AMDGPU::V_ACCVGPR_MOV_B32;
1068 else if (RI.hasVGPRs(SrcRC) ||
1069 (ST.hasGFX90AInsts() && RI.isSGPRClass(SrcRC)))
1070 Opcode = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
1071 else
1072 Opcode = AMDGPU::INSTRUCTION_LIST_END;
1073 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) {
1074 Opcode = AMDGPU::V_ACCVGPR_READ_B32_e64;
1075 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) &&
1076 (RI.isProperlyAlignedRC(*RC) &&
1077 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
1078 // TODO: In 96-bit case, could do a 64-bit mov and then a 32-bit mov.
1079 if (ST.hasMovB64()) {
1080 Opcode = AMDGPU::V_MOV_B64_e32;
1081 EltSize = 8;
1082 } else if (ST.hasPkMovB32()) {
1083 Opcode = AMDGPU::V_PK_MOV_B32;
1084 EltSize = 8;
1085 }
1086 }
1087
1088 // For the cases where we need an intermediate instruction/temporary register
1089 // (destination is an AGPR), we need a scavenger.
1090 //
1091 // FIXME: The pass should maintain this for us so we don't have to re-scan the
1092 // whole block for every handled copy.
1093 std::unique_ptr<RegScavenger> RS;
1094 if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
1095 RS.reset(new RegScavenger());
1096
1097 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
1098
1099 // If there is an overlap, we can't kill the super-register on the last
1100 // instruction, since it will also kill the components made live by this def.
1101 const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
1102 const bool CanKillSuperReg = KillSrc && !Overlap;
1103
1104 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1105 unsigned SubIdx;
1106 if (Forward)
1107 SubIdx = SubIndices[Idx];
1108 else
1109 SubIdx = SubIndices[SubIndices.size() - Idx - 1];
1110 Register DestSubReg = RI.getSubReg(DestReg, SubIdx);
1111 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
1112 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
1113
1114 bool IsFirstSubreg = Idx == 0;
1115 bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
1116
1117 if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
1118 Register ImpDefSuper = IsFirstSubreg ? Register(DestReg) : Register();
1119 Register ImpUseSuper = SrcReg;
1120 indirectCopyToAGPR(*this, MBB, MI, DL, DestSubReg, SrcSubReg, UseKill,
1121 *RS, Overlap, ImpDefSuper, ImpUseSuper);
1122 } else if (Opcode == AMDGPU::V_PK_MOV_B32) {
1124 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
1126 .addReg(SrcSubReg)
1128 .addReg(SrcSubReg)
1129 .addImm(0) // op_sel_lo
1130 .addImm(0) // op_sel_hi
1131 .addImm(0) // neg_lo
1132 .addImm(0) // neg_hi
1133 .addImm(0) // clamp
1134 .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
1135 if (IsFirstSubreg)
1137 } else {
1138 MachineInstrBuilder Builder =
1139 BuildMI(MBB, MI, DL, get(Opcode), DestSubReg).addReg(SrcSubReg);
1140 if (IsFirstSubreg)
1141 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
1142
1143 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
1144 }
1145 }
1146}
1147
1148int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
1149 int NewOpc;
1150
1151 // Try to map original to commuted opcode
1152 NewOpc = AMDGPU::getCommuteRev(Opcode);
1153 if (NewOpc != -1)
1154 // Check if the commuted (REV) opcode exists on the target.
1155 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1156
1157 // Try to map commuted to original opcode
1158 NewOpc = AMDGPU::getCommuteOrig(Opcode);
1159 if (NewOpc != -1)
1160 // Check if the original (non-REV) opcode exists on the target.
1161 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1162
1163 return Opcode;
1164}
1165
1168 const DebugLoc &DL, Register DestReg,
1169 int64_t Value) const {
1171 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1172 if (RegClass == &AMDGPU::SReg_32RegClass ||
1173 RegClass == &AMDGPU::SGPR_32RegClass ||
1174 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
1175 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
1176 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
1177 .addImm(Value);
1178 return;
1179 }
1180
1181 if (RegClass == &AMDGPU::SReg_64RegClass ||
1182 RegClass == &AMDGPU::SGPR_64RegClass ||
1183 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
1184 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
1185 .addImm(Value);
1186 return;
1187 }
1188
1189 if (RegClass == &AMDGPU::VGPR_32RegClass) {
1190 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
1191 .addImm(Value);
1192 return;
1193 }
1194 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {
1195 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
1196 .addImm(Value);
1197 return;
1198 }
1199
1200 unsigned EltSize = 4;
1201 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1202 if (RI.isSGPRClass(RegClass)) {
1203 if (RI.getRegSizeInBits(*RegClass) > 32) {
1204 Opcode = AMDGPU::S_MOV_B64;
1205 EltSize = 8;
1206 } else {
1207 Opcode = AMDGPU::S_MOV_B32;
1208 EltSize = 4;
1209 }
1210 }
1211
1212 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
1213 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1214 int64_t IdxValue = Idx == 0 ? Value : 0;
1215
1216 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
1217 get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx]));
1218 Builder.addImm(IdxValue);
1219 }
1220}
1221
1222const TargetRegisterClass *
1224 return &AMDGPU::VGPR_32RegClass;
1225}
1226
1229 const DebugLoc &DL, Register DstReg,
1231 Register TrueReg,
1232 Register FalseReg) const {
1234 const TargetRegisterClass *BoolXExecRC =
1235 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
1236 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
1237 "Not a VGPR32 reg");
1238
1239 if (Cond.size() == 1) {
1240 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1241 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1242 .add(Cond[0]);
1243 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1244 .addImm(0)
1245 .addReg(FalseReg)
1246 .addImm(0)
1247 .addReg(TrueReg)
1248 .addReg(SReg);
1249 } else if (Cond.size() == 2) {
1250 assert(Cond[0].isImm() && "Cond[0] is not an immediate");
1251 switch (Cond[0].getImm()) {
1252 case SIInstrInfo::SCC_TRUE: {
1253 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1254 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1255 : AMDGPU::S_CSELECT_B64), SReg)
1256 .addImm(1)
1257 .addImm(0);
1258 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1259 .addImm(0)
1260 .addReg(FalseReg)
1261 .addImm(0)
1262 .addReg(TrueReg)
1263 .addReg(SReg);
1264 break;
1265 }
1266 case SIInstrInfo::SCC_FALSE: {
1267 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1268 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1269 : AMDGPU::S_CSELECT_B64), SReg)
1270 .addImm(0)
1271 .addImm(1);
1272 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1273 .addImm(0)
1274 .addReg(FalseReg)
1275 .addImm(0)
1276 .addReg(TrueReg)
1277 .addReg(SReg);
1278 break;
1279 }
1280 case SIInstrInfo::VCCNZ: {
1281 MachineOperand RegOp = Cond[1];
1282 RegOp.setImplicit(false);
1283 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1284 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1285 .add(RegOp);
1286 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1287 .addImm(0)
1288 .addReg(FalseReg)
1289 .addImm(0)
1290 .addReg(TrueReg)
1291 .addReg(SReg);
1292 break;
1293 }
1294 case SIInstrInfo::VCCZ: {
1295 MachineOperand RegOp = Cond[1];
1296 RegOp.setImplicit(false);
1297 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1298 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1299 .add(RegOp);
1300 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1301 .addImm(0)
1302 .addReg(TrueReg)
1303 .addImm(0)
1304 .addReg(FalseReg)
1305 .addReg(SReg);
1306 break;
1307 }
1308 case SIInstrInfo::EXECNZ: {
1309 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1310 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
1311 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1312 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1313 .addImm(0);
1314 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1315 : AMDGPU::S_CSELECT_B64), SReg)
1316 .addImm(1)
1317 .addImm(0);
1318 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1319 .addImm(0)
1320 .addReg(FalseReg)
1321 .addImm(0)
1322 .addReg(TrueReg)
1323 .addReg(SReg);
1324 break;
1325 }
1326 case SIInstrInfo::EXECZ: {
1327 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1328 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
1329 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1330 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1331 .addImm(0);
1332 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1333 : AMDGPU::S_CSELECT_B64), SReg)
1334 .addImm(0)
1335 .addImm(1);
1336 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1337 .addImm(0)
1338 .addReg(FalseReg)
1339 .addImm(0)
1340 .addReg(TrueReg)
1341 .addReg(SReg);
1342 llvm_unreachable("Unhandled branch predicate EXECZ");
1343 break;
1344 }
1345 default:
1346 llvm_unreachable("invalid branch predicate");
1347 }
1348 } else {
1349 llvm_unreachable("Can only handle Cond size 1 or 2");
1350 }
1351}
1352
1355 const DebugLoc &DL,
1356 Register SrcReg, int Value) const {
1358 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1359 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
1360 .addImm(Value)
1361 .addReg(SrcReg);
1362
1363 return Reg;
1364}
1365
1368 const DebugLoc &DL,
1369 Register SrcReg, int Value) const {
1371 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1372 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1373 .addImm(Value)
1374 .addReg(SrcReg);
1375
1376 return Reg;
1377}
1378
1380
1381 if (RI.isAGPRClass(DstRC))
1382 return AMDGPU::COPY;
1383 if (RI.getRegSizeInBits(*DstRC) == 16) {
1384 // Assume hi bits are unneeded. Only _e64 true16 instructions are legal
1385 // before RA.
1386 return RI.isSGPRClass(DstRC) ? AMDGPU::COPY : AMDGPU::V_MOV_B16_t16_e64;
1387 } else if (RI.getRegSizeInBits(*DstRC) == 32) {
1388 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1389 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1390 return AMDGPU::S_MOV_B64;
1391 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
1392 return AMDGPU::V_MOV_B64_PSEUDO;
1393 }
1394 return AMDGPU::COPY;
1395}
1396
1397const MCInstrDesc &
1399 bool IsIndirectSrc) const {
1400 if (IsIndirectSrc) {
1401 if (VecSize <= 32) // 4 bytes
1402 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1);
1403 if (VecSize <= 64) // 8 bytes
1404 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2);
1405 if (VecSize <= 96) // 12 bytes
1406 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3);
1407 if (VecSize <= 128) // 16 bytes
1408 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4);
1409 if (VecSize <= 160) // 20 bytes
1410 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5);
1411 if (VecSize <= 256) // 32 bytes
1412 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8);
1413 if (VecSize <= 288) // 36 bytes
1414 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V9);
1415 if (VecSize <= 320) // 40 bytes
1416 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V10);
1417 if (VecSize <= 352) // 44 bytes
1418 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V11);
1419 if (VecSize <= 384) // 48 bytes
1420 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V12);
1421 if (VecSize <= 512) // 64 bytes
1422 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16);
1423 if (VecSize <= 1024) // 128 bytes
1424 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32);
1425
1426 llvm_unreachable("unsupported size for IndirectRegReadGPRIDX pseudos");
1427 }
1428
1429 if (VecSize <= 32) // 4 bytes
1430 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1);
1431 if (VecSize <= 64) // 8 bytes
1432 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2);
1433 if (VecSize <= 96) // 12 bytes
1434 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3);
1435 if (VecSize <= 128) // 16 bytes
1436 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4);
1437 if (VecSize <= 160) // 20 bytes
1438 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5);
1439 if (VecSize <= 256) // 32 bytes
1440 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8);
1441 if (VecSize <= 288) // 36 bytes
1442 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9);
1443 if (VecSize <= 320) // 40 bytes
1444 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10);
1445 if (VecSize <= 352) // 44 bytes
1446 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V11);
1447 if (VecSize <= 384) // 48 bytes
1448 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V12);
1449 if (VecSize <= 512) // 64 bytes
1450 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16);
1451 if (VecSize <= 1024) // 128 bytes
1452 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32);
1453
1454 llvm_unreachable("unsupported size for IndirectRegWriteGPRIDX pseudos");
1455}
1456
1457static unsigned getIndirectVGPRWriteMovRelPseudoOpc(unsigned VecSize) {
1458 if (VecSize <= 32) // 4 bytes
1459 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1460 if (VecSize <= 64) // 8 bytes
1461 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1462 if (VecSize <= 96) // 12 bytes
1463 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1464 if (VecSize <= 128) // 16 bytes
1465 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1466 if (VecSize <= 160) // 20 bytes
1467 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1468 if (VecSize <= 256) // 32 bytes
1469 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1470 if (VecSize <= 288) // 36 bytes
1471 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V9;
1472 if (VecSize <= 320) // 40 bytes
1473 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V10;
1474 if (VecSize <= 352) // 44 bytes
1475 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V11;
1476 if (VecSize <= 384) // 48 bytes
1477 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V12;
1478 if (VecSize <= 512) // 64 bytes
1479 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1480 if (VecSize <= 1024) // 128 bytes
1481 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1482
1483 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1484}
1485
1486static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
1487 if (VecSize <= 32) // 4 bytes
1488 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1489 if (VecSize <= 64) // 8 bytes
1490 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1491 if (VecSize <= 96) // 12 bytes
1492 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1493 if (VecSize <= 128) // 16 bytes
1494 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1495 if (VecSize <= 160) // 20 bytes
1496 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1497 if (VecSize <= 256) // 32 bytes
1498 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1499 if (VecSize <= 288) // 36 bytes
1500 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9;
1501 if (VecSize <= 320) // 40 bytes
1502 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10;
1503 if (VecSize <= 352) // 44 bytes
1504 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11;
1505 if (VecSize <= 384) // 48 bytes
1506 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12;
1507 if (VecSize <= 512) // 64 bytes
1508 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1509 if (VecSize <= 1024) // 128 bytes
1510 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1511
1512 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1513}
1514
1515static unsigned getIndirectSGPRWriteMovRelPseudo64(unsigned VecSize) {
1516 if (VecSize <= 64) // 8 bytes
1517 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1;
1518 if (VecSize <= 128) // 16 bytes
1519 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2;
1520 if (VecSize <= 256) // 32 bytes
1521 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4;
1522 if (VecSize <= 512) // 64 bytes
1523 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8;
1524 if (VecSize <= 1024) // 128 bytes
1525 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16;
1526
1527 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1528}
1529
1530const MCInstrDesc &
1531SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,
1532 bool IsSGPR) const {
1533 if (IsSGPR) {
1534 switch (EltSize) {
1535 case 32:
1536 return get(getIndirectSGPRWriteMovRelPseudo32(VecSize));
1537 case 64:
1538 return get(getIndirectSGPRWriteMovRelPseudo64(VecSize));
1539 default:
1540 llvm_unreachable("invalid reg indexing elt size");
1541 }
1542 }
1543
1544 assert(EltSize == 32 && "invalid reg indexing elt size");
1546}
1547
1548static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
1549 switch (Size) {
1550 case 4:
1551 return AMDGPU::SI_SPILL_S32_SAVE;
1552 case 8:
1553 return AMDGPU::SI_SPILL_S64_SAVE;
1554 case 12:
1555 return AMDGPU::SI_SPILL_S96_SAVE;
1556 case 16:
1557 return AMDGPU::SI_SPILL_S128_SAVE;
1558 case 20:
1559 return AMDGPU::SI_SPILL_S160_SAVE;
1560 case 24:
1561 return AMDGPU::SI_SPILL_S192_SAVE;
1562 case 28:
1563 return AMDGPU::SI_SPILL_S224_SAVE;
1564 case 32:
1565 return AMDGPU::SI_SPILL_S256_SAVE;
1566 case 36:
1567 return AMDGPU::SI_SPILL_S288_SAVE;
1568 case 40:
1569 return AMDGPU::SI_SPILL_S320_SAVE;
1570 case 44:
1571 return AMDGPU::SI_SPILL_S352_SAVE;
1572 case 48:
1573 return AMDGPU::SI_SPILL_S384_SAVE;
1574 case 64:
1575 return AMDGPU::SI_SPILL_S512_SAVE;
1576 case 128:
1577 return AMDGPU::SI_SPILL_S1024_SAVE;
1578 default:
1579 llvm_unreachable("unknown register size");
1580 }
1581}
1582
1583static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
1584 switch (Size) {
1585 case 4:
1586 return AMDGPU::SI_SPILL_V32_SAVE;
1587 case 8:
1588 return AMDGPU::SI_SPILL_V64_SAVE;
1589 case 12:
1590 return AMDGPU::SI_SPILL_V96_SAVE;
1591 case 16:
1592 return AMDGPU::SI_SPILL_V128_SAVE;
1593 case 20:
1594 return AMDGPU::SI_SPILL_V160_SAVE;
1595 case 24:
1596 return AMDGPU::SI_SPILL_V192_SAVE;
1597 case 28:
1598 return AMDGPU::SI_SPILL_V224_SAVE;
1599 case 32:
1600 return AMDGPU::SI_SPILL_V256_SAVE;
1601 case 36:
1602 return AMDGPU::SI_SPILL_V288_SAVE;
1603 case 40:
1604 return AMDGPU::SI_SPILL_V320_SAVE;
1605 case 44:
1606 return AMDGPU::SI_SPILL_V352_SAVE;
1607 case 48:
1608 return AMDGPU::SI_SPILL_V384_SAVE;
1609 case 64:
1610 return AMDGPU::SI_SPILL_V512_SAVE;
1611 case 128:
1612 return AMDGPU::SI_SPILL_V1024_SAVE;
1613 default:
1614 llvm_unreachable("unknown register size");
1615 }
1616}
1617
1618static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
1619 switch (Size) {
1620 case 4:
1621 return AMDGPU::SI_SPILL_A32_SAVE;
1622 case 8:
1623 return AMDGPU::SI_SPILL_A64_SAVE;
1624 case 12:
1625 return AMDGPU::SI_SPILL_A96_SAVE;
1626 case 16:
1627 return AMDGPU::SI_SPILL_A128_SAVE;
1628 case 20:
1629 return AMDGPU::SI_SPILL_A160_SAVE;
1630 case 24:
1631 return AMDGPU::SI_SPILL_A192_SAVE;
1632 case 28:
1633 return AMDGPU::SI_SPILL_A224_SAVE;
1634 case 32:
1635 return AMDGPU::SI_SPILL_A256_SAVE;
1636 case 36:
1637 return AMDGPU::SI_SPILL_A288_SAVE;
1638 case 40:
1639 return AMDGPU::SI_SPILL_A320_SAVE;
1640 case 44:
1641 return AMDGPU::SI_SPILL_A352_SAVE;
1642 case 48:
1643 return AMDGPU::SI_SPILL_A384_SAVE;
1644 case 64:
1645 return AMDGPU::SI_SPILL_A512_SAVE;
1646 case 128:
1647 return AMDGPU::SI_SPILL_A1024_SAVE;
1648 default:
1649 llvm_unreachable("unknown register size");
1650 }
1651}
1652
1653static unsigned getAVSpillSaveOpcode(unsigned Size) {
1654 switch (Size) {
1655 case 4:
1656 return AMDGPU::SI_SPILL_AV32_SAVE;
1657 case 8:
1658 return AMDGPU::SI_SPILL_AV64_SAVE;
1659 case 12:
1660 return AMDGPU::SI_SPILL_AV96_SAVE;
1661 case 16:
1662 return AMDGPU::SI_SPILL_AV128_SAVE;
1663 case 20:
1664 return AMDGPU::SI_SPILL_AV160_SAVE;
1665 case 24:
1666 return AMDGPU::SI_SPILL_AV192_SAVE;
1667 case 28:
1668 return AMDGPU::SI_SPILL_AV224_SAVE;
1669 case 32:
1670 return AMDGPU::SI_SPILL_AV256_SAVE;
1671 case 36:
1672 return AMDGPU::SI_SPILL_AV288_SAVE;
1673 case 40:
1674 return AMDGPU::SI_SPILL_AV320_SAVE;
1675 case 44:
1676 return AMDGPU::SI_SPILL_AV352_SAVE;
1677 case 48:
1678 return AMDGPU::SI_SPILL_AV384_SAVE;
1679 case 64:
1680 return AMDGPU::SI_SPILL_AV512_SAVE;
1681 case 128:
1682 return AMDGPU::SI_SPILL_AV1024_SAVE;
1683 default:
1684 llvm_unreachable("unknown register size");
1685 }
1686}
1687
1688static unsigned getWWMRegSpillSaveOpcode(unsigned Size,
1689 bool IsVectorSuperClass) {
1690 // Currently, there is only 32-bit WWM register spills needed.
1691 if (Size != 4)
1692 llvm_unreachable("unknown wwm register spill size");
1693
1694 if (IsVectorSuperClass)
1695 return AMDGPU::SI_SPILL_WWM_AV32_SAVE;
1696
1697 return AMDGPU::SI_SPILL_WWM_V32_SAVE;
1698}
1699
1701 const TargetRegisterClass *RC,
1702 unsigned Size,
1703 const SIRegisterInfo &TRI,
1704 const SIMachineFunctionInfo &MFI) {
1705 bool IsVectorSuperClass = TRI.isVectorSuperClass(RC);
1706
1707 // Choose the right opcode if spilling a WWM register.
1709 return getWWMRegSpillSaveOpcode(Size, IsVectorSuperClass);
1710
1711 if (IsVectorSuperClass)
1712 return getAVSpillSaveOpcode(Size);
1713
1714 return TRI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(Size)
1716}
1717
1720 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1721 const TargetRegisterInfo *TRI, Register VReg) const {
1724 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1725 const DebugLoc &DL = MBB.findDebugLoc(MI);
1726
1727 MachinePointerInfo PtrInfo
1728 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1730 PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
1731 FrameInfo.getObjectAlign(FrameIndex));
1732 unsigned SpillSize = TRI->getSpillSize(*RC);
1733
1735 if (RI.isSGPRClass(RC)) {
1736 MFI->setHasSpilledSGPRs();
1737 assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled");
1738 assert(SrcReg != AMDGPU::EXEC_LO && SrcReg != AMDGPU::EXEC_HI &&
1739 SrcReg != AMDGPU::EXEC && "exec should not be spilled");
1740
1741 // We are only allowed to create one new instruction when spilling
1742 // registers, so we need to use pseudo instruction for spilling SGPRs.
1743 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1744
1745 // The SGPR spill/restore instructions only work on number sgprs, so we need
1746 // to make sure we are using the correct register class.
1747 if (SrcReg.isVirtual() && SpillSize == 4) {
1748 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1749 }
1750
1751 BuildMI(MBB, MI, DL, OpDesc)
1752 .addReg(SrcReg, getKillRegState(isKill)) // data
1753 .addFrameIndex(FrameIndex) // addr
1754 .addMemOperand(MMO)
1756
1757 if (RI.spillSGPRToVGPR())
1758 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1759 return;
1760 }
1761
1762 unsigned Opcode = getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC,
1763 SpillSize, RI, *MFI);
1764 MFI->setHasSpilledVGPRs();
1765
1766 BuildMI(MBB, MI, DL, get(Opcode))
1767 .addReg(SrcReg, getKillRegState(isKill)) // data
1768 .addFrameIndex(FrameIndex) // addr
1769 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1770 .addImm(0) // offset
1771 .addMemOperand(MMO);
1772}
1773
1774static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
1775 switch (Size) {
1776 case 4:
1777 return AMDGPU::SI_SPILL_S32_RESTORE;
1778 case 8:
1779 return AMDGPU::SI_SPILL_S64_RESTORE;
1780 case 12:
1781 return AMDGPU::SI_SPILL_S96_RESTORE;
1782 case 16:
1783 return AMDGPU::SI_SPILL_S128_RESTORE;
1784 case 20:
1785 return AMDGPU::SI_SPILL_S160_RESTORE;
1786 case 24:
1787 return AMDGPU::SI_SPILL_S192_RESTORE;
1788 case 28:
1789 return AMDGPU::SI_SPILL_S224_RESTORE;
1790 case 32:
1791 return AMDGPU::SI_SPILL_S256_RESTORE;
1792 case 36:
1793 return AMDGPU::SI_SPILL_S288_RESTORE;
1794 case 40:
1795 return AMDGPU::SI_SPILL_S320_RESTORE;
1796 case 44:
1797 return AMDGPU::SI_SPILL_S352_RESTORE;
1798 case 48:
1799 return AMDGPU::SI_SPILL_S384_RESTORE;
1800 case 64:
1801 return AMDGPU::SI_SPILL_S512_RESTORE;
1802 case 128:
1803 return AMDGPU::SI_SPILL_S1024_RESTORE;
1804 default:
1805 llvm_unreachable("unknown register size");
1806 }
1807}
1808
1809static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
1810 switch (Size) {
1811 case 4:
1812 return AMDGPU::SI_SPILL_V32_RESTORE;
1813 case 8:
1814 return AMDGPU::SI_SPILL_V64_RESTORE;
1815 case 12:
1816 return AMDGPU::SI_SPILL_V96_RESTORE;
1817 case 16:
1818 return AMDGPU::SI_SPILL_V128_RESTORE;
1819 case 20:
1820 return AMDGPU::SI_SPILL_V160_RESTORE;
1821 case 24:
1822 return AMDGPU::SI_SPILL_V192_RESTORE;
1823 case 28:
1824 return AMDGPU::SI_SPILL_V224_RESTORE;
1825 case 32:
1826 return AMDGPU::SI_SPILL_V256_RESTORE;
1827 case 36:
1828 return AMDGPU::SI_SPILL_V288_RESTORE;
1829 case 40:
1830 return AMDGPU::SI_SPILL_V320_RESTORE;
1831 case 44:
1832 return AMDGPU::SI_SPILL_V352_RESTORE;
1833 case 48:
1834 return AMDGPU::SI_SPILL_V384_RESTORE;
1835 case 64:
1836 return AMDGPU::SI_SPILL_V512_RESTORE;
1837 case 128:
1838 return AMDGPU::SI_SPILL_V1024_RESTORE;
1839 default:
1840 llvm_unreachable("unknown register size");
1841 }
1842}
1843
1844static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
1845 switch (Size) {
1846 case 4:
1847 return AMDGPU::SI_SPILL_A32_RESTORE;
1848 case 8:
1849 return AMDGPU::SI_SPILL_A64_RESTORE;
1850 case 12:
1851 return AMDGPU::SI_SPILL_A96_RESTORE;
1852 case 16:
1853 return AMDGPU::SI_SPILL_A128_RESTORE;
1854 case 20:
1855 return AMDGPU::SI_SPILL_A160_RESTORE;
1856 case 24:
1857 return AMDGPU::SI_SPILL_A192_RESTORE;
1858 case 28:
1859 return AMDGPU::SI_SPILL_A224_RESTORE;
1860 case 32:
1861 return AMDGPU::SI_SPILL_A256_RESTORE;
1862 case 36:
1863 return AMDGPU::SI_SPILL_A288_RESTORE;
1864 case 40:
1865 return AMDGPU::SI_SPILL_A320_RESTORE;
1866 case 44:
1867 return AMDGPU::SI_SPILL_A352_RESTORE;
1868 case 48:
1869 return AMDGPU::SI_SPILL_A384_RESTORE;
1870 case 64:
1871 return AMDGPU::SI_SPILL_A512_RESTORE;
1872 case 128:
1873 return AMDGPU::SI_SPILL_A1024_RESTORE;
1874 default:
1875 llvm_unreachable("unknown register size");
1876 }
1877}
1878
1879static unsigned getAVSpillRestoreOpcode(unsigned Size) {
1880 switch (Size) {
1881 case 4:
1882 return AMDGPU::SI_SPILL_AV32_RESTORE;
1883 case 8:
1884 return AMDGPU::SI_SPILL_AV64_RESTORE;
1885 case 12:
1886 return AMDGPU::SI_SPILL_AV96_RESTORE;
1887 case 16:
1888 return AMDGPU::SI_SPILL_AV128_RESTORE;
1889 case 20:
1890 return AMDGPU::SI_SPILL_AV160_RESTORE;
1891 case 24:
1892 return AMDGPU::SI_SPILL_AV192_RESTORE;
1893 case 28:
1894 return AMDGPU::SI_SPILL_AV224_RESTORE;
1895 case 32:
1896 return AMDGPU::SI_SPILL_AV256_RESTORE;
1897 case 36:
1898 return AMDGPU::SI_SPILL_AV288_RESTORE;
1899 case 40:
1900 return AMDGPU::SI_SPILL_AV320_RESTORE;
1901 case 44:
1902 return AMDGPU::SI_SPILL_AV352_RESTORE;
1903 case 48:
1904 return AMDGPU::SI_SPILL_AV384_RESTORE;
1905 case 64:
1906 return AMDGPU::SI_SPILL_AV512_RESTORE;
1907 case 128:
1908 return AMDGPU::SI_SPILL_AV1024_RESTORE;
1909 default:
1910 llvm_unreachable("unknown register size");
1911 }
1912}
1913
1914static unsigned getWWMRegSpillRestoreOpcode(unsigned Size,
1915 bool IsVectorSuperClass) {
1916 // Currently, there is only 32-bit WWM register spills needed.
1917 if (Size != 4)
1918 llvm_unreachable("unknown wwm register spill size");
1919
1920 if (IsVectorSuperClass)
1921 return AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
1922
1923 return AMDGPU::SI_SPILL_WWM_V32_RESTORE;
1924}
1925
1926static unsigned
1928 unsigned Size, const SIRegisterInfo &TRI,
1929 const SIMachineFunctionInfo &MFI) {
1930 bool IsVectorSuperClass = TRI.isVectorSuperClass(RC);
1931
1932 // Choose the right opcode if restoring a WWM register.
1934 return getWWMRegSpillRestoreOpcode(Size, IsVectorSuperClass);
1935
1936 if (IsVectorSuperClass)
1938
1939 return TRI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(Size)
1941}
1942
1945 Register DestReg, int FrameIndex,
1946 const TargetRegisterClass *RC,
1947 const TargetRegisterInfo *TRI,
1948 Register VReg) const {
1951 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1952 const DebugLoc &DL = MBB.findDebugLoc(MI);
1953 unsigned SpillSize = TRI->getSpillSize(*RC);
1954
1955 MachinePointerInfo PtrInfo
1956 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1957
1959 PtrInfo, MachineMemOperand::MOLoad, FrameInfo.getObjectSize(FrameIndex),
1960 FrameInfo.getObjectAlign(FrameIndex));
1961
1962 if (RI.isSGPRClass(RC)) {
1963 MFI->setHasSpilledSGPRs();
1964 assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into");
1965 assert(DestReg != AMDGPU::EXEC_LO && DestReg != AMDGPU::EXEC_HI &&
1966 DestReg != AMDGPU::EXEC && "exec should not be spilled");
1967
1968 // FIXME: Maybe this should not include a memoperand because it will be
1969 // lowered to non-memory instructions.
1970 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1971 if (DestReg.isVirtual() && SpillSize == 4) {
1973 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1974 }
1975
1976 if (RI.spillSGPRToVGPR())
1977 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1978 BuildMI(MBB, MI, DL, OpDesc, DestReg)
1979 .addFrameIndex(FrameIndex) // addr
1980 .addMemOperand(MMO)
1982
1983 return;
1984 }
1985
1986 unsigned Opcode = getVectorRegSpillRestoreOpcode(VReg ? VReg : DestReg, RC,
1987 SpillSize, RI, *MFI);
1988 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1989 .addFrameIndex(FrameIndex) // vaddr
1990 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1991 .addImm(0) // offset
1992 .addMemOperand(MMO);
1993}
1994
1997 insertNoops(MBB, MI, 1);
1998}
1999
2002 unsigned Quantity) const {
2004 while (Quantity > 0) {
2005 unsigned Arg = std::min(Quantity, 8u);
2006 Quantity -= Arg;
2007 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)).addImm(Arg - 1);
2008 }
2009}
2010
2012 auto MF = MBB.getParent();
2014
2015 assert(Info->isEntryFunction());
2016
2017 if (MBB.succ_empty()) {
2018 bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
2019 if (HasNoTerminator) {
2020 if (Info->returnsVoid()) {
2021 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
2022 } else {
2023 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
2024 }
2025 }
2026 }
2027}
2028
2032 const DebugLoc &DL) const {
2034 constexpr unsigned DoorbellIDMask = 0x3ff;
2035 constexpr unsigned ECQueueWaveAbort = 0x400;
2036
2037 MachineBasicBlock *TrapBB = &MBB;
2038 MachineBasicBlock *ContBB = &MBB;
2039 MachineBasicBlock *HaltLoopBB = MF->CreateMachineBasicBlock();
2040
2041 if (!MBB.succ_empty() || std::next(MI.getIterator()) != MBB.end()) {
2042 ContBB = MBB.splitAt(MI, /*UpdateLiveIns=*/false);
2043 TrapBB = MF->CreateMachineBasicBlock();
2044 BuildMI(MBB, MI, DL, get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(TrapBB);
2045 MF->push_back(TrapBB);
2046 MBB.addSuccessor(TrapBB);
2047 }
2048
2049 // Start with a `s_trap 2`, if we're in PRIV=1 and we need the workaround this
2050 // will be a nop.
2051 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_TRAP))
2052 .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap));
2053 Register DoorbellReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2054 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_SENDMSG_RTN_B32),
2055 DoorbellReg)
2057 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_MOV_B32), AMDGPU::TTMP2)
2058 .addUse(AMDGPU::M0);
2059 Register DoorbellRegMasked =
2060 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2061 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_AND_B32), DoorbellRegMasked)
2062 .addUse(DoorbellReg)
2063 .addImm(DoorbellIDMask);
2064 Register SetWaveAbortBit =
2065 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2066 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_OR_B32), SetWaveAbortBit)
2067 .addUse(DoorbellRegMasked)
2068 .addImm(ECQueueWaveAbort);
2069 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0)
2070 .addUse(SetWaveAbortBit);
2071 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_SENDMSG))
2073 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0)
2074 .addUse(AMDGPU::TTMP2);
2075 BuildMI(*TrapBB, TrapBB->end(), DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoopBB);
2076 TrapBB->addSuccessor(HaltLoopBB);
2077
2078 BuildMI(*HaltLoopBB, HaltLoopBB->end(), DL, get(AMDGPU::S_SETHALT)).addImm(5);
2079 BuildMI(*HaltLoopBB, HaltLoopBB->end(), DL, get(AMDGPU::S_BRANCH))
2080 .addMBB(HaltLoopBB);
2081 MF->push_back(HaltLoopBB);
2082 HaltLoopBB->addSuccessor(HaltLoopBB);
2083
2084 return ContBB;
2085}
2086
2088 switch (MI.getOpcode()) {
2089 default:
2090 if (MI.isMetaInstruction())
2091 return 0;
2092 return 1; // FIXME: Do wait states equal cycles?
2093
2094 case AMDGPU::S_NOP:
2095 return MI.getOperand(0).getImm() + 1;
2096 // SI_RETURN_TO_EPILOG is a fallthrough to code outside of the function. The
2097 // hazard, even if one exist, won't really be visible. Should we handle it?
2098 }
2099}
2100
2102 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2103 MachineBasicBlock &MBB = *MI.getParent();
2105 switch (MI.getOpcode()) {
2106 default: return TargetInstrInfo::expandPostRAPseudo(MI);
2107 case AMDGPU::S_MOV_B64_term:
2108 // This is only a terminator to get the correct spill code placement during
2109 // register allocation.
2110 MI.setDesc(get(AMDGPU::S_MOV_B64));
2111 break;
2112
2113 case AMDGPU::S_MOV_B32_term:
2114 // This is only a terminator to get the correct spill code placement during
2115 // register allocation.
2116 MI.setDesc(get(AMDGPU::S_MOV_B32));
2117 break;
2118
2119 case AMDGPU::S_XOR_B64_term:
2120 // This is only a terminator to get the correct spill code placement during
2121 // register allocation.
2122 MI.setDesc(get(AMDGPU::S_XOR_B64));
2123 break;
2124
2125 case AMDGPU::S_XOR_B32_term:
2126 // This is only a terminator to get the correct spill code placement during
2127 // register allocation.
2128 MI.setDesc(get(AMDGPU::S_XOR_B32));
2129 break;
2130 case AMDGPU::S_OR_B64_term:
2131 // This is only a terminator to get the correct spill code placement during
2132 // register allocation.
2133 MI.setDesc(get(AMDGPU::S_OR_B64));
2134 break;
2135 case AMDGPU::S_OR_B32_term:
2136 // This is only a terminator to get the correct spill code placement during
2137 // register allocation.
2138 MI.setDesc(get(AMDGPU::S_OR_B32));
2139 break;
2140
2141 case AMDGPU::S_ANDN2_B64_term:
2142 // This is only a terminator to get the correct spill code placement during
2143 // register allocation.
2144 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
2145 break;
2146
2147 case AMDGPU::S_ANDN2_B32_term:
2148 // This is only a terminator to get the correct spill code placement during
2149 // register allocation.
2150 MI.setDesc(get(AMDGPU::S_ANDN2_B32));
2151 break;
2152
2153 case AMDGPU::S_AND_B64_term:
2154 // This is only a terminator to get the correct spill code placement during
2155 // register allocation.
2156 MI.setDesc(get(AMDGPU::S_AND_B64));
2157 break;
2158
2159 case AMDGPU::S_AND_B32_term:
2160 // This is only a terminator to get the correct spill code placement during
2161 // register allocation.
2162 MI.setDesc(get(AMDGPU::S_AND_B32));
2163 break;
2164
2165 case AMDGPU::S_AND_SAVEEXEC_B64_term:
2166 // This is only a terminator to get the correct spill code placement during
2167 // register allocation.
2168 MI.setDesc(get(AMDGPU::S_AND_SAVEEXEC_B64));
2169 break;
2170
2171 case AMDGPU::S_AND_SAVEEXEC_B32_term:
2172 // This is only a terminator to get the correct spill code placement during
2173 // register allocation.
2174 MI.setDesc(get(AMDGPU::S_AND_SAVEEXEC_B32));
2175 break;
2176
2177 case AMDGPU::SI_SPILL_S32_TO_VGPR:
2178 MI.setDesc(get(AMDGPU::V_WRITELANE_B32));
2179 break;
2180
2181 case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
2182 MI.setDesc(get(AMDGPU::V_READLANE_B32));
2183 break;
2184
2185 case AMDGPU::V_MOV_B64_PSEUDO: {
2186 Register Dst = MI.getOperand(0).getReg();
2187 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2188 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2189
2190 const MachineOperand &SrcOp = MI.getOperand(1);
2191 // FIXME: Will this work for 64-bit floating point immediates?
2192 assert(!SrcOp.isFPImm());
2193 if (ST.hasMovB64()) {
2194 MI.setDesc(get(AMDGPU::V_MOV_B64_e32));
2195 if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
2196 isUInt<32>(SrcOp.getImm()))
2197 break;
2198 }
2199 if (SrcOp.isImm()) {
2200 APInt Imm(64, SrcOp.getImm());
2201 APInt Lo(32, Imm.getLoBits(32).getZExtValue());
2202 APInt Hi(32, Imm.getHiBits(32).getZExtValue());
2203 if (ST.hasPkMovB32() && Lo == Hi && isInlineConstant(Lo)) {
2204 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
2206 .addImm(Lo.getSExtValue())
2208 .addImm(Lo.getSExtValue())
2209 .addImm(0) // op_sel_lo
2210 .addImm(0) // op_sel_hi
2211 .addImm(0) // neg_lo
2212 .addImm(0) // neg_hi
2213 .addImm(0); // clamp
2214 } else {
2215 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2216 .addImm(Lo.getSExtValue())
2218 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
2219 .addImm(Hi.getSExtValue())
2221 }
2222 } else {
2223 assert(SrcOp.isReg());
2224 if (ST.hasPkMovB32() &&
2225 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
2226 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
2227 .addImm(SISrcMods::OP_SEL_1) // src0_mod
2228 .addReg(SrcOp.getReg())
2230 .addReg(SrcOp.getReg())
2231 .addImm(0) // op_sel_lo
2232 .addImm(0) // op_sel_hi
2233 .addImm(0) // neg_lo
2234 .addImm(0) // neg_hi
2235 .addImm(0); // clamp
2236 } else {
2237 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2238 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
2240 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
2241 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
2243 }
2244 }
2245 MI.eraseFromParent();
2246 break;
2247 }
2248 case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
2250 break;
2251 }
2252 case AMDGPU::S_MOV_B64_IMM_PSEUDO: {
2253 const MachineOperand &SrcOp = MI.getOperand(1);
2254 assert(!SrcOp.isFPImm());
2255 APInt Imm(64, SrcOp.getImm());
2256 if (Imm.isIntN(32) || isInlineConstant(Imm)) {
2257 MI.setDesc(get(AMDGPU::S_MOV_B64));
2258 break;
2259 }
2260
2261 Register Dst = MI.getOperand(0).getReg();
2262 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2263 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2264
2265 APInt Lo(32, Imm.getLoBits(32).getZExtValue());
2266 APInt Hi(32, Imm.getHiBits(32).getZExtValue());
2267 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo)
2268 .addImm(Lo.getSExtValue())
2270 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi)
2271 .addImm(Hi.getSExtValue())
2273 MI.eraseFromParent();
2274 break;
2275 }
2276 case AMDGPU::V_SET_INACTIVE_B32: {
2277 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
2278 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2279 // FIXME: We may possibly optimize the COPY once we find ways to make LLVM
2280 // optimizations (mainly Register Coalescer) aware of WWM register liveness.
2281 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
2282 .add(MI.getOperand(1));
2283 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
2284 FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
2285 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
2286 .add(MI.getOperand(2));
2287 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
2288 .addReg(Exec);
2289 MI.eraseFromParent();
2290 break;
2291 }
2292 case AMDGPU::V_SET_INACTIVE_B64: {
2293 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
2294 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2295 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
2296 MI.getOperand(0).getReg())
2297 .add(MI.getOperand(1));
2298 expandPostRAPseudo(*Copy);
2299 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
2300 FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
2301 Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
2302 MI.getOperand(0).getReg())
2303 .add(MI.getOperand(2));
2304 expandPostRAPseudo(*Copy);
2305 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
2306 .addReg(Exec);
2307 MI.eraseFromParent();
2308 break;
2309 }
2310 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1:
2311 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2:
2312 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3:
2313 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4:
2314 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2315 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8:
2316 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V9:
2317 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V10:
2318 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V11:
2319 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V12:
2320 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16:
2321 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32:
2322 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1:
2323 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2:
2324 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
2325 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
2326 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2327 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
2328 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9:
2329 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10:
2330 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11:
2331 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12:
2332 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16:
2333 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32:
2334 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1:
2335 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2:
2336 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4:
2337 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8:
2338 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16: {
2339 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);
2340
2341 unsigned Opc;
2342 if (RI.hasVGPRs(EltRC)) {
2343 Opc = AMDGPU::V_MOVRELD_B32_e32;
2344 } else {
2345 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64
2346 : AMDGPU::S_MOVRELD_B32;
2347 }
2348
2349 const MCInstrDesc &OpDesc = get(Opc);
2350 Register VecReg = MI.getOperand(0).getReg();
2351 bool IsUndef = MI.getOperand(1).isUndef();
2352 unsigned SubReg = MI.getOperand(3).getImm();
2353 assert(VecReg == MI.getOperand(1).getReg());
2354
2356 BuildMI(MBB, MI, DL, OpDesc)
2357 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2358 .add(MI.getOperand(2))
2360 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2361
2362 const int ImpDefIdx =
2363 OpDesc.getNumOperands() + OpDesc.implicit_uses().size();
2364 const int ImpUseIdx = ImpDefIdx + 1;
2365 MIB->tieOperands(ImpDefIdx, ImpUseIdx);
2366 MI.eraseFromParent();
2367 break;
2368 }
2369 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1:
2370 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2:
2371 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3:
2372 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4:
2373 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5:
2374 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8:
2375 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9:
2376 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10:
2377 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V11:
2378 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V12:
2379 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16:
2380 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32: {
2382 Register VecReg = MI.getOperand(0).getReg();
2383 bool IsUndef = MI.getOperand(1).isUndef();
2384 Register Idx = MI.getOperand(3).getReg();
2385 Register SubReg = MI.getOperand(4).getImm();
2386
2387 MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
2388 .addReg(Idx)
2390 SetOn->getOperand(3).setIsUndef();
2391
2392 const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write);
2394 BuildMI(MBB, MI, DL, OpDesc)
2395 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2396 .add(MI.getOperand(2))
2398 .addReg(VecReg,
2399 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2400
2401 const int ImpDefIdx =
2402 OpDesc.getNumOperands() + OpDesc.implicit_uses().size();
2403 const int ImpUseIdx = ImpDefIdx + 1;
2404 MIB->tieOperands(ImpDefIdx, ImpUseIdx);
2405
2406 MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2407
2408 finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2409
2410 MI.eraseFromParent();
2411 break;
2412 }
2413 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1:
2414 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2:
2415 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3:
2416 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4:
2417 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5:
2418 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8:
2419 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V9:
2420 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V10:
2421 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V11:
2422 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V12:
2423 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16:
2424 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32: {
2426 Register Dst = MI.getOperand(0).getReg();
2427 Register VecReg = MI.getOperand(1).getReg();
2428 bool IsUndef = MI.getOperand(1).isUndef();
2429 Register Idx = MI.getOperand(2).getReg();
2430 Register SubReg = MI.getOperand(3).getImm();
2431
2432 MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
2433 .addReg(Idx)
2435 SetOn->getOperand(3).setIsUndef();
2436
2437 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read))
2438 .addDef(Dst)
2439 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2440 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2441
2442 MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2443
2444 finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2445
2446 MI.eraseFromParent();
2447 break;
2448 }
2449 case AMDGPU::SI_PC_ADD_REL_OFFSET: {
2450 MachineFunction &MF = *MBB.getParent();
2451 Register Reg = MI.getOperand(0).getReg();
2452 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
2453 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
2454 MachineOperand OpLo = MI.getOperand(1);
2455 MachineOperand OpHi = MI.getOperand(2);
2456
2457 // Create a bundle so these instructions won't be re-ordered by the
2458 // post-RA scheduler.
2459 MIBundleBuilder Bundler(MBB, MI);
2460 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
2461
2462 // What we want here is an offset from the value returned by s_getpc (which
2463 // is the address of the s_add_u32 instruction) to the global variable, but
2464 // since the encoding of $symbol starts 4 bytes after the start of the
2465 // s_add_u32 instruction, we end up with an offset that is 4 bytes too
2466 // small. This requires us to add 4 to the global variable offset in order
2467 // to compute the correct address. Similarly for the s_addc_u32 instruction,
2468 // the encoding of $symbol starts 12 bytes after the start of the s_add_u32
2469 // instruction.
2470
2471 int64_t Adjust = 0;
2472 if (ST.hasGetPCZeroExtension()) {
2473 // Fix up hardware that does not sign-extend the 48-bit PC value by
2474 // inserting: s_sext_i32_i16 reghi, reghi
2475 Bundler.append(
2476 BuildMI(MF, DL, get(AMDGPU::S_SEXT_I32_I16), RegHi).addReg(RegHi));
2477 Adjust += 4;
2478 }
2479
2480 if (OpLo.isGlobal())
2481 OpLo.setOffset(OpLo.getOffset() + Adjust + 4);
2482 Bundler.append(
2483 BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo));
2484
2485 if (OpHi.isGlobal())
2486 OpHi.setOffset(OpHi.getOffset() + Adjust + 12);
2487 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
2488 .addReg(RegHi)
2489 .add(OpHi));
2490
2491 finalizeBundle(MBB, Bundler.begin());
2492
2493 MI.eraseFromParent();
2494 break;
2495 }
2496 case AMDGPU::ENTER_STRICT_WWM: {
2497 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2498 // Whole Wave Mode is entered.
2499 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
2500 : AMDGPU::S_OR_SAVEEXEC_B64));
2501 break;
2502 }
2503 case AMDGPU::ENTER_STRICT_WQM: {
2504 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2505 // STRICT_WQM is entered.
2506 const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2507 const unsigned WQMOp = ST.isWave32() ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64;
2508 const unsigned MovOp = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
2509 BuildMI(MBB, MI, DL, get(MovOp), MI.getOperand(0).getReg()).addReg(Exec);
2510 BuildMI(MBB, MI, DL, get(WQMOp), Exec).addReg(Exec);
2511
2512 MI.eraseFromParent();
2513 break;
2514 }
2515 case AMDGPU::EXIT_STRICT_WWM:
2516 case AMDGPU::EXIT_STRICT_WQM: {
2517 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2518 // WWM/STICT_WQM is exited.
2519 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
2520 break;
2521 }
2522 case AMDGPU::SI_RETURN: {
2523 const MachineFunction *MF = MBB.getParent();
2524 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2525 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2526 // Hiding the return address use with SI_RETURN may lead to extra kills in
2527 // the function and missing live-ins. We are fine in practice because callee
2528 // saved register handling ensures the register value is restored before
2529 // RET, but we need the undef flag here to appease the MachineVerifier
2530 // liveness checks.
2532 BuildMI(MBB, MI, DL, get(AMDGPU::S_SETPC_B64_return))
2533 .addReg(TRI->getReturnAddressReg(*MF), RegState::Undef);
2534
2535 MIB.copyImplicitOps(MI);
2536 MI.eraseFromParent();
2537 break;
2538 }
2539
2540 case AMDGPU::S_MUL_U64_U32_PSEUDO:
2541 case AMDGPU::S_MUL_I64_I32_PSEUDO:
2542 MI.setDesc(get(AMDGPU::S_MUL_U64));
2543 break;
2544
2545 case AMDGPU::S_GETPC_B64_pseudo:
2546 MI.setDesc(get(AMDGPU::S_GETPC_B64));
2547 if (ST.hasGetPCZeroExtension()) {
2548 Register Dst = MI.getOperand(0).getReg();
2549 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2550 // Fix up hardware that does not sign-extend the 48-bit PC value by
2551 // inserting: s_sext_i32_i16 dsthi, dsthi
2552 BuildMI(MBB, std::next(MI.getIterator()), DL, get(AMDGPU::S_SEXT_I32_I16),
2553 DstHi)
2554 .addReg(DstHi);
2555 }
2556 break;
2557 }
2558 return true;
2559}
2560
2563 unsigned SubIdx, const MachineInstr &Orig,
2564 const TargetRegisterInfo &RI) const {
2565
2566 // Try shrinking the instruction to remat only the part needed for current
2567 // context.
2568 // TODO: Handle more cases.
2569 unsigned Opcode = Orig.getOpcode();
2570 switch (Opcode) {
2571 case AMDGPU::S_LOAD_DWORDX16_IMM:
2572 case AMDGPU::S_LOAD_DWORDX8_IMM: {
2573 if (SubIdx != 0)
2574 break;
2575
2576 if (I == MBB.end())
2577 break;
2578
2579 if (I->isBundled())
2580 break;
2581
2582 // Look for a single use of the register that is also a subreg.
2583 Register RegToFind = Orig.getOperand(0).getReg();
2584 MachineOperand *UseMO = nullptr;
2585 for (auto &CandMO : I->operands()) {
2586 if (!CandMO.isReg() || CandMO.getReg() != RegToFind || CandMO.isDef())
2587 continue;
2588 if (UseMO) {
2589 UseMO = nullptr;
2590 break;
2591 }
2592 UseMO = &CandMO;
2593 }
2594 if (!UseMO || UseMO->getSubReg() == AMDGPU::NoSubRegister)
2595 break;
2596
2597 unsigned Offset = RI.getSubRegIdxOffset(UseMO->getSubReg());
2598 unsigned SubregSize = RI.getSubRegIdxSize(UseMO->getSubReg());
2599
2602 assert(MRI.use_nodbg_empty(DestReg) && "DestReg should have no users yet.");
2603
2604 unsigned NewOpcode = -1;
2605 if (SubregSize == 256)
2606 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM;
2607 else if (SubregSize == 128)
2608 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM;
2609 else
2610 break;
2611
2612 const MCInstrDesc &TID = get(NewOpcode);
2613 const TargetRegisterClass *NewRC =
2614 RI.getAllocatableClass(getRegClass(TID, 0, &RI, *MF));
2615 MRI.setRegClass(DestReg, NewRC);
2616
2617 UseMO->setReg(DestReg);
2618 UseMO->setSubReg(AMDGPU::NoSubRegister);
2619
2620 // Use a smaller load with the desired size, possibly with updated offset.
2621 MachineInstr *MI = MF->CloneMachineInstr(&Orig);
2622 MI->setDesc(TID);
2623 MI->getOperand(0).setReg(DestReg);
2624 MI->getOperand(0).setSubReg(AMDGPU::NoSubRegister);
2625 if (Offset) {
2626 MachineOperand *OffsetMO = getNamedOperand(*MI, AMDGPU::OpName::offset);
2627 int64_t FinalOffset = OffsetMO->getImm() + Offset / 8;
2628 OffsetMO->setImm(FinalOffset);
2629 }
2631 for (const MachineMemOperand *MemOp : Orig.memoperands())
2632 NewMMOs.push_back(MF->getMachineMemOperand(MemOp, MemOp->getPointerInfo(),
2633 SubregSize / 8));
2634 MI->setMemRefs(*MF, NewMMOs);
2635
2636 MBB.insert(I, MI);
2637 return;
2638 }
2639
2640 default:
2641 break;
2642 }
2643
2644 TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI);
2645}
2646
2647std::pair<MachineInstr*, MachineInstr*>
2649 assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
2650
2651 if (ST.hasMovB64() &&
2653 getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl)->getImm())) {
2654 MI.setDesc(get(AMDGPU::V_MOV_B64_dpp));
2655 return std::pair(&MI, nullptr);
2656 }
2657
2658 MachineBasicBlock &MBB = *MI.getParent();
2662 Register Dst = MI.getOperand(0).getReg();
2663 unsigned Part = 0;
2664 MachineInstr *Split[2];
2665
2666 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
2667 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
2668 if (Dst.isPhysical()) {
2669 MovDPP.addDef(RI.getSubReg(Dst, Sub));
2670 } else {
2671 assert(MRI.isSSA());
2672 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2673 MovDPP.addDef(Tmp);
2674 }
2675
2676 for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
2677 const MachineOperand &SrcOp = MI.getOperand(I);
2678 assert(!SrcOp.isFPImm());
2679 if (SrcOp.isImm()) {
2680 APInt Imm(64, SrcOp.getImm());
2681 Imm.ashrInPlace(Part * 32);
2682 MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
2683 } else {
2684 assert(SrcOp.isReg());
2685 Register Src = SrcOp.getReg();
2686 if (Src.isPhysical())
2687 MovDPP.addReg(RI.getSubReg(Src, Sub));
2688 else
2689 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
2690 }
2691 }
2692
2693 for (const MachineOperand &MO : llvm::drop_begin(MI.explicit_operands(), 3))
2694 MovDPP.addImm(MO.getImm());
2695
2696 Split[Part] = MovDPP;
2697 ++Part;
2698 }
2699
2700 if (Dst.isVirtual())
2701 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
2702 .addReg(Split[0]->getOperand(0).getReg())
2703 .addImm(AMDGPU::sub0)
2704 .addReg(Split[1]->getOperand(0).getReg())
2705 .addImm(AMDGPU::sub1);
2706
2707 MI.eraseFromParent();
2708 return std::pair(Split[0], Split[1]);
2709}
2710
2711std::optional<DestSourcePair>
2713 if (MI.getOpcode() == AMDGPU::WWM_COPY)
2714 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
2715
2716 return std::nullopt;
2717}
2718
2720 MachineOperand &Src0,
2721 unsigned Src0OpName,
2722 MachineOperand &Src1,
2723 unsigned Src1OpName) const {
2724 MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
2725 if (!Src0Mods)
2726 return false;
2727
2728 MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
2729 assert(Src1Mods &&
2730 "All commutable instructions have both src0 and src1 modifiers");
2731
2732 int Src0ModsVal = Src0Mods->getImm();
2733 int Src1ModsVal = Src1Mods->getImm();
2734
2735 Src1Mods->setImm(Src0ModsVal);
2736 Src0Mods->setImm(Src1ModsVal);
2737 return true;
2738}
2739
2741 MachineOperand &RegOp,
2742 MachineOperand &NonRegOp) {
2743 Register Reg = RegOp.getReg();
2744 unsigned SubReg = RegOp.getSubReg();
2745 bool IsKill = RegOp.isKill();
2746 bool IsDead = RegOp.isDead();
2747 bool IsUndef = RegOp.isUndef();
2748 bool IsDebug = RegOp.isDebug();
2749
2750 if (NonRegOp.isImm())
2751 RegOp.ChangeToImmediate(NonRegOp.getImm());
2752 else if (NonRegOp.isFI())
2753 RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
2754 else if (NonRegOp.isGlobal()) {
2755 RegOp.ChangeToGA(NonRegOp.getGlobal(), NonRegOp.getOffset(),
2756 NonRegOp.getTargetFlags());
2757 } else
2758 return nullptr;
2759
2760 // Make sure we don't reinterpret a subreg index in the target flags.
2761 RegOp.setTargetFlags(NonRegOp.getTargetFlags());
2762
2763 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
2764 NonRegOp.setSubReg(SubReg);
2765
2766 return &MI;
2767}
2768
2770 unsigned Src0Idx,
2771 unsigned Src1Idx) const {
2772 assert(!NewMI && "this should never be used");
2773
2774 unsigned Opc = MI.getOpcode();
2775 int CommutedOpcode = commuteOpcode(Opc);
2776 if (CommutedOpcode == -1)
2777 return nullptr;
2778
2779 if (Src0Idx > Src1Idx)
2780 std::swap(Src0Idx, Src1Idx);
2781
2782 assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
2783 static_cast<int>(Src0Idx) &&
2784 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
2785 static_cast<int>(Src1Idx) &&
2786 "inconsistency with findCommutedOpIndices");
2787
2788 MachineOperand &Src0 = MI.getOperand(Src0Idx);
2789 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2790
2791 MachineInstr *CommutedMI = nullptr;
2792 if (Src0.isReg() && Src1.isReg()) {
2793 if (isOperandLegal(MI, Src1Idx, &Src0)) {
2794 // Be sure to copy the source modifiers to the right place.
2795 CommutedMI
2796 = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
2797 }
2798
2799 } else if (Src0.isReg() && !Src1.isReg()) {
2800 // src0 should always be able to support any operand type, so no need to
2801 // check operand legality.
2802 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2803 } else if (!Src0.isReg() && Src1.isReg()) {
2804 if (isOperandLegal(MI, Src1Idx, &Src0))
2805 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2806 } else {
2807 // FIXME: Found two non registers to commute. This does happen.
2808 return nullptr;
2809 }
2810
2811 if (CommutedMI) {
2812 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2813 Src1, AMDGPU::OpName::src1_modifiers);
2814
2815 CommutedMI->setDesc(get(CommutedOpcode));
2816 }
2817
2818 return CommutedMI;
2819}
2820
2821// This needs to be implemented because the source modifiers may be inserted
2822// between the true commutable operands, and the base
2823// TargetInstrInfo::commuteInstruction uses it.
2825 unsigned &SrcOpIdx0,
2826 unsigned &SrcOpIdx1) const {
2827 return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
2828}
2829
2831 unsigned &SrcOpIdx0,
2832 unsigned &SrcOpIdx1) const {
2833 if (!Desc.isCommutable())
2834 return false;
2835
2836 unsigned Opc = Desc.getOpcode();
2837 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
2838 if (Src0Idx == -1)
2839 return false;
2840
2841 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
2842 if (Src1Idx == -1)
2843 return false;
2844
2845 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
2846}
2847
2849 int64_t BrOffset) const {
2850 // BranchRelaxation should never have to check s_setpc_b64 because its dest
2851 // block is unanalyzable.
2852 assert(BranchOp != AMDGPU::S_SETPC_B64);
2853
2854 // Convert to dwords.
2855 BrOffset /= 4;
2856
2857 // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
2858 // from the next instruction.
2859 BrOffset -= 1;
2860
2861 return isIntN(BranchOffsetBits, BrOffset);
2862}
2863
2866 return MI.getOperand(0).getMBB();
2867}
2868
2870 for (const MachineInstr &MI : MBB->terminators()) {
2871 if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
2872 MI.getOpcode() == AMDGPU::SI_IF || MI.getOpcode() == AMDGPU::SI_ELSE ||
2873 MI.getOpcode() == AMDGPU::SI_LOOP)
2874 return true;
2875 }
2876 return false;
2877}
2878
2880 MachineBasicBlock &DestBB,
2881 MachineBasicBlock &RestoreBB,
2882 const DebugLoc &DL, int64_t BrOffset,
2883 RegScavenger *RS) const {
2884 assert(RS && "RegScavenger required for long branching");
2885 assert(MBB.empty() &&
2886 "new block should be inserted for expanding unconditional branch");
2887 assert(MBB.pred_size() == 1);
2888 assert(RestoreBB.empty() &&
2889 "restore block should be inserted for restoring clobbered registers");
2890
2894
2895 // FIXME: Virtual register workaround for RegScavenger not working with empty
2896 // blocks.
2897 Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2898
2899 auto I = MBB.end();
2900
2901 // We need to compute the offset relative to the instruction immediately after
2902 // s_getpc_b64. Insert pc arithmetic code before last terminator.
2903 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2904
2905 auto &MCCtx = MF->getContext();
2906 MCSymbol *PostGetPCLabel =
2907 MCCtx.createTempSymbol("post_getpc", /*AlwaysAddSuffix=*/true);
2908 GetPC->setPostInstrSymbol(*MF, PostGetPCLabel);
2909
2910 MCSymbol *OffsetLo =
2911 MCCtx.createTempSymbol("offset_lo", /*AlwaysAddSuffix=*/true);
2912 MCSymbol *OffsetHi =
2913 MCCtx.createTempSymbol("offset_hi", /*AlwaysAddSuffix=*/true);
2914 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
2915 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
2916 .addReg(PCReg, 0, AMDGPU::sub0)
2917 .addSym(OffsetLo, MO_FAR_BRANCH_OFFSET);
2918 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
2919 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
2920 .addReg(PCReg, 0, AMDGPU::sub1)
2921 .addSym(OffsetHi, MO_FAR_BRANCH_OFFSET);
2922
2923 // Insert the indirect branch after the other terminator.
2924 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2925 .addReg(PCReg);
2926
2927 // If a spill is needed for the pc register pair, we need to insert a spill
2928 // restore block right before the destination block, and insert a short branch
2929 // into the old destination block's fallthrough predecessor.
2930 // e.g.:
2931 //
2932 // s_cbranch_scc0 skip_long_branch:
2933 //
2934 // long_branch_bb:
2935 // spill s[8:9]
2936 // s_getpc_b64 s[8:9]
2937 // s_add_u32 s8, s8, restore_bb
2938 // s_addc_u32 s9, s9, 0
2939 // s_setpc_b64 s[8:9]
2940 //
2941 // skip_long_branch:
2942 // foo;
2943 //
2944 // .....
2945 //
2946 // dest_bb_fallthrough_predecessor:
2947 // bar;
2948 // s_branch dest_bb
2949 //
2950 // restore_bb:
2951 // restore s[8:9]
2952 // fallthrough dest_bb
2953 ///
2954 // dest_bb:
2955 // buzz;
2956
2957 Register LongBranchReservedReg = MFI->getLongBranchReservedReg();
2958 Register Scav;
2959
2960 // If we've previously reserved a register for long branches
2961 // avoid running the scavenger and just use those registers
2962 if (LongBranchReservedReg) {
2963 RS->enterBasicBlock(MBB);
2964 Scav = LongBranchReservedReg;
2965 } else {
2967 Scav = RS->scavengeRegisterBackwards(
2968 AMDGPU::SReg_64RegClass, MachineBasicBlock::iterator(GetPC),
2969 /* RestoreAfter */ false, 0, /* AllowSpill */ false);
2970 }
2971 if (Scav) {
2972 RS->setRegUsed(Scav);
2973 MRI.replaceRegWith(PCReg, Scav);
2974 MRI.clearVirtRegs();
2975 } else {
2976 // As SGPR needs VGPR to be spilled, we reuse the slot of temporary VGPR for
2977 // SGPR spill.
2978 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2979 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2980 TRI->spillEmergencySGPR(GetPC, RestoreBB, AMDGPU::SGPR0_SGPR1, RS);
2981 MRI.replaceRegWith(PCReg, AMDGPU::SGPR0_SGPR1);
2982 MRI.clearVirtRegs();
2983 }
2984
2985 MCSymbol *DestLabel = Scav ? DestBB.getSymbol() : RestoreBB.getSymbol();
2986 // Now, the distance could be defined.
2988 MCSymbolRefExpr::create(DestLabel, MCCtx),
2989 MCSymbolRefExpr::create(PostGetPCLabel, MCCtx), MCCtx);
2990 // Add offset assignments.
2991 auto *Mask = MCConstantExpr::create(0xFFFFFFFFULL, MCCtx);
2992 OffsetLo->setVariableValue(MCBinaryExpr::createAnd(Offset, Mask, MCCtx));
2993 auto *ShAmt = MCConstantExpr::create(32, MCCtx);
2994 OffsetHi->setVariableValue(MCBinaryExpr::createAShr(Offset, ShAmt, MCCtx));
2995}
2996
2997unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
2998 switch (Cond) {
2999 case SIInstrInfo::SCC_TRUE:
3000 return AMDGPU::S_CBRANCH_SCC1;
3001 case SIInstrInfo::SCC_FALSE:
3002 return AMDGPU::S_CBRANCH_SCC0;
3003 case SIInstrInfo::VCCNZ:
3004 return AMDGPU::S_CBRANCH_VCCNZ;
3005 case SIInstrInfo::VCCZ:
3006 return AMDGPU::S_CBRANCH_VCCZ;
3007 case SIInstrInfo::EXECNZ:
3008 return AMDGPU::S_CBRANCH_EXECNZ;
3009 case SIInstrInfo::EXECZ:
3010 return AMDGPU::S_CBRANCH_EXECZ;
3011 default:
3012 llvm_unreachable("invalid branch predicate");
3013 }
3014}
3015
3016SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
3017 switch (Opcode) {
3018 case AMDGPU::S_CBRANCH_SCC0:
3019 return SCC_FALSE;
3020 case AMDGPU::S_CBRANCH_SCC1:
3021 return SCC_TRUE;
3022 case AMDGPU::S_CBRANCH_VCCNZ:
3023 return VCCNZ;
3024 case AMDGPU::S_CBRANCH_VCCZ:
3025 return VCCZ;
3026 case AMDGPU::S_CBRANCH_EXECNZ:
3027 return EXECNZ;
3028 case AMDGPU::S_CBRANCH_EXECZ:
3029 return EXECZ;
3030 default:
3031 return INVALID_BR;
3032 }
3033}
3034
3038 MachineBasicBlock *&FBB,
3040 bool AllowModify) const {
3041 if (I->getOpcode() == AMDGPU::S_BRANCH) {
3042 // Unconditional Branch
3043 TBB = I->getOperand(0).getMBB();
3044 return false;
3045 }
3046
3047 MachineBasicBlock *CondBB = nullptr;
3048
3049 if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
3050 CondBB = I->getOperand(1).getMBB();
3051 Cond.push_back(I->getOperand(0));
3052 } else {
3053 BranchPredicate Pred = getBranchPredicate(I->getOpcode());
3054 if (Pred == INVALID_BR)
3055 return true;
3056
3057 CondBB = I->getOperand(0).getMBB();
3058 Cond.push_back(MachineOperand::CreateImm(Pred));
3059 Cond.push_back(I->getOperand(1)); // Save the branch register.
3060 }
3061 ++I;
3062
3063 if (I == MBB.end()) {
3064 // Conditional branch followed by fall-through.
3065 TBB = CondBB;
3066 return false;
3067 }
3068
3069 if (I->getOpcode() == AMDGPU::S_BRANCH) {
3070 TBB = CondBB;
3071 FBB = I->getOperand(0).getMBB();
3072 return false;
3073 }
3074
3075 return true;
3076}
3077
3079 MachineBasicBlock *&FBB,
3081 bool AllowModify) const {
3083 auto E = MBB.end();
3084 if (I == E)
3085 return false;
3086
3087 // Skip over the instructions that are artificially terminators for special
3088 // exec management.
3089 while (I != E && !I->isBranch() && !I->isReturn()) {
3090 switch (I->getOpcode()) {
3091 case AMDGPU::S_MOV_B64_term:
3092 case AMDGPU::S_XOR_B64_term:
3093 case AMDGPU::S_OR_B64_term:
3094 case AMDGPU::S_ANDN2_B64_term:
3095 case AMDGPU::S_AND_B64_term:
3096 case AMDGPU::S_AND_SAVEEXEC_B64_term:
3097 case AMDGPU::S_MOV_B32_term:
3098 case AMDGPU::S_XOR_B32_term:
3099 case AMDGPU::S_OR_B32_term:
3100 case AMDGPU::S_ANDN2_B32_term:
3101 case AMDGPU::S_AND_B32_term:
3102 case AMDGPU::S_AND_SAVEEXEC_B32_term:
3103 break;
3104 case AMDGPU::SI_IF:
3105 case AMDGPU::SI_ELSE:
3106 case AMDGPU::SI_KILL_I1_TERMINATOR:
3107 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
3108 // FIXME: It's messy that these need to be considered here at all.
3109 return true;
3110 default:
3111 llvm_unreachable("unexpected non-branch terminator inst");
3112 }
3113
3114 ++I;
3115 }
3116
3117 if (I == E)
3118 return false;
3119
3120 return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
3121}
3122
3124 int *BytesRemoved) const {
3125 unsigned Count = 0;
3126 unsigned RemovedSize = 0;
3128 // Skip over artificial terminators when removing instructions.
3129 if (MI.isBranch() || MI.isReturn()) {
3130 RemovedSize += getInstSizeInBytes(MI);
3131 MI.eraseFromParent();
3132 ++Count;
3133 }
3134 }
3135
3136 if (BytesRemoved)
3137 *BytesRemoved = RemovedSize;
3138
3139 return Count;
3140}
3141
3142// Copy the flags onto the implicit condition register operand.
3144 const MachineOperand &OrigCond) {
3145 CondReg.setIsUndef(OrigCond.isUndef());
3146 CondReg.setIsKill(OrigCond.isKill());
3147}
3148
3151 MachineBasicBlock *FBB,
3153 const DebugLoc &DL,
3154 int *BytesAdded) const {
3155 if (!FBB && Cond.empty()) {
3156 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
3157 .addMBB(TBB);
3158 if (BytesAdded)
3159 *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
3160 return 1;
3161 }
3162
3163 if(Cond.size() == 1 && Cond[0].isReg()) {
3164 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
3165 .add(Cond[0])
3166 .addMBB(TBB);
3167 return 1;
3168 }
3169
3170 assert(TBB && Cond[0].isImm());
3171
3172 unsigned Opcode
3173 = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
3174
3175 if (!FBB) {
3176 MachineInstr *CondBr =
3177 BuildMI(&MBB, DL, get(Opcode))
3178 .addMBB(TBB);
3179
3180 // Copy the flags onto the implicit condition register operand.
3181 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
3182 fixImplicitOperands(*CondBr);
3183
3184 if (BytesAdded)
3185 *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
3186 return 1;
3187 }
3188
3189 assert(TBB && FBB);
3190
3191 MachineInstr *CondBr =
3192 BuildMI(&MBB, DL, get(Opcode))
3193 .addMBB(TBB);
3194 fixImplicitOperands(*CondBr);
3195 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
3196 .addMBB(FBB);
3197
3198 MachineOperand &CondReg = CondBr->getOperand(1);
3199 CondReg.setIsUndef(Cond[1].isUndef());
3200 CondReg.setIsKill(Cond[1].isKill());
3201
3202 if (BytesAdded)
3203 *BytesAdded = ST.hasOffset3fBug() ? 16 : 8;
3204
3205 return 2;
3206}
3207
3210 if (Cond.size() != 2) {
3211 return true;
3212 }
3213
3214 if (Cond[0].isImm()) {
3215 Cond[0].setImm(-Cond[0].getImm());
3216 return false;
3217 }
3218
3219 return true;
3220}
3221
3224 Register DstReg, Register TrueReg,
3225 Register FalseReg, int &CondCycles,
3226 int &TrueCycles, int &FalseCycles) const {
3227 switch (Cond[0].getImm()) {
3228 case VCCNZ:
3229 case VCCZ: {
3231 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3232 if (MRI.getRegClass(FalseReg) != RC)
3233 return false;
3234
3235 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32;
3236 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
3237
3238 // Limit to equal cost for branch vs. N v_cndmask_b32s.
3239 return RI.hasVGPRs(RC) && NumInsts <= 6;
3240 }
3241 case SCC_TRUE:
3242 case SCC_FALSE: {
3243 // FIXME: We could insert for VGPRs if we could replace the original compare
3244 // with a vector one.
3246 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3247 if (MRI.getRegClass(FalseReg) != RC)
3248 return false;
3249
3250 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32;
3251
3252 // Multiples of 8 can do s_cselect_b64
3253 if (NumInsts % 2 == 0)
3254 NumInsts /= 2;
3255
3256 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
3257 return RI.isSGPRClass(RC);
3258 }
3259 default:
3260 return false;
3261 }
3262}
3263
3267 Register TrueReg, Register FalseReg) const {
3268 BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
3269 if (Pred == VCCZ || Pred == SCC_FALSE) {
3270 Pred = static_cast<BranchPredicate>(-Pred);
3271 std::swap(TrueReg, FalseReg);
3272 }
3273
3275 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
3276 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
3277
3278 if (DstSize == 32) {
3280 if (Pred == SCC_TRUE) {
3281 Select = BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B32), DstReg)
3282 .addReg(TrueReg)
3283 .addReg(FalseReg);
3284 } else {
3285 // Instruction's operands are backwards from what is expected.
3286 Select = BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e32), DstReg)
3287 .addReg(FalseReg)
3288 .addReg(TrueReg);
3289 }
3290
3291 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3292 return;
3293 }
3294
3295 if (DstSize == 64 && Pred == SCC_TRUE) {
3297 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
3298 .addReg(TrueReg)
3299 .addReg(FalseReg);
3300
3301 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3302 return;
3303 }
3304
3305 static const int16_t Sub0_15[] = {
3306 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
3307 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
3308 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
3309 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
3310 };
3311
3312 static const int16_t Sub0_15_64[] = {
3313 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
3314 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
3315 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
3316 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
3317 };
3318
3319 unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
3320 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
3321 const int16_t *SubIndices = Sub0_15;
3322 int NElts = DstSize / 32;
3323
3324 // 64-bit select is only available for SALU.
3325 // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
3326 if (Pred == SCC_TRUE) {
3327 if (NElts % 2) {
3328 SelOp = AMDGPU::S_CSELECT_B32;
3329 EltRC = &AMDGPU::SGPR_32RegClass;
3330 } else {
3331 SelOp = AMDGPU::S_CSELECT_B64;
3332 EltRC = &AMDGPU::SGPR_64RegClass;
3333 SubIndices = Sub0_15_64;
3334 NElts /= 2;
3335 }
3336 }
3337
3339 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
3340
3341 I = MIB->getIterator();
3342
3344 for (int Idx = 0; Idx != NElts; ++Idx) {
3345 Register DstElt = MRI.createVirtualRegister(EltRC);
3346 Regs.push_back(DstElt);
3347
3348 unsigned SubIdx = SubIndices[Idx];
3349
3351 if (SelOp == AMDGPU::V_CNDMASK_B32_e32) {
3352 Select =
3353 BuildMI(MBB, I, DL, get(SelOp), DstElt)
3354 .addReg(FalseReg, 0, SubIdx)
3355 .addReg(TrueReg, 0, SubIdx);
3356 } else {
3357 Select =
3358 BuildMI(MBB, I, DL, get(SelOp), DstElt)
3359 .addReg(TrueReg, 0, SubIdx)
3360 .addReg(FalseReg, 0, SubIdx);
3361 }
3362
3363 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3365
3366 MIB.addReg(DstElt)
3367 .addImm(SubIdx);
3368 }
3369}
3370
3372 switch (MI.getOpcode()) {
3373 case AMDGPU::V_MOV_B32_e32:
3374 case AMDGPU::V_MOV_B32_e64:
3375 case AMDGPU::V_MOV_B64_PSEUDO:
3376 case AMDGPU::V_MOV_B64_e32:
3377 case AMDGPU::V_MOV_B64_e64:
3378 case AMDGPU::S_MOV_B32:
3379 case AMDGPU::S_MOV_B64:
3380 case AMDGPU::S_MOV_B64_IMM_PSEUDO:
3381 case AMDGPU::COPY:
3382 case AMDGPU::WWM_COPY:
3383 case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
3384 case AMDGPU::V_ACCVGPR_READ_B32_e64:
3385 case AMDGPU::V_ACCVGPR_MOV_B32:
3386 return true;
3387 default:
3388 return false;
3389 }
3390}
3391
3392static constexpr unsigned ModifierOpNames[] = {
3393 AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
3394 AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
3395 AMDGPU::OpName::omod, AMDGPU::OpName::op_sel};
3396
3398 unsigned Opc = MI.getOpcode();
3399 for (unsigned Name : reverse(ModifierOpNames)) {
3401 if (Idx >= 0)
3402 MI.removeOperand(Idx);
3403 }
3404}
3405
3407 Register Reg, MachineRegisterInfo *MRI) const {
3408 if (!MRI->hasOneNonDBGUse(Reg))
3409 return false;
3410
3411 switch (DefMI.getOpcode()) {
3412 default:
3413 return false;
3414 case AMDGPU::V_MOV_B64_e32:
3415 case AMDGPU::S_MOV_B64:
3416 case AMDGPU::V_MOV_B64_PSEUDO:
3417 case AMDGPU::S_MOV_B64_IMM_PSEUDO:
3418 case AMDGPU::V_MOV_B32_e32:
3419 case AMDGPU::S_MOV_B32:
3420 case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
3421 break;
3422 }
3423
3424 const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
3425 assert(ImmOp);
3426 // FIXME: We could handle FrameIndex values here.
3427 if (!ImmOp->isImm())
3428 return false;
3429
3430 auto getImmFor = [ImmOp](const MachineOperand &UseOp) -> int64_t {
3431 int64_t Imm = ImmOp->getImm();
3432 switch (UseOp.getSubReg()) {
3433 default:
3434 return Imm;
3435 case AMDGPU::sub0:
3436 return Lo_32(Imm);
3437 case AMDGPU::sub1:
3438 return Hi_32(Imm);
3439 case AMDGPU::lo16:
3440 return APInt(16, Imm).getSExtValue();
3441 case AMDGPU::hi16:
3442 return APInt(32, Imm).ashr(16).getSExtValue();
3443 case AMDGPU::sub1_lo16:
3444 return APInt(16, Hi_32(Imm)).getSExtValue();
3445 case AMDGPU::sub1_hi16:
3446 return APInt(32, Hi_32(Imm)).ashr(16).getSExtValue();
3447 }
3448 };
3449
3450 assert(!DefMI.getOperand(0).getSubReg() && "Expected SSA form");
3451
3452 unsigned Opc = UseMI.getOpcode();
3453 if (Opc == AMDGPU::COPY) {
3454 assert(!UseMI.getOperand(0).getSubReg() && "Expected SSA form");
3455
3456 Register DstReg = UseMI.getOperand(0).getReg();
3457 unsigned OpSize = getOpSize(UseMI, 0);
3458 bool Is16Bit = OpSize == 2;
3459 bool Is64Bit = OpSize == 8;
3460 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
3461 unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO
3462 : AMDGPU::V_MOV_B32_e32
3463 : Is64Bit ? AMDGPU::S_MOV_B64_IMM_PSEUDO
3464 : AMDGPU::S_MOV_B32;
3465 APInt Imm(Is64Bit ? 64 : 32, getImmFor(UseMI.getOperand(1)));
3466
3467 if (RI.isAGPR(*MRI, DstReg)) {
3468 if (Is64Bit || !isInlineConstant(Imm))
3469 return false;
3470 NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
3471 }
3472
3473 if (Is16Bit) {
3474 if (isVGPRCopy)
3475 return false; // Do not clobber vgpr_hi16
3476
3477 if (DstReg.isVirtual() && UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
3478 return false;
3479
3480 UseMI.getOperand(0).setSubReg(0);
3481 if (DstReg.isPhysical()) {
3482 DstReg = RI.get32BitRegister(DstReg);
3483 UseMI.getOperand(0).setReg(DstReg);
3484 }
3485 assert(UseMI.getOperand(1).getReg().isVirtual());
3486 }
3487
3488 const MCInstrDesc &NewMCID = get(NewOpc);
3489 if (DstReg.isPhysical() &&
3490 !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
3491 return false;
3492
3493 UseMI.setDesc(NewMCID);
3494 UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
3495 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
3496 return true;
3497 }
3498
3499 if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
3500 Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3501 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3502 Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3503 Opc == AMDGPU::V_FMAC_F16_t16_e64) {
3504 // Don't fold if we are using source or output modifiers. The new VOP2
3505 // instructions don't have them.
3507 return false;
3508
3509 // If this is a free constant, there's no reason to do this.
3510 // TODO: We could fold this here instead of letting SIFoldOperands do it
3511 // later.
3512 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
3513
3514 // Any src operand can be used for the legality check.
3515 if (isInlineConstant(UseMI, *Src0, *ImmOp))
3516 return false;
3517
3518 bool IsF32 = Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
3519 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64;
3520 bool IsFMA =
3521 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3522 Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3523 Opc == AMDGPU::V_FMAC_F16_t16_e64;
3524 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
3525 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
3526
3527 // Multiplied part is the constant: Use v_madmk_{f16, f32}.
3528 if ((Src0->isReg() && Src0->getReg() == Reg) ||
3529 (Src1->isReg() && Src1->getReg() == Reg)) {
3530 MachineOperand *RegSrc =
3531 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1;
3532 if (!RegSrc->isReg())
3533 return false;
3534 if (RI.isSGPRClass(MRI->getRegClass(RegSrc->getReg())) &&
3535 ST.getConstantBusLimit(Opc) < 2)
3536 return false;
3537
3538 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
3539 return false;
3540
3541 // If src2 is also a literal constant then we have to choose which one to
3542 // fold. In general it is better to choose madak so that the other literal
3543 // can be materialized in an sgpr instead of a vgpr:
3544 // s_mov_b32 s0, literal
3545 // v_madak_f32 v0, s0, v0, literal
3546 // Instead of:
3547 // v_mov_b32 v1, literal
3548 // v_madmk_f32 v0, v0, literal, v1
3549 MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg());
3550 if (Def && Def->isMoveImmediate() &&
3551 !isInlineConstant(Def->getOperand(1)))
3552 return false;
3553
3554 unsigned NewOpc =
3555 IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32
3556 : ST.hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16
3557 : AMDGPU::V_FMAMK_F16)
3558 : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
3559 if (pseudoToMCOpcode(NewOpc) == -1)
3560 return false;
3561
3562 // V_FMAMK_F16_t16 takes VGPR_32_Lo128 operands, so the rewrite
3563 // would also require restricting their register classes. For now
3564 // just bail out.
3565 if (NewOpc == AMDGPU::V_FMAMK_F16_t16)
3566 return false;
3567
3568 const int64_t Imm = getImmFor(RegSrc == Src1 ? *Src0 : *Src1);
3569
3570 // FIXME: This would be a lot easier if we could return a new instruction
3571 // instead of having to modify in place.
3572
3573 Register SrcReg = RegSrc->getReg();
3574 unsigned SrcSubReg = RegSrc->getSubReg();
3575 Src0->setReg(SrcReg);
3576 Src0->setSubReg(SrcSubReg);
3577 Src0->setIsKill(RegSrc->isKill());
3578
3579 if (Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3580 Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3581 Opc == AMDGPU::V_FMAC_F16_e64)
3582 UseMI.untieRegOperand(
3583 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
3584
3585 Src1->ChangeToImmediate(Imm);
3586
3588 UseMI.setDesc(get(NewOpc));
3589
3590 bool DeleteDef = MRI->use_nodbg_empty(Reg);
3591 if (DeleteDef)
3592 DefMI.eraseFromParent();
3593
3594 return true;
3595 }
3596
3597 // Added part is the constant: Use v_madak_{f16, f32}.
3598 if (Src2->isReg() && Src2->getReg() == Reg) {
3599 if (ST.getConstantBusLimit(Opc) < 2) {
3600 // Not allowed to use constant bus for another operand.
3601 // We can however allow an inline immediate as src0.
3602 bool Src0Inlined = false;
3603 if (Src0->isReg()) {
3604 // Try to inline constant if possible.
3605 // If the Def moves immediate and the use is single
3606 // We are saving VGPR here.
3607 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
3608 if (Def && Def->isMoveImmediate() &&
3609 isInlineConstant(Def->getOperand(1)) &&
3610 MRI->hasOneUse(Src0->getReg())) {
3611 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3612 Src0Inlined = true;
3613 } else if (ST.getConstantBusLimit(Opc) <= 1 &&
3614 RI.isSGPRReg(*MRI, Src0->getReg())) {
3615 return false;
3616 }
3617 // VGPR is okay as Src0 - fallthrough
3618 }
3619
3620 if (Src1->isReg() && !Src0Inlined) {
3621 // We have one slot for inlinable constant so far - try to fill it
3622 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
3623 if (Def && Def->isMoveImmediate() &&
3624 isInlineConstant(Def->getOperand(1)) &&
3625 MRI->hasOneUse(Src1->getReg()) && commuteInstruction(UseMI))
3626 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3627 else if (RI.isSGPRReg(*MRI, Src1->getReg()))
3628 return false;
3629 // VGPR is okay as Src1 - fallthrough
3630 }
3631 }
3632
3633 unsigned NewOpc =
3634 IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32
3635 : ST.hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16
3636 : AMDGPU::V_FMAAK_F16)
3637 : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
3638 if (pseudoToMCOpcode(NewOpc) == -1)
3639 return false;
3640
3641 // V_FMAAK_F16_t16 takes VGPR_32_Lo128 operands, so the rewrite
3642 // would also require restricting their register classes. For now
3643 // just bail out.
3644 if (NewOpc == AMDGPU::V_FMAAK_F16_t16)
3645 return false;
3646
3647 // FIXME: This would be a lot easier if we could return a new instruction
3648 // instead of having to modify in place.
3649
3650 if (Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3651 Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3652 Opc == AMDGPU::V_FMAC_F16_e64)
3653 UseMI.untieRegOperand(
3654 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
3655
3656 // ChangingToImmediate adds Src2 back to the instruction.
3657 Src2->ChangeToImmediate(getImmFor(*Src2));
3658
3659 // These come before src2.
3661 UseMI.setDesc(get(NewOpc));
3662 // It might happen that UseMI was commuted
3663 // and we now have SGPR as SRC1. If so 2 inlined
3664 // constant and SGPR are illegal.
3666
3667 bool DeleteDef = MRI->use_nodbg_empty(Reg);
3668 if (DeleteDef)
3669 DefMI.eraseFromParent();
3670
3671 return true;
3672 }
3673 }
3674
3675 return false;
3676}
3677
3678static bool
3681 if (BaseOps1.size() != BaseOps2.size())
3682 return false;
3683 for (size_t I = 0, E = BaseOps1.size(); I < E; ++I) {
3684 if (!BaseOps1[I]->isIdenticalTo(*BaseOps2[I]))
3685 return false;
3686 }
3687 return true;
3688}
3689
3690static bool offsetsDoNotOverlap(LocationSize WidthA, int OffsetA,
3691 LocationSize WidthB, int OffsetB) {
3692 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
3693 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
3694 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
3695 return LowWidth.hasValue() &&
3696 LowOffset + (int)LowWidth.getValue() <= HighOffset;
3697}
3698
3699bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
3700 const MachineInstr &MIb) const {
3701 SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
3702 int64_t Offset0, Offset1;
3703 LocationSize Dummy0 = 0, Dummy1 = 0;
3704 bool Offset0IsScalable, Offset1IsScalable;
3705 if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
3706 Dummy0, &RI) ||
3707 !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
3708 Dummy1, &RI))
3709 return false;
3710
3711 if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))
3712 return false;
3713
3714 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
3715 // FIXME: Handle ds_read2 / ds_write2.
3716 return false;
3717 }
3718 LocationSize Width0 = MIa.memoperands().front()->getSize();
3719 LocationSize Width1 = MIb.memoperands().front()->getSize();
3720 return offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1);
3721}
3722
3724 const MachineInstr &MIb) const {
3725 assert(MIa.mayLoadOrStore() &&
3726 "MIa must load from or modify a memory location");
3727 assert(MIb.mayLoadOrStore() &&
3728 "MIb must load from or modify a memory location");
3729
3731 return false;
3732
3733 // XXX - Can we relax this between address spaces?
3734 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
3735 return false;
3736
3737 if (isLDSDMA(MIa) || isLDSDMA(MIb))
3738 return false;
3739
3740 // TODO: Should we check the address space from the MachineMemOperand? That
3741 // would allow us to distinguish objects we know don't alias based on the
3742 // underlying address space, even if it was lowered to a different one,
3743 // e.g. private accesses lowered to use MUBUF instructions on a scratch
3744 // buffer.
3745 if (isDS(MIa)) {
3746 if (isDS(MIb))
3747 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3748
3749 return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
3750 }
3751
3752 if (isMUBUF(MIa) || isMTBUF(MIa)) {
3753 if (isMUBUF(MIb) || isMTBUF(MIb))
3754 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3755
3756 if (isFLAT(MIb))
3757 return isFLATScratch(MIb);
3758
3759 return !isSMRD(MIb);
3760 }
3761
3762 if (isSMRD(MIa)) {
3763 if (isSMRD(MIb))
3764 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3765
3766 if (isFLAT(MIb))
3767 return isFLATScratch(MIb);
3768
3769 return !isMUBUF(MIb) && !isMTBUF(MIb);
3770 }
3771
3772 if (isFLAT(MIa)) {
3773 if (isFLAT(MIb)) {
3774 if ((isFLATScratch(MIa) && isFLATGlobal(MIb)) ||
3775 (isFLATGlobal(MIa) && isFLATScratch(MIb)))
3776 return true;
3777
3778 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3779 }
3780
3781 return false;
3782 }
3783
3784 return false;
3785}
3786
3788 int64_t &Imm, MachineInstr **DefMI = nullptr) {
3789 if (Reg.isPhysical())
3790 return false;
3791 auto *Def = MRI.getUniqueVRegDef(Reg);
3792 if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {
3793 Imm = Def->getOperand(1).getImm();
3794 if (DefMI)
3795 *DefMI = Def;
3796 return true;
3797 }
3798 return false;
3799}
3800
3801static bool getFoldableImm(const MachineOperand *MO, int64_t &Imm,
3802 MachineInstr **DefMI = nullptr) {
3803 if (!MO->isReg())
3804 return false;
3805 const MachineFunction *MF = MO->getParent()->getParent()->getParent();
3806 const MachineRegisterInfo &MRI = MF->getRegInfo();
3807 return getFoldableImm(MO->getReg(), MRI, Imm, DefMI);
3808}
3809
3811 MachineInstr &NewMI) {
3812 if (LV) {
3813 unsigned NumOps = MI.getNumOperands();
3814 for (unsigned I = 1; I < NumOps; ++I) {
3815 MachineOperand &Op = MI.getOperand(I);
3816 if (Op.isReg() && Op.isKill())
3817 LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
3818 }
3819 }
3820}
3821
3823 LiveVariables *LV,
3824 LiveIntervals *LIS) const {
3825 MachineBasicBlock &MBB = *MI.getParent();
3826 unsigned Opc = MI.getOpcode();
3827
3828 // Handle MFMA.
3829 int NewMFMAOpc = AMDGPU::getMFMAEarlyClobberOp(Opc);
3830 if (NewMFMAOpc != -1) {
3832 BuildMI(MBB, MI, MI.getDebugLoc(), get(NewMFMAOpc));
3833 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3834 MIB.add(MI.getOperand(I));
3835 updateLiveVariables(LV, MI, *MIB);
3836 if (LIS) {
3837 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3838 // SlotIndex of defs needs to be updated when converting to early-clobber
3839 MachineOperand &Def = MIB->getOperand(0);
3840 if (Def.isEarlyClobber() && Def.isReg() &&
3841 LIS->hasInterval(Def.getReg())) {
3842 SlotIndex OldIndex = LIS->getInstructionIndex(*MIB).getRegSlot(false);
3843 SlotIndex NewIndex = LIS->getInstructionIndex(*MIB).getRegSlot(true);
3844 auto &LI = LIS->getInterval(Def.getReg());
3845 auto UpdateDefIndex = [&](LiveRange &LR) {
3846 auto S = LR.find(OldIndex);
3847 if (S != LR.end() && S->start == OldIndex) {
3848 assert(S->valno && S->valno->def == OldIndex);
3849 S->start = NewIndex;
3850 S->valno->def = NewIndex;
3851 }
3852 };
3853 UpdateDefIndex(LI);
3854 for (auto &SR : LI.subranges())
3855 UpdateDefIndex(SR);
3856 }
3857 }
3858 return MIB;
3859 }
3860
3861 if (SIInstrInfo::isWMMA(MI)) {
3862 unsigned NewOpc = AMDGPU::mapWMMA2AddrTo3AddrOpcode(MI.getOpcode());
3863 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3864 .setMIFlags(MI.getFlags());
3865 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3866 MIB->addOperand(MI.getOperand(I));
3867
3868 updateLiveVariables(LV, MI, *MIB);
3869 if (LIS)
3870 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3871
3872 return MIB;
3873 }
3874
3875 assert(Opc != AMDGPU::V_FMAC_F16_t16_e32 &&
3876 "V_FMAC_F16_t16_e32 is not supported and not expected to be present "
3877 "pre-RA");
3878
3879 // Handle MAC/FMAC.
3880 bool IsF16 = Opc == AMDGPU::V_MAC_F16_e32 || Opc == AMDGPU::V_MAC_F16_e64 ||
3881 Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3882 Opc == AMDGPU::V_FMAC_F16_t16_e64;
3883 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3884 Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
3885 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64 ||
3886 Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3887 Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3888 Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3889 bool IsF64 = Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3890 bool IsLegacy = Opc == AMDGPU::V_MAC_LEGACY_F32_e32 ||
3891 Opc == AMDGPU::V_MAC_LEGACY_F32_e64 ||
3892 Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
3893 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64;
3894 bool Src0Literal = false;
3895
3896 switch (Opc) {
3897 default:
3898 return nullptr;
3899 case AMDGPU::V_MAC_F16_e64:
3900 case AMDGPU::V_FMAC_F16_e64:
3901 case AMDGPU::V_FMAC_F16_t16_e64:
3902 case AMDGPU::V_MAC_F32_e64:
3903 case AMDGPU::V_MAC_LEGACY_F32_e64:
3904 case AMDGPU::V_FMAC_F32_e64:
3905 case AMDGPU::V_FMAC_LEGACY_F32_e64:
3906 case AMDGPU::V_FMAC_F64_e64:
3907 break;
3908 case AMDGPU::V_MAC_F16_e32:
3909 case AMDGPU::V_FMAC_F16_e32:
3910 case AMDGPU::V_MAC_F32_e32:
3911 case AMDGPU::V_MAC_LEGACY_F32_e32:
3912 case AMDGPU::V_FMAC_F32_e32:
3913 case AMDGPU::V_FMAC_LEGACY_F32_e32:
3914 case AMDGPU::V_FMAC_F64_e32: {
3915 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3916 AMDGPU::OpName::src0);
3917 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3918 if (!Src0->isReg() && !Src0->isImm())
3919 return nullptr;
3920
3921 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
3922 Src0Literal = true;
3923
3924 break;
3925 }
3926 }
3927
3929 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3930 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
3931 const MachineOperand *Src0Mods =
3932 getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
3933 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3934 const MachineOperand *Src1Mods =
3935 getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
3936 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3937 const MachineOperand *Src2Mods =
3938 getNamedOperand(MI, AMDGPU::OpName::src2_modifiers);
3939 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3940 const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
3941 const MachineOperand *OpSel = getNamedOperand(MI, AMDGPU::OpName::op_sel);
3942
3943 if (!Src0Mods && !Src1Mods && !Src2Mods && !Clamp && !Omod && !IsF64 &&
3944 !IsLegacy &&
3945 // If we have an SGPR input, we will violate the constant bus restriction.
3946 (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
3947 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
3949 const auto killDef = [&]() -> void {
3951 // The only user is the instruction which will be killed.
3952 Register DefReg = DefMI->getOperand(0).getReg();
3953 if (!MRI.hasOneNonDBGUse(DefReg))
3954 return;
3955 // We cannot just remove the DefMI here, calling pass will crash.
3956 DefMI->setDesc(get(AMDGPU::IMPLICIT_DEF));
3957 for (unsigned I = DefMI->getNumOperands() - 1; I != 0; --I)
3959 if (LV)
3960 LV->getVarInfo(DefReg).AliveBlocks.clear();
3961 };
3962
3963 int64_t Imm;
3964 if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {
3965 unsigned NewOpc =
3966 IsFMA ? (IsF16 ? (ST.hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16
3967 : AMDGPU::V_FMAAK_F16)
3968 : AMDGPU::V_FMAAK_F32)
3969 : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
3970 if (pseudoToMCOpcode(NewOpc) != -1) {
3971 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3972 .add(*Dst)
3973 .add(*Src0)
3974 .add(*Src1)
3975 .addImm(Imm)
3976 .setMIFlags(MI.getFlags());
3977 updateLiveVariables(LV, MI, *MIB);
3978 if (LIS)
3979 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3980 killDef();
3981 return MIB;
3982 }
3983 }
3984 unsigned NewOpc =
3985 IsFMA ? (IsF16 ? (ST.hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16
3986 : AMDGPU::V_FMAMK_F16)
3987 : AMDGPU::V_FMAMK_F32)
3988 : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
3989 if (!Src0Literal && getFoldableImm(Src1, Imm, &DefMI)) {
3990 if (pseudoToMCOpcode(NewOpc) != -1) {
3991 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3992 .add(*Dst)
3993 .add(*Src0)
3994 .addImm(Imm)
3995 .add(*Src2)
3996 .setMIFlags(MI.getFlags());
3997 updateLiveVariables(LV, MI, *MIB);
3998 if (LIS)
3999 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
4000 killDef();
4001 return MIB;
4002 }
4003 }
4004 if (Src0Literal || getFoldableImm(Src0, Imm, &DefMI)) {
4005 if (Src0Literal) {
4006 Imm = Src0->getImm();
4007 DefMI = nullptr;
4008 }
4009 if (pseudoToMCOpcode(NewOpc) != -1 &&
4011 MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
4012 Src1)) {
4013 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
4014 .add(*Dst)
4015 .add(*Src1)
4016 .addImm(Imm)
4017 .add(*Src2)
4018 .setMIFlags(MI.getFlags());
4019 updateLiveVariables(LV, MI, *MIB);
4020 if (LIS)
4021 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
4022 if (DefMI)
4023 killDef();
4024 return MIB;
4025 }
4026 }
4027 }
4028
4029 // VOP2 mac/fmac with a literal operand cannot be converted to VOP3 mad/fma
4030 // if VOP3 does not allow a literal operand.
4031 if (Src0Literal && !ST.hasVOP3Literal())
4032 return nullptr;
4033
4034 unsigned NewOpc = IsFMA ? IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
4035 : IsF64 ? AMDGPU::V_FMA_F64_e64
4036 : IsLegacy
4037 ? AMDGPU::V_FMA_LEGACY_F32_e64
4038 : AMDGPU::V_FMA_F32_e64
4039 : IsF16 ? AMDGPU::V_MAD_F16_e64
4040 : IsLegacy ? AMDGPU::V_MAD_LEGACY_F32_e64
4041 : AMDGPU::V_MAD_F32_e64;
4042 if (pseudoToMCOpcode(NewOpc) == -1)
4043 return nullptr;
4044
4045 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
4046 .add(*Dst)
4047 .addImm(Src0Mods ? Src0Mods->getImm() : 0)
4048 .add(*Src0)
4049 .addImm(Src1Mods ? Src1Mods->getImm() : 0)
4050 .add(*Src1)
4051 .addImm(Src2Mods ? Src2Mods->getImm() : 0)
4052 .add(*Src2)
4053 .addImm(Clamp ? Clamp->getImm() : 0)
4054 .addImm(Omod ? Omod->getImm() : 0)
4055 .setMIFlags(MI.getFlags());
4056 if (AMDGPU::hasNamedOperand(NewOpc, AMDGPU::OpName::op_sel))
4057 MIB.addImm(OpSel ? OpSel->getImm() : 0);
4058 updateLiveVariables(LV, MI, *MIB);
4059 if (LIS)
4060 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
4061 return MIB;
4062}
4063
4064// It's not generally safe to move VALU instructions across these since it will
4065// start using the register as a base index rather than directly.
4066// XXX - Why isn't hasSideEffects sufficient for these?
4068 switch (MI.getOpcode()) {
4069 case AMDGPU::S_SET_GPR_IDX_ON:
4070 case AMDGPU::S_SET_GPR_IDX_MODE:
4071 case AMDGPU::S_SET_GPR_IDX_OFF:
4072 return true;
4073 default:
4074 return false;
4075 }
4076}
4077
4079 const MachineBasicBlock *MBB,
4080 const MachineFunction &MF) const {
4081 // Skipping the check for SP writes in the base implementation. The reason it
4082 // was added was apparently due to compile time concerns.
4083 //
4084 // TODO: Do we really want this barrier? It triggers unnecessary hazard nops
4085 // but is probably avoidable.
4086
4087 // Copied from base implementation.
4088 // Terminators and labels can't be scheduled around.
4089 if (MI.isTerminator() || MI.isPosition())
4090 return true;
4091
4092 // INLINEASM_BR can jump to another block
4093 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
4094 return true;
4095
4096 if (MI.getOpcode() == AMDGPU::SCHED_BARRIER && MI.getOperand(0).getImm() == 0)
4097 return true;
4098
4099 // Target-independent instructions do not have an implicit-use of EXEC, even
4100 // when they operate on VGPRs. Treating EXEC modifications as scheduling
4101 // boundaries prevents incorrect movements of such instructions.
4102 return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
4103 MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
4104 MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
4105 MI.getOpcode() == AMDGPU::S_SETPRIO ||
4107}
4108
4110 return Opcode == AMDGPU::DS_ORDERED_COUNT || isGWS(Opcode);
4111}
4112
4114 // Skip the full operand and register alias search modifiesRegister
4115 // does. There's only a handful of instructions that touch this, it's only an
4116 // implicit def, and doesn't alias any other registers.
4117 return is_contained(MI.getDesc().implicit_defs(), AMDGPU::MODE);
4118}
4119
4121 unsigned Opcode = MI.getOpcode();
4122
4123 if (MI.mayStore() && isSMRD(MI))
4124 return true; // scalar store or atomic
4125
4126 // This will terminate the function when other lanes may need to continue.
4127 if (MI.isReturn())
4128 return true;
4129
4130 // These instructions cause shader I/O that may cause hardware lockups
4131 // when executed with an empty EXEC mask.
4132 //
4133 // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
4134 // EXEC = 0, but checking for that case here seems not worth it
4135 // given the typical code patterns.
4136 if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
4137 isEXP(Opcode) ||
4138 Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
4139 Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
4140 return true;
4141
4142 if (MI.isCall() || MI.isInlineAsm())
4143 return true; // conservative assumption
4144
4145 // A mode change is a scalar operation that influences vector instructions.
4147 return true;
4148
4149 // These are like SALU instructions in terms of effects, so it's questionable
4150 // whether we should return true for those.
4151 //
4152 // However, executing them with EXEC = 0 causes them to operate on undefined
4153 // data, which we avoid by returning true here.
4154 if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
4155 Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32 ||
4156 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
4157 Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR)
4158 return true;
4159
4160 return false;
4161}
4162
4164 const MachineInstr &MI) const {
4165 if (MI.isMetaInstruction())
4166 return false;
4167
4168 // This won't read exec if this is an SGPR->SGPR copy.
4169 if (MI.isCopyLike()) {
4170 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
4171 return true;
4172
4173 // Make sure this isn't copying exec as a normal operand
4174 return MI.readsRegister(AMDGPU::EXEC, &RI);
4175 }
4176
4177 // Make a conservative assumption about the callee.
4178 if (MI.isCall())
4179 return true;
4180
4181 // Be conservative with any unhandled generic opcodes.
4182 if (!isTargetSpecificOpcode(MI.getOpcode()))
4183 return true;
4184
4185 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
4186}
4187
4188bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
4189 switch (Imm.getBitWidth()) {
4190 case 1: // This likely will be a condition code mask.
4191 return true;
4192
4193 case 32:
4194 return AMDGPU::isInlinableLiteral32(Imm.getSExtValue(),
4195 ST.hasInv2PiInlineImm());
4196 case 64:
4197 return AMDGPU::isInlinableLiteral64(Imm.getSExtValue(),
4198 ST.hasInv2PiInlineImm());
4199 case 16:
4200 return ST.has16BitInsts() &&
4201 AMDGPU::isInlinableLiteralI16(Imm.getSExtValue(),
4202 ST.hasInv2PiInlineImm());
4203 default:
4204 llvm_unreachable("invalid bitwidth");
4205 }
4206}
4207
4209 APInt IntImm = Imm.bitcastToAPInt();
4210 int64_t IntImmVal = IntImm.getSExtValue();
4211 bool HasInv2Pi = ST.hasInv2PiInlineImm();
4212 switch (APFloat::SemanticsToEnum(Imm.getSemantics())) {
4213 default:
4214 llvm_unreachable("invalid fltSemantics");
4217 return isInlineConstant(IntImm);
4219 return ST.has16BitInsts() &&
4220 AMDGPU::isInlinableLiteralBF16(IntImmVal, HasInv2Pi);
4222 return ST.has16BitInsts() &&
4223 AMDGPU::isInlinableLiteralFP16(IntImmVal, HasInv2Pi);
4224 }
4225}
4226
4228 uint8_t OperandType) const {
4229 assert(!MO.isReg() && "isInlineConstant called on register operand!");
4230 if (!MO.isImm())
4231 return false;
4232
4233 // MachineOperand provides no way to tell the true operand size, since it only
4234 // records a 64-bit value. We need to know the size to determine if a 32-bit
4235 // floating point immediate bit pattern is legal for an integer immediate. It
4236 // would be for any 32-bit integer operand, but would not be for a 64-bit one.
4237
4238 int64_t Imm = MO.getImm();
4239 switch (OperandType) {
4252 int32_t Trunc = static_cast<int32_t>(Imm);
4254 }
4261 ST.hasInv2PiInlineImm());
4265 // We would expect inline immediates to not be concerned with an integer/fp
4266 // distinction. However, in the case of 16-bit integer operations, the
4267 // "floating point" values appear to not work. It seems read the low 16-bits
4268 // of 32-bit immediates, which happens to always work for the integer
4269 // values.
4270 //
4271 // See llvm bugzilla 46302.
4272 //
4273 // TODO: Theoretically we could use op-sel to use the high bits of the
4274 // 32-bit FP values.
4292 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
4293 // A few special case instructions have 16-bit operands on subtargets
4294 // where 16-bit instructions are not legal.
4295 // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
4296 // constants in these cases
4297 int16_t Trunc = static_cast<int16_t>(Imm);
4298 return ST.has16BitInsts() &&
4300 }
4301
4302 return false;
4303 }
4308 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
4309 int16_t Trunc = static_cast<int16_t>(Imm);
4310 return ST.has16BitInsts() &&
4312 }
4313 return false;
4314 }
4317 return false;
4320 // Always embedded in the instruction for free.
4321 return true;
4331 // Just ignore anything else.
4332 return true;
4333 default:
4334 llvm_unreachable("invalid operand type");
4335 }
4336}
4337
4338static bool compareMachineOp(const MachineOperand &Op0,
4339 const MachineOperand &Op1) {
4340 if (Op0.getType() != Op1.getType())
4341 return false;
4342
4343 switch (Op0.getType()) {
4345 return Op0.getReg() == Op1.getReg();
4347 return Op0.getImm() == Op1.getImm();
4348 default:
4349 llvm_unreachable("Didn't expect to be comparing these operand types");
4350 }
4351}
4352
4354 const MachineOperand &MO) const {
4355 const MCInstrDesc &InstDesc = MI.getDesc();
4356 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
4357
4358 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
4359
4361 return true;
4362
4363 if (OpInfo.RegClass < 0)
4364 return false;
4365
4366 if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
4367 if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
4368 OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
4369 AMDGPU::OpName::src2))
4370 return false;
4371 return RI.opCanUseInlineConstant(OpInfo.OperandType);
4372 }
4373
4374 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
4375 return false;
4376
4377 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
4378 return true;
4379
4380 return ST.hasVOP3Literal();
4381}
4382
4383bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
4384 // GFX90A does not have V_MUL_LEGACY_F32_e32.
4385 if (Opcode == AMDGPU::V_MUL_LEGACY_F32_e64 && ST.hasGFX90AInsts())
4386 return false;
4387
4388 int Op32 = AMDGPU::getVOPe32(Opcode);
4389 if (Op32 == -1)
4390 return false;
4391
4392 return pseudoToMCOpcode(Op32) != -1;
4393}
4394
4395bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
4396 // The src0_modifier operand is present on all instructions
4397 // that have modifiers.
4398
4399 return AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers);
4400}
4401
4403 unsigned OpName) const {
4404 const MachineOperand *Mods = getNamedOperand(MI, OpName);
4405 return Mods && Mods->getImm();
4406}
4407
4409 return any_of(ModifierOpNames,
4410 [&](unsigned Name) { return hasModifiersSet(MI, Name); });
4411}
4412
4414 const MachineRegisterInfo &MRI) const {
4415 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4416 // Can't shrink instruction with three operands.
4417 if (Src2) {
4418 switch (MI.getOpcode()) {
4419 default: return false;
4420
4421 case AMDGPU::V_ADDC_U32_e64:
4422 case AMDGPU::V_SUBB_U32_e64:
4423 case AMDGPU::V_SUBBREV_U32_e64: {
4424 const MachineOperand *Src1
4425 = getNamedOperand(MI, AMDGPU::OpName::src1);
4426 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
4427 return false;
4428 // Additional verification is needed for sdst/src2.
4429 return true;
4430 }
4431 case AMDGPU::V_MAC_F16_e64:
4432 case AMDGPU::V_MAC_F32_e64:
4433 case AMDGPU::V_MAC_LEGACY_F32_e64:
4434 case AMDGPU::V_FMAC_F16_e64:
4435 case AMDGPU::V_FMAC_F16_t16_e64:
4436 case AMDGPU::V_FMAC_F32_e64:
4437 case AMDGPU::V_FMAC_F64_e64:
4438 case AMDGPU::V_FMAC_LEGACY_F32_e64:
4439 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
4440 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
4441 return false;
4442 break;
4443
4444 case AMDGPU::V_CNDMASK_B32_e64:
4445 break;
4446 }
4447 }
4448
4449 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
4450 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
4451 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
4452 return false;
4453
4454 // We don't need to check src0, all input types are legal, so just make sure
4455 // src0 isn't using any modifiers.
4456 if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
4457 return false;
4458
4459 // Can it be shrunk to a valid 32 bit opcode?
4460 if (!hasVALU32BitEncoding(MI.getOpcode()))
4461 return false;
4462
4463 // Check output modifiers
4464 return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
4465 !hasModifiersSet(MI, AMDGPU::OpName::clamp) &&
4466 !hasModifiersSet(MI, AMDGPU::OpName::byte_sel);
4467}
4468
4469// Set VCC operand with all flags from \p Orig, except for setting it as
4470// implicit.
4472 const MachineOperand &Orig) {
4473
4474 for (MachineOperand &Use : MI.implicit_operands()) {
4475 if (Use.isUse() &&
4476 (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
4477 Use.setIsUndef(Orig.isUndef());
4478 Use.setIsKill(Orig.isKill());
4479 return;
4480 }
4481 }
4482}
4483
4485 unsigned Op32) const {
4486 MachineBasicBlock *MBB = MI.getParent();
4487
4488 const MCInstrDesc &Op32Desc = get(Op32);
4489 MachineInstrBuilder Inst32 =
4490 BuildMI(*MBB, MI, MI.getDebugLoc(), Op32Desc)
4491 .setMIFlags(MI.getFlags());
4492
4493 // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
4494 // For VOPC instructions, this is replaced by an implicit def of vcc.
4495
4496 // We assume the defs of the shrunk opcode are in the same order, and the
4497 // shrunk opcode loses the last def (SGPR def, in the VOP3->VOPC case).
4498 for (int I = 0, E = Op32Desc.getNumDefs(); I != E; ++I)
4499 Inst32.add(MI.getOperand(I));
4500
4501 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4502
4503 int Idx = MI.getNumExplicitDefs();
4504 for (const MachineOperand &Use : MI.explicit_uses()) {
4505 int OpTy = MI.getDesc().operands()[Idx++].OperandType;
4507 continue;
4508
4509 if (&Use == Src2) {
4510 if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2) == -1) {
4511 // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
4512 // replaced with an implicit read of vcc or vcc_lo. The implicit read
4513 // of vcc was already added during the initial BuildMI, but we
4514 // 1) may need to change vcc to vcc_lo to preserve the original register
4515 // 2) have to preserve the original flags.
4516 fixImplicitOperands(*Inst32);
4517 copyFlagsToImplicitVCC(*Inst32, *Src2);
4518 continue;
4519 }
4520 }
4521
4522 Inst32.add(Use);
4523 }
4524
4525 // FIXME: Losing implicit operands
4526
4527 return Inst32;
4528}
4529
4531 const MachineOperand &MO,
4532 const MCOperandInfo &OpInfo) const {
4533 // Literal constants use the constant bus.
4534 if (!MO.isReg())
4535 return !isInlineConstant(MO, OpInfo);
4536
4537 if (!MO.isUse())
4538 return false;
4539
4540 if (MO.getReg().isVirtual())
4541 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
4542
4543 // Null is free
4544 if (MO.getReg() == AMDGPU::SGPR_NULL || MO.getReg() == AMDGPU::SGPR_NULL64)
4545 return false;
4546
4547 // SGPRs use the constant bus
4548 if (MO.isImplicit()) {
4549 return MO.getReg() == AMDGPU::M0 ||
4550 MO.getReg() == AMDGPU::VCC ||
4551 MO.getReg() == AMDGPU::VCC_LO;
4552 } else {
4553 return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
4554 AMDGPU::SReg_64RegClass.contains(MO.getReg());
4555 }
4556}
4557
4559 for (const MachineOperand &MO : MI.implicit_operands()) {
4560 // We only care about reads.
4561 if (MO.isDef())
4562 continue;
4563
4564 switch (MO.getReg()) {
4565 case AMDGPU::VCC:
4566 case AMDGPU::VCC_LO:
4567 case AMDGPU::VCC_HI:
4568 case AMDGPU::M0:
4569 case AMDGPU::FLAT_SCR:
4570 return MO.getReg();
4571
4572 default:
4573 break;
4574 }
4575 }
4576
4577 return Register();
4578}
4579
4580static bool shouldReadExec(const MachineInstr &MI) {
4581 if (SIInstrInfo::isVALU(MI)) {
4582 switch (MI.getOpcode()) {
4583 case AMDGPU::V_READLANE_B32:
4584 case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
4585 case AMDGPU::V_WRITELANE_B32:
4586 case AMDGPU::SI_SPILL_S32_TO_VGPR:
4587 return false;
4588 }
4589
4590 return true;
4591 }
4592
4593 if (MI.isPreISelOpcode() ||
4594 SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
4597 return false;
4598
4599 return true;
4600}
4601
4602static bool isSubRegOf(const SIRegisterInfo &TRI,
4603 const MachineOperand &SuperVec,
4604 const MachineOperand &SubReg) {
4605 if (SubReg.getReg().isPhysical())
4606 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
4607
4608 return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
4609 SubReg.getReg() == SuperVec.getReg();
4610}
4611
4613 StringRef &ErrInfo) const {
4614 uint16_t Opcode = MI.getOpcode();
4615 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
4616 return true;
4617
4618 const MachineFunction *MF = MI.getParent()->getParent();
4619 const MachineRegisterInfo &MRI = MF->getRegInfo();
4620
4621 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
4622 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
4623 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
4624 int Src3Idx = -1;