LLVM 19.0.0git
SIInstrInfo.cpp
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1//===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIInstrInfo.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "GCNHazardRecognizer.h"
18#include "GCNSubtarget.h"
31#include "llvm/IR/IntrinsicsAMDGPU.h"
32#include "llvm/MC/MCContext.h"
35
36using namespace llvm;
37
38#define DEBUG_TYPE "si-instr-info"
39
40#define GET_INSTRINFO_CTOR_DTOR
41#include "AMDGPUGenInstrInfo.inc"
42
43namespace llvm {
44namespace AMDGPU {
45#define GET_D16ImageDimIntrinsics_IMPL
46#define GET_ImageDimIntrinsicTable_IMPL
47#define GET_RsrcIntrinsics_IMPL
48#include "AMDGPUGenSearchableTables.inc"
49}
50}
51
52
53// Must be at least 4 to be able to branch over minimum unconditional branch
54// code. This is only for making it possible to write reasonably small tests for
55// long branches.
57BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
58 cl::desc("Restrict range of branch instructions (DEBUG)"));
59
61 "amdgpu-fix-16-bit-physreg-copies",
62 cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"),
63 cl::init(true),
65
67 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
68 RI(ST), ST(ST) {
69 SchedModel.init(&ST);
70}
71
72//===----------------------------------------------------------------------===//
73// TargetInstrInfo callbacks
74//===----------------------------------------------------------------------===//
75
76static unsigned getNumOperandsNoGlue(SDNode *Node) {
77 unsigned N = Node->getNumOperands();
78 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
79 --N;
80 return N;
81}
82
83/// Returns true if both nodes have the same value for the given
84/// operand \p Op, or if both nodes do not have this operand.
85static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
86 unsigned Opc0 = N0->getMachineOpcode();
87 unsigned Opc1 = N1->getMachineOpcode();
88
89 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
90 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
91
92 if (Op0Idx == -1 && Op1Idx == -1)
93 return true;
94
95
96 if ((Op0Idx == -1 && Op1Idx != -1) ||
97 (Op1Idx == -1 && Op0Idx != -1))
98 return false;
99
100 // getNamedOperandIdx returns the index for the MachineInstr's operands,
101 // which includes the result as the first operand. We are indexing into the
102 // MachineSDNode's operands, so we need to skip the result operand to get
103 // the real index.
104 --Op0Idx;
105 --Op1Idx;
106
107 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
108}
109
110static bool canRemat(const MachineInstr &MI) {
111
115 return true;
116
117 if (SIInstrInfo::isSMRD(MI)) {
118 return !MI.memoperands_empty() &&
119 llvm::all_of(MI.memoperands(), [](const MachineMemOperand *MMO) {
120 return MMO->isLoad() && MMO->isInvariant();
121 });
122 }
123
124 return false;
125}
126
128 const MachineInstr &MI) const {
129
130 if (canRemat(MI)) {
131 // Normally VALU use of exec would block the rematerialization, but that
132 // is OK in this case to have an implicit exec read as all VALU do.
133 // We really want all of the generic logic for this except for this.
134
135 // Another potential implicit use is mode register. The core logic of
136 // the RA will not attempt rematerialization if mode is set anywhere
137 // in the function, otherwise it is safe since mode is not changed.
138
139 // There is difference to generic method which does not allow
140 // rematerialization if there are virtual register uses. We allow this,
141 // therefore this method includes SOP instructions as well.
142 if (!MI.hasImplicitDef() &&
143 MI.getNumImplicitOperands() == MI.getDesc().implicit_uses().size() &&
144 !MI.mayRaiseFPException())
145 return true;
146 }
147
149}
150
151// Returns true if the scalar result of a VALU instruction depends on exec.
153 // Ignore comparisons which are only used masked with exec.
154 // This allows some hoisting/sinking of VALU comparisons.
155 if (MI.isCompare()) {
156 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
157 Register DstReg = MI.getOperand(0).getReg();
158 if (!DstReg.isVirtual())
159 return true;
160 for (MachineInstr &Use : MRI.use_nodbg_instructions(DstReg)) {
161 switch (Use.getOpcode()) {
162 case AMDGPU::S_AND_SAVEEXEC_B32:
163 case AMDGPU::S_AND_SAVEEXEC_B64:
164 break;
165 case AMDGPU::S_AND_B32:
166 case AMDGPU::S_AND_B64:
167 if (!Use.readsRegister(AMDGPU::EXEC))
168 return true;
169 break;
170 default:
171 return true;
172 }
173 }
174 return false;
175 }
176
177 switch (MI.getOpcode()) {
178 default:
179 break;
180 case AMDGPU::V_READFIRSTLANE_B32:
181 return true;
182 }
183
184 return false;
185}
186
188 // Any implicit use of exec by VALU is not a real register read.
189 return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
191}
192
194 MachineBasicBlock *SuccToSinkTo,
195 MachineCycleInfo *CI) const {
196 // Allow sinking if MI edits lane mask (divergent i1 in sgpr).
197 if (MI.getOpcode() == AMDGPU::SI_IF_BREAK)
198 return true;
199
200 MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
201 // Check if sinking of MI would create temporal divergent use.
202 for (auto Op : MI.uses()) {
203 if (Op.isReg() && Op.getReg().isVirtual() &&
204 RI.isSGPRClass(MRI.getRegClass(Op.getReg()))) {
205 MachineInstr *SgprDef = MRI.getVRegDef(Op.getReg());
206
207 // SgprDef defined inside cycle
208 MachineCycle *FromCycle = CI->getCycle(SgprDef->getParent());
209 if (FromCycle == nullptr)
210 continue;
211
212 MachineCycle *ToCycle = CI->getCycle(SuccToSinkTo);
213 // Check if there is a FromCycle that contains SgprDef's basic block but
214 // does not contain SuccToSinkTo and also has divergent exit condition.
215 while (FromCycle && !FromCycle->contains(ToCycle)) {
216 // After structurize-cfg, there should be exactly one cycle exit.
218 FromCycle->getExitBlocks(ExitBlocks);
219 assert(ExitBlocks.size() == 1);
220 assert(ExitBlocks[0]->getSinglePredecessor());
221
222 // FromCycle has divergent exit condition.
223 if (hasDivergentBranch(ExitBlocks[0]->getSinglePredecessor())) {
224 return false;
225 }
226
227 FromCycle = FromCycle->getParentCycle();
228 }
229 }
230 }
231
232 return true;
233}
234
236 int64_t &Offset0,
237 int64_t &Offset1) const {
238 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
239 return false;
240
241 unsigned Opc0 = Load0->getMachineOpcode();
242 unsigned Opc1 = Load1->getMachineOpcode();
243
244 // Make sure both are actually loads.
245 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
246 return false;
247
248 // A mayLoad instruction without a def is not a load. Likely a prefetch.
249 if (!get(Opc0).getNumDefs() || !get(Opc1).getNumDefs())
250 return false;
251
252 if (isDS(Opc0) && isDS(Opc1)) {
253
254 // FIXME: Handle this case:
255 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
256 return false;
257
258 // Check base reg.
259 if (Load0->getOperand(0) != Load1->getOperand(0))
260 return false;
261
262 // Skip read2 / write2 variants for simplicity.
263 // TODO: We should report true if the used offsets are adjacent (excluded
264 // st64 versions).
265 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
266 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
267 if (Offset0Idx == -1 || Offset1Idx == -1)
268 return false;
269
270 // XXX - be careful of dataless loads
271 // getNamedOperandIdx returns the index for MachineInstrs. Since they
272 // include the output in the operand list, but SDNodes don't, we need to
273 // subtract the index by one.
274 Offset0Idx -= get(Opc0).NumDefs;
275 Offset1Idx -= get(Opc1).NumDefs;
276 Offset0 = Load0->getConstantOperandVal(Offset0Idx);
277 Offset1 = Load1->getConstantOperandVal(Offset1Idx);
278 return true;
279 }
280
281 if (isSMRD(Opc0) && isSMRD(Opc1)) {
282 // Skip time and cache invalidation instructions.
283 if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) ||
284 !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase))
285 return false;
286
287 unsigned NumOps = getNumOperandsNoGlue(Load0);
288 if (NumOps != getNumOperandsNoGlue(Load1))
289 return false;
290
291 // Check base reg.
292 if (Load0->getOperand(0) != Load1->getOperand(0))
293 return false;
294
295 // Match register offsets, if both register and immediate offsets present.
296 assert(NumOps == 4 || NumOps == 5);
297 if (NumOps == 5 && Load0->getOperand(1) != Load1->getOperand(1))
298 return false;
299
300 const ConstantSDNode *Load0Offset =
301 dyn_cast<ConstantSDNode>(Load0->getOperand(NumOps - 3));
302 const ConstantSDNode *Load1Offset =
303 dyn_cast<ConstantSDNode>(Load1->getOperand(NumOps - 3));
304
305 if (!Load0Offset || !Load1Offset)
306 return false;
307
308 Offset0 = Load0Offset->getZExtValue();
309 Offset1 = Load1Offset->getZExtValue();
310 return true;
311 }
312
313 // MUBUF and MTBUF can access the same addresses.
314 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
315
316 // MUBUF and MTBUF have vaddr at different indices.
317 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
318 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
319 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
320 return false;
321
322 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
323 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
324
325 if (OffIdx0 == -1 || OffIdx1 == -1)
326 return false;
327
328 // getNamedOperandIdx returns the index for MachineInstrs. Since they
329 // include the output in the operand list, but SDNodes don't, we need to
330 // subtract the index by one.
331 OffIdx0 -= get(Opc0).NumDefs;
332 OffIdx1 -= get(Opc1).NumDefs;
333
334 SDValue Off0 = Load0->getOperand(OffIdx0);
335 SDValue Off1 = Load1->getOperand(OffIdx1);
336
337 // The offset might be a FrameIndexSDNode.
338 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
339 return false;
340
341 Offset0 = Off0->getAsZExtVal();
342 Offset1 = Off1->getAsZExtVal();
343 return true;
344 }
345
346 return false;
347}
348
349static bool isStride64(unsigned Opc) {
350 switch (Opc) {
351 case AMDGPU::DS_READ2ST64_B32:
352 case AMDGPU::DS_READ2ST64_B64:
353 case AMDGPU::DS_WRITE2ST64_B32:
354 case AMDGPU::DS_WRITE2ST64_B64:
355 return true;
356 default:
357 return false;
358 }
359}
360
363 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
364 const TargetRegisterInfo *TRI) const {
365 if (!LdSt.mayLoadOrStore())
366 return false;
367
368 unsigned Opc = LdSt.getOpcode();
369 OffsetIsScalable = false;
370 const MachineOperand *BaseOp, *OffsetOp;
371 int DataOpIdx;
372
373 if (isDS(LdSt)) {
374 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
375 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
376 if (OffsetOp) {
377 // Normal, single offset LDS instruction.
378 if (!BaseOp) {
379 // DS_CONSUME/DS_APPEND use M0 for the base address.
380 // TODO: find the implicit use operand for M0 and use that as BaseOp?
381 return false;
382 }
383 BaseOps.push_back(BaseOp);
384 Offset = OffsetOp->getImm();
385 // Get appropriate operand, and compute width accordingly.
386 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
387 if (DataOpIdx == -1)
388 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
389 Width = getOpSize(LdSt, DataOpIdx);
390 } else {
391 // The 2 offset instructions use offset0 and offset1 instead. We can treat
392 // these as a load with a single offset if the 2 offsets are consecutive.
393 // We will use this for some partially aligned loads.
394 const MachineOperand *Offset0Op =
395 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
396 const MachineOperand *Offset1Op =
397 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
398
399 unsigned Offset0 = Offset0Op->getImm() & 0xff;
400 unsigned Offset1 = Offset1Op->getImm() & 0xff;
401 if (Offset0 + 1 != Offset1)
402 return false;
403
404 // Each of these offsets is in element sized units, so we need to convert
405 // to bytes of the individual reads.
406
407 unsigned EltSize;
408 if (LdSt.mayLoad())
409 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
410 else {
411 assert(LdSt.mayStore());
412 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
413 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
414 }
415
416 if (isStride64(Opc))
417 EltSize *= 64;
418
419 BaseOps.push_back(BaseOp);
420 Offset = EltSize * Offset0;
421 // Get appropriate operand(s), and compute width accordingly.
422 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
423 if (DataOpIdx == -1) {
424 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
425 Width = getOpSize(LdSt, DataOpIdx);
426 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
427 Width += getOpSize(LdSt, DataOpIdx);
428 } else {
429 Width = getOpSize(LdSt, DataOpIdx);
430 }
431 }
432 return true;
433 }
434
435 if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
436 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
437 if (!RSrc) // e.g. BUFFER_WBINVL1_VOL
438 return false;
439 BaseOps.push_back(RSrc);
440 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
441 if (BaseOp && !BaseOp->isFI())
442 BaseOps.push_back(BaseOp);
443 const MachineOperand *OffsetImm =
444 getNamedOperand(LdSt, AMDGPU::OpName::offset);
445 Offset = OffsetImm->getImm();
446 const MachineOperand *SOffset =
447 getNamedOperand(LdSt, AMDGPU::OpName::soffset);
448 if (SOffset) {
449 if (SOffset->isReg())
450 BaseOps.push_back(SOffset);
451 else
452 Offset += SOffset->getImm();
453 }
454 // Get appropriate operand, and compute width accordingly.
455 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
456 if (DataOpIdx == -1)
457 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
458 if (DataOpIdx == -1) // LDS DMA
459 return false;
460 Width = getOpSize(LdSt, DataOpIdx);
461 return true;
462 }
463
464 if (isMIMG(LdSt)) {
465 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
466 BaseOps.push_back(&LdSt.getOperand(SRsrcIdx));
467 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
468 if (VAddr0Idx >= 0) {
469 // GFX10 possible NSA encoding.
470 for (int I = VAddr0Idx; I < SRsrcIdx; ++I)
471 BaseOps.push_back(&LdSt.getOperand(I));
472 } else {
473 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr));
474 }
475 Offset = 0;
476 // Get appropriate operand, and compute width accordingly.
477 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
478 Width = getOpSize(LdSt, DataOpIdx);
479 return true;
480 }
481
482 if (isSMRD(LdSt)) {
483 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
484 if (!BaseOp) // e.g. S_MEMTIME
485 return false;
486 BaseOps.push_back(BaseOp);
487 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
488 Offset = OffsetOp ? OffsetOp->getImm() : 0;
489 // Get appropriate operand, and compute width accordingly.
490 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
491 if (DataOpIdx == -1)
492 return false;
493 Width = getOpSize(LdSt, DataOpIdx);
494 return true;
495 }
496
497 if (isFLAT(LdSt)) {
498 // Instructions have either vaddr or saddr or both or none.
499 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
500 if (BaseOp)
501 BaseOps.push_back(BaseOp);
502 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
503 if (BaseOp)
504 BaseOps.push_back(BaseOp);
505 Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
506 // Get appropriate operand, and compute width accordingly.
507 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
508 if (DataOpIdx == -1)
509 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
510 if (DataOpIdx == -1) // LDS DMA
511 return false;
512 Width = getOpSize(LdSt, DataOpIdx);
513 return true;
514 }
515
516 return false;
517}
518
519static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
521 const MachineInstr &MI2,
523 // Only examine the first "base" operand of each instruction, on the
524 // assumption that it represents the real base address of the memory access.
525 // Other operands are typically offsets or indices from this base address.
526 if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front()))
527 return true;
528
529 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
530 return false;
531
532 auto MO1 = *MI1.memoperands_begin();
533 auto MO2 = *MI2.memoperands_begin();
534 if (MO1->getAddrSpace() != MO2->getAddrSpace())
535 return false;
536
537 auto Base1 = MO1->getValue();
538 auto Base2 = MO2->getValue();
539 if (!Base1 || !Base2)
540 return false;
541 Base1 = getUnderlyingObject(Base1);
542 Base2 = getUnderlyingObject(Base2);
543
544 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
545 return false;
546
547 return Base1 == Base2;
548}
549
551 int64_t Offset1, bool OffsetIsScalable1,
553 int64_t Offset2, bool OffsetIsScalable2,
554 unsigned ClusterSize,
555 unsigned NumBytes) const {
556 // If the mem ops (to be clustered) do not have the same base ptr, then they
557 // should not be clustered
558 if (!BaseOps1.empty() && !BaseOps2.empty()) {
559 const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
560 const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
561 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
562 return false;
563 } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
564 // If only one base op is empty, they do not have the same base ptr
565 return false;
566 }
567
568 // In order to avoid register pressure, on an average, the number of DWORDS
569 // loaded together by all clustered mem ops should not exceed 8. This is an
570 // empirical value based on certain observations and performance related
571 // experiments.
572 // The good thing about this heuristic is - it avoids clustering of too many
573 // sub-word loads, and also avoids clustering of wide loads. Below is the
574 // brief summary of how the heuristic behaves for various `LoadSize`.
575 // (1) 1 <= LoadSize <= 4: cluster at max 8 mem ops
576 // (2) 5 <= LoadSize <= 8: cluster at max 4 mem ops
577 // (3) 9 <= LoadSize <= 12: cluster at max 2 mem ops
578 // (4) 13 <= LoadSize <= 16: cluster at max 2 mem ops
579 // (5) LoadSize >= 17: do not cluster
580 const unsigned LoadSize = NumBytes / ClusterSize;
581 const unsigned NumDWORDs = ((LoadSize + 3) / 4) * ClusterSize;
582 return NumDWORDs <= 8;
583}
584
585// FIXME: This behaves strangely. If, for example, you have 32 load + stores,
586// the first 16 loads will be interleaved with the stores, and the next 16 will
587// be clustered as expected. It should really split into 2 16 store batches.
588//
589// Loads are clustered until this returns false, rather than trying to schedule
590// groups of stores. This also means we have to deal with saying different
591// address space loads should be clustered, and ones which might cause bank
592// conflicts.
593//
594// This might be deprecated so it might not be worth that much effort to fix.
596 int64_t Offset0, int64_t Offset1,
597 unsigned NumLoads) const {
598 assert(Offset1 > Offset0 &&
599 "Second offset should be larger than first offset!");
600 // If we have less than 16 loads in a row, and the offsets are within 64
601 // bytes, then schedule together.
602
603 // A cacheline is 64 bytes (for global memory).
604 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
605}
606
609 const DebugLoc &DL, MCRegister DestReg,
610 MCRegister SrcReg, bool KillSrc,
611 const char *Msg = "illegal VGPR to SGPR copy") {
613 DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(), Msg, DL, DS_Error);
615 C.diagnose(IllegalCopy);
616
617 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
618 .addReg(SrcReg, getKillRegState(KillSrc));
619}
620
621/// Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. It is not
622/// possible to have a direct copy in these cases on GFX908, so an intermediate
623/// VGPR copy is required.
627 const DebugLoc &DL, MCRegister DestReg,
628 MCRegister SrcReg, bool KillSrc,
629 RegScavenger &RS, bool RegsOverlap,
630 Register ImpDefSuperReg = Register(),
631 Register ImpUseSuperReg = Register()) {
632 assert((TII.getSubtarget().hasMAIInsts() &&
633 !TII.getSubtarget().hasGFX90AInsts()) &&
634 "Expected GFX908 subtarget.");
635
636 assert((AMDGPU::SReg_32RegClass.contains(SrcReg) ||
637 AMDGPU::AGPR_32RegClass.contains(SrcReg)) &&
638 "Source register of the copy should be either an SGPR or an AGPR.");
639
640 assert(AMDGPU::AGPR_32RegClass.contains(DestReg) &&
641 "Destination register of the copy should be an AGPR.");
642
643 const SIRegisterInfo &RI = TII.getRegisterInfo();
644
645 // First try to find defining accvgpr_write to avoid temporary registers.
646 // In the case of copies of overlapping AGPRs, we conservatively do not
647 // reuse previous accvgpr_writes. Otherwise, we may incorrectly pick up
648 // an accvgpr_write used for this same copy due to implicit-defs
649 if (!RegsOverlap) {
650 for (auto Def = MI, E = MBB.begin(); Def != E; ) {
651 --Def;
652
653 if (!Def->modifiesRegister(SrcReg, &RI))
654 continue;
655
656 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
657 Def->getOperand(0).getReg() != SrcReg)
658 break;
659
660 MachineOperand &DefOp = Def->getOperand(1);
661 assert(DefOp.isReg() || DefOp.isImm());
662
663 if (DefOp.isReg()) {
664 bool SafeToPropagate = true;
665 // Check that register source operand is not clobbered before MI.
666 // Immediate operands are always safe to propagate.
667 for (auto I = Def; I != MI && SafeToPropagate; ++I)
668 if (I->modifiesRegister(DefOp.getReg(), &RI))
669 SafeToPropagate = false;
670
671 if (!SafeToPropagate)
672 break;
673
674 DefOp.setIsKill(false);
675 }
676
677 MachineInstrBuilder Builder =
678 BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
679 .add(DefOp);
680 if (ImpDefSuperReg)
681 Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
682
683 if (ImpUseSuperReg) {
684 Builder.addReg(ImpUseSuperReg,
686 }
687
688 return;
689 }
690 }
691
693 RS.backward(std::next(MI));
694
695 // Ideally we want to have three registers for a long reg_sequence copy
696 // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
697 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
698 *MBB.getParent());
699
700 // Registers in the sequence are allocated contiguously so we can just
701 // use register number to pick one of three round-robin temps.
702 unsigned RegNo = (DestReg - AMDGPU::AGPR0) % 3;
703 Register Tmp =
704 MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getVGPRForAGPRCopy();
706 "VGPR used for an intermediate copy should have been reserved.");
707
708 // Only loop through if there are any free registers left. We don't want to
709 // spill.
710 while (RegNo--) {
711 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI,
712 /* RestoreAfter */ false, 0,
713 /* AllowSpill */ false);
714 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
715 break;
716 Tmp = Tmp2;
717 RS.setRegUsed(Tmp);
718 }
719
720 // Insert copy to temporary VGPR.
721 unsigned TmpCopyOp = AMDGPU::V_MOV_B32_e32;
722 if (AMDGPU::AGPR_32RegClass.contains(SrcReg)) {
723 TmpCopyOp = AMDGPU::V_ACCVGPR_READ_B32_e64;
724 } else {
725 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
726 }
727
728 MachineInstrBuilder UseBuilder = BuildMI(MBB, MI, DL, TII.get(TmpCopyOp), Tmp)
729 .addReg(SrcReg, getKillRegState(KillSrc));
730 if (ImpUseSuperReg) {
731 UseBuilder.addReg(ImpUseSuperReg,
733 }
734
735 MachineInstrBuilder DefBuilder
736 = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
737 .addReg(Tmp, RegState::Kill);
738
739 if (ImpDefSuperReg)
740 DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
741}
742
745 MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
746 const TargetRegisterClass *RC, bool Forward) {
747 const SIRegisterInfo &RI = TII.getRegisterInfo();
748 ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4);
750 MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
751
752 for (unsigned Idx = 0; Idx < BaseIndices.size(); ++Idx) {
753 int16_t SubIdx = BaseIndices[Idx];
754 Register DestSubReg = RI.getSubReg(DestReg, SubIdx);
755 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
756 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
757 unsigned Opcode = AMDGPU::S_MOV_B32;
758
759 // Is SGPR aligned? If so try to combine with next.
760 bool AlignedDest = ((DestSubReg - AMDGPU::SGPR0) % 2) == 0;
761 bool AlignedSrc = ((SrcSubReg - AMDGPU::SGPR0) % 2) == 0;
762 if (AlignedDest && AlignedSrc && (Idx + 1 < BaseIndices.size())) {
763 // Can use SGPR64 copy
764 unsigned Channel = RI.getChannelFromSubReg(SubIdx);
765 SubIdx = RI.getSubRegFromChannel(Channel, 2);
766 DestSubReg = RI.getSubReg(DestReg, SubIdx);
767 SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
768 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
769 Opcode = AMDGPU::S_MOV_B64;
770 Idx++;
771 }
772
773 LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), DestSubReg)
774 .addReg(SrcSubReg)
775 .addReg(SrcReg, RegState::Implicit);
776
777 if (!FirstMI)
778 FirstMI = LastMI;
779
780 if (!Forward)
781 I--;
782 }
783
784 assert(FirstMI && LastMI);
785 if (!Forward)
786 std::swap(FirstMI, LastMI);
787
788 FirstMI->addOperand(
789 MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
790
791 if (KillSrc)
792 LastMI->addRegisterKilled(SrcReg, &RI);
793}
794
797 const DebugLoc &DL, MCRegister DestReg,
798 MCRegister SrcReg, bool KillSrc) const {
799 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
800 unsigned Size = RI.getRegSizeInBits(*RC);
801 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
802 unsigned SrcSize = RI.getRegSizeInBits(*SrcRC);
803
804 // The rest of copyPhysReg assumes Src and Dst size are the same size.
805 // TODO-GFX11_16BIT If all true 16 bit instruction patterns are completed can
806 // we remove Fix16BitCopies and this code block?
807 if (Fix16BitCopies) {
808 if (((Size == 16) != (SrcSize == 16))) {
809 // Non-VGPR Src and Dst will later be expanded back to 32 bits.
811 MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
812 MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
813 RegToFix = SubReg;
814
815 if (DestReg == SrcReg) {
816 // Identity copy. Insert empty bundle since ExpandPostRA expects an
817 // instruction here.
818 BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
819 return;
820 }
821 RC = RI.getPhysRegBaseClass(DestReg);
822 Size = RI.getRegSizeInBits(*RC);
823 SrcRC = RI.getPhysRegBaseClass(SrcReg);
824 SrcSize = RI.getRegSizeInBits(*SrcRC);
825 }
826 }
827
828 if (RC == &AMDGPU::VGPR_32RegClass) {
829 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
830 AMDGPU::SReg_32RegClass.contains(SrcReg) ||
831 AMDGPU::AGPR_32RegClass.contains(SrcReg));
832 unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
833 AMDGPU::V_ACCVGPR_READ_B32_e64 : AMDGPU::V_MOV_B32_e32;
834 BuildMI(MBB, MI, DL, get(Opc), DestReg)
835 .addReg(SrcReg, getKillRegState(KillSrc));
836 return;
837 }
838
839 if (RC == &AMDGPU::SReg_32_XM0RegClass ||
840 RC == &AMDGPU::SReg_32RegClass) {
841 if (SrcReg == AMDGPU::SCC) {
842 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
843 .addImm(1)
844 .addImm(0);
845 return;
846 }
847
848 if (DestReg == AMDGPU::VCC_LO) {
849 if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
850 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
851 .addReg(SrcReg, getKillRegState(KillSrc));
852 } else {
853 // FIXME: Hack until VReg_1 removed.
854 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
855 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
856 .addImm(0)
857 .addReg(SrcReg, getKillRegState(KillSrc));
858 }
859
860 return;
861 }
862
863 if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
864 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
865 return;
866 }
867
868 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
869 .addReg(SrcReg, getKillRegState(KillSrc));
870 return;
871 }
872
873 if (RC == &AMDGPU::SReg_64RegClass) {
874 if (SrcReg == AMDGPU::SCC) {
875 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg)
876 .addImm(1)
877 .addImm(0);
878 return;
879 }
880
881 if (DestReg == AMDGPU::VCC) {
882 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
883 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
884 .addReg(SrcReg, getKillRegState(KillSrc));
885 } else {
886 // FIXME: Hack until VReg_1 removed.
887 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
888 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
889 .addImm(0)
890 .addReg(SrcReg, getKillRegState(KillSrc));
891 }
892
893 return;
894 }
895
896 if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
897 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
898 return;
899 }
900
901 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
902 .addReg(SrcReg, getKillRegState(KillSrc));
903 return;
904 }
905
906 if (DestReg == AMDGPU::SCC) {
907 // Copying 64-bit or 32-bit sources to SCC barely makes sense,
908 // but SelectionDAG emits such copies for i1 sources.
909 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
910 // This copy can only be produced by patterns
911 // with explicit SCC, which are known to be enabled
912 // only for subtargets with S_CMP_LG_U64 present.
914 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U64))
915 .addReg(SrcReg, getKillRegState(KillSrc))
916 .addImm(0);
917 } else {
918 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
919 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
920 .addReg(SrcReg, getKillRegState(KillSrc))
921 .addImm(0);
922 }
923
924 return;
925 }
926
927 if (RC == &AMDGPU::AGPR_32RegClass) {
928 if (AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
929 (ST.hasGFX90AInsts() && AMDGPU::SReg_32RegClass.contains(SrcReg))) {
930 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
931 .addReg(SrcReg, getKillRegState(KillSrc));
932 return;
933 }
934
935 if (AMDGPU::AGPR_32RegClass.contains(SrcReg) && ST.hasGFX90AInsts()) {
936 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_MOV_B32), DestReg)
937 .addReg(SrcReg, getKillRegState(KillSrc));
938 return;
939 }
940
941 // FIXME: Pass should maintain scavenger to avoid scan through the block on
942 // every AGPR spill.
943 RegScavenger RS;
944 const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
945 indirectCopyToAGPR(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RS, Overlap);
946 return;
947 }
948
949 if (Size == 16) {
950 assert(AMDGPU::VGPR_16RegClass.contains(SrcReg) ||
951 AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
952 AMDGPU::AGPR_LO16RegClass.contains(SrcReg));
953
954 bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
955 bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
956 bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
957 bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
958 bool DstLow = !AMDGPU::isHi(DestReg, RI);
959 bool SrcLow = !AMDGPU::isHi(SrcReg, RI);
960 MCRegister NewDestReg = RI.get32BitRegister(DestReg);
961 MCRegister NewSrcReg = RI.get32BitRegister(SrcReg);
962
963 if (IsSGPRDst) {
964 if (!IsSGPRSrc) {
965 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
966 return;
967 }
968
969 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
970 .addReg(NewSrcReg, getKillRegState(KillSrc));
971 return;
972 }
973
974 if (IsAGPRDst || IsAGPRSrc) {
975 if (!DstLow || !SrcLow) {
976 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
977 "Cannot use hi16 subreg with an AGPR!");
978 }
979
980 copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
981 return;
982 }
983
984 if (ST.hasTrue16BitInsts()) {
985 if (IsSGPRSrc) {
986 assert(SrcLow);
987 SrcReg = NewSrcReg;
988 }
989 // Use the smaller instruction encoding if possible.
990 if (AMDGPU::VGPR_16_Lo128RegClass.contains(DestReg) &&
991 (IsSGPRSrc || AMDGPU::VGPR_16_Lo128RegClass.contains(SrcReg))) {
992 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B16_t16_e32), DestReg)
993 .addReg(SrcReg);
994 } else {
995 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B16_t16_e64), DestReg)
996 .addImm(0) // src0_modifiers
997 .addReg(SrcReg)
998 .addImm(0); // op_sel
999 }
1000 return;
1001 }
1002
1003 if (IsSGPRSrc && !ST.hasSDWAScalar()) {
1004 if (!DstLow || !SrcLow) {
1005 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
1006 "Cannot use hi16 subreg on VI!");
1007 }
1008
1009 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
1010 .addReg(NewSrcReg, getKillRegState(KillSrc));
1011 return;
1012 }
1013
1014 auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
1015 .addImm(0) // src0_modifiers
1016 .addReg(NewSrcReg)
1017 .addImm(0) // clamp
1024 // First implicit operand is $exec.
1025 MIB->tieOperands(0, MIB->getNumOperands() - 1);
1026 return;
1027 }
1028
1029 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
1030 if (ST.hasMovB64()) {
1031 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_e32), DestReg)
1032 .addReg(SrcReg, getKillRegState(KillSrc));
1033 return;
1034 }
1035 if (ST.hasPkMovB32()) {
1036 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestReg)
1038 .addReg(SrcReg)
1040 .addReg(SrcReg)
1041 .addImm(0) // op_sel_lo
1042 .addImm(0) // op_sel_hi
1043 .addImm(0) // neg_lo
1044 .addImm(0) // neg_hi
1045 .addImm(0) // clamp
1046 .addReg(SrcReg, getKillRegState(KillSrc) | RegState::Implicit);
1047 return;
1048 }
1049 }
1050
1051 const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
1052 if (RI.isSGPRClass(RC)) {
1053 if (!RI.isSGPRClass(SrcRC)) {
1054 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
1055 return;
1056 }
1057 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg);
1058 expandSGPRCopy(*this, MBB, MI, DL, DestReg, SrcReg, CanKillSuperReg, RC,
1059 Forward);
1060 return;
1061 }
1062
1063 unsigned EltSize = 4;
1064 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1065 if (RI.isAGPRClass(RC)) {
1066 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC))
1067 Opcode = AMDGPU::V_ACCVGPR_MOV_B32;
1068 else if (RI.hasVGPRs(SrcRC) ||
1069 (ST.hasGFX90AInsts() && RI.isSGPRClass(SrcRC)))
1070 Opcode = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
1071 else
1072 Opcode = AMDGPU::INSTRUCTION_LIST_END;
1073 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) {
1074 Opcode = AMDGPU::V_ACCVGPR_READ_B32_e64;
1075 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) &&
1076 (RI.isProperlyAlignedRC(*RC) &&
1077 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
1078 // TODO: In 96-bit case, could do a 64-bit mov and then a 32-bit mov.
1079 if (ST.hasMovB64()) {
1080 Opcode = AMDGPU::V_MOV_B64_e32;
1081 EltSize = 8;
1082 } else if (ST.hasPkMovB32()) {
1083 Opcode = AMDGPU::V_PK_MOV_B32;
1084 EltSize = 8;
1085 }
1086 }
1087
1088 // For the cases where we need an intermediate instruction/temporary register
1089 // (destination is an AGPR), we need a scavenger.
1090 //
1091 // FIXME: The pass should maintain this for us so we don't have to re-scan the
1092 // whole block for every handled copy.
1093 std::unique_ptr<RegScavenger> RS;
1094 if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
1095 RS.reset(new RegScavenger());
1096
1097 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
1098
1099 // If there is an overlap, we can't kill the super-register on the last
1100 // instruction, since it will also kill the components made live by this def.
1101 const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
1102 const bool CanKillSuperReg = KillSrc && !Overlap;
1103
1104 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1105 unsigned SubIdx;
1106 if (Forward)
1107 SubIdx = SubIndices[Idx];
1108 else
1109 SubIdx = SubIndices[SubIndices.size() - Idx - 1];
1110 Register DestSubReg = RI.getSubReg(DestReg, SubIdx);
1111 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
1112 assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
1113
1114 bool IsFirstSubreg = Idx == 0;
1115 bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
1116
1117 if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
1118 Register ImpDefSuper = IsFirstSubreg ? Register(DestReg) : Register();
1119 Register ImpUseSuper = SrcReg;
1120 indirectCopyToAGPR(*this, MBB, MI, DL, DestSubReg, SrcSubReg, UseKill,
1121 *RS, Overlap, ImpDefSuper, ImpUseSuper);
1122 } else if (Opcode == AMDGPU::V_PK_MOV_B32) {
1124 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
1126 .addReg(SrcSubReg)
1128 .addReg(SrcSubReg)
1129 .addImm(0) // op_sel_lo
1130 .addImm(0) // op_sel_hi
1131 .addImm(0) // neg_lo
1132 .addImm(0) // neg_hi
1133 .addImm(0) // clamp
1134 .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
1135 if (IsFirstSubreg)
1137 } else {
1138 MachineInstrBuilder Builder =
1139 BuildMI(MBB, MI, DL, get(Opcode), DestSubReg).addReg(SrcSubReg);
1140 if (IsFirstSubreg)
1141 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
1142
1143 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
1144 }
1145 }
1146}
1147
1148int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
1149 int NewOpc;
1150
1151 // Try to map original to commuted opcode
1152 NewOpc = AMDGPU::getCommuteRev(Opcode);
1153 if (NewOpc != -1)
1154 // Check if the commuted (REV) opcode exists on the target.
1155 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1156
1157 // Try to map commuted to original opcode
1158 NewOpc = AMDGPU::getCommuteOrig(Opcode);
1159 if (NewOpc != -1)
1160 // Check if the original (non-REV) opcode exists on the target.
1161 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1162
1163 return Opcode;
1164}
1165
1168 const DebugLoc &DL, Register DestReg,
1169 int64_t Value) const {
1171 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1172 if (RegClass == &AMDGPU::SReg_32RegClass ||
1173 RegClass == &AMDGPU::SGPR_32RegClass ||
1174 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
1175 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
1176 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
1177 .addImm(Value);
1178 return;
1179 }
1180
1181 if (RegClass == &AMDGPU::SReg_64RegClass ||
1182 RegClass == &AMDGPU::SGPR_64RegClass ||
1183 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
1184 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
1185 .addImm(Value);
1186 return;
1187 }
1188
1189 if (RegClass == &AMDGPU::VGPR_32RegClass) {
1190 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
1191 .addImm(Value);
1192 return;
1193 }
1194 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {
1195 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
1196 .addImm(Value);
1197 return;
1198 }
1199
1200 unsigned EltSize = 4;
1201 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1202 if (RI.isSGPRClass(RegClass)) {
1203 if (RI.getRegSizeInBits(*RegClass) > 32) {
1204 Opcode = AMDGPU::S_MOV_B64;
1205 EltSize = 8;
1206 } else {
1207 Opcode = AMDGPU::S_MOV_B32;
1208 EltSize = 4;
1209 }
1210 }
1211
1212 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
1213 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1214 int64_t IdxValue = Idx == 0 ? Value : 0;
1215
1216 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
1217 get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx]));
1218 Builder.addImm(IdxValue);
1219 }
1220}
1221
1222const TargetRegisterClass *
1224 return &AMDGPU::VGPR_32RegClass;
1225}
1226
1229 const DebugLoc &DL, Register DstReg,
1231 Register TrueReg,
1232 Register FalseReg) const {
1234 const TargetRegisterClass *BoolXExecRC =
1235 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
1236 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
1237 "Not a VGPR32 reg");
1238
1239 if (Cond.size() == 1) {
1240 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1241 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1242 .add(Cond[0]);
1243 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1244 .addImm(0)
1245 .addReg(FalseReg)
1246 .addImm(0)
1247 .addReg(TrueReg)
1248 .addReg(SReg);
1249 } else if (Cond.size() == 2) {
1250 assert(Cond[0].isImm() && "Cond[0] is not an immediate");
1251 switch (Cond[0].getImm()) {
1252 case SIInstrInfo::SCC_TRUE: {
1253 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1254 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1255 : AMDGPU::S_CSELECT_B64), SReg)
1256 .addImm(1)
1257 .addImm(0);
1258 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1259 .addImm(0)
1260 .addReg(FalseReg)
1261 .addImm(0)
1262 .addReg(TrueReg)
1263 .addReg(SReg);
1264 break;
1265 }
1266 case SIInstrInfo::SCC_FALSE: {
1267 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1268 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1269 : AMDGPU::S_CSELECT_B64), SReg)
1270 .addImm(0)
1271 .addImm(1);
1272 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1273 .addImm(0)
1274 .addReg(FalseReg)
1275 .addImm(0)
1276 .addReg(TrueReg)
1277 .addReg(SReg);
1278 break;
1279 }
1280 case SIInstrInfo::VCCNZ: {
1281 MachineOperand RegOp = Cond[1];
1282 RegOp.setImplicit(false);
1283 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1284 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1285 .add(RegOp);
1286 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1287 .addImm(0)
1288 .addReg(FalseReg)
1289 .addImm(0)
1290 .addReg(TrueReg)
1291 .addReg(SReg);
1292 break;
1293 }
1294 case SIInstrInfo::VCCZ: {
1295 MachineOperand RegOp = Cond[1];
1296 RegOp.setImplicit(false);
1297 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1298 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1299 .add(RegOp);
1300 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1301 .addImm(0)
1302 .addReg(TrueReg)
1303 .addImm(0)
1304 .addReg(FalseReg)
1305 .addReg(SReg);
1306 break;
1307 }
1308 case SIInstrInfo::EXECNZ: {
1309 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1310 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
1311 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1312 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1313 .addImm(0);
1314 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1315 : AMDGPU::S_CSELECT_B64), SReg)
1316 .addImm(1)
1317 .addImm(0);
1318 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1319 .addImm(0)
1320 .addReg(FalseReg)
1321 .addImm(0)
1322 .addReg(TrueReg)
1323 .addReg(SReg);
1324 break;
1325 }
1326 case SIInstrInfo::EXECZ: {
1327 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1328 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
1329 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1330 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1331 .addImm(0);
1332 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1333 : AMDGPU::S_CSELECT_B64), SReg)
1334 .addImm(0)
1335 .addImm(1);
1336 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1337 .addImm(0)
1338 .addReg(FalseReg)
1339 .addImm(0)
1340 .addReg(TrueReg)
1341 .addReg(SReg);
1342 llvm_unreachable("Unhandled branch predicate EXECZ");
1343 break;
1344 }
1345 default:
1346 llvm_unreachable("invalid branch predicate");
1347 }
1348 } else {
1349 llvm_unreachable("Can only handle Cond size 1 or 2");
1350 }
1351}
1352
1355 const DebugLoc &DL,
1356 Register SrcReg, int Value) const {
1358 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1359 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
1360 .addImm(Value)
1361 .addReg(SrcReg);
1362
1363 return Reg;
1364}
1365
1368 const DebugLoc &DL,
1369 Register SrcReg, int Value) const {
1371 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1372 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1373 .addImm(Value)
1374 .addReg(SrcReg);
1375
1376 return Reg;
1377}
1378
1380
1381 if (RI.isAGPRClass(DstRC))
1382 return AMDGPU::COPY;
1383 if (RI.getRegSizeInBits(*DstRC) == 16) {
1384 // Assume hi bits are unneeded. Only _e64 true16 instructions are legal
1385 // before RA.
1386 return RI.isSGPRClass(DstRC) ? AMDGPU::COPY : AMDGPU::V_MOV_B16_t16_e64;
1387 } else if (RI.getRegSizeInBits(*DstRC) == 32) {
1388 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1389 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1390 return AMDGPU::S_MOV_B64;
1391 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
1392 return AMDGPU::V_MOV_B64_PSEUDO;
1393 }
1394 return AMDGPU::COPY;
1395}
1396
1397const MCInstrDesc &
1399 bool IsIndirectSrc) const {
1400 if (IsIndirectSrc) {
1401 if (VecSize <= 32) // 4 bytes
1402 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1);
1403 if (VecSize <= 64) // 8 bytes
1404 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2);
1405 if (VecSize <= 96) // 12 bytes
1406 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3);
1407 if (VecSize <= 128) // 16 bytes
1408 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4);
1409 if (VecSize <= 160) // 20 bytes
1410 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5);
1411 if (VecSize <= 256) // 32 bytes
1412 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8);
1413 if (VecSize <= 288) // 36 bytes
1414 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V9);
1415 if (VecSize <= 320) // 40 bytes
1416 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V10);
1417 if (VecSize <= 352) // 44 bytes
1418 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V11);
1419 if (VecSize <= 384) // 48 bytes
1420 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V12);
1421 if (VecSize <= 512) // 64 bytes
1422 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16);
1423 if (VecSize <= 1024) // 128 bytes
1424 return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32);
1425
1426 llvm_unreachable("unsupported size for IndirectRegReadGPRIDX pseudos");
1427 }
1428
1429 if (VecSize <= 32) // 4 bytes
1430 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1);
1431 if (VecSize <= 64) // 8 bytes
1432 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2);
1433 if (VecSize <= 96) // 12 bytes
1434 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3);
1435 if (VecSize <= 128) // 16 bytes
1436 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4);
1437 if (VecSize <= 160) // 20 bytes
1438 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5);
1439 if (VecSize <= 256) // 32 bytes
1440 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8);
1441 if (VecSize <= 288) // 36 bytes
1442 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9);
1443 if (VecSize <= 320) // 40 bytes
1444 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10);
1445 if (VecSize <= 352) // 44 bytes
1446 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V11);
1447 if (VecSize <= 384) // 48 bytes
1448 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V12);
1449 if (VecSize <= 512) // 64 bytes
1450 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16);
1451 if (VecSize <= 1024) // 128 bytes
1452 return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32);
1453
1454 llvm_unreachable("unsupported size for IndirectRegWriteGPRIDX pseudos");
1455}
1456
1457static unsigned getIndirectVGPRWriteMovRelPseudoOpc(unsigned VecSize) {
1458 if (VecSize <= 32) // 4 bytes
1459 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1460 if (VecSize <= 64) // 8 bytes
1461 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1462 if (VecSize <= 96) // 12 bytes
1463 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1464 if (VecSize <= 128) // 16 bytes
1465 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1466 if (VecSize <= 160) // 20 bytes
1467 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1468 if (VecSize <= 256) // 32 bytes
1469 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1470 if (VecSize <= 288) // 36 bytes
1471 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V9;
1472 if (VecSize <= 320) // 40 bytes
1473 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V10;
1474 if (VecSize <= 352) // 44 bytes
1475 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V11;
1476 if (VecSize <= 384) // 48 bytes
1477 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V12;
1478 if (VecSize <= 512) // 64 bytes
1479 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1480 if (VecSize <= 1024) // 128 bytes
1481 return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1482
1483 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1484}
1485
1486static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
1487 if (VecSize <= 32) // 4 bytes
1488 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1489 if (VecSize <= 64) // 8 bytes
1490 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1491 if (VecSize <= 96) // 12 bytes
1492 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1493 if (VecSize <= 128) // 16 bytes
1494 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1495 if (VecSize <= 160) // 20 bytes
1496 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1497 if (VecSize <= 256) // 32 bytes
1498 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1499 if (VecSize <= 288) // 36 bytes
1500 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9;
1501 if (VecSize <= 320) // 40 bytes
1502 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10;
1503 if (VecSize <= 352) // 44 bytes
1504 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11;
1505 if (VecSize <= 384) // 48 bytes
1506 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12;
1507 if (VecSize <= 512) // 64 bytes
1508 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1509 if (VecSize <= 1024) // 128 bytes
1510 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1511
1512 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1513}
1514
1515static unsigned getIndirectSGPRWriteMovRelPseudo64(unsigned VecSize) {
1516 if (VecSize <= 64) // 8 bytes
1517 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1;
1518 if (VecSize <= 128) // 16 bytes
1519 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2;
1520 if (VecSize <= 256) // 32 bytes
1521 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4;
1522 if (VecSize <= 512) // 64 bytes
1523 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8;
1524 if (VecSize <= 1024) // 128 bytes
1525 return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16;
1526
1527 llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1528}
1529
1530const MCInstrDesc &
1531SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,
1532 bool IsSGPR) const {
1533 if (IsSGPR) {
1534 switch (EltSize) {
1535 case 32:
1536 return get(getIndirectSGPRWriteMovRelPseudo32(VecSize));
1537 case 64:
1538 return get(getIndirectSGPRWriteMovRelPseudo64(VecSize));
1539 default:
1540 llvm_unreachable("invalid reg indexing elt size");
1541 }
1542 }
1543
1544 assert(EltSize == 32 && "invalid reg indexing elt size");
1546}
1547
1548static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
1549 switch (Size) {
1550 case 4:
1551 return AMDGPU::SI_SPILL_S32_SAVE;
1552 case 8:
1553 return AMDGPU::SI_SPILL_S64_SAVE;
1554 case 12:
1555 return AMDGPU::SI_SPILL_S96_SAVE;
1556 case 16:
1557 return AMDGPU::SI_SPILL_S128_SAVE;
1558 case 20:
1559 return AMDGPU::SI_SPILL_S160_SAVE;
1560 case 24:
1561 return AMDGPU::SI_SPILL_S192_SAVE;
1562 case 28:
1563 return AMDGPU::SI_SPILL_S224_SAVE;
1564 case 32:
1565 return AMDGPU::SI_SPILL_S256_SAVE;
1566 case 36:
1567 return AMDGPU::SI_SPILL_S288_SAVE;
1568 case 40:
1569 return AMDGPU::SI_SPILL_S320_SAVE;
1570 case 44:
1571 return AMDGPU::SI_SPILL_S352_SAVE;
1572 case 48:
1573 return AMDGPU::SI_SPILL_S384_SAVE;
1574 case 64:
1575 return AMDGPU::SI_SPILL_S512_SAVE;
1576 case 128:
1577 return AMDGPU::SI_SPILL_S1024_SAVE;
1578 default:
1579 llvm_unreachable("unknown register size");
1580 }
1581}
1582
1583static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
1584 switch (Size) {
1585 case 4:
1586 return AMDGPU::SI_SPILL_V32_SAVE;
1587 case 8:
1588 return AMDGPU::SI_SPILL_V64_SAVE;
1589 case 12:
1590 return AMDGPU::SI_SPILL_V96_SAVE;
1591 case 16:
1592 return AMDGPU::SI_SPILL_V128_SAVE;
1593 case 20:
1594 return AMDGPU::SI_SPILL_V160_SAVE;
1595 case 24:
1596 return AMDGPU::SI_SPILL_V192_SAVE;
1597 case 28:
1598 return AMDGPU::SI_SPILL_V224_SAVE;
1599 case 32:
1600 return AMDGPU::SI_SPILL_V256_SAVE;
1601 case 36:
1602 return AMDGPU::SI_SPILL_V288_SAVE;
1603 case 40:
1604 return AMDGPU::SI_SPILL_V320_SAVE;
1605 case 44:
1606 return AMDGPU::SI_SPILL_V352_SAVE;
1607 case 48:
1608 return AMDGPU::SI_SPILL_V384_SAVE;
1609 case 64:
1610 return AMDGPU::SI_SPILL_V512_SAVE;
1611 case 128:
1612 return AMDGPU::SI_SPILL_V1024_SAVE;
1613 default:
1614 llvm_unreachable("unknown register size");
1615 }
1616}
1617
1618static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
1619 switch (Size) {
1620 case 4:
1621 return AMDGPU::SI_SPILL_A32_SAVE;
1622 case 8:
1623 return AMDGPU::SI_SPILL_A64_SAVE;
1624 case 12:
1625 return AMDGPU::SI_SPILL_A96_SAVE;
1626 case 16:
1627 return AMDGPU::SI_SPILL_A128_SAVE;
1628 case 20:
1629 return AMDGPU::SI_SPILL_A160_SAVE;
1630 case 24:
1631 return AMDGPU::SI_SPILL_A192_SAVE;
1632 case 28:
1633 return AMDGPU::SI_SPILL_A224_SAVE;
1634 case 32:
1635 return AMDGPU::SI_SPILL_A256_SAVE;
1636 case 36:
1637 return AMDGPU::SI_SPILL_A288_SAVE;
1638 case 40:
1639 return AMDGPU::SI_SPILL_A320_SAVE;
1640 case 44:
1641 return AMDGPU::SI_SPILL_A352_SAVE;
1642 case 48:
1643 return AMDGPU::SI_SPILL_A384_SAVE;
1644 case 64:
1645 return AMDGPU::SI_SPILL_A512_SAVE;
1646 case 128:
1647 return AMDGPU::SI_SPILL_A1024_SAVE;
1648 default:
1649 llvm_unreachable("unknown register size");
1650 }
1651}
1652
1653static unsigned getAVSpillSaveOpcode(unsigned Size) {
1654 switch (Size) {
1655 case 4:
1656 return AMDGPU::SI_SPILL_AV32_SAVE;
1657 case 8:
1658 return AMDGPU::SI_SPILL_AV64_SAVE;
1659 case 12:
1660 return AMDGPU::SI_SPILL_AV96_SAVE;
1661 case 16:
1662 return AMDGPU::SI_SPILL_AV128_SAVE;
1663 case 20:
1664 return AMDGPU::SI_SPILL_AV160_SAVE;
1665 case 24:
1666 return AMDGPU::SI_SPILL_AV192_SAVE;
1667 case 28:
1668 return AMDGPU::SI_SPILL_AV224_SAVE;
1669 case 32:
1670 return AMDGPU::SI_SPILL_AV256_SAVE;
1671 case 36:
1672 return AMDGPU::SI_SPILL_AV288_SAVE;
1673 case 40:
1674 return AMDGPU::SI_SPILL_AV320_SAVE;
1675 case 44:
1676 return AMDGPU::SI_SPILL_AV352_SAVE;
1677 case 48:
1678 return AMDGPU::SI_SPILL_AV384_SAVE;
1679 case 64:
1680 return AMDGPU::SI_SPILL_AV512_SAVE;
1681 case 128:
1682 return AMDGPU::SI_SPILL_AV1024_SAVE;
1683 default:
1684 llvm_unreachable("unknown register size");
1685 }
1686}
1687
1688static unsigned getWWMRegSpillSaveOpcode(unsigned Size,
1689 bool IsVectorSuperClass) {
1690 // Currently, there is only 32-bit WWM register spills needed.
1691 if (Size != 4)
1692 llvm_unreachable("unknown wwm register spill size");
1693
1694 if (IsVectorSuperClass)
1695 return AMDGPU::SI_SPILL_WWM_AV32_SAVE;
1696
1697 return AMDGPU::SI_SPILL_WWM_V32_SAVE;
1698}
1699
1701 const TargetRegisterClass *RC,
1702 unsigned Size,
1703 const SIRegisterInfo &TRI,
1704 const SIMachineFunctionInfo &MFI) {
1705 bool IsVectorSuperClass = TRI.isVectorSuperClass(RC);
1706
1707 // Choose the right opcode if spilling a WWM register.
1709 return getWWMRegSpillSaveOpcode(Size, IsVectorSuperClass);
1710
1711 if (IsVectorSuperClass)
1712 return getAVSpillSaveOpcode(Size);
1713
1714 return TRI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(Size)
1716}
1717
1720 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1721 const TargetRegisterInfo *TRI, Register VReg) const {
1724 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1725 const DebugLoc &DL = MBB.findDebugLoc(MI);
1726
1727 MachinePointerInfo PtrInfo
1728 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1730 PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
1731 FrameInfo.getObjectAlign(FrameIndex));
1732 unsigned SpillSize = TRI->getSpillSize(*RC);
1733
1735 if (RI.isSGPRClass(RC)) {
1736 MFI->setHasSpilledSGPRs();
1737 assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled");
1738 assert(SrcReg != AMDGPU::EXEC_LO && SrcReg != AMDGPU::EXEC_HI &&
1739 SrcReg != AMDGPU::EXEC && "exec should not be spilled");
1740
1741 // We are only allowed to create one new instruction when spilling
1742 // registers, so we need to use pseudo instruction for spilling SGPRs.
1743 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1744
1745 // The SGPR spill/restore instructions only work on number sgprs, so we need
1746 // to make sure we are using the correct register class.
1747 if (SrcReg.isVirtual() && SpillSize == 4) {
1748 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1749 }
1750
1751 BuildMI(MBB, MI, DL, OpDesc)
1752 .addReg(SrcReg, getKillRegState(isKill)) // data
1753 .addFrameIndex(FrameIndex) // addr
1754 .addMemOperand(MMO)
1756
1757 if (RI.spillSGPRToVGPR())
1758 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1759 return;
1760 }
1761
1762 unsigned Opcode = getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC,
1763 SpillSize, RI, *MFI);
1764 MFI->setHasSpilledVGPRs();
1765
1766 BuildMI(MBB, MI, DL, get(Opcode))
1767 .addReg(SrcReg, getKillRegState(isKill)) // data
1768 .addFrameIndex(FrameIndex) // addr
1769 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1770 .addImm(0) // offset
1771 .addMemOperand(MMO);
1772}
1773
1774static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
1775 switch (Size) {
1776 case 4:
1777 return AMDGPU::SI_SPILL_S32_RESTORE;
1778 case 8:
1779 return AMDGPU::SI_SPILL_S64_RESTORE;
1780 case 12:
1781 return AMDGPU::SI_SPILL_S96_RESTORE;
1782 case 16:
1783 return AMDGPU::SI_SPILL_S128_RESTORE;
1784 case 20:
1785 return AMDGPU::SI_SPILL_S160_RESTORE;
1786 case 24:
1787 return AMDGPU::SI_SPILL_S192_RESTORE;
1788 case 28:
1789 return AMDGPU::SI_SPILL_S224_RESTORE;
1790 case 32:
1791 return AMDGPU::SI_SPILL_S256_RESTORE;
1792 case 36:
1793 return AMDGPU::SI_SPILL_S288_RESTORE;
1794 case 40:
1795 return AMDGPU::SI_SPILL_S320_RESTORE;
1796 case 44:
1797 return AMDGPU::SI_SPILL_S352_RESTORE;
1798 case 48:
1799 return AMDGPU::SI_SPILL_S384_RESTORE;
1800 case 64:
1801 return AMDGPU::SI_SPILL_S512_RESTORE;
1802 case 128:
1803 return AMDGPU::SI_SPILL_S1024_RESTORE;
1804 default:
1805 llvm_unreachable("unknown register size");
1806 }
1807}
1808
1809static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
1810 switch (Size) {
1811 case 4:
1812 return AMDGPU::SI_SPILL_V32_RESTORE;
1813 case 8:
1814 return AMDGPU::SI_SPILL_V64_RESTORE;
1815 case 12:
1816 return AMDGPU::SI_SPILL_V96_RESTORE;
1817 case 16:
1818 return AMDGPU::SI_SPILL_V128_RESTORE;
1819 case 20:
1820 return AMDGPU::SI_SPILL_V160_RESTORE;
1821 case 24:
1822 return AMDGPU::SI_SPILL_V192_RESTORE;
1823 case 28:
1824 return AMDGPU::SI_SPILL_V224_RESTORE;
1825 case 32:
1826 return AMDGPU::SI_SPILL_V256_RESTORE;
1827 case 36:
1828 return AMDGPU::SI_SPILL_V288_RESTORE;
1829 case 40:
1830 return AMDGPU::SI_SPILL_V320_RESTORE;
1831 case 44:
1832 return AMDGPU::SI_SPILL_V352_RESTORE;
1833 case 48:
1834 return AMDGPU::SI_SPILL_V384_RESTORE;
1835 case 64:
1836 return AMDGPU::SI_SPILL_V512_RESTORE;
1837 case 128:
1838 return AMDGPU::SI_SPILL_V1024_RESTORE;
1839 default:
1840 llvm_unreachable("unknown register size");
1841 }
1842}
1843
1844static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
1845 switch (Size) {
1846 case 4:
1847 return AMDGPU::SI_SPILL_A32_RESTORE;
1848 case 8:
1849 return AMDGPU::SI_SPILL_A64_RESTORE;
1850 case 12:
1851 return AMDGPU::SI_SPILL_A96_RESTORE;
1852 case 16:
1853 return AMDGPU::SI_SPILL_A128_RESTORE;
1854 case 20:
1855 return AMDGPU::SI_SPILL_A160_RESTORE;
1856 case 24:
1857 return AMDGPU::SI_SPILL_A192_RESTORE;
1858 case 28:
1859 return AMDGPU::SI_SPILL_A224_RESTORE;
1860 case 32:
1861 return AMDGPU::SI_SPILL_A256_RESTORE;
1862 case 36:
1863 return AMDGPU::SI_SPILL_A288_RESTORE;
1864 case 40:
1865 return AMDGPU::SI_SPILL_A320_RESTORE;
1866 case 44:
1867 return AMDGPU::SI_SPILL_A352_RESTORE;
1868 case 48:
1869 return AMDGPU::SI_SPILL_A384_RESTORE;
1870 case 64:
1871 return AMDGPU::SI_SPILL_A512_RESTORE;
1872 case 128:
1873 return AMDGPU::SI_SPILL_A1024_RESTORE;
1874 default:
1875 llvm_unreachable("unknown register size");
1876 }
1877}
1878
1879static unsigned getAVSpillRestoreOpcode(unsigned Size) {
1880 switch (Size) {
1881 case 4:
1882 return AMDGPU::SI_SPILL_AV32_RESTORE;
1883 case 8:
1884 return AMDGPU::SI_SPILL_AV64_RESTORE;
1885 case 12:
1886 return AMDGPU::SI_SPILL_AV96_RESTORE;
1887 case 16:
1888 return AMDGPU::SI_SPILL_AV128_RESTORE;
1889 case 20:
1890 return AMDGPU::SI_SPILL_AV160_RESTORE;
1891 case 24:
1892 return AMDGPU::SI_SPILL_AV192_RESTORE;
1893 case 28:
1894 return AMDGPU::SI_SPILL_AV224_RESTORE;
1895 case 32:
1896 return AMDGPU::SI_SPILL_AV256_RESTORE;
1897 case 36:
1898 return AMDGPU::SI_SPILL_AV288_RESTORE;
1899 case 40:
1900 return AMDGPU::SI_SPILL_AV320_RESTORE;
1901 case 44:
1902 return AMDGPU::SI_SPILL_AV352_RESTORE;
1903 case 48:
1904 return AMDGPU::SI_SPILL_AV384_RESTORE;
1905 case 64:
1906 return AMDGPU::SI_SPILL_AV512_RESTORE;
1907 case 128:
1908 return AMDGPU::SI_SPILL_AV1024_RESTORE;
1909 default:
1910 llvm_unreachable("unknown register size");
1911 }
1912}
1913
1914static unsigned getWWMRegSpillRestoreOpcode(unsigned Size,
1915 bool IsVectorSuperClass) {
1916 // Currently, there is only 32-bit WWM register spills needed.
1917 if (Size != 4)
1918 llvm_unreachable("unknown wwm register spill size");
1919
1920 if (IsVectorSuperClass)
1921 return AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
1922
1923 return AMDGPU::SI_SPILL_WWM_V32_RESTORE;
1924}
1925
1926static unsigned
1928 unsigned Size, const SIRegisterInfo &TRI,
1929 const SIMachineFunctionInfo &MFI) {
1930 bool IsVectorSuperClass = TRI.isVectorSuperClass(RC);
1931
1932 // Choose the right opcode if restoring a WWM register.
1934 return getWWMRegSpillRestoreOpcode(Size, IsVectorSuperClass);
1935
1936 if (IsVectorSuperClass)
1938
1939 return TRI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(Size)
1941}
1942
1945 Register DestReg, int FrameIndex,
1946 const TargetRegisterClass *RC,
1947 const TargetRegisterInfo *TRI,
1948 Register VReg) const {
1951 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1952 const DebugLoc &DL = MBB.findDebugLoc(MI);
1953 unsigned SpillSize = TRI->getSpillSize(*RC);
1954
1955 MachinePointerInfo PtrInfo
1956 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1957
1959 PtrInfo, MachineMemOperand::MOLoad, FrameInfo.getObjectSize(FrameIndex),
1960 FrameInfo.getObjectAlign(FrameIndex));
1961
1962 if (RI.isSGPRClass(RC)) {
1963 MFI->setHasSpilledSGPRs();
1964 assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into");
1965 assert(DestReg != AMDGPU::EXEC_LO && DestReg != AMDGPU::EXEC_HI &&
1966 DestReg != AMDGPU::EXEC && "exec should not be spilled");
1967
1968 // FIXME: Maybe this should not include a memoperand because it will be
1969 // lowered to non-memory instructions.
1970 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1971 if (DestReg.isVirtual() && SpillSize == 4) {
1973 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1974 }
1975
1976 if (RI.spillSGPRToVGPR())
1977 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1978 BuildMI(MBB, MI, DL, OpDesc, DestReg)
1979 .addFrameIndex(FrameIndex) // addr
1980 .addMemOperand(MMO)
1982
1983 return;
1984 }
1985
1986 unsigned Opcode = getVectorRegSpillRestoreOpcode(VReg ? VReg : DestReg, RC,
1987 SpillSize, RI, *MFI);
1988 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1989 .addFrameIndex(FrameIndex) // vaddr
1990 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1991 .addImm(0) // offset
1992 .addMemOperand(MMO);
1993}
1994
1997 insertNoops(MBB, MI, 1);
1998}
1999
2002 unsigned Quantity) const {
2004 while (Quantity > 0) {
2005 unsigned Arg = std::min(Quantity, 8u);
2006 Quantity -= Arg;
2007 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)).addImm(Arg - 1);
2008 }
2009}
2010
2012 auto MF = MBB.getParent();
2014
2015 assert(Info->isEntryFunction());
2016
2017 if (MBB.succ_empty()) {
2018 bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
2019 if (HasNoTerminator) {
2020 if (Info->returnsVoid()) {
2021 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
2022 } else {
2023 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
2024 }
2025 }
2026 }
2027}
2028
2030 switch (MI.getOpcode()) {
2031 default:
2032 if (MI.isMetaInstruction())
2033 return 0;
2034 return 1; // FIXME: Do wait states equal cycles?
2035
2036 case AMDGPU::S_NOP:
2037 return MI.getOperand(0).getImm() + 1;
2038 // SI_RETURN_TO_EPILOG is a fallthrough to code outside of the function. The
2039 // hazard, even if one exist, won't really be visible. Should we handle it?
2040 }
2041}
2042
2044 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2045 MachineBasicBlock &MBB = *MI.getParent();
2047 switch (MI.getOpcode()) {
2048 default: return TargetInstrInfo::expandPostRAPseudo(MI);
2049 case AMDGPU::S_MOV_B64_term:
2050 // This is only a terminator to get the correct spill code placement during
2051 // register allocation.
2052 MI.setDesc(get(AMDGPU::S_MOV_B64));
2053 break;
2054
2055 case AMDGPU::S_MOV_B32_term:
2056 // This is only a terminator to get the correct spill code placement during
2057 // register allocation.
2058 MI.setDesc(get(AMDGPU::S_MOV_B32));
2059 break;
2060
2061 case AMDGPU::S_XOR_B64_term:
2062 // This is only a terminator to get the correct spill code placement during
2063 // register allocation.
2064 MI.setDesc(get(AMDGPU::S_XOR_B64));
2065 break;
2066
2067 case AMDGPU::S_XOR_B32_term:
2068 // This is only a terminator to get the correct spill code placement during
2069 // register allocation.
2070 MI.setDesc(get(AMDGPU::S_XOR_B32));
2071 break;
2072 case AMDGPU::S_OR_B64_term:
2073 // This is only a terminator to get the correct spill code placement during
2074 // register allocation.
2075 MI.setDesc(get(AMDGPU::S_OR_B64));
2076 break;
2077 case AMDGPU::S_OR_B32_term:
2078 // This is only a terminator to get the correct spill code placement during
2079 // register allocation.
2080 MI.setDesc(get(AMDGPU::S_OR_B32));
2081 break;
2082
2083 case AMDGPU::S_ANDN2_B64_term:
2084 // This is only a terminator to get the correct spill code placement during
2085 // register allocation.
2086 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
2087 break;
2088
2089 case AMDGPU::S_ANDN2_B32_term:
2090 // This is only a terminator to get the correct spill code placement during
2091 // register allocation.
2092 MI.setDesc(get(AMDGPU::S_ANDN2_B32));
2093 break;
2094
2095 case AMDGPU::S_AND_B64_term:
2096 // This is only a terminator to get the correct spill code placement during
2097 // register allocation.
2098 MI.setDesc(get(AMDGPU::S_AND_B64));
2099 break;
2100
2101 case AMDGPU::S_AND_B32_term:
2102 // This is only a terminator to get the correct spill code placement during
2103 // register allocation.
2104 MI.setDesc(get(AMDGPU::S_AND_B32));
2105 break;
2106
2107 case AMDGPU::S_AND_SAVEEXEC_B64_term:
2108 // This is only a terminator to get the correct spill code placement during
2109 // register allocation.
2110 MI.setDesc(get(AMDGPU::S_AND_SAVEEXEC_B64));
2111 break;
2112
2113 case AMDGPU::S_AND_SAVEEXEC_B32_term:
2114 // This is only a terminator to get the correct spill code placement during
2115 // register allocation.
2116 MI.setDesc(get(AMDGPU::S_AND_SAVEEXEC_B32));
2117 break;
2118
2119 case AMDGPU::SI_SPILL_S32_TO_VGPR:
2120 MI.setDesc(get(AMDGPU::V_WRITELANE_B32));
2121 break;
2122
2123 case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
2124 MI.setDesc(get(AMDGPU::V_READLANE_B32));
2125 break;
2126
2127 case AMDGPU::V_MOV_B64_PSEUDO: {
2128 Register Dst = MI.getOperand(0).getReg();
2129 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2130 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2131
2132 const MachineOperand &SrcOp = MI.getOperand(1);
2133 // FIXME: Will this work for 64-bit floating point immediates?
2134 assert(!SrcOp.isFPImm());
2135 if (ST.hasMovB64()) {
2136 MI.setDesc(get(AMDGPU::V_MOV_B64_e32));
2137 if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
2138 isUInt<32>(SrcOp.getImm()))
2139 break;
2140 }
2141 if (SrcOp.isImm()) {
2142 APInt Imm(64, SrcOp.getImm());
2143 APInt Lo(32, Imm.getLoBits(32).getZExtValue());
2144 APInt Hi(32, Imm.getHiBits(32).getZExtValue());
2145 if (ST.hasPkMovB32() && Lo == Hi && isInlineConstant(Lo)) {
2146 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
2148 .addImm(Lo.getSExtValue())
2150 .addImm(Lo.getSExtValue())
2151 .addImm(0) // op_sel_lo
2152 .addImm(0) // op_sel_hi
2153 .addImm(0) // neg_lo
2154 .addImm(0) // neg_hi
2155 .addImm(0); // clamp
2156 } else {
2157 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2158 .addImm(Lo.getSExtValue())
2160 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
2161 .addImm(Hi.getSExtValue())
2163 }
2164 } else {
2165 assert(SrcOp.isReg());
2166 if (ST.hasPkMovB32() &&
2167 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
2168 BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
2169 .addImm(SISrcMods::OP_SEL_1) // src0_mod
2170 .addReg(SrcOp.getReg())
2172 .addReg(SrcOp.getReg())
2173 .addImm(0) // op_sel_lo
2174 .addImm(0) // op_sel_hi
2175 .addImm(0) // neg_lo
2176 .addImm(0) // neg_hi
2177 .addImm(0); // clamp
2178 } else {
2179 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
2180 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
2182 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
2183 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
2185 }
2186 }
2187 MI.eraseFromParent();
2188 break;
2189 }
2190 case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
2192 break;
2193 }
2194 case AMDGPU::S_MOV_B64_IMM_PSEUDO: {
2195 const MachineOperand &SrcOp = MI.getOperand(1);
2196 assert(!SrcOp.isFPImm());
2197 APInt Imm(64, SrcOp.getImm());
2198 if (Imm.isIntN(32) || isInlineConstant(Imm)) {
2199 MI.setDesc(get(AMDGPU::S_MOV_B64));
2200 break;
2201 }
2202
2203 Register Dst = MI.getOperand(0).getReg();
2204 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
2205 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2206
2207 APInt Lo(32, Imm.getLoBits(32).getZExtValue());
2208 APInt Hi(32, Imm.getHiBits(32).getZExtValue());
2209 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo)
2210 .addImm(Lo.getSExtValue())
2212 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi)
2213 .addImm(Hi.getSExtValue())
2215 MI.eraseFromParent();
2216 break;
2217 }
2218 case AMDGPU::V_SET_INACTIVE_B32: {
2219 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
2220 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2221 // FIXME: We may possibly optimize the COPY once we find ways to make LLVM
2222 // optimizations (mainly Register Coalescer) aware of WWM register liveness.
2223 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
2224 .add(MI.getOperand(1));
2225 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
2226 FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
2227 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
2228 .add(MI.getOperand(2));
2229 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
2230 .addReg(Exec);
2231 MI.eraseFromParent();
2232 break;
2233 }
2234 case AMDGPU::V_SET_INACTIVE_B64: {
2235 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
2236 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2237 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
2238 MI.getOperand(0).getReg())
2239 .add(MI.getOperand(1));
2240 expandPostRAPseudo(*Copy);
2241 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
2242 FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
2243 Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
2244 MI.getOperand(0).getReg())
2245 .add(MI.getOperand(2));
2246 expandPostRAPseudo(*Copy);
2247 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
2248 .addReg(Exec);
2249 MI.eraseFromParent();
2250 break;
2251 }
2252 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1:
2253 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2:
2254 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3:
2255 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4:
2256 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2257 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8:
2258 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V9:
2259 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V10:
2260 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V11:
2261 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V12:
2262 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16:
2263 case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32:
2264 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1:
2265 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2:
2266 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
2267 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
2268 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2269 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
2270 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9:
2271 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10:
2272 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11:
2273 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12:
2274 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16:
2275 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32:
2276 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1:
2277 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2:
2278 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4:
2279 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8:
2280 case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16: {
2281 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);
2282
2283 unsigned Opc;
2284 if (RI.hasVGPRs(EltRC)) {
2285 Opc = AMDGPU::V_MOVRELD_B32_e32;
2286 } else {
2287 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64
2288 : AMDGPU::S_MOVRELD_B32;
2289 }
2290
2291 const MCInstrDesc &OpDesc = get(Opc);
2292 Register VecReg = MI.getOperand(0).getReg();
2293 bool IsUndef = MI.getOperand(1).isUndef();
2294 unsigned SubReg = MI.getOperand(3).getImm();
2295 assert(VecReg == MI.getOperand(1).getReg());
2296
2298 BuildMI(MBB, MI, DL, OpDesc)
2299 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2300 .add(MI.getOperand(2))
2302 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2303
2304 const int ImpDefIdx =
2305 OpDesc.getNumOperands() + OpDesc.implicit_uses().size();
2306 const int ImpUseIdx = ImpDefIdx + 1;
2307 MIB->tieOperands(ImpDefIdx, ImpUseIdx);
2308 MI.eraseFromParent();
2309 break;
2310 }
2311 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1:
2312 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2:
2313 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3:
2314 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4:
2315 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5:
2316 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8:
2317 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9:
2318 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10:
2319 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V11:
2320 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V12:
2321 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16:
2322 case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32: {
2324 Register VecReg = MI.getOperand(0).getReg();
2325 bool IsUndef = MI.getOperand(1).isUndef();
2326 Register Idx = MI.getOperand(3).getReg();
2327 Register SubReg = MI.getOperand(4).getImm();
2328
2329 MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
2330 .addReg(Idx)
2332 SetOn->getOperand(3).setIsUndef();
2333
2334 const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write);
2336 BuildMI(MBB, MI, DL, OpDesc)
2337 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2338 .add(MI.getOperand(2))
2340 .addReg(VecReg,
2341 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2342
2343 const int ImpDefIdx =
2344 OpDesc.getNumOperands() + OpDesc.implicit_uses().size();
2345 const int ImpUseIdx = ImpDefIdx + 1;
2346 MIB->tieOperands(ImpDefIdx, ImpUseIdx);
2347
2348 MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2349
2350 finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2351
2352 MI.eraseFromParent();
2353 break;
2354 }
2355 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1:
2356 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2:
2357 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3:
2358 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4:
2359 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5:
2360 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8:
2361 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V9:
2362 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V10:
2363 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V11:
2364 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V12:
2365 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16:
2366 case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32: {
2368 Register Dst = MI.getOperand(0).getReg();
2369 Register VecReg = MI.getOperand(1).getReg();
2370 bool IsUndef = MI.getOperand(1).isUndef();
2371 Register Idx = MI.getOperand(2).getReg();
2372 Register SubReg = MI.getOperand(3).getImm();
2373
2374 MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
2375 .addReg(Idx)
2377 SetOn->getOperand(3).setIsUndef();
2378
2379 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read))
2380 .addDef(Dst)
2381 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2382 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2383
2384 MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2385
2386 finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2387
2388 MI.eraseFromParent();
2389 break;
2390 }
2391 case AMDGPU::SI_PC_ADD_REL_OFFSET: {
2392 MachineFunction &MF = *MBB.getParent();
2393 Register Reg = MI.getOperand(0).getReg();
2394 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
2395 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
2396 MachineOperand OpLo = MI.getOperand(1);
2397 MachineOperand OpHi = MI.getOperand(2);
2398
2399 // Create a bundle so these instructions won't be re-ordered by the
2400 // post-RA scheduler.
2401 MIBundleBuilder Bundler(MBB, MI);
2402 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
2403
2404 // What we want here is an offset from the value returned by s_getpc (which
2405 // is the address of the s_add_u32 instruction) to the global variable, but
2406 // since the encoding of $symbol starts 4 bytes after the start of the
2407 // s_add_u32 instruction, we end up with an offset that is 4 bytes too
2408 // small. This requires us to add 4 to the global variable offset in order
2409 // to compute the correct address. Similarly for the s_addc_u32 instruction,
2410 // the encoding of $symbol starts 12 bytes after the start of the s_add_u32
2411 // instruction.
2412
2413 int64_t Adjust = 0;
2414 if (ST.hasGetPCZeroExtension()) {
2415 // Fix up hardware that does not sign-extend the 48-bit PC value by
2416 // inserting: s_sext_i32_i16 reghi, reghi
2417 Bundler.append(
2418 BuildMI(MF, DL, get(AMDGPU::S_SEXT_I32_I16), RegHi).addReg(RegHi));
2419 Adjust += 4;
2420 }
2421
2422 if (OpLo.isGlobal())
2423 OpLo.setOffset(OpLo.getOffset() + Adjust + 4);
2424 Bundler.append(
2425 BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo));
2426
2427 if (OpHi.isGlobal())
2428 OpHi.setOffset(OpHi.getOffset() + Adjust + 12);
2429 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
2430 .addReg(RegHi)
2431 .add(OpHi));
2432
2433 finalizeBundle(MBB, Bundler.begin());
2434
2435 MI.eraseFromParent();
2436 break;
2437 }
2438 case AMDGPU::ENTER_STRICT_WWM: {
2439 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2440 // Whole Wave Mode is entered.
2441 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
2442 : AMDGPU::S_OR_SAVEEXEC_B64));
2443 break;
2444 }
2445 case AMDGPU::ENTER_STRICT_WQM: {
2446 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2447 // STRICT_WQM is entered.
2448 const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2449 const unsigned WQMOp = ST.isWave32() ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64;
2450 const unsigned MovOp = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
2451 BuildMI(MBB, MI, DL, get(MovOp), MI.getOperand(0).getReg()).addReg(Exec);
2452 BuildMI(MBB, MI, DL, get(WQMOp), Exec).addReg(Exec);
2453
2454 MI.eraseFromParent();
2455 break;
2456 }
2457 case AMDGPU::EXIT_STRICT_WWM:
2458 case AMDGPU::EXIT_STRICT_WQM: {
2459 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2460 // WWM/STICT_WQM is exited.
2461 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
2462 break;
2463 }
2464 case AMDGPU::ENTER_PSEUDO_WM:
2465 case AMDGPU::EXIT_PSEUDO_WM: {
2466 // These do nothing.
2467 MI.eraseFromParent();
2468 break;
2469 }
2470 case AMDGPU::SI_RETURN: {
2471 const MachineFunction *MF = MBB.getParent();
2472 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2473 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2474 // Hiding the return address use with SI_RETURN may lead to extra kills in
2475 // the function and missing live-ins. We are fine in practice because callee
2476 // saved register handling ensures the register value is restored before
2477 // RET, but we need the undef flag here to appease the MachineVerifier
2478 // liveness checks.
2480 BuildMI(MBB, MI, DL, get(AMDGPU::S_SETPC_B64_return))
2481 .addReg(TRI->getReturnAddressReg(*MF), RegState::Undef);
2482
2483 MIB.copyImplicitOps(MI);
2484 MI.eraseFromParent();
2485 break;
2486 }
2487
2488 case AMDGPU::S_MUL_U64_U32_PSEUDO:
2489 case AMDGPU::S_MUL_I64_I32_PSEUDO:
2490 MI.setDesc(get(AMDGPU::S_MUL_U64));
2491 break;
2492
2493 case AMDGPU::S_GETPC_B64_pseudo:
2494 MI.setDesc(get(AMDGPU::S_GETPC_B64));
2495 if (ST.hasGetPCZeroExtension()) {
2496 Register Dst = MI.getOperand(0).getReg();
2497 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
2498 // Fix up hardware that does not sign-extend the 48-bit PC value by
2499 // inserting: s_sext_i32_i16 dsthi, dsthi
2500 BuildMI(MBB, std::next(MI.getIterator()), DL, get(AMDGPU::S_SEXT_I32_I16),
2501 DstHi)
2502 .addReg(DstHi);
2503 }
2504 break;
2505 }
2506 return true;
2507}
2508
2511 unsigned SubIdx, const MachineInstr &Orig,
2512 const TargetRegisterInfo &RI) const {
2513
2514 // Try shrinking the instruction to remat only the part needed for current
2515 // context.
2516 // TODO: Handle more cases.
2517 unsigned Opcode = Orig.getOpcode();
2518 switch (Opcode) {
2519 case AMDGPU::S_LOAD_DWORDX16_IMM:
2520 case AMDGPU::S_LOAD_DWORDX8_IMM: {
2521 if (SubIdx != 0)
2522 break;
2523
2524 if (I == MBB.end())
2525 break;
2526
2527 if (I->isBundled())
2528 break;
2529
2530 // Look for a single use of the register that is also a subreg.
2531 Register RegToFind = Orig.getOperand(0).getReg();
2532 MachineOperand *UseMO = nullptr;
2533 for (auto &CandMO : I->operands()) {
2534 if (!CandMO.isReg() || CandMO.getReg() != RegToFind || CandMO.isDef())
2535 continue;
2536 if (UseMO) {
2537 UseMO = nullptr;
2538 break;
2539 }
2540 UseMO = &CandMO;
2541 }
2542 if (!UseMO || UseMO->getSubReg() == AMDGPU::NoSubRegister)
2543 break;
2544
2545 unsigned Offset = RI.getSubRegIdxOffset(UseMO->getSubReg());
2546 unsigned SubregSize = RI.getSubRegIdxSize(UseMO->getSubReg());
2547
2550 assert(MRI.use_nodbg_empty(DestReg) && "DestReg should have no users yet.");
2551
2552 unsigned NewOpcode = -1;
2553 if (SubregSize == 256)
2554 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM;
2555 else if (SubregSize == 128)
2556 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM;
2557 else
2558 break;
2559
2560 const MCInstrDesc &TID = get(NewOpcode);
2561 const TargetRegisterClass *NewRC =
2562 RI.getAllocatableClass(getRegClass(TID, 0, &RI, *MF));
2563 MRI.setRegClass(DestReg, NewRC);
2564
2565 UseMO->setReg(DestReg);
2566 UseMO->setSubReg(AMDGPU::NoSubRegister);
2567
2568 // Use a smaller load with the desired size, possibly with updated offset.
2569 MachineInstr *MI = MF->CloneMachineInstr(&Orig);
2570 MI->setDesc(TID);
2571 MI->getOperand(0).setReg(DestReg);
2572 MI->getOperand(0).setSubReg(AMDGPU::NoSubRegister);
2573 if (Offset) {
2574 MachineOperand *OffsetMO = getNamedOperand(*MI, AMDGPU::OpName::offset);
2575 int64_t FinalOffset = OffsetMO->getImm() + Offset / 8;
2576 OffsetMO->setImm(FinalOffset);
2577 }
2579 for (const MachineMemOperand *MemOp : Orig.memoperands())
2580 NewMMOs.push_back(MF->getMachineMemOperand(MemOp, MemOp->getPointerInfo(),
2581 SubregSize / 8));
2582 MI->setMemRefs(*MF, NewMMOs);
2583
2584 MBB.insert(I, MI);
2585 return;
2586 }
2587
2588 default:
2589 break;
2590 }
2591
2592 TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI);
2593}
2594
2595std::pair<MachineInstr*, MachineInstr*>
2597 assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
2598
2599 if (ST.hasMovB64() &&
2601 getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl)->getImm())) {
2602 MI.setDesc(get(AMDGPU::V_MOV_B64_dpp));
2603 return std::pair(&MI, nullptr);
2604 }
2605
2606 MachineBasicBlock &MBB = *MI.getParent();
2610 Register Dst = MI.getOperand(0).getReg();
2611 unsigned Part = 0;
2612 MachineInstr *Split[2];
2613
2614 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
2615 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
2616 if (Dst.isPhysical()) {
2617 MovDPP.addDef(RI.getSubReg(Dst, Sub));
2618 } else {
2619 assert(MRI.isSSA());
2620 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2621 MovDPP.addDef(Tmp);
2622 }
2623
2624 for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
2625 const MachineOperand &SrcOp = MI.getOperand(I);
2626 assert(!SrcOp.isFPImm());
2627 if (SrcOp.isImm()) {
2628 APInt Imm(64, SrcOp.getImm());
2629 Imm.ashrInPlace(Part * 32);
2630 MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
2631 } else {
2632 assert(SrcOp.isReg());
2633 Register Src = SrcOp.getReg();
2634 if (Src.isPhysical())
2635 MovDPP.addReg(RI.getSubReg(Src, Sub));
2636 else
2637 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
2638 }
2639 }
2640
2641 for (const MachineOperand &MO : llvm::drop_begin(MI.explicit_operands(), 3))
2642 MovDPP.addImm(MO.getImm());
2643
2644 Split[Part] = MovDPP;
2645 ++Part;
2646 }
2647
2648 if (Dst.isVirtual())
2649 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
2650 .addReg(Split[0]->getOperand(0).getReg())
2651 .addImm(AMDGPU::sub0)
2652 .addReg(Split[1]->getOperand(0).getReg())
2653 .addImm(AMDGPU::sub1);
2654
2655 MI.eraseFromParent();
2656 return std::pair(Split[0], Split[1]);
2657}
2658
2659std::optional<DestSourcePair>
2661 if (MI.getOpcode() == AMDGPU::WWM_COPY)
2662 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
2663
2664 return std::nullopt;
2665}
2666
2668 MachineOperand &Src0,
2669 unsigned Src0OpName,
2670 MachineOperand &Src1,
2671 unsigned Src1OpName) const {
2672 MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
2673 if (!Src0Mods)
2674 return false;
2675
2676 MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
2677 assert(Src1Mods &&
2678 "All commutable instructions have both src0 and src1 modifiers");
2679
2680 int Src0ModsVal = Src0Mods->getImm();
2681 int Src1ModsVal = Src1Mods->getImm();
2682
2683 Src1Mods->setImm(Src0ModsVal);
2684 Src0Mods->setImm(Src1ModsVal);
2685 return true;
2686}
2687
2689 MachineOperand &RegOp,
2690 MachineOperand &NonRegOp) {
2691 Register Reg = RegOp.getReg();
2692 unsigned SubReg = RegOp.getSubReg();
2693 bool IsKill = RegOp.isKill();
2694 bool IsDead = RegOp.isDead();
2695 bool IsUndef = RegOp.isUndef();
2696 bool IsDebug = RegOp.isDebug();
2697
2698 if (NonRegOp.isImm())
2699 RegOp.ChangeToImmediate(NonRegOp.getImm());
2700 else if (NonRegOp.isFI())
2701 RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
2702 else if (NonRegOp.isGlobal()) {
2703 RegOp.ChangeToGA(NonRegOp.getGlobal(), NonRegOp.getOffset(),
2704 NonRegOp.getTargetFlags());
2705 } else
2706 return nullptr;
2707
2708 // Make sure we don't reinterpret a subreg index in the target flags.
2709 RegOp.setTargetFlags(NonRegOp.getTargetFlags());
2710
2711 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
2712 NonRegOp.setSubReg(SubReg);
2713
2714 return &MI;
2715}
2716
2718 unsigned Src0Idx,
2719 unsigned Src1Idx) const {
2720 assert(!NewMI && "this should never be used");
2721
2722 unsigned Opc = MI.getOpcode();
2723 int CommutedOpcode = commuteOpcode(Opc);
2724 if (CommutedOpcode == -1)
2725 return nullptr;
2726
2727 if (Src0Idx > Src1Idx)
2728 std::swap(Src0Idx, Src1Idx);
2729
2730 assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
2731 static_cast<int>(Src0Idx) &&
2732 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
2733 static_cast<int>(Src1Idx) &&
2734 "inconsistency with findCommutedOpIndices");
2735
2736 MachineOperand &Src0 = MI.getOperand(Src0Idx);
2737 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2738
2739 MachineInstr *CommutedMI = nullptr;
2740 if (Src0.isReg() && Src1.isReg()) {
2741 if (isOperandLegal(MI, Src1Idx, &Src0)) {
2742 // Be sure to copy the source modifiers to the right place.
2743 CommutedMI
2744 = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
2745 }
2746
2747 } else if (Src0.isReg() && !Src1.isReg()) {
2748 // src0 should always be able to support any operand type, so no need to
2749 // check operand legality.
2750 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2751 } else if (!Src0.isReg() && Src1.isReg()) {
2752 if (isOperandLegal(MI, Src1Idx, &Src0))
2753 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2754 } else {
2755 // FIXME: Found two non registers to commute. This does happen.
2756 return nullptr;
2757 }
2758
2759 if (CommutedMI) {
2760 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2761 Src1, AMDGPU::OpName::src1_modifiers);
2762
2763 CommutedMI->setDesc(get(CommutedOpcode));
2764 }
2765
2766 return CommutedMI;
2767}
2768
2769// This needs to be implemented because the source modifiers may be inserted
2770// between the true commutable operands, and the base
2771// TargetInstrInfo::commuteInstruction uses it.
2773 unsigned &SrcOpIdx0,
2774 unsigned &SrcOpIdx1) const {
2775 return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
2776}
2777
2779 unsigned &SrcOpIdx0,
2780 unsigned &SrcOpIdx1) const {
2781 if (!Desc.isCommutable())
2782 return false;
2783
2784 unsigned Opc = Desc.getOpcode();
2785 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
2786 if (Src0Idx == -1)
2787 return false;
2788
2789 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
2790 if (Src1Idx == -1)
2791 return false;
2792
2793 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
2794}
2795
2797 int64_t BrOffset) const {
2798 // BranchRelaxation should never have to check s_setpc_b64 because its dest
2799 // block is unanalyzable.
2800 assert(BranchOp != AMDGPU::S_SETPC_B64);
2801
2802 // Convert to dwords.
2803 BrOffset /= 4;
2804
2805 // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
2806 // from the next instruction.
2807 BrOffset -= 1;
2808
2809 return isIntN(BranchOffsetBits, BrOffset);
2810}
2811
2814 return MI.getOperand(0).getMBB();
2815}
2816
2818 for (const MachineInstr &MI : MBB->terminators()) {
2819 if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
2820 MI.getOpcode() == AMDGPU::SI_IF || MI.getOpcode() == AMDGPU::SI_ELSE ||
2821 MI.getOpcode() == AMDGPU::SI_LOOP)
2822 return true;
2823 }
2824 return false;
2825}
2826
2828 MachineBasicBlock &DestBB,
2829 MachineBasicBlock &RestoreBB,
2830 const DebugLoc &DL, int64_t BrOffset,
2831 RegScavenger *RS) const {
2832 assert(RS && "RegScavenger required for long branching");
2833 assert(MBB.empty() &&
2834 "new block should be inserted for expanding unconditional branch");
2835 assert(MBB.pred_size() == 1);
2836 assert(RestoreBB.empty() &&
2837 "restore block should be inserted for restoring clobbered registers");
2838
2842
2843 // FIXME: Virtual register workaround for RegScavenger not working with empty
2844 // blocks.
2845 Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2846
2847 auto I = MBB.end();
2848
2849 // We need to compute the offset relative to the instruction immediately after
2850 // s_getpc_b64. Insert pc arithmetic code before last terminator.
2851 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2852
2853 auto &MCCtx = MF->getContext();
2854 MCSymbol *PostGetPCLabel =
2855 MCCtx.createTempSymbol("post_getpc", /*AlwaysAddSuffix=*/true);
2856 GetPC->setPostInstrSymbol(*MF, PostGetPCLabel);
2857
2858 MCSymbol *OffsetLo =
2859 MCCtx.createTempSymbol("offset_lo", /*AlwaysAddSuffix=*/true);
2860 MCSymbol *OffsetHi =
2861 MCCtx.createTempSymbol("offset_hi", /*AlwaysAddSuffix=*/true);
2862 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
2863 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
2864 .addReg(PCReg, 0, AMDGPU::sub0)
2865 .addSym(OffsetLo, MO_FAR_BRANCH_OFFSET);
2866 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
2867 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
2868 .addReg(PCReg, 0, AMDGPU::sub1)
2869 .addSym(OffsetHi, MO_FAR_BRANCH_OFFSET);
2870
2871 // Insert the indirect branch after the other terminator.
2872 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2873 .addReg(PCReg);
2874
2875 // If a spill is needed for the pc register pair, we need to insert a spill
2876 // restore block right before the destination block, and insert a short branch
2877 // into the old destination block's fallthrough predecessor.
2878 // e.g.:
2879 //
2880 // s_cbranch_scc0 skip_long_branch:
2881 //
2882 // long_branch_bb:
2883 // spill s[8:9]
2884 // s_getpc_b64 s[8:9]
2885 // s_add_u32 s8, s8, restore_bb
2886 // s_addc_u32 s9, s9, 0
2887 // s_setpc_b64 s[8:9]
2888 //
2889 // skip_long_branch:
2890 // foo;
2891 //
2892 // .....
2893 //
2894 // dest_bb_fallthrough_predecessor:
2895 // bar;
2896 // s_branch dest_bb
2897 //
2898 // restore_bb:
2899 // restore s[8:9]
2900 // fallthrough dest_bb
2901 ///
2902 // dest_bb:
2903 // buzz;
2904
2905 Register LongBranchReservedReg = MFI->getLongBranchReservedReg();
2906 Register Scav;
2907
2908 // If we've previously reserved a register for long branches
2909 // avoid running the scavenger and just use those registers
2910 if (LongBranchReservedReg) {
2911 RS->enterBasicBlock(MBB);
2912 Scav = LongBranchReservedReg;
2913 } else {
2915 Scav = RS->scavengeRegisterBackwards(
2916 AMDGPU::SReg_64RegClass, MachineBasicBlock::iterator(GetPC),
2917 /* RestoreAfter */ false, 0, /* AllowSpill */ false);
2918 }
2919 if (Scav) {
2920 RS->setRegUsed(Scav);
2921 MRI.replaceRegWith(PCReg, Scav);
2922 MRI.clearVirtRegs();
2923 } else {
2924 // As SGPR needs VGPR to be spilled, we reuse the slot of temporary VGPR for
2925 // SGPR spill.
2926 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2927 const SIRegisterInfo *TRI = ST.getRegisterInfo();
2928 TRI->spillEmergencySGPR(GetPC, RestoreBB, AMDGPU::SGPR0_SGPR1, RS);
2929 MRI.replaceRegWith(PCReg, AMDGPU::SGPR0_SGPR1);
2930 MRI.clearVirtRegs();
2931 }
2932
2933 MCSymbol *DestLabel = Scav ? DestBB.getSymbol() : RestoreBB.getSymbol();
2934 // Now, the distance could be defined.
2936 MCSymbolRefExpr::create(DestLabel, MCCtx),
2937 MCSymbolRefExpr::create(PostGetPCLabel, MCCtx), MCCtx);
2938 // Add offset assignments.
2939 auto *Mask = MCConstantExpr::create(0xFFFFFFFFULL, MCCtx);
2940 OffsetLo->setVariableValue(MCBinaryExpr::createAnd(Offset, Mask, MCCtx));
2941 auto *ShAmt = MCConstantExpr::create(32, MCCtx);
2942 OffsetHi->setVariableValue(MCBinaryExpr::createAShr(Offset, ShAmt, MCCtx));
2943}
2944
2945unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
2946 switch (Cond) {
2947 case SIInstrInfo::SCC_TRUE:
2948 return AMDGPU::S_CBRANCH_SCC1;
2949 case SIInstrInfo::SCC_FALSE:
2950 return AMDGPU::S_CBRANCH_SCC0;
2951 case SIInstrInfo::VCCNZ:
2952 return AMDGPU::S_CBRANCH_VCCNZ;
2953 case SIInstrInfo::VCCZ:
2954 return AMDGPU::S_CBRANCH_VCCZ;
2955 case SIInstrInfo::EXECNZ:
2956 return AMDGPU::S_CBRANCH_EXECNZ;
2957 case SIInstrInfo::EXECZ:
2958 return AMDGPU::S_CBRANCH_EXECZ;
2959 default:
2960 llvm_unreachable("invalid branch predicate");
2961 }
2962}
2963
2964SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
2965 switch (Opcode) {
2966 case AMDGPU::S_CBRANCH_SCC0:
2967 return SCC_FALSE;
2968 case AMDGPU::S_CBRANCH_SCC1:
2969 return SCC_TRUE;
2970 case AMDGPU::S_CBRANCH_VCCNZ:
2971 return VCCNZ;
2972 case AMDGPU::S_CBRANCH_VCCZ:
2973 return VCCZ;
2974 case AMDGPU::S_CBRANCH_EXECNZ:
2975 return EXECNZ;
2976 case AMDGPU::S_CBRANCH_EXECZ:
2977 return EXECZ;
2978 default:
2979 return INVALID_BR;
2980 }
2981}
2982
2986 MachineBasicBlock *&FBB,
2988 bool AllowModify) const {
2989 if (I->getOpcode() == AMDGPU::S_BRANCH) {
2990 // Unconditional Branch
2991 TBB = I->getOperand(0).getMBB();
2992 return false;
2993 }
2994
2995 MachineBasicBlock *CondBB = nullptr;
2996
2997 if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
2998 CondBB = I->getOperand(1).getMBB();
2999 Cond.push_back(I->getOperand(0));
3000 } else {
3001 BranchPredicate Pred = getBranchPredicate(I->getOpcode());
3002 if (Pred == INVALID_BR)
3003 return true;
3004
3005 CondBB = I->getOperand(0).getMBB();
3006 Cond.push_back(MachineOperand::CreateImm(Pred));
3007 Cond.push_back(I->getOperand(1)); // Save the branch register.
3008 }
3009 ++I;
3010
3011 if (I == MBB.end()) {
3012 // Conditional branch followed by fall-through.
3013 TBB = CondBB;
3014 return false;
3015 }
3016
3017 if (I->getOpcode() == AMDGPU::S_BRANCH) {
3018 TBB = CondBB;
3019 FBB = I->getOperand(0).getMBB();
3020 return false;
3021 }
3022
3023 return true;
3024}
3025
3027 MachineBasicBlock *&FBB,
3029 bool AllowModify) const {
3031 auto E = MBB.end();
3032 if (I == E)
3033 return false;
3034
3035 // Skip over the instructions that are artificially terminators for special
3036 // exec management.
3037 while (I != E && !I->isBranch() && !I->isReturn()) {
3038 switch (I->getOpcode()) {
3039 case AMDGPU::S_MOV_B64_term:
3040 case AMDGPU::S_XOR_B64_term:
3041 case AMDGPU::S_OR_B64_term:
3042 case AMDGPU::S_ANDN2_B64_term:
3043 case AMDGPU::S_AND_B64_term:
3044 case AMDGPU::S_AND_SAVEEXEC_B64_term:
3045 case AMDGPU::S_MOV_B32_term:
3046 case AMDGPU::S_XOR_B32_term:
3047 case AMDGPU::S_OR_B32_term:
3048 case AMDGPU::S_ANDN2_B32_term:
3049 case AMDGPU::S_AND_B32_term:
3050 case AMDGPU::S_AND_SAVEEXEC_B32_term:
3051 break;
3052 case AMDGPU::SI_IF:
3053 case AMDGPU::SI_ELSE:
3054 case AMDGPU::SI_KILL_I1_TERMINATOR:
3055 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
3056 // FIXME: It's messy that these need to be considered here at all.
3057 return true;
3058 default:
3059 llvm_unreachable("unexpected non-branch terminator inst");
3060 }
3061
3062 ++I;
3063 }
3064
3065 if (I == E)
3066 return false;
3067
3068 return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
3069}
3070
3072 int *BytesRemoved) const {
3073 unsigned Count = 0;
3074 unsigned RemovedSize = 0;
3076 // Skip over artificial terminators when removing instructions.
3077 if (MI.isBranch() || MI.isReturn()) {
3078 RemovedSize += getInstSizeInBytes(MI);
3079 MI.eraseFromParent();
3080 ++Count;
3081 }
3082 }
3083
3084 if (BytesRemoved)
3085 *BytesRemoved = RemovedSize;
3086
3087 return Count;
3088}
3089
3090// Copy the flags onto the implicit condition register operand.
3092 const MachineOperand &OrigCond) {
3093 CondReg.setIsUndef(OrigCond.isUndef());
3094 CondReg.setIsKill(OrigCond.isKill());
3095}
3096
3099 MachineBasicBlock *FBB,
3101 const DebugLoc &DL,
3102 int *BytesAdded) const {
3103 if (!FBB && Cond.empty()) {
3104 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
3105 .addMBB(TBB);
3106 if (BytesAdded)
3107 *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
3108 return 1;
3109 }
3110
3111 if(Cond.size() == 1 && Cond[0].isReg()) {
3112 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
3113 .add(Cond[0])
3114 .addMBB(TBB);
3115 return 1;
3116 }
3117
3118 assert(TBB && Cond[0].isImm());
3119
3120 unsigned Opcode
3121 = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
3122
3123 if (!FBB) {
3124 MachineInstr *CondBr =
3125 BuildMI(&MBB, DL, get(Opcode))
3126 .addMBB(TBB);
3127
3128 // Copy the flags onto the implicit condition register operand.
3129 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
3130 fixImplicitOperands(*CondBr);
3131
3132 if (BytesAdded)
3133 *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
3134 return 1;
3135 }
3136
3137 assert(TBB && FBB);
3138
3139 MachineInstr *CondBr =
3140 BuildMI(&MBB, DL, get(Opcode))
3141 .addMBB(TBB);
3142 fixImplicitOperands(*CondBr);
3143 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
3144 .addMBB(FBB);
3145
3146 MachineOperand &CondReg = CondBr->getOperand(1);
3147 CondReg.setIsUndef(Cond[1].isUndef());
3148 CondReg.setIsKill(Cond[1].isKill());
3149
3150 if (BytesAdded)
3151 *BytesAdded = ST.hasOffset3fBug() ? 16 : 8;
3152
3153 return 2;
3154}
3155
3158 if (Cond.size() != 2) {
3159 return true;
3160 }
3161
3162 if (Cond[0].isImm()) {
3163 Cond[0].setImm(-Cond[0].getImm());
3164 return false;
3165 }
3166
3167 return true;
3168}
3169
3172 Register DstReg, Register TrueReg,
3173 Register FalseReg, int &CondCycles,
3174 int &TrueCycles, int &FalseCycles) const {
3175 switch (Cond[0].getImm()) {
3176 case VCCNZ:
3177 case VCCZ: {
3179 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3180 if (MRI.getRegClass(FalseReg) != RC)
3181 return false;
3182
3183 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32;
3184 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
3185
3186 // Limit to equal cost for branch vs. N v_cndmask_b32s.
3187 return RI.hasVGPRs(RC) && NumInsts <= 6;
3188 }
3189 case SCC_TRUE:
3190 case SCC_FALSE: {
3191 // FIXME: We could insert for VGPRs if we could replace the original compare
3192 // with a vector one.
3194 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
3195 if (MRI.getRegClass(FalseReg) != RC)
3196 return false;
3197
3198 int NumInsts = AMDGPU::getRegBitWidth(*RC) / 32;
3199
3200 // Multiples of 8 can do s_cselect_b64
3201 if (NumInsts % 2 == 0)
3202 NumInsts /= 2;
3203
3204 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
3205 return RI.isSGPRClass(RC);
3206 }
3207 default:
3208 return false;
3209 }
3210}
3211
3215 Register TrueReg, Register FalseReg) const {
3216 BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
3217 if (Pred == VCCZ || Pred == SCC_FALSE) {
3218 Pred = static_cast<BranchPredicate>(-Pred);
3219 std::swap(TrueReg, FalseReg);
3220 }
3221
3223 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
3224 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
3225
3226 if (DstSize == 32) {
3228 if (Pred == SCC_TRUE) {
3229 Select = BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B32), DstReg)
3230 .addReg(TrueReg)
3231 .addReg(FalseReg);
3232 } else {
3233 // Instruction's operands are backwards from what is expected.
3234 Select = BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e32), DstReg)
3235 .addReg(FalseReg)
3236 .addReg(TrueReg);
3237 }
3238
3239 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3240 return;
3241 }
3242
3243 if (DstSize == 64 && Pred == SCC_TRUE) {
3245 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
3246 .addReg(TrueReg)
3247 .addReg(FalseReg);
3248
3249 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3250 return;
3251 }
3252
3253 static const int16_t Sub0_15[] = {
3254 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
3255 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
3256 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
3257 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
3258 };
3259
3260 static const int16_t Sub0_15_64[] = {
3261 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
3262 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
3263 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
3264 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
3265 };
3266
3267 unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
3268 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
3269 const int16_t *SubIndices = Sub0_15;
3270 int NElts = DstSize / 32;
3271
3272 // 64-bit select is only available for SALU.
3273 // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
3274 if (Pred == SCC_TRUE) {
3275 if (NElts % 2) {
3276 SelOp = AMDGPU::S_CSELECT_B32;
3277 EltRC = &AMDGPU::SGPR_32RegClass;
3278 } else {
3279 SelOp = AMDGPU::S_CSELECT_B64;
3280 EltRC = &AMDGPU::SGPR_64RegClass;
3281 SubIndices = Sub0_15_64;
3282 NElts /= 2;
3283 }
3284 }
3285
3287 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
3288
3289 I = MIB->getIterator();
3290
3292 for (int Idx = 0; Idx != NElts; ++Idx) {
3293 Register DstElt = MRI.createVirtualRegister(EltRC);
3294 Regs.push_back(DstElt);
3295
3296 unsigned SubIdx = SubIndices[Idx];
3297
3299 if (SelOp == AMDGPU::V_CNDMASK_B32_e32) {
3300 Select =
3301 BuildMI(MBB, I, DL, get(SelOp), DstElt)
3302 .addReg(FalseReg, 0, SubIdx)
3303 .addReg(TrueReg, 0, SubIdx);
3304 } else {
3305 Select =
3306 BuildMI(MBB, I, DL, get(SelOp), DstElt)
3307 .addReg(TrueReg, 0, SubIdx)
3308 .addReg(FalseReg, 0, SubIdx);
3309 }
3310
3311 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
3313
3314 MIB.addReg(DstElt)
3315 .addImm(SubIdx);
3316 }
3317}
3318
3320 switch (MI.getOpcode()) {
3321 case AMDGPU::V_MOV_B32_e32:
3322 case AMDGPU::V_MOV_B32_e64:
3323 case AMDGPU::V_MOV_B64_PSEUDO:
3324 case AMDGPU::V_MOV_B64_e32:
3325 case AMDGPU::V_MOV_B64_e64:
3326 case AMDGPU::S_MOV_B32:
3327 case AMDGPU::S_MOV_B64:
3328 case AMDGPU::S_MOV_B64_IMM_PSEUDO:
3329 case AMDGPU::COPY:
3330 case AMDGPU::WWM_COPY:
3331 case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
3332 case AMDGPU::V_ACCVGPR_READ_B32_e64:
3333 case AMDGPU::V_ACCVGPR_MOV_B32:
3334 return true;
3335 default:
3336 return false;
3337 }
3338}
3339
3340static constexpr unsigned ModifierOpNames[] = {
3341 AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
3342 AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
3343 AMDGPU::OpName::omod, AMDGPU::OpName::op_sel};
3344
3346 unsigned Opc = MI.getOpcode();
3347 for (unsigned Name : reverse(ModifierOpNames)) {
3349 if (Idx >= 0)
3350 MI.removeOperand(Idx);
3351 }
3352}
3353
3355 Register Reg, MachineRegisterInfo *MRI) const {
3356 if (!MRI->hasOneNonDBGUse(Reg))
3357 return false;
3358
3359 switch (DefMI.getOpcode()) {
3360 default:
3361 return false;
3362 case AMDGPU::V_MOV_B64_e32:
3363 case AMDGPU::S_MOV_B64:
3364 case AMDGPU::V_MOV_B64_PSEUDO:
3365 case AMDGPU::S_MOV_B64_IMM_PSEUDO:
3366 case AMDGPU::V_MOV_B32_e32:
3367 case AMDGPU::S_MOV_B32:
3368 case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
3369 break;
3370 }
3371
3372 const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
3373 assert(ImmOp);
3374 // FIXME: We could handle FrameIndex values here.
3375 if (!ImmOp->isImm())
3376 return false;
3377
3378 auto getImmFor = [ImmOp](const MachineOperand &UseOp) -> int64_t {
3379 int64_t Imm = ImmOp->getImm();
3380 switch (UseOp.getSubReg()) {
3381 default:
3382 return Imm;
3383 case AMDGPU::sub0:
3384 return Lo_32(Imm);
3385 case AMDGPU::sub1:
3386 return Hi_32(Imm);
3387 case AMDGPU::lo16:
3388 return APInt(16, Imm).getSExtValue();
3389 case AMDGPU::hi16:
3390 return APInt(32, Imm).ashr(16).getSExtValue();
3391 case AMDGPU::sub1_lo16:
3392 return APInt(16, Hi_32(Imm)).getSExtValue();
3393 case AMDGPU::sub1_hi16:
3394 return APInt(32, Hi_32(Imm)).ashr(16).getSExtValue();
3395 }
3396 };
3397
3398 assert(!DefMI.getOperand(0).getSubReg() && "Expected SSA form");
3399
3400 unsigned Opc = UseMI.getOpcode();
3401 if (Opc == AMDGPU::COPY) {
3402 assert(!UseMI.getOperand(0).getSubReg() && "Expected SSA form");
3403
3404 Register DstReg = UseMI.getOperand(0).getReg();
3405 unsigned OpSize = getOpSize(UseMI, 0);
3406 bool Is16Bit = OpSize == 2;
3407 bool Is64Bit = OpSize == 8;
3408 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
3409 unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO
3410 : AMDGPU::V_MOV_B32_e32
3411 : Is64Bit ? AMDGPU::S_MOV_B64_IMM_PSEUDO
3412 : AMDGPU::S_MOV_B32;
3413 APInt Imm(Is64Bit ? 64 : 32, getImmFor(UseMI.getOperand(1)));
3414
3415 if (RI.isAGPR(*MRI, DstReg)) {
3416 if (Is64Bit || !isInlineConstant(Imm))
3417 return false;
3418 NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
3419 }
3420
3421 if (Is16Bit) {
3422 if (isVGPRCopy)
3423 return false; // Do not clobber vgpr_hi16
3424
3425 if (DstReg.isVirtual() && UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
3426 return false;
3427
3428 UseMI.getOperand(0).setSubReg(0);
3429 if (DstReg.isPhysical()) {
3430 DstReg = RI.get32BitRegister(DstReg);
3431 UseMI.getOperand(0).setReg(DstReg);
3432 }
3433 assert(UseMI.getOperand(1).getReg().isVirtual());
3434 }
3435
3436 const MCInstrDesc &NewMCID = get(NewOpc);
3437 if (DstReg.isPhysical() &&
3438 !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
3439 return false;
3440
3441 UseMI.setDesc(NewMCID);
3442 UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
3443 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
3444 return true;
3445 }
3446
3447 if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
3448 Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3449 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3450 Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3451 Opc == AMDGPU::V_FMAC_F16_t16_e64) {
3452 // Don't fold if we are using source or output modifiers. The new VOP2
3453 // instructions don't have them.
3455 return false;
3456
3457 // If this is a free constant, there's no reason to do this.
3458 // TODO: We could fold this here instead of letting SIFoldOperands do it
3459 // later.
3460 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
3461
3462 // Any src operand can be used for the legality check.
3463 if (isInlineConstant(UseMI, *Src0, *ImmOp))
3464 return false;
3465
3466 bool IsF32 = Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
3467 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64;
3468 bool IsFMA =
3469 Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3470 Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3471 Opc == AMDGPU::V_FMAC_F16_t16_e64;
3472 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
3473 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
3474
3475 // Multiplied part is the constant: Use v_madmk_{f16, f32}.
3476 if ((Src0->isReg() && Src0->getReg() == Reg) ||
3477 (Src1->isReg() && Src1->getReg() == Reg)) {
3478 MachineOperand *RegSrc =
3479 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1;
3480 if (!RegSrc->isReg())
3481 return false;
3482 if (RI.isSGPRClass(MRI->getRegClass(RegSrc->getReg())) &&
3483 ST.getConstantBusLimit(Opc) < 2)
3484 return false;
3485
3486 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
3487 return false;
3488
3489 // If src2 is also a literal constant then we have to choose which one to
3490 // fold. In general it is better to choose madak so that the other literal
3491 // can be materialized in an sgpr instead of a vgpr:
3492 // s_mov_b32 s0, literal
3493 // v_madak_f32 v0, s0, v0, literal
3494 // Instead of:
3495 // v_mov_b32 v1, literal
3496 // v_madmk_f32 v0, v0, literal, v1
3497 MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg());
3498 if (Def && Def->isMoveImmediate() &&
3499 !isInlineConstant(Def->getOperand(1)))
3500 return false;
3501
3502 unsigned NewOpc =
3503 IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32
3504 : ST.hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16
3505 : AMDGPU::V_FMAMK_F16)
3506 : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
3507 if (pseudoToMCOpcode(NewOpc) == -1)
3508 return false;
3509
3510 // V_FMAMK_F16_t16 takes VGPR_32_Lo128 operands, so the rewrite
3511 // would also require restricting their register classes. For now
3512 // just bail out.
3513 if (NewOpc == AMDGPU::V_FMAMK_F16_t16)
3514 return false;
3515
3516 const int64_t Imm = getImmFor(RegSrc == Src1 ? *Src0 : *Src1);
3517
3518 // FIXME: This would be a lot easier if we could return a new instruction
3519 // instead of having to modify in place.
3520
3521 Register SrcReg = RegSrc->getReg();
3522 unsigned SrcSubReg = RegSrc->getSubReg();
3523 Src0->setReg(SrcReg);
3524 Src0->setSubReg(SrcSubReg);
3525 Src0->setIsKill(RegSrc->isKill());
3526
3527 if (Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3528 Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3529 Opc == AMDGPU::V_FMAC_F16_e64)
3530 UseMI.untieRegOperand(
3531 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
3532
3533 Src1->ChangeToImmediate(Imm);
3534
3536 UseMI.setDesc(get(NewOpc));
3537
3538 bool DeleteDef = MRI->use_nodbg_empty(Reg);
3539 if (DeleteDef)
3540 DefMI.eraseFromParent();
3541
3542 return true;
3543 }
3544
3545 // Added part is the constant: Use v_madak_{f16, f32}.
3546 if (Src2->isReg() && Src2->getReg() == Reg) {
3547 if (ST.getConstantBusLimit(Opc) < 2) {
3548 // Not allowed to use constant bus for another operand.
3549 // We can however allow an inline immediate as src0.
3550 bool Src0Inlined = false;
3551 if (Src0->isReg()) {
3552 // Try to inline constant if possible.
3553 // If the Def moves immediate and the use is single
3554 // We are saving VGPR here.
3555 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
3556 if (Def && Def->isMoveImmediate() &&
3557 isInlineConstant(Def->getOperand(1)) &&
3558 MRI->hasOneUse(Src0->getReg())) {
3559 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3560 Src0Inlined = true;
3561 } else if (ST.getConstantBusLimit(Opc) <= 1 &&
3562 RI.isSGPRReg(*MRI, Src0->getReg())) {
3563 return false;
3564 }
3565 // VGPR is okay as Src0 - fallthrough
3566 }
3567
3568 if (Src1->isReg() && !Src0Inlined) {
3569 // We have one slot for inlinable constant so far - try to fill it
3570 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
3571 if (Def && Def->isMoveImmediate() &&
3572 isInlineConstant(Def->getOperand(1)) &&
3573 MRI->hasOneUse(Src1->getReg()) && commuteInstruction(UseMI))
3574 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3575 else if (RI.isSGPRReg(*MRI, Src1->getReg()))
3576 return false;
3577 // VGPR is okay as Src1 - fallthrough
3578 }
3579 }
3580
3581 unsigned NewOpc =
3582 IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32
3583 : ST.hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16
3584 : AMDGPU::V_FMAAK_F16)
3585 : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
3586 if (pseudoToMCOpcode(NewOpc) == -1)
3587 return false;
3588
3589 // V_FMAAK_F16_t16 takes VGPR_32_Lo128 operands, so the rewrite
3590 // would also require restricting their register classes. For now
3591 // just bail out.
3592 if (NewOpc == AMDGPU::V_FMAAK_F16_t16)
3593 return false;
3594
3595 // FIXME: This would be a lot easier if we could return a new instruction
3596 // instead of having to modify in place.
3597
3598 if (Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
3599 Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3600 Opc == AMDGPU::V_FMAC_F16_e64)
3601 UseMI.untieRegOperand(
3602 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
3603
3604 // ChangingToImmediate adds Src2 back to the instruction.
3605 Src2->ChangeToImmediate(getImmFor(*Src2));
3606
3607 // These come before src2.
3609 UseMI.setDesc(get(NewOpc));
3610 // It might happen that UseMI was commuted
3611 // and we now have SGPR as SRC1. If so 2 inlined
3612 // constant and SGPR are illegal.
3614
3615 bool DeleteDef = MRI->use_nodbg_empty(Reg);
3616 if (DeleteDef)
3617 DefMI.eraseFromParent();
3618
3619 return true;
3620 }
3621 }
3622
3623 return false;
3624}
3625
3626static bool
3629 if (BaseOps1.size() != BaseOps2.size())
3630 return false;
3631 for (size_t I = 0, E = BaseOps1.size(); I < E; ++I) {
3632 if (!BaseOps1[I]->isIdenticalTo(*BaseOps2[I]))
3633 return false;
3634 }
3635 return true;
3636}
3637
3638static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
3639 int WidthB, int OffsetB) {
3640 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
3641 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
3642 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
3643 return LowOffset + LowWidth <= HighOffset;
3644}
3645
3646bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
3647 const MachineInstr &MIb) const {
3648 SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
3649 int64_t Offset0, Offset1;
3650 unsigned Dummy0, Dummy1;
3651 bool Offset0IsScalable, Offset1IsScalable;
3652 if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
3653 Dummy0, &RI) ||
3654 !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
3655 Dummy1, &RI))
3656 return false;
3657
3658 if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))
3659 return false;
3660
3661 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
3662 // FIXME: Handle ds_read2 / ds_write2.
3663 return false;
3664 }
3665 unsigned Width0 = MIa.memoperands().front()->getSize();
3666 unsigned Width1 = MIb.memoperands().front()->getSize();
3667 return offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1);
3668}
3669
3671 const MachineInstr &MIb) const {
3672 assert(MIa.mayLoadOrStore() &&
3673 "MIa must load from or modify a memory location");
3674 assert(MIb.mayLoadOrStore() &&
3675 "MIb must load from or modify a memory location");
3676
3678 return false;
3679
3680 // XXX - Can we relax this between address spaces?
3681 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
3682 return false;
3683
3684 if (isLDSDMA(MIa) || isLDSDMA(MIb))
3685 return false;
3686
3687 // TODO: Should we check the address space from the MachineMemOperand? That
3688 // would allow us to distinguish objects we know don't alias based on the
3689 // underlying address space, even if it was lowered to a different one,
3690 // e.g. private accesses lowered to use MUBUF instructions on a scratch
3691 // buffer.
3692 if (isDS(MIa)) {
3693 if (isDS(MIb))
3694 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3695
3696 return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
3697 }
3698
3699 if (isMUBUF(MIa) || isMTBUF(MIa)) {
3700 if (isMUBUF(MIb) || isMTBUF(MIb))
3701 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3702
3703 if (isFLAT(MIb))
3704 return isFLATScratch(MIb);
3705
3706 return !isSMRD(MIb);
3707 }
3708
3709 if (isSMRD(MIa)) {
3710 if (isSMRD(MIb))
3711 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3712
3713 if (isFLAT(MIb))
3714 return isFLATScratch(MIb);
3715
3716 return !isMUBUF(MIb) && !isMTBUF(MIb);
3717 }
3718
3719 if (isFLAT(MIa)) {
3720 if (isFLAT(MIb)) {
3721 if ((isFLATScratch(MIa) && isFLATGlobal(MIb)) ||
3722 (isFLATGlobal(MIa) && isFLATScratch(MIb)))
3723 return true;
3724
3725 return checkInstOffsetsDoNotOverlap(MIa, MIb);
3726 }
3727
3728 return false;
3729 }
3730
3731 return false;
3732}
3733
3735 int64_t &Imm, MachineInstr **DefMI = nullptr) {
3736 if (Reg.isPhysical())
3737 return false;
3738 auto *Def = MRI.getUniqueVRegDef(Reg);
3739 if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {
3740 Imm = Def->getOperand(1).getImm();
3741 if (DefMI)
3742 *DefMI = Def;
3743 return true;
3744 }
3745 return false;
3746}
3747
3748static bool getFoldableImm(const MachineOperand *MO, int64_t &Imm,
3749 MachineInstr **DefMI = nullptr) {
3750 if (!MO->isReg())
3751 return false;
3752 const MachineFunction *MF = MO->getParent()->getParent()->getParent();
3753 const MachineRegisterInfo &MRI = MF->getRegInfo();
3754 return getFoldableImm(MO->getReg(), MRI, Imm, DefMI);
3755}
3756
3758 MachineInstr &NewMI) {
3759 if (LV) {
3760 unsigned NumOps = MI.getNumOperands();
3761 for (unsigned I = 1; I < NumOps; ++I) {
3762 MachineOperand &Op = MI.getOperand(I);
3763 if (Op.isReg() && Op.isKill())
3764 LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
3765 }
3766 }
3767}
3768
3770 LiveVariables *LV,
3771 LiveIntervals *LIS) const {
3772 MachineBasicBlock &MBB = *MI.getParent();
3773 unsigned Opc = MI.getOpcode();
3774
3775 // Handle MFMA.
3776 int NewMFMAOpc = AMDGPU::getMFMAEarlyClobberOp(Opc);
3777 if (NewMFMAOpc != -1) {
3779 BuildMI(MBB, MI, MI.getDebugLoc(), get(NewMFMAOpc));
3780 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3781 MIB.add(MI.getOperand(I));
3782 updateLiveVariables(LV, MI, *MIB);
3783 if (LIS)
3784 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3785 return MIB;
3786 }
3787
3788 if (SIInstrInfo::isWMMA(MI)) {
3789 unsigned NewOpc = AMDGPU::mapWMMA2AddrTo3AddrOpcode(MI.getOpcode());
3790 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3791 .setMIFlags(MI.getFlags());
3792 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3793 MIB->addOperand(MI.getOperand(I));
3794
3795 updateLiveVariables(LV, MI, *MIB);
3796 if (LIS)
3797 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3798
3799 return MIB;
3800 }
3801
3802 assert(Opc != AMDGPU::V_FMAC_F16_t16_e32 &&
3803 "V_FMAC_F16_t16_e32 is not supported and not expected to be present "
3804 "pre-RA");
3805
3806 // Handle MAC/FMAC.
3807 bool IsF16 = Opc == AMDGPU::V_MAC_F16_e32 || Opc == AMDGPU::V_MAC_F16_e64 ||
3808 Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3809 Opc == AMDGPU::V_FMAC_F16_t16_e64;
3810 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3811 Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
3812 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64 ||
3813 Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3814 Opc == AMDGPU::V_FMAC_F16_t16_e64 ||
3815 Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3816 bool IsF64 = Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3817 bool IsLegacy = Opc == AMDGPU::V_MAC_LEGACY_F32_e32 ||
3818 Opc == AMDGPU::V_MAC_LEGACY_F32_e64 ||
3819 Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
3820 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64;
3821 bool Src0Literal = false;
3822
3823 switch (Opc) {
3824 default:
3825 return nullptr;
3826 case AMDGPU::V_MAC_F16_e64:
3827 case AMDGPU::V_FMAC_F16_e64:
3828 case AMDGPU::V_FMAC_F16_t16_e64:
3829 case AMDGPU::V_MAC_F32_e64:
3830 case AMDGPU::V_MAC_LEGACY_F32_e64:
3831 case AMDGPU::V_FMAC_F32_e64:
3832 case AMDGPU::V_FMAC_LEGACY_F32_e64:
3833 case AMDGPU::V_FMAC_F64_e64:
3834 break;
3835 case AMDGPU::V_MAC_F16_e32:
3836 case AMDGPU::V_FMAC_F16_e32:
3837 case AMDGPU::V_MAC_F32_e32:
3838 case AMDGPU::V_MAC_LEGACY_F32_e32:
3839 case AMDGPU::V_FMAC_F32_e32:
3840 case AMDGPU::V_FMAC_LEGACY_F32_e32:
3841 case AMDGPU::V_FMAC_F64_e32: {
3842 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3843 AMDGPU::OpName::src0);
3844 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3845 if (!Src0->isReg() && !Src0->isImm())
3846 return nullptr;
3847
3848 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
3849 Src0Literal = true;
3850
3851 break;
3852 }
3853 }
3854
3856 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3857 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
3858 const MachineOperand *Src0Mods =
3859 getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
3860 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3861 const MachineOperand *Src1Mods =
3862 getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
3863 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3864 const MachineOperand *Src2Mods =
3865 getNamedOperand(MI, AMDGPU::OpName::src2_modifiers);
3866 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3867 const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
3868 const MachineOperand *OpSel = getNamedOperand(MI, AMDGPU::OpName::op_sel);
3869
3870 if (!Src0Mods && !Src1Mods && !Src2Mods && !Clamp && !Omod && !IsF64 &&
3871 !IsLegacy &&
3872 // If we have an SGPR input, we will violate the constant bus restriction.
3873 (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
3874 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
3876 const auto killDef = [&]() -> void {
3878 // The only user is the instruction which will be killed.
3879 Register DefReg = DefMI->getOperand(0).getReg();
3880 if (!MRI.hasOneNonDBGUse(DefReg))
3881 return;
3882 // We cannot just remove the DefMI here, calling pass will crash.
3883 DefMI->setDesc(get(AMDGPU::IMPLICIT_DEF));
3884 for (unsigned I = DefMI->getNumOperands() - 1; I != 0; --I)
3886 if (LV)
3887 LV->getVarInfo(DefReg).AliveBlocks.clear();
3888 };
3889
3890 int64_t Imm;
3891 if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {
3892 unsigned NewOpc =
3893 IsFMA ? (IsF16 ? (ST.hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16
3894 : AMDGPU::V_FMAAK_F16)
3895 : AMDGPU::V_FMAAK_F32)
3896 : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
3897 if (pseudoToMCOpcode(NewOpc) != -1) {
3898 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3899 .add(*Dst)
3900 .add(*Src0)
3901 .add(*Src1)
3902 .addImm(Imm);
3903 updateLiveVariables(LV, MI, *MIB);
3904 if (LIS)
3905 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3906 killDef();
3907 return MIB;
3908 }
3909 }
3910 unsigned NewOpc =
3911 IsFMA ? (IsF16 ? (ST.hasTrue16BitInsts() ? AMDGPU::V_FMAMK_F16_t16
3912 : AMDGPU::V_FMAMK_F16)
3913 : AMDGPU::V_FMAMK_F32)
3914 : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
3915 if (!Src0Literal && getFoldableImm(Src1, Imm, &DefMI)) {
3916 if (pseudoToMCOpcode(NewOpc) != -1) {
3917 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3918 .add(*Dst)
3919 .add(*Src0)
3920 .addImm(Imm)
3921 .add(*Src2);
3922 updateLiveVariables(LV, MI, *MIB);
3923 if (LIS)
3924 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3925 killDef();
3926 return MIB;
3927 }
3928 }
3929 if (Src0Literal || getFoldableImm(Src0, Imm, &DefMI)) {
3930 if (Src0Literal) {
3931 Imm = Src0->getImm();
3932 DefMI = nullptr;
3933 }
3934 if (pseudoToMCOpcode(NewOpc) != -1 &&
3936 MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
3937 Src1)) {
3938 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3939 .add(*Dst)
3940 .add(*Src1)
3941 .addImm(Imm)
3942 .add(*Src2);
3943 updateLiveVariables(LV, MI, *MIB);
3944 if (LIS)
3945 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3946 if (DefMI)
3947 killDef();
3948 return MIB;
3949 }
3950 }
3951 }
3952
3953 // VOP2 mac/fmac with a literal operand cannot be converted to VOP3 mad/fma
3954 // if VOP3 does not allow a literal operand.
3955 if (Src0Literal && !ST.hasVOP3Literal())
3956 return nullptr;
3957
3958 unsigned NewOpc = IsFMA ? IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
3959 : IsF64 ? AMDGPU::V_FMA_F64_e64
3960 : IsLegacy
3961 ? AMDGPU::V_FMA_LEGACY_F32_e64
3962 : AMDGPU::V_FMA_F32_e64
3963 : IsF16 ? AMDGPU::V_MAD_F16_e64
3964 : IsLegacy ? AMDGPU::V_MAD_LEGACY_F32_e64
3965 : AMDGPU::V_MAD_F32_e64;
3966 if (pseudoToMCOpcode(NewOpc) == -1)
3967 return nullptr;
3968
3969 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3970 .add(*Dst)
3971 .addImm(Src0Mods ? Src0Mods->getImm() : 0)
3972 .add(*Src0)
3973 .addImm(Src1Mods ? Src1Mods->getImm() : 0)
3974 .add(*Src1)
3975 .addImm(Src2Mods ? Src2Mods->getImm() : 0)
3976 .add(*Src2)
3977 .addImm(Clamp ? Clamp->getImm() : 0)
3978 .addImm(Omod ? Omod->getImm() : 0);
3979 if (AMDGPU::hasNamedOperand(NewOpc, AMDGPU::OpName::op_sel))
3980 MIB.addImm(OpSel ? OpSel->getImm() : 0);
3981 updateLiveVariables(LV, MI, *MIB);
3982 if (LIS)
3983 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3984 return MIB;
3985}
3986
3987// It's not generally safe to move VALU instructions across these since it will
3988// start using the register as a base index rather than directly.
3989// XXX - Why isn't hasSideEffects sufficient for these?
3991 switch (MI.getOpcode()) {
3992 case AMDGPU::S_SET_GPR_IDX_ON:
3993 case AMDGPU::S_SET_GPR_IDX_MODE:
3994 case AMDGPU::S_SET_GPR_IDX_OFF:
3995 return true;
3996 default:
3997 return false;
3998 }
3999}
4000
4002 const MachineBasicBlock *MBB,
4003 const MachineFunction &MF) const {
4004 // Skipping the check for SP writes in the base implementation. The reason it
4005 // was added was apparently due to compile time concerns.
4006 //
4007 // TODO: Do we really want this barrier? It triggers unnecessary hazard nops
4008 // but is probably avoidable.
4009
4010 // Copied from base implementation.
4011 // Terminators and labels can't be scheduled around.
4012 if (MI.isTerminator() || MI.isPosition())
4013 return true;
4014
4015 // INLINEASM_BR can jump to another block
4016 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
4017 return true;
4018
4019 if (MI.getOpcode() == AMDGPU::SCHED_BARRIER && MI.getOperand(0).getImm() == 0)
4020 return true;
4021
4022 // Target-independent instructions do not have an implicit-use of EXEC, even
4023 // when they operate on VGPRs. Treating EXEC modifications as scheduling
4024 // boundaries prevents incorrect movements of such instructions.
4025 return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
4026 MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
4027 MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
4028 MI.getOpcode() == AMDGPU::S_SETPRIO ||
4030}
4031
4033 return Opcode == AMDGPU::DS_ORDERED_COUNT || isGWS(Opcode);
4034}
4035
4037 // Skip the full operand and register alias search modifiesRegister
4038 // does. There's only a handful of instructions that touch this, it's only an
4039 // implicit def, and doesn't alias any other registers.
4040 return is_contained(MI.getDesc().implicit_defs(), AMDGPU::MODE);
4041}
4042
4044 unsigned Opcode = MI.getOpcode();
4045
4046 if (MI.mayStore() && isSMRD(MI))
4047 return true; // scalar store or atomic
4048
4049 // This will terminate the function when other lanes may need to continue.
4050 if (MI.isReturn())
4051 return true;
4052
4053 // These instructions cause shader I/O that may cause hardware lockups
4054 // when executed with an empty EXEC mask.
4055 //
4056 // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
4057 // EXEC = 0, but checking for that case here seems not worth it
4058 // given the typical code patterns.
4059 if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
4060 isEXP(Opcode) ||
4061 Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
4062 Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
4063 return true;
4064
4065 if (MI.isCall() || MI.isInlineAsm())
4066 return true; // conservative assumption
4067
4068 // A mode change is a scalar operation that influences vector instructions.
4070 return true;
4071
4072 // These are like SALU instructions in terms of effects, so it's questionable
4073 // whether we should return true for those.
4074 //
4075 // However, executing them with EXEC = 0 causes them to operate on undefined
4076 // data, which we avoid by returning true here.
4077 if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
4078 Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32 ||
4079 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
4080 Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR)
4081 return true;
4082
4083 return false;
4084}
4085
4087 const MachineInstr &MI) const {
4088 if (MI.isMetaInstruction())
4089 return false;
4090
4091 // This won't read exec if this is an SGPR->SGPR copy.
4092 if (MI.isCopyLike()) {
4093 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
4094 return true;
4095
4096 // Make sure this isn't copying exec as a normal operand
4097 return MI.readsRegister(AMDGPU::EXEC, &RI);
4098 }
4099
4100 // Make a conservative assumption about the callee.
4101 if (MI.isCall())
4102 return true;
4103
4104 // Be conservative with any unhandled generic opcodes.
4105 if (!isTargetSpecificOpcode(MI.getOpcode()))
4106 return true;
4107
4108 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
4109}
4110
4111bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
4112 switch (Imm.getBitWidth()) {
4113 case 1: // This likely will be a condition code mask.
4114 return true;
4115
4116 case 32:
4117 return AMDGPU::isInlinableLiteral32(Imm.getSExtValue(),
4118 ST.hasInv2PiInlineImm());
4119 case 64:
4120 return AMDGPU::isInlinableLiteral64(Imm.getSExtValue(),
4121 ST.hasInv2PiInlineImm());
4122 case 16:
4123 return ST.has16BitInsts() &&
4124 AMDGPU::isInlinableLiteral16(Imm.getSExtValue(),
4125 ST.hasInv2PiInlineImm());
4126 default:
4127 llvm_unreachable("invalid bitwidth");
4128 }
4129}
4130
4132 uint8_t OperandType) const {
4133 assert(!MO.isReg() && "isInlineConstant called on register operand!");
4134 if (!MO.isImm())
4135 return false;
4136
4137 // MachineOperand provides no way to tell the true operand size, since it only
4138 // records a 64-bit value. We need to know the size to determine if a 32-bit
4139 // floating point immediate bit pattern is legal for an integer immediate. It
4140 // would be for any 32-bit integer operand, but would not be for a 64-bit one.
4141
4142 int64_t Imm = MO.getImm();
4143 switch (OperandType) {
4156 int32_t Trunc = static_cast<int32_t>(Imm);
4158 }
4165 ST.hasInv2PiInlineImm());
4169 // We would expect inline immediates to not be concerned with an integer/fp
4170 // distinction. However, in the case of 16-bit integer operations, the
4171 // "floating point" values appear to not work. It seems read the low 16-bits
4172 // of 32-bit immediates, which happens to always work for the integer
4173 // values.
4174 //
4175 // See llvm bugzilla 46302.
4176 //
4177 // TODO: Theoretically we could use op-sel to use the high bits of the
4178 // 32-bit FP values.
4196 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
4197 // A few special case instructions have 16-bit operands on subtargets
4198 // where 16-bit instructions are not legal.
4199 // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
4200 // constants in these cases
4201 int16_t Trunc = static_cast<int16_t>(Imm);
4202 return ST.has16BitInsts() &&
4204 }
4205
4206 return false;
4207 }
4212 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
4213 int16_t Trunc = static_cast<int16_t>(Imm);
4214 return ST.has16BitInsts() &&
4216 }
4217 return false;
4218 }
4221 return false;
4224 // Always embedded in the instruction for free.
4225 return true;
4235 // Just ignore anything else.
4236 return true;
4237 default:
4238 llvm_unreachable("invalid operand type");
4239 }
4240}
4241
4242static bool compareMachineOp(const MachineOperand &Op0,
4243 const MachineOperand &Op1) {
4244 if (Op0.getType() != Op1.getType())
4245 return false;
4246
4247 switch (Op0.getType()) {
4249 return Op0.getReg() == Op1.getReg();
4251 return Op0.getImm() == Op1.getImm();
4252 default:
4253 llvm_unreachable("Didn't expect to be comparing these operand types");
4254 }
4255}
4256
4258 const MachineOperand &MO) const {
4259 const MCInstrDesc &InstDesc = MI.getDesc();
4260 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
4261
4262 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
4263
4265 return true;
4266
4267 if (OpInfo.RegClass < 0)
4268 return false;
4269
4270 if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
4271 if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
4272 OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
4273 AMDGPU::OpName::src2))
4274 return false;
4275 return RI.opCanUseInlineConstant(OpInfo.OperandType);
4276 }
4277
4278 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
4279 return false;
4280
4281 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
4282 return true;
4283
4284 return ST.hasVOP3Literal();
4285}
4286
4287bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
4288 // GFX90A does not have V_MUL_LEGACY_F32_e32.
4289 if (Opcode == AMDGPU::V_MUL_LEGACY_F32_e64 && ST.hasGFX90AInsts())
4290 return false;
4291
4292 int Op32 = AMDGPU::getVOPe32(Opcode);
4293 if (Op32 == -1)
4294 return false;
4295
4296 return pseudoToMCOpcode(Op32) != -1;
4297}
4298
4299bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
4300 // The src0_modifier operand is present on all instructions
4301 // that have modifiers.
4302
4303 return AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers);
4304}
4305
4307 unsigned OpName) const {
4308 const MachineOperand *Mods = getNamedOperand(MI, OpName);
4309 return Mods && Mods->getImm();
4310}
4311
4313 return any_of(ModifierOpNames,
4314 [&](unsigned Name) { return hasModifiersSet(MI, Name); });
4315}
4316
4318 const MachineRegisterInfo &MRI) const {
4319 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4320 // Can't shrink instruction with three operands.
4321 if (Src2) {
4322 switch (MI.getOpcode()) {
4323 default: return false;
4324
4325 case AMDGPU::V_ADDC_U32_e64:
4326 case AMDGPU::V_SUBB_U32_e64:
4327 case AMDGPU::V_SUBBREV_U32_e64: {
4328 const MachineOperand *Src1
4329 = getNamedOperand(MI, AMDGPU::OpName::src1);
4330 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
4331 return false;
4332 // Additional verification is needed for sdst/src2.
4333 return true;
4334 }
4335 case AMDGPU::V_MAC_F16_e64:
4336 case AMDGPU::V_MAC_F32_e64:
4337 case AMDGPU::V_MAC_LEGACY_F32_e64:
4338 case AMDGPU::V_FMAC_F16_e64:
4339 case AMDGPU::V_FMAC_F16_t16_e64:
4340 case AMDGPU::V_FMAC_F32_e64:
4341 case AMDGPU::V_FMAC_F64_e64:
4342 case AMDGPU::V_FMAC_LEGACY_F32_e64:
4343 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
4344 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
4345 return false;
4346 break;
4347
4348 case AMDGPU::V_CNDMASK_B32_e64:
4349 break;
4350 }
4351 }
4352
4353 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
4354 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
4355 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
4356 return false;
4357
4358 // We don't need to check src0, all input types are legal, so just make sure
4359 // src0 isn't using any modifiers.
4360 if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
4361 return false;
4362
4363 // Can it be shrunk to a valid 32 bit opcode?
4364 if (!hasVALU32BitEncoding(MI.getOpcode()))
4365 return false;
4366
4367 // Check output modifiers
4368 return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
4369 !hasModifiersSet(MI, AMDGPU::OpName::clamp);
4370}
4371
4372// Set VCC operand with all flags from \p Orig, except for setting it as
4373// implicit.
4375 const MachineOperand &Orig) {
4376
4377 for (MachineOperand &Use : MI.implicit_operands()) {
4378 if (Use.isUse() &&
4379 (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
4380 Use.setIsUndef(Orig.isUndef());
4381 Use.setIsKill(Orig.isKill());
4382 return;
4383 }
4384 }
4385}
4386
4388 unsigned Op32) const {
4389 MachineBasicBlock *MBB = MI.getParent();
4390 MachineInstrBuilder Inst32 =
4391 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32))
4392 .setMIFlags(MI.getFlags());
4393
4394 // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
4395 // For VOPC instructions, this is replaced by an implicit def of vcc.
4396 if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::vdst)) {
4397 // dst
4398 Inst32.add(MI.getOperand(0));
4399 } else if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::sdst)) {
4400 // VOPCX instructions won't be writing to an explicit dst, so this should
4401 // not fail for these instructions.
4402 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
4403 (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
4404 "Unexpected case");
4405 }
4406
4407 Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
4408
4409 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
4410 if (Src1)
4411 Inst32.add(*Src1);
4412
4413 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4414
4415 if (Src2) {
4416 int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
4417 if (Op32Src2Idx != -1) {
4418 Inst32.add(*Src2);
4419 } else {
4420 // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
4421 // replaced with an implicit read of vcc or vcc_lo. The implicit read
4422 // of vcc was already added during the initial BuildMI, but we
4423 // 1) may need to change vcc to vcc_lo to preserve the original register
4424 // 2) have to preserve the original flags.
4425 fixImplicitOperands(*Inst32);
4426 copyFlagsToImplicitVCC(*Inst32, *Src2);
4427 }
4428 }
4429
4430 return Inst32;
4431}
4432
4434 const MachineOperand &MO,
4435 const MCOperandInfo &OpInfo) const {
4436 // Literal constants use the constant bus.
4437 if (!MO.isReg())
4438 return !isInlineConstant(MO, OpInfo);
4439
4440 if (!MO.isUse())
4441 return false;
4442
4443 if (MO.getReg().isVirtual())
4444 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
4445
4446 // Null is free
4447 if (MO.getReg() == AMDGPU::SGPR_NULL || MO.getReg() == AMDGPU::SGPR_NULL64)
4448 return false;
4449
4450 // SGPRs use the constant bus
4451 if (MO.isImplicit()) {
4452 return MO.getReg() == AMDGPU::M0 ||
4453 MO.getReg() == AMDGPU::VCC ||
4454 MO.getReg() == AMDGPU::VCC_LO;
4455 } else {
4456 return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
4457 AMDGPU::SReg_64RegClass.contains(MO.getReg());
4458 }
4459}
4460
4462 for (const MachineOperand &MO : MI.implicit_operands()) {
4463 // We only care about reads.
4464 if (MO.isDef())
4465 continue;
4466
4467 switch (MO.getReg()) {
4468 case AMDGPU::VCC:
4469 case AMDGPU::VCC_LO:
4470 case AMDGPU::VCC_HI:
4471 case AMDGPU::M0:
4472 case AMDGPU::FLAT_SCR:
4473 return MO.getReg();
4474
4475 default:
4476 break;
4477 }
4478 }
4479
4480 return Register();
4481}
4482
4483static bool shouldReadExec(const MachineInstr &MI) {
4484 if (SIInstrInfo::isVALU(MI)) {
4485 switch (MI.getOpcode()) {
4486 case AMDGPU::V_READLANE_B32:
4487 case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
4488 case AMDGPU::V_WRITELANE_B32:
4489 case AMDGPU::SI_SPILL_S32_TO_VGPR:
4490 return false;
4491 }
4492
4493 return true;
4494 }
4495
4496 if (MI.isPreISelOpcode() ||
4497 SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
4500 return false;
4501
4502 return true;
4503}
4504
4505static bool isSubRegOf(const SIRegisterInfo &TRI,
4506 const MachineOperand &SuperVec,
4507 const MachineOperand &SubReg) {
4508 if (SubReg.getReg().isPhysical())
4509 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
4510
4511 return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
4512 SubReg.getReg() == SuperVec.getReg();
4513}
4514
4516 StringRef &ErrInfo) const {
4517 uint16_t Opcode = MI.getOpcode();
4518 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
4519 return true;
4520
4521 const MachineFunction *MF = MI.getParent()->getParent();
4522 const MachineRegisterInfo &MRI = MF->getRegInfo();
4523
4524 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
4525 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
4526 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
4527 int Src3Idx = -1;
4528 if (Src0Idx == -1) {
4529 // VOPD V_DUAL_* instructions use different operand names.
4530 Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0X);
4531 Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vsrc1X);
4532 Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0Y);
4533 Src3Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vsrc1Y);
4534 }
4535
4536 // Make sure the number of operands is correct.
4537 const MCInstrDesc &Desc = get(Opcode);
4538 if (!Desc.isVariadic() &&
4539 Desc.getNumOperands() != MI.getNumExplicitOperands()) {
4540 ErrInfo = "Instruction has wrong number of operands.";
4541 return false;
4542 }
4543
4544 if (MI.isInlineAsm()) {
4545 // Verify register classes for inlineasm constraints.
4546 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
4547 I != E; ++I) {
4548 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
4549 if (!RC)
4550 continue;
4551
4552 const MachineOperand &Op = MI.getOperand(I);
4553 if (!Op.isReg())
4554 continue;
4555
4556 Register Reg = Op.getReg();
4557 if (!Reg.isVirtual() && !RC->contains(Reg)) {
4558 ErrInfo = "inlineasm operand has incorrect register class.";
4559 return false;
4560 }
4561 }
4562
4563 return true;
4564 }
4565
4566 if (isImage(MI) && MI.memoperands_empty() && MI.mayLoadOrStore()) {
4567 ErrInfo = "missing memory operand from image instruction.";
4568 return false;
4569 }
4570
4571 // Make sure the register classes are correct.
4572 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
4573 const MachineOperand &MO = MI.getOperand(i);
4574 if (MO.isFPImm()) {
4575 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
4576 "all fp values to integers.";
4577 return false;
4578 }
4579
4580 int RegClass = Desc.operands()[i].RegClass;
4581
4582 switch (Desc.operands()[i].OperandType) {
4584 if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
4585 ErrInfo = "Illegal immediate value for operand.";
4586 return false;
4587 }
4588 break;
4593 break;
4605 if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
4606 ErrInfo = "Illegal immediate value for operand.";
4607 return false;
4608 }
4609 break;
4610 }
4612 if (!MI.getOperand(i).isImm() || !isInlineConstant(MI, i)) {
4613 ErrInfo = "Expected inline constant for operand.";
4614 return false;
4615 }
4616 break;
4619 // Check if this operand is an immediate.
4620 // FrameIndex operands will be replaced by immediates, so they are
4621 // allowed.
4622 if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
4623 ErrInfo = "Expected immediate, but got non-immediate";
4624 return false;
4625 }
4626 [[fallthrough]];
4627 default:
4628 continue;
4629 }
4630
4631 if (!MO.isReg())
4632 continue;
4633 Register Reg = MO.getReg();
4634 if (!Reg)
4635 continue;
4636
4637 // FIXME: Ideally we would have separate instruction definitions with the
4638 // aligned register constraint.
4639 // FIXME: We do not verify inline asm operands, but custom inline asm
4640 // verification is broken anyway
4641 if (ST.needsAlignedVGPRs()) {
4642 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg);
4643 if (RI.hasVectorRegisters(RC) && MO.getSubReg()) {
4644 const TargetRegisterClass *SubRC =
4645 RI.getSubRegisterClass(RC, MO.getSubReg());
4646 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg());
4647 if (RC)
4648 RC = SubRC;
4649 }
4650
4651 // Check that this is the aligned version of the class.