LLVM  13.0.0git
SIInstrInfo.cpp
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1 //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI Implementation of TargetInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SIInstrInfo.h"
15 #include "AMDGPU.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "GCNHazardRecognizer.h"
18 #include "GCNSubtarget.h"
20 #include "SIMachineFunctionInfo.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/IntrinsicsAMDGPU.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "si-instr-info"
34 
35 #define GET_INSTRINFO_CTOR_DTOR
36 #include "AMDGPUGenInstrInfo.inc"
37 
38 namespace llvm {
39 
40 class AAResults;
41 
42 namespace AMDGPU {
43 #define GET_D16ImageDimIntrinsics_IMPL
44 #define GET_ImageDimIntrinsicTable_IMPL
45 #define GET_RsrcIntrinsics_IMPL
46 #include "AMDGPUGenSearchableTables.inc"
47 }
48 }
49 
50 
51 // Must be at least 4 to be able to branch over minimum unconditional branch
52 // code. This is only for making it possible to write reasonably small tests for
53 // long branches.
54 static cl::opt<unsigned>
55 BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
56  cl::desc("Restrict range of branch instructions (DEBUG)"));
57 
59  "amdgpu-fix-16-bit-physreg-copies",
60  cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"),
61  cl::init(true),
63 
65  : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
66  RI(ST), ST(ST) {
67  SchedModel.init(&ST);
68 }
69 
70 //===----------------------------------------------------------------------===//
71 // TargetInstrInfo callbacks
72 //===----------------------------------------------------------------------===//
73 
74 static unsigned getNumOperandsNoGlue(SDNode *Node) {
75  unsigned N = Node->getNumOperands();
76  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
77  --N;
78  return N;
79 }
80 
81 /// Returns true if both nodes have the same value for the given
82 /// operand \p Op, or if both nodes do not have this operand.
83 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
84  unsigned Opc0 = N0->getMachineOpcode();
85  unsigned Opc1 = N1->getMachineOpcode();
86 
87  int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
88  int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
89 
90  if (Op0Idx == -1 && Op1Idx == -1)
91  return true;
92 
93 
94  if ((Op0Idx == -1 && Op1Idx != -1) ||
95  (Op1Idx == -1 && Op0Idx != -1))
96  return false;
97 
98  // getNamedOperandIdx returns the index for the MachineInstr's operands,
99  // which includes the result as the first operand. We are indexing into the
100  // MachineSDNode's operands, so we need to skip the result operand to get
101  // the real index.
102  --Op0Idx;
103  --Op1Idx;
104 
105  return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
106 }
107 
109  AAResults *AA) const {
110  // TODO: The generic check fails for VALU instructions that should be
111  // rematerializable due to implicit reads of exec. We really want all of the
112  // generic logic for this except for this.
113  switch (MI.getOpcode()) {
114  case AMDGPU::V_MOV_B32_e32:
115  case AMDGPU::V_MOV_B32_e64:
116  case AMDGPU::V_MOV_B64_PSEUDO:
117  case AMDGPU::V_ACCVGPR_READ_B32_e64:
118  case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
119  // No non-standard implicit operands.
120  assert(MI.getDesc().getNumOperands() == 2);
121  assert(MI.getDesc().getNumImplicitDefs() == 0);
122  assert(MI.getDesc().getNumImplicitUses() == 1);
123  return MI.getNumOperands() == 3;
124  default:
125  return false;
126  }
127 }
128 
130  int64_t &Offset0,
131  int64_t &Offset1) const {
132  if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
133  return false;
134 
135  unsigned Opc0 = Load0->getMachineOpcode();
136  unsigned Opc1 = Load1->getMachineOpcode();
137 
138  // Make sure both are actually loads.
139  if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
140  return false;
141 
142  if (isDS(Opc0) && isDS(Opc1)) {
143 
144  // FIXME: Handle this case:
145  if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
146  return false;
147 
148  // Check base reg.
149  if (Load0->getOperand(0) != Load1->getOperand(0))
150  return false;
151 
152  // Skip read2 / write2 variants for simplicity.
153  // TODO: We should report true if the used offsets are adjacent (excluded
154  // st64 versions).
155  int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
156  int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
157  if (Offset0Idx == -1 || Offset1Idx == -1)
158  return false;
159 
160  // XXX - be careful of datalesss loads
161  // getNamedOperandIdx returns the index for MachineInstrs. Since they
162  // include the output in the operand list, but SDNodes don't, we need to
163  // subtract the index by one.
164  Offset0Idx -= get(Opc0).NumDefs;
165  Offset1Idx -= get(Opc1).NumDefs;
166  Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
167  Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
168  return true;
169  }
170 
171  if (isSMRD(Opc0) && isSMRD(Opc1)) {
172  // Skip time and cache invalidation instructions.
173  if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
174  AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
175  return false;
176 
178 
179  // Check base reg.
180  if (Load0->getOperand(0) != Load1->getOperand(0))
181  return false;
182 
183  const ConstantSDNode *Load0Offset =
184  dyn_cast<ConstantSDNode>(Load0->getOperand(1));
185  const ConstantSDNode *Load1Offset =
186  dyn_cast<ConstantSDNode>(Load1->getOperand(1));
187 
188  if (!Load0Offset || !Load1Offset)
189  return false;
190 
191  Offset0 = Load0Offset->getZExtValue();
192  Offset1 = Load1Offset->getZExtValue();
193  return true;
194  }
195 
196  // MUBUF and MTBUF can access the same addresses.
197  if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
198 
199  // MUBUF and MTBUF have vaddr at different indices.
200  if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
201  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
202  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
203  return false;
204 
205  int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
206  int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
207 
208  if (OffIdx0 == -1 || OffIdx1 == -1)
209  return false;
210 
211  // getNamedOperandIdx returns the index for MachineInstrs. Since they
212  // include the output in the operand list, but SDNodes don't, we need to
213  // subtract the index by one.
214  OffIdx0 -= get(Opc0).NumDefs;
215  OffIdx1 -= get(Opc1).NumDefs;
216 
217  SDValue Off0 = Load0->getOperand(OffIdx0);
218  SDValue Off1 = Load1->getOperand(OffIdx1);
219 
220  // The offset might be a FrameIndexSDNode.
221  if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
222  return false;
223 
224  Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
225  Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
226  return true;
227  }
228 
229  return false;
230 }
231 
232 static bool isStride64(unsigned Opc) {
233  switch (Opc) {
234  case AMDGPU::DS_READ2ST64_B32:
235  case AMDGPU::DS_READ2ST64_B64:
236  case AMDGPU::DS_WRITE2ST64_B32:
237  case AMDGPU::DS_WRITE2ST64_B64:
238  return true;
239  default:
240  return false;
241  }
242 }
243 
246  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
247  const TargetRegisterInfo *TRI) const {
248  if (!LdSt.mayLoadOrStore())
249  return false;
250 
251  unsigned Opc = LdSt.getOpcode();
252  OffsetIsScalable = false;
253  const MachineOperand *BaseOp, *OffsetOp;
254  int DataOpIdx;
255 
256  if (isDS(LdSt)) {
257  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
258  OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
259  if (OffsetOp) {
260  // Normal, single offset LDS instruction.
261  if (!BaseOp) {
262  // DS_CONSUME/DS_APPEND use M0 for the base address.
263  // TODO: find the implicit use operand for M0 and use that as BaseOp?
264  return false;
265  }
266  BaseOps.push_back(BaseOp);
267  Offset = OffsetOp->getImm();
268  // Get appropriate operand, and compute width accordingly.
269  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
270  if (DataOpIdx == -1)
271  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
272  Width = getOpSize(LdSt, DataOpIdx);
273  } else {
274  // The 2 offset instructions use offset0 and offset1 instead. We can treat
275  // these as a load with a single offset if the 2 offsets are consecutive.
276  // We will use this for some partially aligned loads.
277  const MachineOperand *Offset0Op =
278  getNamedOperand(LdSt, AMDGPU::OpName::offset0);
279  const MachineOperand *Offset1Op =
280  getNamedOperand(LdSt, AMDGPU::OpName::offset1);
281 
282  unsigned Offset0 = Offset0Op->getImm();
283  unsigned Offset1 = Offset1Op->getImm();
284  if (Offset0 + 1 != Offset1)
285  return false;
286 
287  // Each of these offsets is in element sized units, so we need to convert
288  // to bytes of the individual reads.
289 
290  unsigned EltSize;
291  if (LdSt.mayLoad())
292  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
293  else {
294  assert(LdSt.mayStore());
295  int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
296  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
297  }
298 
299  if (isStride64(Opc))
300  EltSize *= 64;
301 
302  BaseOps.push_back(BaseOp);
303  Offset = EltSize * Offset0;
304  // Get appropriate operand(s), and compute width accordingly.
305  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
306  if (DataOpIdx == -1) {
307  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
308  Width = getOpSize(LdSt, DataOpIdx);
309  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
310  Width += getOpSize(LdSt, DataOpIdx);
311  } else {
312  Width = getOpSize(LdSt, DataOpIdx);
313  }
314  }
315  return true;
316  }
317 
318  if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
319  const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
320  if (SOffset && SOffset->isReg()) {
321  // We can only handle this if it's a stack access, as any other resource
322  // would require reporting multiple base registers.
323  const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
324  if (AddrReg && !AddrReg->isFI())
325  return false;
326 
327  const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
328  const SIMachineFunctionInfo *MFI
330  if (RSrc->getReg() != MFI->getScratchRSrcReg())
331  return false;
332 
333  const MachineOperand *OffsetImm =
334  getNamedOperand(LdSt, AMDGPU::OpName::offset);
335  BaseOps.push_back(RSrc);
336  BaseOps.push_back(SOffset);
337  Offset = OffsetImm->getImm();
338  } else {
339  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
340  if (!BaseOp) // e.g. BUFFER_WBINVL1_VOL
341  return false;
342  BaseOps.push_back(BaseOp);
343 
344  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
345  if (BaseOp)
346  BaseOps.push_back(BaseOp);
347 
348  const MachineOperand *OffsetImm =
349  getNamedOperand(LdSt, AMDGPU::OpName::offset);
350  Offset = OffsetImm->getImm();
351  if (SOffset) // soffset can be an inline immediate.
352  Offset += SOffset->getImm();
353  }
354  // Get appropriate operand, and compute width accordingly.
355  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
356  if (DataOpIdx == -1)
357  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
358  Width = getOpSize(LdSt, DataOpIdx);
359  return true;
360  }
361 
362  if (isMIMG(LdSt)) {
363  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
364  BaseOps.push_back(&LdSt.getOperand(SRsrcIdx));
365  int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
366  if (VAddr0Idx >= 0) {
367  // GFX10 possible NSA encoding.
368  for (int I = VAddr0Idx; I < SRsrcIdx; ++I)
369  BaseOps.push_back(&LdSt.getOperand(I));
370  } else {
371  BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr));
372  }
373  Offset = 0;
374  // Get appropriate operand, and compute width accordingly.
375  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
376  Width = getOpSize(LdSt, DataOpIdx);
377  return true;
378  }
379 
380  if (isSMRD(LdSt)) {
381  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
382  if (!BaseOp) // e.g. S_MEMTIME
383  return false;
384  BaseOps.push_back(BaseOp);
385  OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
386  Offset = OffsetOp ? OffsetOp->getImm() : 0;
387  // Get appropriate operand, and compute width accordingly.
388  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
389  Width = getOpSize(LdSt, DataOpIdx);
390  return true;
391  }
392 
393  if (isFLAT(LdSt)) {
394  // Instructions have either vaddr or saddr or both or none.
395  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
396  if (BaseOp)
397  BaseOps.push_back(BaseOp);
398  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
399  if (BaseOp)
400  BaseOps.push_back(BaseOp);
401  Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
402  // Get appropriate operand, and compute width accordingly.
403  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
404  if (DataOpIdx == -1)
405  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
406  Width = getOpSize(LdSt, DataOpIdx);
407  return true;
408  }
409 
410  return false;
411 }
412 
413 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
415  const MachineInstr &MI2,
417  // Only examine the first "base" operand of each instruction, on the
418  // assumption that it represents the real base address of the memory access.
419  // Other operands are typically offsets or indices from this base address.
420  if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front()))
421  return true;
422 
423  if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
424  return false;
425 
426  auto MO1 = *MI1.memoperands_begin();
427  auto MO2 = *MI2.memoperands_begin();
428  if (MO1->getAddrSpace() != MO2->getAddrSpace())
429  return false;
430 
431  auto Base1 = MO1->getValue();
432  auto Base2 = MO2->getValue();
433  if (!Base1 || !Base2)
434  return false;
435  Base1 = getUnderlyingObject(Base1);
436  Base2 = getUnderlyingObject(Base2);
437 
438  if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
439  return false;
440 
441  return Base1 == Base2;
442 }
443 
446  unsigned NumLoads,
447  unsigned NumBytes) const {
448  // If the mem ops (to be clustered) do not have the same base ptr, then they
449  // should not be clustered
450  if (!BaseOps1.empty() && !BaseOps2.empty()) {
451  const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
452  const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
453  if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
454  return false;
455  } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
456  // If only one base op is empty, they do not have the same base ptr
457  return false;
458  }
459 
460  // In order to avoid regester pressure, on an average, the number of DWORDS
461  // loaded together by all clustered mem ops should not exceed 8. This is an
462  // empirical value based on certain observations and performance related
463  // experiments.
464  // The good thing about this heuristic is - it avoids clustering of too many
465  // sub-word loads, and also avoids clustering of wide loads. Below is the
466  // brief summary of how the heuristic behaves for various `LoadSize`.
467  // (1) 1 <= LoadSize <= 4: cluster at max 8 mem ops
468  // (2) 5 <= LoadSize <= 8: cluster at max 4 mem ops
469  // (3) 9 <= LoadSize <= 12: cluster at max 2 mem ops
470  // (4) 13 <= LoadSize <= 16: cluster at max 2 mem ops
471  // (5) LoadSize >= 17: do not cluster
472  const unsigned LoadSize = NumBytes / NumLoads;
473  const unsigned NumDWORDs = ((LoadSize + 3) / 4) * NumLoads;
474  return NumDWORDs <= 8;
475 }
476 
477 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
478 // the first 16 loads will be interleaved with the stores, and the next 16 will
479 // be clustered as expected. It should really split into 2 16 store batches.
480 //
481 // Loads are clustered until this returns false, rather than trying to schedule
482 // groups of stores. This also means we have to deal with saying different
483 // address space loads should be clustered, and ones which might cause bank
484 // conflicts.
485 //
486 // This might be deprecated so it might not be worth that much effort to fix.
488  int64_t Offset0, int64_t Offset1,
489  unsigned NumLoads) const {
490  assert(Offset1 > Offset0 &&
491  "Second offset should be larger than first offset!");
492  // If we have less than 16 loads in a row, and the offsets are within 64
493  // bytes, then schedule together.
494 
495  // A cacheline is 64 bytes (for global memory).
496  return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
497 }
498 
501  const DebugLoc &DL, MCRegister DestReg,
502  MCRegister SrcReg, bool KillSrc,
503  const char *Msg = "illegal SGPR to VGPR copy") {
504  MachineFunction *MF = MBB.getParent();
505  DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(), Msg, DL, DS_Error);
506  LLVMContext &C = MF->getFunction().getContext();
507  C.diagnose(IllegalCopy);
508 
509  BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
510  .addReg(SrcReg, getKillRegState(KillSrc));
511 }
512 
513 /// Handle copying from SGPR to AGPR, or from AGPR to AGPR. It is not possible
514 /// to directly copy, so an intermediate VGPR needs to be used.
515 static void indirectCopyToAGPR(const SIInstrInfo &TII,
518  const DebugLoc &DL, MCRegister DestReg,
519  MCRegister SrcReg, bool KillSrc,
520  RegScavenger &RS,
521  Register ImpDefSuperReg = Register(),
522  Register ImpUseSuperReg = Register()) {
523  const SIRegisterInfo &RI = TII.getRegisterInfo();
524 
525  assert(AMDGPU::SReg_32RegClass.contains(SrcReg) ||
526  AMDGPU::AGPR_32RegClass.contains(SrcReg));
527 
528  // First try to find defining accvgpr_write to avoid temporary registers.
529  for (auto Def = MI, E = MBB.begin(); Def != E; ) {
530  --Def;
531  if (!Def->definesRegister(SrcReg, &RI))
532  continue;
533  if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64)
534  break;
535 
536  MachineOperand &DefOp = Def->getOperand(1);
537  assert(DefOp.isReg() || DefOp.isImm());
538 
539  if (DefOp.isReg()) {
540  // Check that register source operand if not clobbered before MI.
541  // Immediate operands are always safe to propagate.
542  bool SafeToPropagate = true;
543  for (auto I = Def; I != MI && SafeToPropagate; ++I)
544  if (I->modifiesRegister(DefOp.getReg(), &RI))
545  SafeToPropagate = false;
546 
547  if (!SafeToPropagate)
548  break;
549 
550  DefOp.setIsKill(false);
551  }
552 
554  BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
555  .add(DefOp);
556  if (ImpDefSuperReg)
557  Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
558 
559  if (ImpUseSuperReg) {
560  Builder.addReg(ImpUseSuperReg,
562  }
563 
564  return;
565  }
566 
567  RS.enterBasicBlock(MBB);
568  RS.forward(MI);
569 
570  // Ideally we want to have three registers for a long reg_sequence copy
571  // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
572  unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
573  *MBB.getParent());
574 
575  // Registers in the sequence are allocated contiguously so we can just
576  // use register number to pick one of three round-robin temps.
577  unsigned RegNo = DestReg % 3;
578  Register Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
579  if (!Tmp)
580  report_fatal_error("Cannot scavenge VGPR to copy to AGPR");
581  RS.setRegUsed(Tmp);
582 
583  if (!TII.getSubtarget().hasGFX90AInsts()) {
584  // Only loop through if there are any free registers left, otherwise
585  // scavenger may report a fatal error without emergency spill slot
586  // or spill with the slot.
587  while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
588  Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
589  if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
590  break;
591  Tmp = Tmp2;
592  RS.setRegUsed(Tmp);
593  }
594  }
595 
596  // Insert copy to temporary VGPR.
597  unsigned TmpCopyOp = AMDGPU::V_MOV_B32_e32;
598  if (AMDGPU::AGPR_32RegClass.contains(SrcReg)) {
599  TmpCopyOp = AMDGPU::V_ACCVGPR_READ_B32_e64;
600  } else {
601  assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
602  }
603 
604  MachineInstrBuilder UseBuilder = BuildMI(MBB, MI, DL, TII.get(TmpCopyOp), Tmp)
605  .addReg(SrcReg, getKillRegState(KillSrc));
606  if (ImpUseSuperReg) {
607  UseBuilder.addReg(ImpUseSuperReg,
609  }
610 
611  MachineInstrBuilder DefBuilder
612  = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
613  .addReg(Tmp, RegState::Kill);
614 
615  if (ImpDefSuperReg)
616  DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
617 }
618 
621  MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
622  const TargetRegisterClass *RC, bool Forward) {
623  const SIRegisterInfo &RI = TII.getRegisterInfo();
624  ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4);
626  MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
627 
628  for (unsigned Idx = 0; Idx < BaseIndices.size(); ++Idx) {
629  int16_t SubIdx = BaseIndices[Idx];
630  Register Reg = RI.getSubReg(DestReg, SubIdx);
631  unsigned Opcode = AMDGPU::S_MOV_B32;
632 
633  // Is SGPR aligned? If so try to combine with next.
634  Register Src = RI.getSubReg(SrcReg, SubIdx);
635  bool AlignedDest = ((Reg - AMDGPU::SGPR0) % 2) == 0;
636  bool AlignedSrc = ((Src - AMDGPU::SGPR0) % 2) == 0;
637  if (AlignedDest && AlignedSrc && (Idx + 1 < BaseIndices.size())) {
638  // Can use SGPR64 copy
639  unsigned Channel = RI.getChannelFromSubReg(SubIdx);
640  SubIdx = RI.getSubRegFromChannel(Channel, 2);
641  Opcode = AMDGPU::S_MOV_B64;
642  Idx++;
643  }
644 
645  LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), RI.getSubReg(DestReg, SubIdx))
646  .addReg(RI.getSubReg(SrcReg, SubIdx))
647  .addReg(SrcReg, RegState::Implicit);
648 
649  if (!FirstMI)
650  FirstMI = LastMI;
651 
652  if (!Forward)
653  I--;
654  }
655 
656  assert(FirstMI && LastMI);
657  if (!Forward)
658  std::swap(FirstMI, LastMI);
659 
660  FirstMI->addOperand(
661  MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
662 
663  if (KillSrc)
664  LastMI->addRegisterKilled(SrcReg, &RI);
665 }
666 
669  const DebugLoc &DL, MCRegister DestReg,
670  MCRegister SrcReg, bool KillSrc) const {
671  const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
672 
673  // FIXME: This is hack to resolve copies between 16 bit and 32 bit
674  // registers until all patterns are fixed.
675  if (Fix16BitCopies &&
676  ((RI.getRegSizeInBits(*RC) == 16) ^
677  (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) {
678  MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg;
679  MCRegister Super = RI.get32BitRegister(RegToFix);
680  assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix);
681  RegToFix = Super;
682 
683  if (DestReg == SrcReg) {
684  // Insert empty bundle since ExpandPostRA expects an instruction here.
685  BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
686  return;
687  }
688 
689  RC = RI.getPhysRegClass(DestReg);
690  }
691 
692  if (RC == &AMDGPU::VGPR_32RegClass) {
693  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
694  AMDGPU::SReg_32RegClass.contains(SrcReg) ||
695  AMDGPU::AGPR_32RegClass.contains(SrcReg));
696  unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
697  AMDGPU::V_ACCVGPR_READ_B32_e64 : AMDGPU::V_MOV_B32_e32;
698  BuildMI(MBB, MI, DL, get(Opc), DestReg)
699  .addReg(SrcReg, getKillRegState(KillSrc));
700  return;
701  }
702 
703  if (RC == &AMDGPU::SReg_32_XM0RegClass ||
704  RC == &AMDGPU::SReg_32RegClass) {
705  if (SrcReg == AMDGPU::SCC) {
706  BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
707  .addImm(1)
708  .addImm(0);
709  return;
710  }
711 
712  if (DestReg == AMDGPU::VCC_LO) {
713  if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
714  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
715  .addReg(SrcReg, getKillRegState(KillSrc));
716  } else {
717  // FIXME: Hack until VReg_1 removed.
718  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
719  BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
720  .addImm(0)
721  .addReg(SrcReg, getKillRegState(KillSrc));
722  }
723 
724  return;
725  }
726 
727  if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
728  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
729  return;
730  }
731 
732  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
733  .addReg(SrcReg, getKillRegState(KillSrc));
734  return;
735  }
736 
737  if (RC == &AMDGPU::SReg_64RegClass) {
738  if (SrcReg == AMDGPU::SCC) {
739  BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg)
740  .addImm(1)
741  .addImm(0);
742  return;
743  }
744 
745  if (DestReg == AMDGPU::VCC) {
746  if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
747  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
748  .addReg(SrcReg, getKillRegState(KillSrc));
749  } else {
750  // FIXME: Hack until VReg_1 removed.
751  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
752  BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
753  .addImm(0)
754  .addReg(SrcReg, getKillRegState(KillSrc));
755  }
756 
757  return;
758  }
759 
760  if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
761  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
762  return;
763  }
764 
765  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
766  .addReg(SrcReg, getKillRegState(KillSrc));
767  return;
768  }
769 
770  if (DestReg == AMDGPU::SCC) {
771  // Copying 64-bit or 32-bit sources to SCC barely makes sense,
772  // but SelectionDAG emits such copies for i1 sources.
773  if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
774  // This copy can only be produced by patterns
775  // with explicit SCC, which are known to be enabled
776  // only for subtargets with S_CMP_LG_U64 present.
778  BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U64))
779  .addReg(SrcReg, getKillRegState(KillSrc))
780  .addImm(0);
781  } else {
782  assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
783  BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
784  .addReg(SrcReg, getKillRegState(KillSrc))
785  .addImm(0);
786  }
787 
788  return;
789  }
790 
791  if (RC == &AMDGPU::AGPR_32RegClass) {
792  if (AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
793  BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
794  .addReg(SrcReg, getKillRegState(KillSrc));
795  return;
796  }
797 
798  if (AMDGPU::AGPR_32RegClass.contains(SrcReg) && ST.hasGFX90AInsts()) {
799  BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_MOV_B32), DestReg)
800  .addReg(SrcReg, getKillRegState(KillSrc));
801  return;
802  }
803 
804  // FIXME: Pass should maintain scavenger to avoid scan through the block on
805  // every AGPR spill.
806  RegScavenger RS;
807  indirectCopyToAGPR(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RS);
808  return;
809  }
810 
811  const unsigned Size = RI.getRegSizeInBits(*RC);
812  if (Size == 16) {
813  assert(AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
814  AMDGPU::VGPR_HI16RegClass.contains(SrcReg) ||
815  AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
816  AMDGPU::AGPR_LO16RegClass.contains(SrcReg));
817 
818  bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
819  bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
820  bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
821  bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
822  bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) ||
823  AMDGPU::SReg_LO16RegClass.contains(DestReg) ||
824  AMDGPU::AGPR_LO16RegClass.contains(DestReg);
825  bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
826  AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
827  AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
828  MCRegister NewDestReg = RI.get32BitRegister(DestReg);
829  MCRegister NewSrcReg = RI.get32BitRegister(SrcReg);
830 
831  if (IsSGPRDst) {
832  if (!IsSGPRSrc) {
833  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
834  return;
835  }
836 
837  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
838  .addReg(NewSrcReg, getKillRegState(KillSrc));
839  return;
840  }
841 
842  if (IsAGPRDst || IsAGPRSrc) {
843  if (!DstLow || !SrcLow) {
844  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
845  "Cannot use hi16 subreg with an AGPR!");
846  }
847 
848  copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
849  return;
850  }
851 
852  if (IsSGPRSrc && !ST.hasSDWAScalar()) {
853  if (!DstLow || !SrcLow) {
854  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
855  "Cannot use hi16 subreg on VI!");
856  }
857 
858  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
859  .addReg(NewSrcReg, getKillRegState(KillSrc));
860  return;
861  }
862 
863  auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
864  .addImm(0) // src0_modifiers
865  .addReg(NewSrcReg)
866  .addImm(0) // clamp
872  .addReg(NewDestReg, RegState::Implicit | RegState::Undef);
873  // First implicit operand is $exec.
874  MIB->tieOperands(0, MIB->getNumOperands() - 1);
875  return;
876  }
877 
878  const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg);
879  if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
880  if (ST.hasPackedFP32Ops()) {
881  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestReg)
883  .addReg(SrcReg)
885  .addReg(SrcReg)
886  .addImm(0) // op_sel_lo
887  .addImm(0) // op_sel_hi
888  .addImm(0) // neg_lo
889  .addImm(0) // neg_hi
890  .addImm(0) // clamp
891  .addReg(SrcReg, getKillRegState(KillSrc) | RegState::Implicit);
892  return;
893  }
894  }
895 
896  const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
897  if (RI.isSGPRClass(RC)) {
898  if (!RI.isSGPRClass(SrcRC)) {
899  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
900  return;
901  }
902  expandSGPRCopy(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RC, Forward);
903  return;
904  }
905 
906  unsigned EltSize = 4;
907  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
908  if (RI.hasAGPRs(RC)) {
909  Opcode = (RI.hasVGPRs(SrcRC)) ?
910  AMDGPU::V_ACCVGPR_WRITE_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
911  } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(SrcRC)) {
912  Opcode = AMDGPU::V_ACCVGPR_READ_B32_e64;
913  } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) &&
914  (RI.isProperlyAlignedRC(*RC) &&
915  (SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
916  // TODO: In 96-bit case, could do a 64-bit mov and then a 32-bit mov.
917  if (ST.hasPackedFP32Ops()) {
918  Opcode = AMDGPU::V_PK_MOV_B32;
919  EltSize = 8;
920  }
921  }
922 
923  // For the cases where we need an intermediate instruction/temporary register
924  // (destination is an AGPR), we need a scavenger.
925  //
926  // FIXME: The pass should maintain this for us so we don't have to re-scan the
927  // whole block for every handled copy.
928  std::unique_ptr<RegScavenger> RS;
929  if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
930  RS.reset(new RegScavenger());
931 
932  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
933 
934  // If there is an overlap, we can't kill the super-register on the last
935  // instruction, since it will also kill the components made live by this def.
936  const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg);
937 
938  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
939  unsigned SubIdx;
940  if (Forward)
941  SubIdx = SubIndices[Idx];
942  else
943  SubIdx = SubIndices[SubIndices.size() - Idx - 1];
944 
945  bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
946 
947  if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
948  Register ImpDefSuper = Idx == 0 ? Register(DestReg) : Register();
949  Register ImpUseSuper = SrcReg;
950  indirectCopyToAGPR(*this, MBB, MI, DL, RI.getSubReg(DestReg, SubIdx),
951  RI.getSubReg(SrcReg, SubIdx), UseKill, *RS,
952  ImpDefSuper, ImpUseSuper);
953  } else if (Opcode == AMDGPU::V_PK_MOV_B32) {
954  Register DstSubReg = RI.getSubReg(DestReg, SubIdx);
955  Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
956  MachineInstrBuilder MIB =
957  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DstSubReg)
959  .addReg(SrcSubReg)
961  .addReg(SrcSubReg)
962  .addImm(0) // op_sel_lo
963  .addImm(0) // op_sel_hi
964  .addImm(0) // neg_lo
965  .addImm(0) // neg_hi
966  .addImm(0) // clamp
967  .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
968  if (Idx == 0)
970  } else {
972  BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx))
973  .addReg(RI.getSubReg(SrcReg, SubIdx));
974  if (Idx == 0)
975  Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
976 
977  Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
978  }
979  }
980 }
981 
982 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
983  int NewOpc;
984 
985  // Try to map original to commuted opcode
986  NewOpc = AMDGPU::getCommuteRev(Opcode);
987  if (NewOpc != -1)
988  // Check if the commuted (REV) opcode exists on the target.
989  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
990 
991  // Try to map commuted to original opcode
992  NewOpc = AMDGPU::getCommuteOrig(Opcode);
993  if (NewOpc != -1)
994  // Check if the original (non-REV) opcode exists on the target.
995  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
996 
997  return Opcode;
998 }
999 
1002  const DebugLoc &DL, unsigned DestReg,
1003  int64_t Value) const {
1005  const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1006  if (RegClass == &AMDGPU::SReg_32RegClass ||
1007  RegClass == &AMDGPU::SGPR_32RegClass ||
1008  RegClass == &AMDGPU::SReg_32_XM0RegClass ||
1009  RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
1010  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
1011  .addImm(Value);
1012  return;
1013  }
1014 
1015  if (RegClass == &AMDGPU::SReg_64RegClass ||
1016  RegClass == &AMDGPU::SGPR_64RegClass ||
1017  RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
1018  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
1019  .addImm(Value);
1020  return;
1021  }
1022 
1023  if (RegClass == &AMDGPU::VGPR_32RegClass) {
1024  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
1025  .addImm(Value);
1026  return;
1027  }
1028  if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {
1029  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
1030  .addImm(Value);
1031  return;
1032  }
1033 
1034  unsigned EltSize = 4;
1035  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1036  if (RI.isSGPRClass(RegClass)) {
1037  if (RI.getRegSizeInBits(*RegClass) > 32) {
1038  Opcode = AMDGPU::S_MOV_B64;
1039  EltSize = 8;
1040  } else {
1041  Opcode = AMDGPU::S_MOV_B32;
1042  EltSize = 4;
1043  }
1044  }
1045 
1046  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
1047  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1048  int64_t IdxValue = Idx == 0 ? Value : 0;
1049 
1051  get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx]));
1052  Builder.addImm(IdxValue);
1053  }
1054 }
1055 
1056 const TargetRegisterClass *
1058  return &AMDGPU::VGPR_32RegClass;
1059 }
1060 
1063  const DebugLoc &DL, Register DstReg,
1065  Register TrueReg,
1066  Register FalseReg) const {
1068  const TargetRegisterClass *BoolXExecRC =
1069  RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
1070  assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
1071  "Not a VGPR32 reg");
1072 
1073  if (Cond.size() == 1) {
1074  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1075  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1076  .add(Cond[0]);
1077  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1078  .addImm(0)
1079  .addReg(FalseReg)
1080  .addImm(0)
1081  .addReg(TrueReg)
1082  .addReg(SReg);
1083  } else if (Cond.size() == 2) {
1084  assert(Cond[0].isImm() && "Cond[0] is not an immediate");
1085  switch (Cond[0].getImm()) {
1086  case SIInstrInfo::SCC_TRUE: {
1087  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1088  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1089  : AMDGPU::S_CSELECT_B64), SReg)
1090  .addImm(1)
1091  .addImm(0);
1092  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1093  .addImm(0)
1094  .addReg(FalseReg)
1095  .addImm(0)
1096  .addReg(TrueReg)
1097  .addReg(SReg);
1098  break;
1099  }
1100  case SIInstrInfo::SCC_FALSE: {
1101  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1102  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1103  : AMDGPU::S_CSELECT_B64), SReg)
1104  .addImm(0)
1105  .addImm(1);
1106  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1107  .addImm(0)
1108  .addReg(FalseReg)
1109  .addImm(0)
1110  .addReg(TrueReg)
1111  .addReg(SReg);
1112  break;
1113  }
1114  case SIInstrInfo::VCCNZ: {
1115  MachineOperand RegOp = Cond[1];
1116  RegOp.setImplicit(false);
1117  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1118  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1119  .add(RegOp);
1120  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1121  .addImm(0)
1122  .addReg(FalseReg)
1123  .addImm(0)
1124  .addReg(TrueReg)
1125  .addReg(SReg);
1126  break;
1127  }
1128  case SIInstrInfo::VCCZ: {
1129  MachineOperand RegOp = Cond[1];
1130  RegOp.setImplicit(false);
1131  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1132  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1133  .add(RegOp);
1134  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1135  .addImm(0)
1136  .addReg(TrueReg)
1137  .addImm(0)
1138  .addReg(FalseReg)
1139  .addReg(SReg);
1140  break;
1141  }
1142  case SIInstrInfo::EXECNZ: {
1143  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1145  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1146  : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1147  .addImm(0);
1148  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1149  : AMDGPU::S_CSELECT_B64), SReg)
1150  .addImm(1)
1151  .addImm(0);
1152  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1153  .addImm(0)
1154  .addReg(FalseReg)
1155  .addImm(0)
1156  .addReg(TrueReg)
1157  .addReg(SReg);
1158  break;
1159  }
1160  case SIInstrInfo::EXECZ: {
1161  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1163  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1164  : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1165  .addImm(0);
1166  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1167  : AMDGPU::S_CSELECT_B64), SReg)
1168  .addImm(0)
1169  .addImm(1);
1170  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1171  .addImm(0)
1172  .addReg(FalseReg)
1173  .addImm(0)
1174  .addReg(TrueReg)
1175  .addReg(SReg);
1176  llvm_unreachable("Unhandled branch predicate EXECZ");
1177  break;
1178  }
1179  default:
1180  llvm_unreachable("invalid branch predicate");
1181  }
1182  } else {
1183  llvm_unreachable("Can only handle Cond size 1 or 2");
1184  }
1185 }
1186 
1189  const DebugLoc &DL,
1190  Register SrcReg, int Value) const {
1193  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
1194  .addImm(Value)
1195  .addReg(SrcReg);
1196 
1197  return Reg;
1198 }
1199 
1202  const DebugLoc &DL,
1203  Register SrcReg, int Value) const {
1206  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1207  .addImm(Value)
1208  .addReg(SrcReg);
1209 
1210  return Reg;
1211 }
1212 
1213 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
1214 
1215  if (RI.hasAGPRs(DstRC))
1216  return AMDGPU::COPY;
1217  if (RI.getRegSizeInBits(*DstRC) == 32) {
1218  return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1219  } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1220  return AMDGPU::S_MOV_B64;
1221  } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
1222  return AMDGPU::V_MOV_B64_PSEUDO;
1223  }
1224  return AMDGPU::COPY;
1225 }
1226 
1227 const MCInstrDesc &
1229  bool IsIndirectSrc) const {
1230  if (IsIndirectSrc) {
1231  if (VecSize <= 32) // 4 bytes
1232  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1);
1233  if (VecSize <= 64) // 8 bytes
1234  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2);
1235  if (VecSize <= 96) // 12 bytes
1236  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3);
1237  if (VecSize <= 128) // 16 bytes
1238  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4);
1239  if (VecSize <= 160) // 20 bytes
1240  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5);
1241  if (VecSize <= 256) // 32 bytes
1242  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8);
1243  if (VecSize <= 512) // 64 bytes
1244  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16);
1245  if (VecSize <= 1024) // 128 bytes
1246  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32);
1247 
1248  llvm_unreachable("unsupported size for IndirectRegReadGPRIDX pseudos");
1249  }
1250 
1251  if (VecSize <= 32) // 4 bytes
1252  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1);
1253  if (VecSize <= 64) // 8 bytes
1254  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2);
1255  if (VecSize <= 96) // 12 bytes
1256  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3);
1257  if (VecSize <= 128) // 16 bytes
1258  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4);
1259  if (VecSize <= 160) // 20 bytes
1260  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5);
1261  if (VecSize <= 256) // 32 bytes
1262  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8);
1263  if (VecSize <= 512) // 64 bytes
1264  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16);
1265  if (VecSize <= 1024) // 128 bytes
1266  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32);
1267 
1268  llvm_unreachable("unsupported size for IndirectRegWriteGPRIDX pseudos");
1269 }
1270 
1271 static unsigned getIndirectVGPRWriteMovRelPseudoOpc(unsigned VecSize) {
1272  if (VecSize <= 32) // 4 bytes
1273  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1274  if (VecSize <= 64) // 8 bytes
1275  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1276  if (VecSize <= 96) // 12 bytes
1277  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1278  if (VecSize <= 128) // 16 bytes
1279  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1280  if (VecSize <= 160) // 20 bytes
1281  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1282  if (VecSize <= 256) // 32 bytes
1283  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1284  if (VecSize <= 512) // 64 bytes
1285  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1286  if (VecSize <= 1024) // 128 bytes
1287  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1288 
1289  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1290 }
1291 
1292 static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
1293  if (VecSize <= 32) // 4 bytes
1294  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1295  if (VecSize <= 64) // 8 bytes
1296  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1297  if (VecSize <= 96) // 12 bytes
1298  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1299  if (VecSize <= 128) // 16 bytes
1300  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1301  if (VecSize <= 160) // 20 bytes
1302  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1303  if (VecSize <= 256) // 32 bytes
1304  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1305  if (VecSize <= 512) // 64 bytes
1306  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1307  if (VecSize <= 1024) // 128 bytes
1308  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1309 
1310  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1311 }
1312 
1313 static unsigned getIndirectSGPRWriteMovRelPseudo64(unsigned VecSize) {
1314  if (VecSize <= 64) // 8 bytes
1315  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1;
1316  if (VecSize <= 128) // 16 bytes
1317  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2;
1318  if (VecSize <= 256) // 32 bytes
1319  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4;
1320  if (VecSize <= 512) // 64 bytes
1321  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8;
1322  if (VecSize <= 1024) // 128 bytes
1323  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16;
1324 
1325  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1326 }
1327 
1328 const MCInstrDesc &
1329 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,
1330  bool IsSGPR) const {
1331  if (IsSGPR) {
1332  switch (EltSize) {
1333  case 32:
1334  return get(getIndirectSGPRWriteMovRelPseudo32(VecSize));
1335  case 64:
1336  return get(getIndirectSGPRWriteMovRelPseudo64(VecSize));
1337  default:
1338  llvm_unreachable("invalid reg indexing elt size");
1339  }
1340  }
1341 
1342  assert(EltSize == 32 && "invalid reg indexing elt size");
1343  return get(getIndirectVGPRWriteMovRelPseudoOpc(VecSize));
1344 }
1345 
1346 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
1347  switch (Size) {
1348  case 4:
1349  return AMDGPU::SI_SPILL_S32_SAVE;
1350  case 8:
1351  return AMDGPU::SI_SPILL_S64_SAVE;
1352  case 12:
1353  return AMDGPU::SI_SPILL_S96_SAVE;
1354  case 16:
1355  return AMDGPU::SI_SPILL_S128_SAVE;
1356  case 20:
1357  return AMDGPU::SI_SPILL_S160_SAVE;
1358  case 24:
1359  return AMDGPU::SI_SPILL_S192_SAVE;
1360  case 32:
1361  return AMDGPU::SI_SPILL_S256_SAVE;
1362  case 64:
1363  return AMDGPU::SI_SPILL_S512_SAVE;
1364  case 128:
1365  return AMDGPU::SI_SPILL_S1024_SAVE;
1366  default:
1367  llvm_unreachable("unknown register size");
1368  }
1369 }
1370 
1371 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
1372  switch (Size) {
1373  case 4:
1374  return AMDGPU::SI_SPILL_V32_SAVE;
1375  case 8:
1376  return AMDGPU::SI_SPILL_V64_SAVE;
1377  case 12:
1378  return AMDGPU::SI_SPILL_V96_SAVE;
1379  case 16:
1380  return AMDGPU::SI_SPILL_V128_SAVE;
1381  case 20:
1382  return AMDGPU::SI_SPILL_V160_SAVE;
1383  case 24:
1384  return AMDGPU::SI_SPILL_V192_SAVE;
1385  case 32:
1386  return AMDGPU::SI_SPILL_V256_SAVE;
1387  case 64:
1388  return AMDGPU::SI_SPILL_V512_SAVE;
1389  case 128:
1390  return AMDGPU::SI_SPILL_V1024_SAVE;
1391  default:
1392  llvm_unreachable("unknown register size");
1393  }
1394 }
1395 
1396 static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
1397  switch (Size) {
1398  case 4:
1399  return AMDGPU::SI_SPILL_A32_SAVE;
1400  case 8:
1401  return AMDGPU::SI_SPILL_A64_SAVE;
1402  case 12:
1403  return AMDGPU::SI_SPILL_A96_SAVE;
1404  case 16:
1405  return AMDGPU::SI_SPILL_A128_SAVE;
1406  case 20:
1407  return AMDGPU::SI_SPILL_A160_SAVE;
1408  case 24:
1409  return AMDGPU::SI_SPILL_A192_SAVE;
1410  case 32:
1411  return AMDGPU::SI_SPILL_A256_SAVE;
1412  case 64:
1413  return AMDGPU::SI_SPILL_A512_SAVE;
1414  case 128:
1415  return AMDGPU::SI_SPILL_A1024_SAVE;
1416  default:
1417  llvm_unreachable("unknown register size");
1418  }
1419 }
1420 
1423  Register SrcReg, bool isKill,
1424  int FrameIndex,
1425  const TargetRegisterClass *RC,
1426  const TargetRegisterInfo *TRI) const {
1427  MachineFunction *MF = MBB.getParent();
1429  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1430  const DebugLoc &DL = MBB.findDebugLoc(MI);
1431 
1432  MachinePointerInfo PtrInfo
1435  PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
1436  FrameInfo.getObjectAlign(FrameIndex));
1437  unsigned SpillSize = TRI->getSpillSize(*RC);
1438 
1439  if (RI.isSGPRClass(RC)) {
1440  MFI->setHasSpilledSGPRs();
1441  assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled");
1442  assert(SrcReg != AMDGPU::EXEC_LO && SrcReg != AMDGPU::EXEC_HI &&
1443  SrcReg != AMDGPU::EXEC && "exec should not be spilled");
1444 
1445  // We are only allowed to create one new instruction when spilling
1446  // registers, so we need to use pseudo instruction for spilling SGPRs.
1447  const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1448 
1449  // The SGPR spill/restore instructions only work on number sgprs, so we need
1450  // to make sure we are using the correct register class.
1451  if (SrcReg.isVirtual() && SpillSize == 4) {
1453  MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1454  }
1455 
1456  BuildMI(MBB, MI, DL, OpDesc)
1457  .addReg(SrcReg, getKillRegState(isKill)) // data
1458  .addFrameIndex(FrameIndex) // addr
1459  .addMemOperand(MMO)
1461 
1462  if (RI.spillSGPRToVGPR())
1463  FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1464  return;
1465  }
1466 
1467  unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize)
1468  : getVGPRSpillSaveOpcode(SpillSize);
1469  MFI->setHasSpilledVGPRs();
1470 
1471  BuildMI(MBB, MI, DL, get(Opcode))
1472  .addReg(SrcReg, getKillRegState(isKill)) // data
1473  .addFrameIndex(FrameIndex) // addr
1474  .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1475  .addImm(0) // offset
1476  .addMemOperand(MMO);
1477 }
1478 
1479 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
1480  switch (Size) {
1481  case 4:
1482  return AMDGPU::SI_SPILL_S32_RESTORE;
1483  case 8:
1484  return AMDGPU::SI_SPILL_S64_RESTORE;
1485  case 12:
1486  return AMDGPU::SI_SPILL_S96_RESTORE;
1487  case 16:
1488  return AMDGPU::SI_SPILL_S128_RESTORE;
1489  case 20:
1490  return AMDGPU::SI_SPILL_S160_RESTORE;
1491  case 24:
1492  return AMDGPU::SI_SPILL_S192_RESTORE;
1493  case 32:
1494  return AMDGPU::SI_SPILL_S256_RESTORE;
1495  case 64:
1496  return AMDGPU::SI_SPILL_S512_RESTORE;
1497  case 128:
1498  return AMDGPU::SI_SPILL_S1024_RESTORE;
1499  default:
1500  llvm_unreachable("unknown register size");
1501  }
1502 }
1503 
1504 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
1505  switch (Size) {
1506  case 4:
1507  return AMDGPU::SI_SPILL_V32_RESTORE;
1508  case 8:
1509  return AMDGPU::SI_SPILL_V64_RESTORE;
1510  case 12:
1511  return AMDGPU::SI_SPILL_V96_RESTORE;
1512  case 16:
1513  return AMDGPU::SI_SPILL_V128_RESTORE;
1514  case 20:
1515  return AMDGPU::SI_SPILL_V160_RESTORE;
1516  case 24:
1517  return AMDGPU::SI_SPILL_V192_RESTORE;
1518  case 32:
1519  return AMDGPU::SI_SPILL_V256_RESTORE;
1520  case 64:
1521  return AMDGPU::SI_SPILL_V512_RESTORE;
1522  case 128:
1523  return AMDGPU::SI_SPILL_V1024_RESTORE;
1524  default:
1525  llvm_unreachable("unknown register size");
1526  }
1527 }
1528 
1529 static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
1530  switch (Size) {
1531  case 4:
1532  return AMDGPU::SI_SPILL_A32_RESTORE;
1533  case 8:
1534  return AMDGPU::SI_SPILL_A64_RESTORE;
1535  case 12:
1536  return AMDGPU::SI_SPILL_A96_RESTORE;
1537  case 16:
1538  return AMDGPU::SI_SPILL_A128_RESTORE;
1539  case 20:
1540  return AMDGPU::SI_SPILL_A160_RESTORE;
1541  case 24:
1542  return AMDGPU::SI_SPILL_A192_RESTORE;
1543  case 32:
1544  return AMDGPU::SI_SPILL_A256_RESTORE;
1545  case 64:
1546  return AMDGPU::SI_SPILL_A512_RESTORE;
1547  case 128:
1548  return AMDGPU::SI_SPILL_A1024_RESTORE;
1549  default:
1550  llvm_unreachable("unknown register size");
1551  }
1552 }
1553 
1556  Register DestReg, int FrameIndex,
1557  const TargetRegisterClass *RC,
1558  const TargetRegisterInfo *TRI) const {
1559  MachineFunction *MF = MBB.getParent();
1561  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1562  const DebugLoc &DL = MBB.findDebugLoc(MI);
1563  unsigned SpillSize = TRI->getSpillSize(*RC);
1564 
1565  MachinePointerInfo PtrInfo
1567 
1569  PtrInfo, MachineMemOperand::MOLoad, FrameInfo.getObjectSize(FrameIndex),
1570  FrameInfo.getObjectAlign(FrameIndex));
1571 
1572  if (RI.isSGPRClass(RC)) {
1573  MFI->setHasSpilledSGPRs();
1574  assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into");
1575  assert(DestReg != AMDGPU::EXEC_LO && DestReg != AMDGPU::EXEC_HI &&
1576  DestReg != AMDGPU::EXEC && "exec should not be spilled");
1577 
1578  // FIXME: Maybe this should not include a memoperand because it will be
1579  // lowered to non-memory instructions.
1580  const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1581  if (DestReg.isVirtual() && SpillSize == 4) {
1583  MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1584  }
1585 
1586  if (RI.spillSGPRToVGPR())
1587  FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1588  BuildMI(MBB, MI, DL, OpDesc, DestReg)
1589  .addFrameIndex(FrameIndex) // addr
1590  .addMemOperand(MMO)
1592 
1593  return;
1594  }
1595 
1596  unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
1597  : getVGPRSpillRestoreOpcode(SpillSize);
1598  BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1599  .addFrameIndex(FrameIndex) // vaddr
1600  .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1601  .addImm(0) // offset
1602  .addMemOperand(MMO);
1603 }
1604 
1607  insertNoops(MBB, MI, 1);
1608 }
1609 
1612  unsigned Quantity) const {
1614  while (Quantity > 0) {
1615  unsigned Arg = std::min(Quantity, 8u);
1616  Quantity -= Arg;
1617  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)).addImm(Arg - 1);
1618  }
1619 }
1620 
1622  auto MF = MBB.getParent();
1624 
1625  assert(Info->isEntryFunction());
1626 
1627  if (MBB.succ_empty()) {
1628  bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
1629  if (HasNoTerminator) {
1630  if (Info->returnsVoid()) {
1631  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1632  } else {
1633  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1634  }
1635  }
1636  }
1637 }
1638 
1640  switch (MI.getOpcode()) {
1641  default: return 1; // FIXME: Do wait states equal cycles?
1642 
1643  case AMDGPU::S_NOP:
1644  return MI.getOperand(0).getImm() + 1;
1645  }
1646 }
1647 
1649  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1650  MachineBasicBlock &MBB = *MI.getParent();
1652  switch (MI.getOpcode()) {
1653  default: return TargetInstrInfo::expandPostRAPseudo(MI);
1654  case AMDGPU::S_MOV_B64_term:
1655  // This is only a terminator to get the correct spill code placement during
1656  // register allocation.
1657  MI.setDesc(get(AMDGPU::S_MOV_B64));
1658  break;
1659 
1660  case AMDGPU::S_MOV_B32_term:
1661  // This is only a terminator to get the correct spill code placement during
1662  // register allocation.
1663  MI.setDesc(get(AMDGPU::S_MOV_B32));
1664  break;
1665 
1666  case AMDGPU::S_XOR_B64_term:
1667  // This is only a terminator to get the correct spill code placement during
1668  // register allocation.
1669  MI.setDesc(get(AMDGPU::S_XOR_B64));
1670  break;
1671 
1672  case AMDGPU::S_XOR_B32_term:
1673  // This is only a terminator to get the correct spill code placement during
1674  // register allocation.
1675  MI.setDesc(get(AMDGPU::S_XOR_B32));
1676  break;
1677  case AMDGPU::S_OR_B64_term:
1678  // This is only a terminator to get the correct spill code placement during
1679  // register allocation.
1680  MI.setDesc(get(AMDGPU::S_OR_B64));
1681  break;
1682  case AMDGPU::S_OR_B32_term:
1683  // This is only a terminator to get the correct spill code placement during
1684  // register allocation.
1685  MI.setDesc(get(AMDGPU::S_OR_B32));
1686  break;
1687 
1688  case AMDGPU::S_ANDN2_B64_term:
1689  // This is only a terminator to get the correct spill code placement during
1690  // register allocation.
1691  MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1692  break;
1693 
1694  case AMDGPU::S_ANDN2_B32_term:
1695  // This is only a terminator to get the correct spill code placement during
1696  // register allocation.
1697  MI.setDesc(get(AMDGPU::S_ANDN2_B32));
1698  break;
1699 
1700  case AMDGPU::S_AND_B64_term:
1701  // This is only a terminator to get the correct spill code placement during
1702  // register allocation.
1703  MI.setDesc(get(AMDGPU::S_AND_B64));
1704  break;
1705 
1706  case AMDGPU::S_AND_B32_term:
1707  // This is only a terminator to get the correct spill code placement during
1708  // register allocation.
1709  MI.setDesc(get(AMDGPU::S_AND_B32));
1710  break;
1711 
1712  case AMDGPU::V_MOV_B64_PSEUDO: {
1713  Register Dst = MI.getOperand(0).getReg();
1714  Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1715  Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1716 
1717  const MachineOperand &SrcOp = MI.getOperand(1);
1718  // FIXME: Will this work for 64-bit floating point immediates?
1719  assert(!SrcOp.isFPImm());
1720  if (SrcOp.isImm()) {
1721  APInt Imm(64, SrcOp.getImm());
1722  APInt Lo(32, Imm.getLoBits(32).getZExtValue());
1723  APInt Hi(32, Imm.getHiBits(32).getZExtValue());
1724  if (ST.hasPackedFP32Ops() && Lo == Hi && isInlineConstant(Lo)) {
1725  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
1727  .addImm(Lo.getSExtValue())
1729  .addImm(Lo.getSExtValue())
1730  .addImm(0) // op_sel_lo
1731  .addImm(0) // op_sel_hi
1732  .addImm(0) // neg_lo
1733  .addImm(0) // neg_hi
1734  .addImm(0); // clamp
1735  } else {
1736  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1737  .addImm(Lo.getZExtValue())
1739  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1740  .addImm(Hi.getZExtValue())
1742  }
1743  } else {
1744  assert(SrcOp.isReg());
1745  if (ST.hasPackedFP32Ops() &&
1746  !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
1747  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
1748  .addImm(SISrcMods::OP_SEL_1) // src0_mod
1749  .addReg(SrcOp.getReg())
1751  .addReg(SrcOp.getReg())
1752  .addImm(0) // op_sel_lo
1753  .addImm(0) // op_sel_hi
1754  .addImm(0) // neg_lo
1755  .addImm(0) // neg_hi
1756  .addImm(0); // clamp
1757  } else {
1758  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1759  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1761  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1762  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1764  }
1765  }
1766  MI.eraseFromParent();
1767  break;
1768  }
1769  case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
1770  expandMovDPP64(MI);
1771  break;
1772  }
1773  case AMDGPU::V_SET_INACTIVE_B32: {
1774  unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1775  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1776  auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1777  FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
1778  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1779  .add(MI.getOperand(2));
1780  BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1781  .addReg(Exec);
1782  MI.eraseFromParent();
1783  break;
1784  }
1785  case AMDGPU::V_SET_INACTIVE_B64: {
1786  unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1787  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1788  auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1789  FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
1790  MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1791  MI.getOperand(0).getReg())
1792  .add(MI.getOperand(2));
1793  expandPostRAPseudo(*Copy);
1794  BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1795  .addReg(Exec);
1796  MI.eraseFromParent();
1797  break;
1798  }
1799  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1:
1800  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2:
1801  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3:
1802  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4:
1803  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5:
1804  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8:
1805  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16:
1806  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32:
1807  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1:
1808  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2:
1809  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
1810  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
1811  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
1812  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
1813  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16:
1814  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32:
1815  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1:
1816  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2:
1817  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4:
1818  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8:
1819  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16: {
1820  const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);
1821 
1822  unsigned Opc;
1823  if (RI.hasVGPRs(EltRC)) {
1824  Opc = AMDGPU::V_MOVRELD_B32_e32;
1825  } else {
1826  Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64
1827  : AMDGPU::S_MOVRELD_B32;
1828  }
1829 
1830  const MCInstrDesc &OpDesc = get(Opc);
1831  Register VecReg = MI.getOperand(0).getReg();
1832  bool IsUndef = MI.getOperand(1).isUndef();
1833  unsigned SubReg = MI.getOperand(3).getImm();
1834  assert(VecReg == MI.getOperand(1).getReg());
1835 
1836  MachineInstrBuilder MIB =
1837  BuildMI(MBB, MI, DL, OpDesc)
1838  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1839  .add(MI.getOperand(2))
1841  .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1842 
1843  const int ImpDefIdx =
1844  OpDesc.getNumOperands() + OpDesc.getNumImplicitUses();
1845  const int ImpUseIdx = ImpDefIdx + 1;
1846  MIB->tieOperands(ImpDefIdx, ImpUseIdx);
1847  MI.eraseFromParent();
1848  break;
1849  }
1850  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1:
1851  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2:
1852  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3:
1853  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4:
1854  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5:
1855  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8:
1856  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16:
1857  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32: {
1858  assert(ST.useVGPRIndexMode());
1859  Register VecReg = MI.getOperand(0).getReg();
1860  bool IsUndef = MI.getOperand(1).isUndef();
1861  Register Idx = MI.getOperand(3).getReg();
1862  Register SubReg = MI.getOperand(4).getImm();
1863 
1864  MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
1865  .addReg(Idx)
1867  SetOn->getOperand(3).setIsUndef();
1868 
1869  const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect);
1870  MachineInstrBuilder MIB =
1871  BuildMI(MBB, MI, DL, OpDesc)
1872  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1873  .add(MI.getOperand(2))
1875  .addReg(VecReg,
1876  RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1877 
1878  const int ImpDefIdx = OpDesc.getNumOperands() + OpDesc.getNumImplicitUses();
1879  const int ImpUseIdx = ImpDefIdx + 1;
1880  MIB->tieOperands(ImpDefIdx, ImpUseIdx);
1881 
1882  MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
1883 
1884  finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
1885 
1886  MI.eraseFromParent();
1887  break;
1888  }
1889  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1:
1890  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2:
1891  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3:
1892  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4:
1893  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5:
1894  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8:
1895  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16:
1896  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32: {
1897  assert(ST.useVGPRIndexMode());
1898  Register Dst = MI.getOperand(0).getReg();
1899  Register VecReg = MI.getOperand(1).getReg();
1900  bool IsUndef = MI.getOperand(1).isUndef();
1901  Register Idx = MI.getOperand(2).getReg();
1902  Register SubReg = MI.getOperand(3).getImm();
1903 
1904  MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
1905  .addReg(Idx)
1907  SetOn->getOperand(3).setIsUndef();
1908 
1909  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32))
1910  .addDef(Dst)
1911  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1912  .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0))
1914 
1915  MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
1916 
1917  finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
1918 
1919  MI.eraseFromParent();
1920  break;
1921  }
1922  case AMDGPU::SI_PC_ADD_REL_OFFSET: {
1923  MachineFunction &MF = *MBB.getParent();
1924  Register Reg = MI.getOperand(0).getReg();
1925  Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1926  Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1927 
1928  // Create a bundle so these instructions won't be re-ordered by the
1929  // post-RA scheduler.
1930  MIBundleBuilder Bundler(MBB, MI);
1931  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1932 
1933  // Add 32-bit offset from this instruction to the start of the
1934  // constant data.
1935  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1936  .addReg(RegLo)
1937  .add(MI.getOperand(1)));
1938 
1939  MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1940  .addReg(RegHi);
1941  MIB.add(MI.getOperand(2));
1942 
1943  Bundler.append(MIB);
1944  finalizeBundle(MBB, Bundler.begin());
1945 
1946  MI.eraseFromParent();
1947  break;
1948  }
1949  case AMDGPU::ENTER_STRICT_WWM: {
1950  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1951  // Whole Wave Mode is entered.
1952  MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1953  : AMDGPU::S_OR_SAVEEXEC_B64));
1954  break;
1955  }
1956  case AMDGPU::ENTER_STRICT_WQM: {
1957  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1958  // STRICT_WQM is entered.
1959  const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1960  const unsigned WQMOp = ST.isWave32() ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64;
1961  const unsigned MovOp = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1962  BuildMI(MBB, MI, DL, get(MovOp), MI.getOperand(0).getReg()).addReg(Exec);
1963  BuildMI(MBB, MI, DL, get(WQMOp), Exec).addReg(Exec);
1964 
1965  MI.eraseFromParent();
1966  break;
1967  }
1968  case AMDGPU::EXIT_STRICT_WWM:
1969  case AMDGPU::EXIT_STRICT_WQM: {
1970  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1971  // WWM/STICT_WQM is exited.
1972  MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
1973  break;
1974  }
1975  }
1976  return true;
1977 }
1978 
1979 std::pair<MachineInstr*, MachineInstr*>
1981  assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
1982 
1983  MachineBasicBlock &MBB = *MI.getParent();
1985  MachineFunction *MF = MBB.getParent();
1987  Register Dst = MI.getOperand(0).getReg();
1988  unsigned Part = 0;
1989  MachineInstr *Split[2];
1990 
1991  for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
1992  auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
1993  if (Dst.isPhysical()) {
1994  MovDPP.addDef(RI.getSubReg(Dst, Sub));
1995  } else {
1996  assert(MRI.isSSA());
1997  auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1998  MovDPP.addDef(Tmp);
1999  }
2000 
2001  for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
2002  const MachineOperand &SrcOp = MI.getOperand(I);
2003  assert(!SrcOp.isFPImm());
2004  if (SrcOp.isImm()) {
2005  APInt Imm(64, SrcOp.getImm());
2006  Imm.ashrInPlace(Part * 32);
2007  MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
2008  } else {
2009  assert(SrcOp.isReg());
2010  Register Src = SrcOp.getReg();
2011  if (Src.isPhysical())
2012  MovDPP.addReg(RI.getSubReg(Src, Sub));
2013  else
2014  MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
2015  }
2016  }
2017 
2018  for (unsigned I = 3; I < MI.getNumExplicitOperands(); ++I)
2019  MovDPP.addImm(MI.getOperand(I).getImm());
2020 
2021  Split[Part] = MovDPP;
2022  ++Part;
2023  }
2024 
2025  if (Dst.isVirtual())
2026  BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
2027  .addReg(Split[0]->getOperand(0).getReg())
2028  .addImm(AMDGPU::sub0)
2029  .addReg(Split[1]->getOperand(0).getReg())
2030  .addImm(AMDGPU::sub1);
2031 
2032  MI.eraseFromParent();
2033  return std::make_pair(Split[0], Split[1]);
2034 }
2035 
2037  MachineOperand &Src0,
2038  unsigned Src0OpName,
2039  MachineOperand &Src1,
2040  unsigned Src1OpName) const {
2041  MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
2042  if (!Src0Mods)
2043  return false;
2044 
2045  MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
2046  assert(Src1Mods &&
2047  "All commutable instructions have both src0 and src1 modifiers");
2048 
2049  int Src0ModsVal = Src0Mods->getImm();
2050  int Src1ModsVal = Src1Mods->getImm();
2051 
2052  Src1Mods->setImm(Src0ModsVal);
2053  Src0Mods->setImm(Src1ModsVal);
2054  return true;
2055 }
2056 
2058  MachineOperand &RegOp,
2059  MachineOperand &NonRegOp) {
2060  Register Reg = RegOp.getReg();
2061  unsigned SubReg = RegOp.getSubReg();
2062  bool IsKill = RegOp.isKill();
2063  bool IsDead = RegOp.isDead();
2064  bool IsUndef = RegOp.isUndef();
2065  bool IsDebug = RegOp.isDebug();
2066 
2067  if (NonRegOp.isImm())
2068  RegOp.ChangeToImmediate(NonRegOp.getImm());
2069  else if (NonRegOp.isFI())
2070  RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
2071  else if (NonRegOp.isGlobal()) {
2072  RegOp.ChangeToGA(NonRegOp.getGlobal(), NonRegOp.getOffset(),
2073  NonRegOp.getTargetFlags());
2074  } else
2075  return nullptr;
2076 
2077  // Make sure we don't reinterpret a subreg index in the target flags.
2078  RegOp.setTargetFlags(NonRegOp.getTargetFlags());
2079 
2080  NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
2081  NonRegOp.setSubReg(SubReg);
2082 
2083  return &MI;
2084 }
2085 
2087  unsigned Src0Idx,
2088  unsigned Src1Idx) const {
2089  assert(!NewMI && "this should never be used");
2090 
2091  unsigned Opc = MI.getOpcode();
2092  int CommutedOpcode = commuteOpcode(Opc);
2093  if (CommutedOpcode == -1)
2094  return nullptr;
2095 
2096  assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
2097  static_cast<int>(Src0Idx) &&
2098  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
2099  static_cast<int>(Src1Idx) &&
2100  "inconsistency with findCommutedOpIndices");
2101 
2102  MachineOperand &Src0 = MI.getOperand(Src0Idx);
2103  MachineOperand &Src1 = MI.getOperand(Src1Idx);
2104 
2105  MachineInstr *CommutedMI = nullptr;
2106  if (Src0.isReg() && Src1.isReg()) {
2107  if (isOperandLegal(MI, Src1Idx, &Src0)) {
2108  // Be sure to copy the source modifiers to the right place.
2109  CommutedMI
2110  = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
2111  }
2112 
2113  } else if (Src0.isReg() && !Src1.isReg()) {
2114  // src0 should always be able to support any operand type, so no need to
2115  // check operand legality.
2116  CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2117  } else if (!Src0.isReg() && Src1.isReg()) {
2118  if (isOperandLegal(MI, Src1Idx, &Src0))
2119  CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2120  } else {
2121  // FIXME: Found two non registers to commute. This does happen.
2122  return nullptr;
2123  }
2124 
2125  if (CommutedMI) {
2126  swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2127  Src1, AMDGPU::OpName::src1_modifiers);
2128 
2129  CommutedMI->setDesc(get(CommutedOpcode));
2130  }
2131 
2132  return CommutedMI;
2133 }
2134 
2135 // This needs to be implemented because the source modifiers may be inserted
2136 // between the true commutable operands, and the base
2137 // TargetInstrInfo::commuteInstruction uses it.
2139  unsigned &SrcOpIdx0,
2140  unsigned &SrcOpIdx1) const {
2141  return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
2142 }
2143 
2144 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
2145  unsigned &SrcOpIdx1) const {
2146  if (!Desc.isCommutable())
2147  return false;
2148 
2149  unsigned Opc = Desc.getOpcode();
2150  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
2151  if (Src0Idx == -1)
2152  return false;
2153 
2154  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
2155  if (Src1Idx == -1)
2156  return false;
2157 
2158  return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
2159 }
2160 
2161 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
2162  int64_t BrOffset) const {
2163  // BranchRelaxation should never have to check s_setpc_b64 because its dest
2164  // block is unanalyzable.
2165  assert(BranchOp != AMDGPU::S_SETPC_B64);
2166 
2167  // Convert to dwords.
2168  BrOffset /= 4;
2169 
2170  // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
2171  // from the next instruction.
2172  BrOffset -= 1;
2173 
2174  return isIntN(BranchOffsetBits, BrOffset);
2175 }
2176 
2178  const MachineInstr &MI) const {
2179  if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
2180  // This would be a difficult analysis to perform, but can always be legal so
2181  // there's no need to analyze it.
2182  return nullptr;
2183  }
2184 
2185  return MI.getOperand(0).getMBB();
2186 }
2187 
2189  MachineBasicBlock &DestBB,
2190  const DebugLoc &DL,
2191  int64_t BrOffset,
2192  RegScavenger *RS) const {
2193  assert(RS && "RegScavenger required for long branching");
2194  assert(MBB.empty() &&
2195  "new block should be inserted for expanding unconditional branch");
2196  assert(MBB.pred_size() == 1);
2197 
2198  MachineFunction *MF = MBB.getParent();
2200 
2201  // FIXME: Virtual register workaround for RegScavenger not working with empty
2202  // blocks.
2203  Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2204 
2205  auto I = MBB.end();
2206 
2207  // We need to compute the offset relative to the instruction immediately after
2208  // s_getpc_b64. Insert pc arithmetic code before last terminator.
2209  MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2210 
2211  // TODO: Handle > 32-bit block address.
2212  if (BrOffset >= 0) {
2213  BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
2214  .addReg(PCReg, RegState::Define, AMDGPU::sub0)
2215  .addReg(PCReg, 0, AMDGPU::sub0)
2216  .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD);
2217  BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
2218  .addReg(PCReg, RegState::Define, AMDGPU::sub1)
2219  .addReg(PCReg, 0, AMDGPU::sub1)
2220  .addImm(0);
2221  } else {
2222  // Backwards branch.
2223  BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
2224  .addReg(PCReg, RegState::Define, AMDGPU::sub0)
2225  .addReg(PCReg, 0, AMDGPU::sub0)
2226  .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD);
2227  BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
2228  .addReg(PCReg, RegState::Define, AMDGPU::sub1)
2229  .addReg(PCReg, 0, AMDGPU::sub1)
2230  .addImm(0);
2231  }
2232 
2233  // Insert the indirect branch after the other terminator.
2234  BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2235  .addReg(PCReg);
2236 
2237  // FIXME: If spilling is necessary, this will fail because this scavenger has
2238  // no emergency stack slots. It is non-trivial to spill in this situation,
2239  // because the restore code needs to be specially placed after the
2240  // jump. BranchRelaxation then needs to be made aware of the newly inserted
2241  // block.
2242  //
2243  // If a spill is needed for the pc register pair, we need to insert a spill
2244  // restore block right before the destination block, and insert a short branch
2245  // into the old destination block's fallthrough predecessor.
2246  // e.g.:
2247  //
2248  // s_cbranch_scc0 skip_long_branch:
2249  //
2250  // long_branch_bb:
2251  // spill s[8:9]
2252  // s_getpc_b64 s[8:9]
2253  // s_add_u32 s8, s8, restore_bb
2254  // s_addc_u32 s9, s9, 0
2255  // s_setpc_b64 s[8:9]
2256  //
2257  // skip_long_branch:
2258  // foo;
2259  //
2260  // .....
2261  //
2262  // dest_bb_fallthrough_predecessor:
2263  // bar;
2264  // s_branch dest_bb
2265  //
2266  // restore_bb:
2267  // restore s[8:9]
2268  // fallthrough dest_bb
2269  ///
2270  // dest_bb:
2271  // buzz;
2272 
2273  RS->enterBasicBlockEnd(MBB);
2275  AMDGPU::SReg_64RegClass,
2276  MachineBasicBlock::iterator(GetPC), false, 0);
2277  MRI.replaceRegWith(PCReg, Scav);
2278  MRI.clearVirtRegs();
2279  RS->setRegUsed(Scav);
2280 
2281  return 4 + 8 + 4 + 4;
2282 }
2283 
2284 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
2285  switch (Cond) {
2286  case SIInstrInfo::SCC_TRUE:
2287  return AMDGPU::S_CBRANCH_SCC1;
2288  case SIInstrInfo::SCC_FALSE:
2289  return AMDGPU::S_CBRANCH_SCC0;
2290  case SIInstrInfo::VCCNZ:
2291  return AMDGPU::S_CBRANCH_VCCNZ;
2292  case SIInstrInfo::VCCZ:
2293  return AMDGPU::S_CBRANCH_VCCZ;
2294  case SIInstrInfo::EXECNZ:
2295  return AMDGPU::S_CBRANCH_EXECNZ;
2296  case SIInstrInfo::EXECZ:
2297  return AMDGPU::S_CBRANCH_EXECZ;
2298  default:
2299  llvm_unreachable("invalid branch predicate");
2300  }
2301 }
2302 
2303 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
2304  switch (Opcode) {
2305  case AMDGPU::S_CBRANCH_SCC0:
2306  return SCC_FALSE;
2307  case AMDGPU::S_CBRANCH_SCC1:
2308  return SCC_TRUE;
2309  case AMDGPU::S_CBRANCH_VCCNZ:
2310  return VCCNZ;
2311  case AMDGPU::S_CBRANCH_VCCZ:
2312  return VCCZ;
2313  case AMDGPU::S_CBRANCH_EXECNZ:
2314  return EXECNZ;
2315  case AMDGPU::S_CBRANCH_EXECZ:
2316  return EXECZ;
2317  default:
2318  return INVALID_BR;
2319  }
2320 }
2321 
2324  MachineBasicBlock *&TBB,
2325  MachineBasicBlock *&FBB,
2327  bool AllowModify) const {
2328  if (I->getOpcode() == AMDGPU::S_BRANCH) {
2329  // Unconditional Branch
2330  TBB = I->getOperand(0).getMBB();
2331  return false;
2332  }
2333 
2334  MachineBasicBlock *CondBB = nullptr;
2335 
2336  if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
2337  CondBB = I->getOperand(1).getMBB();
2338  Cond.push_back(I->getOperand(0));
2339  } else {
2340  BranchPredicate Pred = getBranchPredicate(I->getOpcode());
2341  if (Pred == INVALID_BR)
2342  return true;
2343 
2344  CondBB = I->getOperand(0).getMBB();
2345  Cond.push_back(MachineOperand::CreateImm(Pred));
2346  Cond.push_back(I->getOperand(1)); // Save the branch register.
2347  }
2348  ++I;
2349 
2350  if (I == MBB.end()) {
2351  // Conditional branch followed by fall-through.
2352  TBB = CondBB;
2353  return false;
2354  }
2355 
2356  if (I->getOpcode() == AMDGPU::S_BRANCH) {
2357  TBB = CondBB;
2358  FBB = I->getOperand(0).getMBB();
2359  return false;
2360  }
2361 
2362  return true;
2363 }
2364 
2366  MachineBasicBlock *&FBB,
2368  bool AllowModify) const {
2370  auto E = MBB.end();
2371  if (I == E)
2372  return false;
2373 
2374  // Skip over the instructions that are artificially terminators for special
2375  // exec management.
2376  while (I != E && !I->isBranch() && !I->isReturn()) {
2377  switch (I->getOpcode()) {
2378  case AMDGPU::S_MOV_B64_term:
2379  case AMDGPU::S_XOR_B64_term:
2380  case AMDGPU::S_OR_B64_term:
2381  case AMDGPU::S_ANDN2_B64_term:
2382  case AMDGPU::S_AND_B64_term:
2383  case AMDGPU::S_MOV_B32_term:
2384  case AMDGPU::S_XOR_B32_term:
2385  case AMDGPU::S_OR_B32_term:
2386  case AMDGPU::S_ANDN2_B32_term:
2387  case AMDGPU::S_AND_B32_term:
2388  break;
2389  case AMDGPU::SI_IF:
2390  case AMDGPU::SI_ELSE:
2391  case AMDGPU::SI_KILL_I1_TERMINATOR:
2392  case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
2393  // FIXME: It's messy that these need to be considered here at all.
2394  return true;
2395  default:
2396  llvm_unreachable("unexpected non-branch terminator inst");
2397  }
2398 
2399  ++I;
2400  }
2401 
2402  if (I == E)
2403  return false;
2404 
2405  return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
2406 }
2407 
2409  int *BytesRemoved) const {
2411 
2412  unsigned Count = 0;
2413  unsigned RemovedSize = 0;
2414  while (I != MBB.end()) {
2415  MachineBasicBlock::iterator Next = std::next(I);
2416  RemovedSize += getInstSizeInBytes(*I);
2417  I->eraseFromParent();
2418  ++Count;
2419  I = Next;
2420  }
2421 
2422  if (BytesRemoved)
2423  *BytesRemoved = RemovedSize;
2424 
2425  return Count;
2426 }
2427 
2428 // Copy the flags onto the implicit condition register operand.
2430  const MachineOperand &OrigCond) {
2431  CondReg.setIsUndef(OrigCond.isUndef());
2432  CondReg.setIsKill(OrigCond.isKill());
2433 }
2434 
2436  MachineBasicBlock *TBB,
2437  MachineBasicBlock *FBB,
2439  const DebugLoc &DL,
2440  int *BytesAdded) const {
2441  if (!FBB && Cond.empty()) {
2442  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2443  .addMBB(TBB);
2444  if (BytesAdded)
2445  *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
2446  return 1;
2447  }
2448 
2449  if(Cond.size() == 1 && Cond[0].isReg()) {
2450  BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2451  .add(Cond[0])
2452  .addMBB(TBB);
2453  return 1;
2454  }
2455 
2456  assert(TBB && Cond[0].isImm());
2457 
2458  unsigned Opcode
2459  = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
2460 
2461  if (!FBB) {
2462  Cond[1].isUndef();
2463  MachineInstr *CondBr =
2464  BuildMI(&MBB, DL, get(Opcode))
2465  .addMBB(TBB);
2466 
2467  // Copy the flags onto the implicit condition register operand.
2468  preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
2469  fixImplicitOperands(*CondBr);
2470 
2471  if (BytesAdded)
2472  *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
2473  return 1;
2474  }
2475 
2476  assert(TBB && FBB);
2477 
2478  MachineInstr *CondBr =
2479  BuildMI(&MBB, DL, get(Opcode))
2480  .addMBB(TBB);
2481  fixImplicitOperands(*CondBr);
2482  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2483  .addMBB(FBB);
2484 
2485  MachineOperand &CondReg = CondBr->getOperand(1);
2486  CondReg.setIsUndef(Cond[1].isUndef());
2487  CondReg.setIsKill(Cond[1].isKill());
2488 
2489  if (BytesAdded)
2490  *BytesAdded = ST.hasOffset3fBug() ? 16 : 8;
2491 
2492  return 2;
2493 }
2494 
2497  if (Cond.size() != 2) {
2498  return true;
2499  }
2500 
2501  if (Cond[0].isImm()) {
2502  Cond[0].setImm(-Cond[0].getImm());
2503  return false;
2504  }
2505 
2506  return true;
2507 }
2508 
2511  Register DstReg, Register TrueReg,
2512  Register FalseReg, int &CondCycles,
2513  int &TrueCycles, int &FalseCycles) const {
2514  switch (Cond[0].getImm()) {
2515  case VCCNZ:
2516  case VCCZ: {
2518  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2519  if (MRI.getRegClass(FalseReg) != RC)
2520  return false;
2521 
2522  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2523  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2524 
2525  // Limit to equal cost for branch vs. N v_cndmask_b32s.
2526  return RI.hasVGPRs(RC) && NumInsts <= 6;
2527  }
2528  case SCC_TRUE:
2529  case SCC_FALSE: {
2530  // FIXME: We could insert for VGPRs if we could replace the original compare
2531  // with a vector one.
2533  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2534  if (MRI.getRegClass(FalseReg) != RC)
2535  return false;
2536 
2537  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2538 
2539  // Multiples of 8 can do s_cselect_b64
2540  if (NumInsts % 2 == 0)
2541  NumInsts /= 2;
2542 
2543  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2544  return RI.isSGPRClass(RC);
2545  }
2546  default:
2547  return false;
2548  }
2549 }
2550 
2554  Register TrueReg, Register FalseReg) const {
2555  BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
2556  if (Pred == VCCZ || Pred == SCC_FALSE) {
2557  Pred = static_cast<BranchPredicate>(-Pred);
2558  std::swap(TrueReg, FalseReg);
2559  }
2560 
2562  const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2563  unsigned DstSize = RI.getRegSizeInBits(*DstRC);
2564 
2565  if (DstSize == 32) {
2567  if (Pred == SCC_TRUE) {
2568  Select = BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B32), DstReg)
2569  .addReg(TrueReg)
2570  .addReg(FalseReg);
2571  } else {
2572  // Instruction's operands are backwards from what is expected.
2573  Select = BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e32), DstReg)
2574  .addReg(FalseReg)
2575  .addReg(TrueReg);
2576  }
2577 
2578  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2579  return;
2580  }
2581 
2582  if (DstSize == 64 && Pred == SCC_TRUE) {
2583  MachineInstr *Select =
2584  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2585  .addReg(TrueReg)
2586  .addReg(FalseReg);
2587 
2588  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2589  return;
2590  }
2591 
2592  static const int16_t Sub0_15[] = {
2593  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
2594  AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
2595  AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
2596  AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
2597  };
2598 
2599  static const int16_t Sub0_15_64[] = {
2600  AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
2601  AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
2602  AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
2603  AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
2604  };
2605 
2606  unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
2607  const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
2608  const int16_t *SubIndices = Sub0_15;
2609  int NElts = DstSize / 32;
2610 
2611  // 64-bit select is only available for SALU.
2612  // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
2613  if (Pred == SCC_TRUE) {
2614  if (NElts % 2) {
2615  SelOp = AMDGPU::S_CSELECT_B32;
2616  EltRC = &AMDGPU::SGPR_32RegClass;
2617  } else {
2618  SelOp = AMDGPU::S_CSELECT_B64;
2619  EltRC = &AMDGPU::SGPR_64RegClass;
2620  SubIndices = Sub0_15_64;
2621  NElts /= 2;
2622  }
2623  }
2624 
2626  MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
2627 
2628  I = MIB->getIterator();
2629 
2631  for (int Idx = 0; Idx != NElts; ++Idx) {
2632  Register DstElt = MRI.createVirtualRegister(EltRC);
2633  Regs.push_back(DstElt);
2634 
2635  unsigned SubIdx = SubIndices[Idx];
2636 
2638  if (SelOp == AMDGPU::V_CNDMASK_B32_e32) {
2639  Select =
2640  BuildMI(MBB, I, DL, get(SelOp), DstElt)
2641  .addReg(FalseReg, 0, SubIdx)
2642  .addReg(TrueReg, 0, SubIdx);
2643  } else {
2644  Select =
2645  BuildMI(MBB, I, DL, get(SelOp), DstElt)
2646  .addReg(TrueReg, 0, SubIdx)
2647  .addReg(FalseReg, 0, SubIdx);
2648  }
2649 
2650  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2652 
2653  MIB.addReg(DstElt)
2654  .addImm(SubIdx);
2655  }
2656 }
2657 
2659  switch (MI.getOpcode()) {
2660  case AMDGPU::V_MOV_B32_e32:
2661  case AMDGPU::V_MOV_B32_e64:
2662  case AMDGPU::V_MOV_B64_PSEUDO: {
2663  // If there are additional implicit register operands, this may be used for
2664  // register indexing so the source register operand isn't simply copied.
2665  unsigned NumOps = MI.getDesc().getNumOperands() +
2666  MI.getDesc().getNumImplicitUses();
2667 
2668  return MI.getNumOperands() == NumOps;
2669  }
2670  case AMDGPU::S_MOV_B32:
2671  case AMDGPU::S_MOV_B64:
2672  case AMDGPU::COPY:
2673  case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
2674  case AMDGPU::V_ACCVGPR_READ_B32_e64:
2675  case AMDGPU::V_ACCVGPR_MOV_B32:
2676  return true;
2677  default:
2678  return false;
2679  }
2680 }
2681 
2683  unsigned Kind) const {
2684  switch(Kind) {
2695  }
2696  return AMDGPUAS::FLAT_ADDRESS;
2697 }
2698 
2700  unsigned Opc = MI.getOpcode();
2701  int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2702  AMDGPU::OpName::src0_modifiers);
2703  int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2704  AMDGPU::OpName::src1_modifiers);
2705  int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2706  AMDGPU::OpName::src2_modifiers);
2707 
2708  MI.RemoveOperand(Src2ModIdx);
2709  MI.RemoveOperand(Src1ModIdx);
2710  MI.RemoveOperand(Src0ModIdx);
2711 }
2712 
2714  Register Reg, MachineRegisterInfo *MRI) const {
2715  if (!MRI->hasOneNonDBGUse(Reg))
2716  return false;
2717 
2718  switch (DefMI.getOpcode()) {
2719  default:
2720  return false;
2721  case AMDGPU::S_MOV_B64:
2722  // TODO: We could fold 64-bit immediates, but this get compilicated
2723  // when there are sub-registers.
2724  return false;
2725 
2726  case AMDGPU::V_MOV_B32_e32:
2727  case AMDGPU::S_MOV_B32:
2728  case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
2729  break;
2730  }
2731 
2732  const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2733  assert(ImmOp);
2734  // FIXME: We could handle FrameIndex values here.
2735  if (!ImmOp->isImm())
2736  return false;
2737 
2738  unsigned Opc = UseMI.getOpcode();
2739  if (Opc == AMDGPU::COPY) {
2740  Register DstReg = UseMI.getOperand(0).getReg();
2741  bool Is16Bit = getOpSize(UseMI, 0) == 2;
2742  bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
2743  unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2744  APInt Imm(32, ImmOp->getImm());
2745 
2746  if (UseMI.getOperand(1).getSubReg() == AMDGPU::hi16)
2747  Imm = Imm.ashr(16);
2748 
2749  if (RI.isAGPR(*MRI, DstReg)) {
2750  if (!isInlineConstant(Imm))
2751  return false;
2752  NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
2753  }
2754 
2755  if (Is16Bit) {
2756  if (isVGPRCopy)
2757  return false; // Do not clobber vgpr_hi16
2758 
2759  if (DstReg.isVirtual() &&
2760  UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
2761  return false;
2762 
2763  UseMI.getOperand(0).setSubReg(0);
2764  if (DstReg.isPhysical()) {
2765  DstReg = RI.get32BitRegister(DstReg);
2766  UseMI.getOperand(0).setReg(DstReg);
2767  }
2768  assert(UseMI.getOperand(1).getReg().isVirtual());
2769  }
2770 
2771  UseMI.setDesc(get(NewOpc));
2772  UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
2773  UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2774  return true;
2775  }
2776 
2777  if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
2778  Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
2779  Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2780  Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64) {
2781  // Don't fold if we are using source or output modifiers. The new VOP2
2782  // instructions don't have them.
2784  return false;
2785 
2786  // If this is a free constant, there's no reason to do this.
2787  // TODO: We could fold this here instead of letting SIFoldOperands do it
2788  // later.
2789  MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2790 
2791  // Any src operand can be used for the legality check.
2792  if (isInlineConstant(UseMI, *Src0, *ImmOp))
2793  return false;
2794 
2795  bool IsF32 = Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
2796  Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64;
2797  bool IsFMA = Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2798  Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64;
2799  MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2800  MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2801 
2802  // Multiplied part is the constant: Use v_madmk_{f16, f32}.
2803  // We should only expect these to be on src0 due to canonicalizations.
2804  if (Src0->isReg() && Src0->getReg() == Reg) {
2805  if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2806  return false;
2807 
2808  if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2809  return false;
2810 
2811  unsigned NewOpc =
2812  IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32 : AMDGPU::V_FMAMK_F16)
2813  : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
2814  if (pseudoToMCOpcode(NewOpc) == -1)
2815  return false;
2816 
2817  // We need to swap operands 0 and 1 since madmk constant is at operand 1.
2818 
2819  const int64_t Imm = ImmOp->getImm();
2820 
2821  // FIXME: This would be a lot easier if we could return a new instruction
2822  // instead of having to modify in place.
2823 
2824  // Remove these first since they are at the end.
2825  UseMI.RemoveOperand(
2826  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2827  UseMI.RemoveOperand(
2828  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2829 
2830  Register Src1Reg = Src1->getReg();
2831  unsigned Src1SubReg = Src1->getSubReg();
2832  Src0->setReg(Src1Reg);
2833  Src0->setSubReg(Src1SubReg);
2834  Src0->setIsKill(Src1->isKill());
2835 
2836  if (Opc == AMDGPU::V_MAC_F32_e64 ||
2837  Opc == AMDGPU::V_MAC_F16_e64 ||
2838  Opc == AMDGPU::V_FMAC_F32_e64 ||
2839  Opc == AMDGPU::V_FMAC_F16_e64)
2840  UseMI.untieRegOperand(
2841  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2842 
2843  Src1->ChangeToImmediate(Imm);
2844 
2846  UseMI.setDesc(get(NewOpc));
2847 
2848  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2849  if (DeleteDef)
2850  DefMI.eraseFromParent();
2851 
2852  return true;
2853  }
2854 
2855  // Added part is the constant: Use v_madak_{f16, f32}.
2856  if (Src2->isReg() && Src2->getReg() == Reg) {
2857  // Not allowed to use constant bus for another operand.
2858  // We can however allow an inline immediate as src0.
2859  bool Src0Inlined = false;
2860  if (Src0->isReg()) {
2861  // Try to inline constant if possible.
2862  // If the Def moves immediate and the use is single
2863  // We are saving VGPR here.
2865  if (Def && Def->isMoveImmediate() &&
2866  isInlineConstant(Def->getOperand(1)) &&
2867  MRI->hasOneUse(Src0->getReg())) {
2868  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2869  Src0Inlined = true;
2870  } else if ((Src0->getReg().isPhysical() &&
2871  (ST.getConstantBusLimit(Opc) <= 1 &&
2872  RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2873  (Src0->getReg().isVirtual() &&
2874  (ST.getConstantBusLimit(Opc) <= 1 &&
2875  RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2876  return false;
2877  // VGPR is okay as Src0 - fallthrough
2878  }
2879 
2880  if (Src1->isReg() && !Src0Inlined ) {
2881  // We have one slot for inlinable constant so far - try to fill it
2883  if (Def && Def->isMoveImmediate() &&
2884  isInlineConstant(Def->getOperand(1)) &&
2885  MRI->hasOneUse(Src1->getReg()) &&
2886  commuteInstruction(UseMI)) {
2887  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2888  } else if ((Src1->getReg().isPhysical() &&
2889  RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
2890  (Src1->getReg().isVirtual() &&
2891  RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
2892  return false;
2893  // VGPR is okay as Src1 - fallthrough
2894  }
2895 
2896  unsigned NewOpc =
2897  IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32 : AMDGPU::V_FMAAK_F16)
2898  : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
2899  if (pseudoToMCOpcode(NewOpc) == -1)
2900  return false;
2901 
2902  const int64_t Imm = ImmOp->getImm();
2903 
2904  // FIXME: This would be a lot easier if we could return a new instruction
2905  // instead of having to modify in place.
2906 
2907  // Remove these first since they are at the end.
2908  UseMI.RemoveOperand(
2909  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2910  UseMI.RemoveOperand(
2911  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2912 
2913  if (Opc == AMDGPU::V_MAC_F32_e64 ||
2914  Opc == AMDGPU::V_MAC_F16_e64 ||
2915  Opc == AMDGPU::V_FMAC_F32_e64 ||
2916  Opc == AMDGPU::V_FMAC_F16_e64)
2917  UseMI.untieRegOperand(
2918  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2919 
2920  // ChangingToImmediate adds Src2 back to the instruction.
2921  Src2->ChangeToImmediate(Imm);
2922 
2923  // These come before src2.
2925  UseMI.setDesc(get(NewOpc));
2926  // It might happen that UseMI was commuted
2927  // and we now have SGPR as SRC1. If so 2 inlined
2928  // constant and SGPR are illegal.
2930 
2931  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2932  if (DeleteDef)
2933  DefMI.eraseFromParent();
2934 
2935  return true;
2936  }
2937  }
2938 
2939  return false;
2940 }
2941 
2942 static bool
2945  if (BaseOps1.size() != BaseOps2.size())
2946  return false;
2947  for (size_t I = 0, E = BaseOps1.size(); I < E; ++I) {
2948  if (!BaseOps1[I]->isIdenticalTo(*BaseOps2[I]))
2949  return false;
2950  }
2951  return true;
2952 }
2953 
2954 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
2955  int WidthB, int OffsetB) {
2956  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2957  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2958  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2959  return LowOffset + LowWidth <= HighOffset;
2960 }
2961 
2962 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
2963  const MachineInstr &MIb) const {
2964  SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
2965  int64_t Offset0, Offset1;
2966  unsigned Dummy0, Dummy1;
2967  bool Offset0IsScalable, Offset1IsScalable;
2968  if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
2969  Dummy0, &RI) ||
2970  !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
2971  Dummy1, &RI))
2972  return false;
2973 
2974  if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))
2975  return false;
2976 
2977  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
2978  // FIXME: Handle ds_read2 / ds_write2.
2979  return false;
2980  }
2981  unsigned Width0 = MIa.memoperands().front()->getSize();
2982  unsigned Width1 = MIb.memoperands().front()->getSize();
2983  return offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1);
2984 }
2985 
2987  const MachineInstr &MIb) const {
2988  assert(MIa.mayLoadOrStore() &&
2989  "MIa must load from or modify a memory location");
2990  assert(MIb.mayLoadOrStore() &&
2991  "MIb must load from or modify a memory location");
2992 
2994  return false;
2995 
2996  // XXX - Can we relax this between address spaces?
2997  if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2998  return false;
2999 
3000  // TODO: Should we check the address space from the MachineMemOperand? That
3001  // would allow us to distinguish objects we know don't alias based on the
3002  // underlying address space, even if it was lowered to a different one,
3003  // e.g. private accesses lowered to use MUBUF instructions on a scratch
3004  // buffer.
3005  if (isDS(MIa)) {
3006  if (isDS(MIb))
3007  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3008 
3009  return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
3010  }
3011 
3012  if (isMUBUF(MIa) || isMTBUF(MIa)) {
3013  if (isMUBUF(MIb) || isMTBUF(MIb))
3014  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3015 
3016  return !isFLAT(MIb) && !isSMRD(MIb);
3017  }
3018 
3019  if (isSMRD(MIa)) {
3020  if (isSMRD(MIb))
3021  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3022 
3023  return !isFLAT(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb);
3024  }
3025 
3026  if (isFLAT(MIa)) {
3027  if (isFLAT(MIb))
3028  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3029 
3030  return false;
3031  }
3032 
3033  return false;
3034 }
3035 
3036 static int64_t getFoldableImm(const MachineOperand* MO) {
3037  if (!MO->isReg())
3038  return false;
3039  const MachineFunction *MF = MO->getParent()->getParent()->getParent();
3040  const MachineRegisterInfo &MRI = MF->getRegInfo();
3041  auto Def = MRI.getUniqueVRegDef(MO->getReg());
3042  if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
3043  Def->getOperand(1).isImm())
3044  return Def->getOperand(1).getImm();
3045  return AMDGPU::NoRegister;
3046 }
3047 
3049  MachineInstr &NewMI) {
3050  if (LV) {
3051  unsigned NumOps = MI.getNumOperands();
3052  for (unsigned I = 1; I < NumOps; ++I) {
3053  MachineOperand &Op = MI.getOperand(I);
3054  if (Op.isReg() && Op.isKill())
3055  LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
3056  }
3057  }
3058 }
3059 
3061  MachineInstr &MI,
3062  LiveVariables *LV) const {
3063  unsigned Opc = MI.getOpcode();
3064  bool IsF16 = false;
3065  bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3066  Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3067  Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3068  bool IsF64 = Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3069 
3070  switch (Opc) {
3071  default:
3072  return nullptr;
3073  case AMDGPU::V_MAC_F16_e64:
3074  case AMDGPU::V_FMAC_F16_e64:
3075  IsF16 = true;
3077  case AMDGPU::V_MAC_F32_e64:
3078  case AMDGPU::V_FMAC_F32_e64:
3079  case AMDGPU::V_FMAC_F64_e64:
3080  break;
3081  case AMDGPU::V_MAC_F16_e32:
3082  case AMDGPU::V_FMAC_F16_e32:
3083  IsF16 = true;
3085  case AMDGPU::V_MAC_F32_e32:
3086  case AMDGPU::V_FMAC_F32_e32:
3087  case AMDGPU::V_FMAC_F64_e32: {
3088  int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3089  AMDGPU::OpName::src0);
3090  const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3091  if (!Src0->isReg() && !Src0->isImm())
3092  return nullptr;
3093 
3094  if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
3095  return nullptr;
3096 
3097  break;
3098  }
3099  }
3100 
3101  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3102  const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
3103  const MachineOperand *Src0Mods =
3104  getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
3105  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3106  const MachineOperand *Src1Mods =
3107  getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
3108  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3109  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3110  const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
3111  MachineInstrBuilder MIB;
3112 
3113  if (!Src0Mods && !Src1Mods && !Clamp && !Omod && !IsF64 &&
3114  // If we have an SGPR input, we will violate the constant bus restriction.
3115  (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
3116  !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
3117  if (auto Imm = getFoldableImm(Src2)) {
3118  unsigned NewOpc =
3119  IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
3120  : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
3121  if (pseudoToMCOpcode(NewOpc) != -1) {
3122  MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3123  .add(*Dst)
3124  .add(*Src0)
3125  .add(*Src1)
3126  .addImm(Imm);
3127  updateLiveVariables(LV, MI, *MIB);
3128  return MIB;
3129  }
3130  }
3131  unsigned NewOpc = IsFMA
3132  ? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
3133  : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
3134  if (auto Imm = getFoldableImm(Src1)) {
3135  if (pseudoToMCOpcode(NewOpc) != -1) {
3136  MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3137  .add(*Dst)
3138  .add(*Src0)
3139  .addImm(Imm)
3140  .add(*Src2);
3141  updateLiveVariables(LV, MI, *MIB);
3142  return MIB;
3143  }
3144  }
3145  if (auto Imm = getFoldableImm(Src0)) {
3146  if (pseudoToMCOpcode(NewOpc) != -1 &&
3148  MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
3149  Src1)) {
3150  MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3151  .add(*Dst)
3152  .add(*Src1)
3153  .addImm(Imm)
3154  .add(*Src2);
3155  updateLiveVariables(LV, MI, *MIB);
3156  return MIB;
3157  }
3158  }
3159  }
3160 
3161  unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_e64
3162  : IsF64 ? AMDGPU::V_FMA_F64_e64
3163  : AMDGPU::V_FMA_F32_e64)
3164  : (IsF16 ? AMDGPU::V_MAD_F16_e64 : AMDGPU::V_MAD_F32_e64);
3165  if (pseudoToMCOpcode(NewOpc) == -1)
3166  return nullptr;
3167 
3168  MIB = BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3169  .add(*Dst)
3170  .addImm(Src0Mods ? Src0Mods->getImm() : 0)
3171  .add(*Src0)
3172  .addImm(Src1Mods ? Src1Mods->getImm() : 0)
3173  .add(*Src1)
3174  .addImm(0) // Src mods
3175  .add(*Src2)
3176  .addImm(Clamp ? Clamp->getImm() : 0)
3177  .addImm(Omod ? Omod->getImm() : 0);
3178  updateLiveVariables(LV, MI, *MIB);
3179  return MIB;
3180 }
3181 
3182 // It's not generally safe to move VALU instructions across these since it will
3183 // start using the register as a base index rather than directly.
3184 // XXX - Why isn't hasSideEffects sufficient for these?
3186  switch (MI.getOpcode()) {
3187  case AMDGPU::S_SET_GPR_IDX_ON:
3188  case AMDGPU::S_SET_GPR_IDX_MODE:
3189  case AMDGPU::S_SET_GPR_IDX_OFF:
3190  return true;
3191  default:
3192  return false;
3193  }
3194 }
3195 
3197  const MachineBasicBlock *MBB,
3198  const MachineFunction &MF) const {
3199  // Skipping the check for SP writes in the base implementation. The reason it
3200  // was added was apparently due to compile time concerns.
3201  //
3202  // TODO: Do we really want this barrier? It triggers unnecessary hazard nops
3203  // but is probably avoidable.
3204 
3205  // Copied from base implementation.
3206  // Terminators and labels can't be scheduled around.
3207  if (MI.isTerminator() || MI.isPosition())
3208  return true;
3209 
3210  // INLINEASM_BR can jump to another block
3211  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
3212  return true;
3213 
3214  // Target-independent instructions do not have an implicit-use of EXEC, even
3215  // when they operate on VGPRs. Treating EXEC modifications as scheduling
3216  // boundaries prevents incorrect movements of such instructions.
3217  return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
3218  MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
3219  MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
3221 }
3222 
3224  return Opcode == AMDGPU::DS_ORDERED_COUNT ||
3225  Opcode == AMDGPU::DS_GWS_INIT ||
3226  Opcode == AMDGPU::DS_GWS_SEMA_V ||
3227  Opcode == AMDGPU::DS_GWS_SEMA_BR ||
3228  Opcode == AMDGPU::DS_GWS_SEMA_P ||
3229  Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
3230  Opcode == AMDGPU::DS_GWS_BARRIER;
3231 }
3232 
3234  // Skip the full operand and register alias search modifiesRegister
3235  // does. There's only a handful of instructions that touch this, it's only an
3236  // implicit def, and doesn't alias any other registers.
3237  if (const MCPhysReg *ImpDef = MI.getDesc().getImplicitDefs()) {
3238  for (; ImpDef && *ImpDef; ++ImpDef) {
3239  if (*ImpDef == AMDGPU::MODE)
3240  return true;
3241  }
3242  }
3243 
3244  return false;
3245 }
3246 
3248  unsigned Opcode = MI.getOpcode();
3249 
3250  if (MI.mayStore() && isSMRD(MI))
3251  return true; // scalar store or atomic
3252 
3253  // This will terminate the function when other lanes may need to continue.
3254  if (MI.isReturn())
3255  return true;
3256 
3257  // These instructions cause shader I/O that may cause hardware lockups
3258  // when executed with an empty EXEC mask.
3259  //
3260  // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
3261  // EXEC = 0, but checking for that case here seems not worth it
3262  // given the typical code patterns.
3263  if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
3264  isEXP(Opcode) ||
3265  Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
3266  Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
3267  return true;
3268 
3269  if (MI.isCall() || MI.isInlineAsm())
3270  return true; // conservative assumption
3271 
3272  // A mode change is a scalar operation that influences vector instructions.
3273  if (modifiesModeRegister(MI))
3274  return true;
3275 
3276  // These are like SALU instructions in terms of effects, so it's questionable
3277  // whether we should return true for those.
3278  //
3279  // However, executing them with EXEC = 0 causes them to operate on undefined
3280  // data, which we avoid by returning true here.
3281  if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
3282  Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32)
3283  return true;
3284 
3285  return false;
3286 }
3287 
3289  const MachineInstr &MI) const {
3290  if (MI.isMetaInstruction())
3291  return false;
3292 
3293  // This won't read exec if this is an SGPR->SGPR copy.
3294  if (MI.isCopyLike()) {
3295  if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
3296  return true;
3297 
3298  // Make sure this isn't copying exec as a normal operand
3299  return MI.readsRegister(AMDGPU::EXEC, &RI);
3300  }
3301 
3302  // Make a conservative assumption about the callee.
3303  if (MI.isCall())
3304  return true;
3305 
3306  // Be conservative with any unhandled generic opcodes.
3307  if (!isTargetSpecificOpcode(MI.getOpcode()))
3308  return true;
3309 
3310  return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
3311 }
3312 
3313 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
3314  switch (Imm.getBitWidth()) {
3315  case 1: // This likely will be a condition code mask.
3316  return true;
3317 
3318  case 32:
3320  ST.hasInv2PiInlineImm());
3321  case 64:
3323  ST.hasInv2PiInlineImm());
3324  case 16:
3325  return ST.has16BitInsts() &&
3327  ST.hasInv2PiInlineImm());
3328  default:
3329  llvm_unreachable("invalid bitwidth");
3330  }
3331 }
3332 
3334  uint8_t OperandType) const {
3335  if (!MO.isImm() ||
3338  return false;
3339 
3340  // MachineOperand provides no way to tell the true operand size, since it only
3341  // records a 64-bit value. We need to know the size to determine if a 32-bit
3342  // floating point immediate bit pattern is legal for an integer immediate. It
3343  // would be for any 32-bit integer operand, but would not be for a 64-bit one.
3344 
3345  int64_t Imm = MO.getImm();
3346  switch (OperandType) {
3357  int32_t Trunc = static_cast<int32_t>(Imm);
3359  }
3366  ST.hasInv2PiInlineImm());
3370  // We would expect inline immediates to not be concerned with an integer/fp
3371  // distinction. However, in the case of 16-bit integer operations, the
3372  // "floating point" values appear to not work. It seems read the low 16-bits
3373  // of 32-bit immediates, which happens to always work for the integer
3374  // values.
3375  //
3376  // See llvm bugzilla 46302.
3377  //
3378  // TODO: Theoretically we could use op-sel to use the high bits of the
3379  // 32-bit FP values.
3380  return AMDGPU::isInlinableIntLiteral(Imm);
3384  // This suffers the same problem as the scalar 16-bit cases.
3389  if (isInt<16>(Imm) || isUInt<16>(Imm)) {
3390  // A few special case instructions have 16-bit operands on subtargets
3391  // where 16-bit instructions are not legal.
3392  // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
3393  // constants in these cases
3394  int16_t Trunc = static_cast<int16_t>(Imm);
3395  return ST.has16BitInsts() &&
3397  }
3398 
3399  return false;
3400  }
3404  uint32_t Trunc = static_cast<uint32_t>(Imm);
3406  }
3407  default:
3408  llvm_unreachable("invalid bitwidth");
3409  }
3410 }
3411 
3413  const MCOperandInfo &OpInfo) const {
3414  switch (MO.getType()) {
3416  return false;
3418  return !isInlineConstant(MO, OpInfo);
3424  return true;
3425  default:
3426  llvm_unreachable("unexpected operand type");
3427  }
3428 }
3429 
3430 static bool compareMachineOp(const MachineOperand &Op0,
3431  const MachineOperand &Op1) {
3432  if (Op0.getType() != Op1.getType())
3433  return false;
3434 
3435  switch (Op0.getType()) {
3437  return Op0.getReg() == Op1.getReg();
3439  return Op0.getImm() == Op1.getImm();
3440  default:
3441  llvm_unreachable("Didn't expect to be comparing these operand types");
3442  }
3443 }
3444 
3446  const MachineOperand &MO) const {
3447  const MCInstrDesc &InstDesc = MI.getDesc();
3448  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
3449 
3450  assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
3451 
3452  if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
3453  return true;
3454 
3455  if (OpInfo.RegClass < 0)
3456  return false;
3457 
3458  if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
3459  if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
3460  OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3461  AMDGPU::OpName::src2))
3462  return false;
3463  return RI.opCanUseInlineConstant(OpInfo.OperandType);
3464  }
3465 
3466  if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
3467  return false;
3468 
3469  if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
3470  return true;
3471 
3472  return ST.hasVOP3Literal();
3473 }
3474 
3475 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
3476  // GFX90A does not have V_MUL_LEGACY_F32_e32.
3477  if (Opcode == AMDGPU::V_MUL_LEGACY_F32_e64 && ST.hasGFX90AInsts())
3478  return false;
3479 
3480  int Op32 = AMDGPU::getVOPe32(Opcode);
3481  if (Op32 == -1)
3482  return false;
3483 
3484  return pseudoToMCOpcode(Op32) != -1;
3485 }
3486 
3487 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
3488  // The src0_modifier operand is present on all instructions
3489  // that have modifiers.
3490 
3491  return AMDGPU::getNamedOperandIdx(Opcode,
3492  AMDGPU::OpName::src0_modifiers) != -1;
3493 }
3494 
3496  unsigned OpName) const {
3497  const MachineOperand *Mods = getNamedOperand(MI, OpName);
3498  return Mods && Mods->getImm();
3499 }
3500 
3502  return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
3503  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
3504  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
3505  hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
3506  hasModifiersSet(MI, AMDGPU::OpName::omod);
3507 }
3508 
3510  const MachineRegisterInfo &MRI) const {
3511  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3512  // Can't shrink instruction with three operands.
3513  // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
3514  // a special case for it. It can only be shrunk if the third operand
3515  // is vcc, and src0_modifiers and src1_modifiers are not set.
3516  // We should handle this the same way we handle vopc, by addding
3517  // a register allocation hint pre-regalloc and then do the shrinking
3518  // post-regalloc.
3519  if (Src2) {
3520  switch (MI.getOpcode()) {
3521  default: return false;
3522 
3523  case AMDGPU::V_ADDC_U32_e64:
3524  case AMDGPU::V_SUBB_U32_e64:
3525  case AMDGPU::V_SUBBREV_U32_e64: {
3526  const MachineOperand *Src1
3527  = getNamedOperand(MI, AMDGPU::OpName::src1);
3528  if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
3529  return false;
3530  // Additional verification is needed for sdst/src2.
3531  return true;
3532  }
3533  case AMDGPU::V_MAC_F32_e64:
3534  case AMDGPU::V_MAC_F16_e64:
3535  case AMDGPU::V_FMAC_F32_e64:
3536  case AMDGPU::V_FMAC_F16_e64:
3537  case AMDGPU::V_FMAC_F64_e64:
3538  if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
3539  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
3540  return false;
3541  break;
3542 
3543  case AMDGPU::V_CNDMASK_B32_e64:
3544  break;
3545  }
3546  }
3547 
3548  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3549  if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
3550  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
3551  return false;
3552 
3553  // We don't need to check src0, all input types are legal, so just make sure
3554  // src0 isn't using any modifiers.
3555  if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
3556  return false;
3557 
3558  // Can it be shrunk to a valid 32 bit opcode?
3559  if (!hasVALU32BitEncoding(MI.getOpcode()))
3560  return false;
3561 
3562  // Check output modifiers
3563  return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
3564  !hasModifiersSet(MI, AMDGPU::OpName::clamp);
3565 }
3566 
3567 // Set VCC operand with all flags from \p Orig, except for setting it as
3568 // implicit.
3570  const MachineOperand &Orig) {
3571 
3572  for (MachineOperand &Use : MI.implicit_operands()) {
3573  if (Use.isUse() &&
3574  (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
3575  Use.setIsUndef(Orig.isUndef());
3576  Use.setIsKill(Orig.isKill());
3577  return;
3578  }
3579  }
3580 }
3581 
3583  unsigned Op32) const {
3584  MachineBasicBlock *MBB = MI.getParent();;
3585  MachineInstrBuilder Inst32 =
3586  BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32))
3587  .setMIFlags(MI.getFlags());
3588 
3589  // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
3590  // For VOPC instructions, this is replaced by an implicit def of vcc.
3591  int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
3592  if (Op32DstIdx != -1) {
3593  // dst
3594  Inst32.add(MI.getOperand(0));
3595  } else {
3596  assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3597  (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
3598  "Unexpected case");
3599  }
3600 
3601  Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
3602 
3603  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3604  if (Src1)
3605  Inst32.add(*Src1);
3606 
3607  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3608 
3609  if (Src2) {
3610  int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
3611  if (Op32Src2Idx != -1) {
3612  Inst32.add(*Src2);
3613  } else {
3614  // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
3615  // replaced with an implicit read of vcc or vcc_lo. The implicit read
3616  // of vcc was already added during the initial BuildMI, but we
3617  // 1) may need to change vcc to vcc_lo to preserve the original register
3618  // 2) have to preserve the original flags.
3619  fixImplicitOperands(*Inst32);
3620  copyFlagsToImplicitVCC(*Inst32, *Src2);
3621  }
3622  }
3623 
3624  return Inst32;
3625 }
3626 
3628  const MachineOperand &MO,
3629  const MCOperandInfo &OpInfo) const {
3630  // Literal constants use the constant bus.
3631  //if (isLiteralConstantLike(MO, OpInfo))
3632  // return true;
3633  if (MO.isImm())
3634  return !isInlineConstant(MO, OpInfo);
3635 
3636  if (!MO.isReg())
3637  return true; // Misc other operands like FrameIndex
3638 
3639  if (!MO.isUse())
3640  return false;
3641 
3642  if (MO.getReg().isVirtual())
3643  return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3644 
3645  // Null is free
3646  if (MO.getReg() == AMDGPU::SGPR_NULL)
3647  return false;
3648 
3649  // SGPRs use the constant bus
3650  if (MO.isImplicit()) {
3651  return MO.getReg() == AMDGPU::M0 ||
3652  MO.getReg() == AMDGPU::VCC ||
3653  MO.getReg() == AMDGPU::VCC_LO;
3654  } else {
3655  return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
3656  AMDGPU::SReg_64RegClass.contains(MO.getReg());
3657  }
3658 }
3659 
3661  for (const MachineOperand &MO : MI.implicit_operands()) {
3662  // We only care about reads.
3663  if (MO.isDef())
3664  continue;
3665 
3666  switch (MO.getReg()) {
3667  case AMDGPU::VCC:
3668  case AMDGPU::VCC_LO:
3669  case AMDGPU::VCC_HI:
3670  case AMDGPU::M0:
3671  case AMDGPU::FLAT_SCR:
3672  return MO.getReg();
3673 
3674  default:
3675  break;
3676  }
3677  }
3678 
3679  return AMDGPU::NoRegister;
3680 }
3681 
3682 static bool shouldReadExec(const MachineInstr &MI) {
3683  if (SIInstrInfo::isVALU(MI)) {
3684  switch (MI.getOpcode()) {
3685  case AMDGPU::V_READLANE_B32:
3686  case AMDGPU::V_WRITELANE_B32:
3687  return false;
3688  }
3689 
3690  return true;
3691  }
3692 
3693  if (MI.isPreISelOpcode() ||
3694  SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
3697  return false;
3698 
3699  return true;
3700 }
3701 
3702 static bool isSubRegOf(const SIRegisterInfo &TRI,
3703  const MachineOperand &SuperVec,
3704  const MachineOperand &SubReg) {
3705  if (SubReg.getReg().isPhysical())
3706  return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
3707 
3708  return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
3709  SubReg.getReg() == SuperVec.getReg();
3710 }
3711 
3713  StringRef &ErrInfo) const {
3714  uint16_t Opcode = MI.getOpcode();
3715  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
3716  return true;
3717 
3718  const MachineFunction *MF = MI.getParent()->getParent();
3719  const MachineRegisterInfo &MRI = MF->getRegInfo();
3720 
3721  int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
3722  int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
3723  int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
3724 
3725  // Make sure the number of operands is correct.
3726  const MCInstrDesc &Desc = get(Opcode);
3727  if (!Desc.isVariadic() &&
3728  Desc.getNumOperands() != MI.getNumExplicitOperands()) {
3729  ErrInfo = "Instruction has wrong number of operands.";
3730  return false;
3731  }
3732 
3733  if (MI.isInlineAsm()) {
3734  // Verify register classes for inlineasm constraints.
3735  for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
3736  I != E; ++I) {
3737  const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
3738  if (!RC)
3739  continue;
3740 
3741  const MachineOperand &Op = MI.getOperand(I);
3742  if (!Op.isReg())
3743  continue;
3744 
3745  Register Reg = Op.getReg();
3746  if (!Reg.isVirtual() && !RC->contains(Reg)) {
3747  ErrInfo = "inlineasm operand has incorrect register class.";
3748  return false;
3749  }
3750  }
3751 
3752  return true;
3753  }
3754 
3755  if (isMIMG(MI) && MI.memoperands_empty() && MI.mayLoadOrStore()) {
3756  ErrInfo = "missing memory operand from MIMG instruction.";
3757  return false;
3758  }
3759 
3760  // Make sure the register classes are correct.
3761  for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
3762  const MachineOperand &MO = MI.getOperand(i);
3763  if (MO.isFPImm()) {
3764  ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
3765  "all fp values to integers.";
3766  return false;
3767  }
3768 
3769  int RegClass = Desc.OpInfo[i].RegClass;
3770 
3771  switch (Desc.OpInfo[i].OperandType) {
3773  if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
3774  ErrInfo = "Illegal immediate value for operand.";
3775  return false;
3776  }
3777  break;
3780  break;
3792  if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
3793  ErrInfo = "Illegal immediate value for operand.";
3794  return false;
3795  }
3796  break;
3797  }
3800  // Check if this operand is an immediate.
3801  // FrameIndex operands will be replaced by immediates, so they are
3802  // allowed.
3803  if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
3804  ErrInfo = "Expected immediate, but got non-immediate";
3805  return false;
3806  }
3808  default:
3809  continue;
3810  }
3811 
3812  if (!MO.isReg())
3813  continue;
3814  Register Reg = MO.getReg();
3815  if (!Reg)
3816  continue;
3817 
3818  // FIXME: Ideally we would have separate instruction definitions with the
3819  // aligned register constraint.
3820  // FIXME: We do not verify inline asm operands, but custom inline asm
3821  // verification is broken anyway
3822  if (ST.needsAlignedVGPRs()) {
3823  const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg);
3824  const bool IsVGPR = RI.hasVGPRs(RC);
3825  const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC);
3826  if ((IsVGPR || IsAGPR) && MO.getSubReg()) {
3827  const TargetRegisterClass *SubRC =
3828  RI.getSubRegClass(RC, MO.getSubReg());
3829  RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg());
3830  if (RC)
3831  RC = SubRC;
3832  }
3833 
3834  // Check that this is the aligned version of the class.
3835  if (!RC || !RI.isProperlyAlignedRC(*RC)) {
3836  ErrInfo = "Subtarget requires even aligned vector registers";
3837  return false;
3838  }
3839  }
3840 
3841  if (RegClass != -1) {
3842  if (Reg.isVirtual())
3843  continue;
3844 
3845  const TargetRegisterClass *RC = RI.getRegClass(RegClass);
3846  if (!RC->contains(Reg)) {
3847  ErrInfo = "Operand has incorrect register class.";
3848  return false;
3849  }
3850  }
3851  }
3852 
3853  // Verify SDWA
3854  if (isSDWA(MI)) {
3855  if (!ST.hasSDWA()) {
3856  ErrInfo = "SDWA is not supported on this target";
3857  return false;
3858  }
3859 
3860  int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
3861 
3862  const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
3863 
3864  for (int OpIdx: OpIndicies) {
3865  if (OpIdx == -1)
3866  continue;
3867  const MachineOperand &MO = MI.getOperand(OpIdx);
3868 
3869  if (!ST.hasSDWAScalar()) {
3870  // Only VGPRS on VI
3871  if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
3872  ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
3873  return false;
3874  }
3875  } else {
3876  // No immediates on GFX9
3877  if (!MO.isReg()) {
3878  ErrInfo =
3879  "Only reg allowed as operands in SDWA instructions on GFX9+";
3880  return false;
3881  }
3882  }
3883  }
3884 
3885  if (!ST.hasSDWAOmod()) {
3886  // No omod allowed on VI
3887  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3888  if (OMod != nullptr &&
3889  (!OMod->isImm() || OMod->getImm() != 0)) {
3890  ErrInfo = "OMod not allowed in SDWA instructions on VI";
3891  return false;
3892  }
3893  }
3894 
3895  uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
3896  if (isVOPC(BasicOpcode)) {
3897  if (!ST.hasSDWASdst() && DstIdx != -1) {
3898  // Only vcc allowed as dst on VI for VOPC
3899  const MachineOperand &Dst = MI.getOperand(DstIdx);
3900  if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3901  ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
3902  return false;
3903  }
3904  } else if (!ST.hasSDWAOutModsVOPC()) {
3905  // No clamp allowed on GFX9 for VOPC
3906  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3907  if (Clamp && (!Clamp->isImm() || Clamp->getImm() != 0)) {
3908  ErrInfo = "Clamp not allowed in VOPC SDWA instructions on VI";
3909  return false;
3910  }
3911 
3912  // No omod allowed on GFX9 for VOPC
3913  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3914  if (OMod && (!OMod->isImm() || OMod->getImm() != 0)) {
3915  ErrInfo = "OMod not allowed in VOPC SDWA instructions on VI";
3916  return false;
3917  }
3918  }
3919  }
3920 
3921  const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
3922  if (DstUnused && DstUnused->isImm() &&
3924  const MachineOperand &Dst = MI.getOperand(DstIdx);
3925  if (!Dst.isReg() || !Dst.isTied()) {
3926  ErrInfo = "Dst register should have tied register";
3927  return false;
3928  }
3929 
3930  const MachineOperand &TiedMO =
3931  MI.getOperand(MI.findTiedOperandIdx(DstIdx));
3932  if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
3933  ErrInfo =
3934  "Dst register should be tied to implicit use of preserved register";
3935  return false;
3936  } else if (TiedMO.getReg().isPhysical() &&
3937  Dst.getReg() != TiedMO.getReg()) {
3938  ErrInfo = "Dst register should use same physical register as preserved";
3939  return false;
3940  }
3941  }
3942  }
3943 
3944  // Verify MIMG
3945  if (isMIMG(MI.getOpcode()) && !MI.mayStore()) {
3946  // Ensure that the return type used is large enough for all the options
3947  // being used TFE/LWE require an extra result register.
3948  const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
3949  if (DMask) {
3950  uint64_t DMaskImm = DMask->getImm();
3951  uint32_t RegCount =
3952  isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm);
3953  const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
3954  const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
3955  const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3956 
3957  // Adjust for packed 16 bit values
3958  if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
3959  RegCount >>= 1;
3960 
3961  // Adjust if using LWE or TFE
3962  if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
3963  RegCount += 1;
3964 
3965  const uint32_t DstIdx =
3966  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
3967  const MachineOperand &Dst = MI.getOperand(DstIdx);
3968  if (Dst.isReg()) {
3969  const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
3970  uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
3971  if (RegCount > DstSize) {
3972  ErrInfo = "MIMG instruction returns too many registers for dst "
3973  "register class";
3974  return false;
3975  }
3976  }
3977  }
3978  }
3979 
3980  // Verify VOP*. Ignore multiple sgpr operands on writelane.
3981  if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
3982  && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
3983  // Only look at the true operands. Only a real operand can use the constant
3984  // bus, and we don't want to check pseudo-operands like the source modifier
3985  // flags.
3986  const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
3987 
3988  unsigned ConstantBusCount = 0;
3989  bool UsesLiteral = false;
3990  const MachineOperand *LiteralVal = nullptr;
3991 
3992  if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
3993  ++ConstantBusCount;
3994 
3995  SmallVector<Register, 2> SGPRsUsed;
3996  Register SGPRUsed;
3997 
3998  for (int OpIdx : OpIndices) {
3999  if (OpIdx == -1)
4000  break;
4001  const MachineOperand &MO = MI.getOperand(OpIdx);
4002  if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
4003  if (MO.isReg()) {
4004  SGPRUsed = MO.getReg();
4005  if (llvm::all_of(SGPRsUsed, [SGPRUsed](unsigned SGPR) {
4006  return SGPRUsed != SGPR;
4007  })) {
4008  ++ConstantBusCount;
4009  SGPRsUsed.push_back(SGPRUsed);
4010  }
4011  } else {
4012  if (!UsesLiteral) {
4013  ++ConstantBusCount;
4014  UsesLiteral = true;
4015  LiteralVal = &MO;
4016  } else if (!MO.isIdenticalTo(*LiteralVal)) {
4017  assert(isVOP3(MI));
4018  ErrInfo = "VOP3 instruction uses more than one literal";
4019  return false;
4020  }
4021  }
4022  }
4023  }
4024 
4025  SGPRUsed = findImplicitSGPRRead(MI);
4026  if (SGPRUsed != AMDGPU::NoRegister) {
4027  // Implicit uses may safely overlap true overands
4028  if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
4029  return !RI.regsOverlap(SGPRUsed, SGPR);
4030  })) {
4031  ++ConstantBusCount;
4032  SGPRsUsed.push_back(SGPRUsed);
4033  }
4034  }
4035 
4036  // v_writelane_b32 is an exception from constant bus restriction:
4037  // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
4038  if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
4039  Opcode != AMDGPU::V_WRITELANE_B32) {
4040  ErrInfo = "VOP* instruction violates constant bus restriction";
4041  return false;
4042  }
4043 
4044  if (isVOP3(MI) && UsesLiteral && !ST.hasVOP3Literal()) {
4045  ErrInfo = "VOP3 instruction uses literal";
4046  return false;
4047  }
4048  }
4049 
4050  // Special case for writelane - this can break the multiple constant bus rule,
4051  // but still can't use more than one SGPR register
4052  if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
4053  unsigned SGPRCount = 0;
4054  Register SGPRUsed = AMDGPU::NoRegister;
4055 
4056  for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
4057  if (OpIdx == -1)
4058  break;
4059 
4060  const MachineOperand &MO = MI.getOperand(OpIdx);
4061 
4062  if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
4063  if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
4064  if (MO.getReg() != SGPRUsed)
4065  ++SGPRCount;
4066  SGPRUsed = MO.getReg();
4067  }
4068  }
4069  if (SGPRCount > ST.getConstantBusLimit(Opcode)) {
4070  ErrInfo = "WRITELANE instruction violates constant bus restriction";
4071  return false;
4072  }
4073  }
4074  }
4075 
4076  // Verify misc. restrictions on specific instructions.
4077  if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32_e64 ||
4078  Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64_e64) {
4079  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4080  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
4081  const MachineOperand &Src2 = MI.getOperand(Src2Idx);
4082  if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
4083  if (!compareMachineOp(Src0, Src1) &&
4084  !compareMachineOp(Src0, Src2)) {
4085  ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
4086  return false;
4087  }
4088  }
4089  if ((getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm() &
4090  SISrcMods::ABS) ||
4091  (getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm() &
4092  SISrcMods::ABS) ||
4093  (getNamedOperand(MI, AMDGPU::OpName::src2_modifiers)->getImm() &
4094  SISrcMods::ABS)) {
4095  ErrInfo = "ABS not allowed in VOP3B instructions";
4096  return false;
4097  }
4098  }
4099 
4100  if (isSOP2(MI) || isSOPC(MI)) {
4101  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4102  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
4103  unsigned Immediates = 0;
4104 
4105  if (!Src0.isReg() &&
4106  !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
4107  Immediates++;
4108  if (!Src1.isReg() &&
4109  !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
4110  Immediates++;
4111 
4112  if (Immediates > 1) {
4113  ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
4114  return false;
4115  }
4116  }
4117 
4118  if (isSOPK(MI)) {
4119  auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
4120  if (Desc.isBranch()) {
4121  if (!Op->isMBB()) {
4122  ErrInfo = "invalid branch target for SOPK instruction";
4123  return false;
4124  }
4125  } else {
4126  uint64_t Imm = Op->getImm();
4127  if (sopkIsZext(MI)) {
4128  if (!isUInt<16>(Imm)) {
4129  ErrInfo = "invalid immediate for SOPK instruction";
4130  return false;
4131  }
4132  } else {
4133  if (!isInt<16>(Imm)) {
4134  ErrInfo = "invalid immediate for SOPK instruction";
4135  return false;
4136  }
4137  }
4138  }
4139  }
4140 
4141  if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
4142  Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
4143  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
4144  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
4145  const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
4146  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;
4147 
4148  const unsigned StaticNumOps = Desc.getNumOperands() +
4149  Desc.getNumImplicitUses();
4150  const unsigned NumImplicitOps = IsDst ? 2 : 1;
4151 
4152  // Allow additional implicit operands. This allows a fixup done by the post
4153  // RA scheduler where the main implicit operand is killed and implicit-defs
4154  // are added for sub-registers that remain live after this instruction.
4155  if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
4156  ErrInfo = "missing implicit register operands";
4157  return false;
4158  }
4159 
4160  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
4161  if (IsDst) {
4162  if (!Dst->isUse()) {
4163  ErrInfo = "v_movreld_b32 vdst should be a use operand";
4164  return false;
4165  }
4166 
4167  unsigned UseOpIdx;
4168  if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) ||
4169  UseOpIdx != StaticNumOps + 1) {
4170  ErrInfo = "movrel implicit operands should be tied";
4171  return false;
4172  }
4173  }
4174 
4175  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4176  const MachineOperand &ImpUse
4177  = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
4178  if (!ImpUse.isReg() || !ImpUse.isUse() ||
4179  !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
4180  ErrInfo = "src0 should be subreg of implicit vector use";
4181  return false;
4182  }
4183  }
4184 
4185  // Make sure we aren't losing exec uses in the td files. This mostly requires
4186  // being careful when using let Uses to try to add other use registers.
4187  if (shouldReadExec(MI)) {
4188  if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
4189  ErrInfo = "VALU instruction does not implicitly read exec mask";
4190  return false;
4191  }
4192  }
4193 
4194  if (isSMRD(MI)) {
4195  if (MI.mayStore()) {
4196  // The register offset form of scalar stores may only use m0 as the
4197  // soffset register.
4198  const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
4199  if (Soff && Soff->getReg() != AMDGPU::M0) {
4200  ErrInfo = "scalar stores must use m0 as offset register";
4201  return false;
4202  }
4203  }
4204  }
4205 
4206  if (isFLAT(MI) && !ST.hasFlatInstOffsets()) {
4207  const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4208  if (Offset->getImm() != 0) {
4209  ErrInfo = "subtarget does not support offsets in flat instructions";
4210  return false;
4211  }
4212  }
4213 
4214  if (isMIMG(MI)) {
4215  const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
4216  if (DimOp) {
4217  int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode,
4218  AMDGPU::OpName::vaddr0);
4219  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
4220  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opcode);
4221  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
4222  AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
4223  const AMDGPU::MIMGDimInfo *Dim =
4225 
4226  if (!Dim) {
4227  ErrInfo = "dim is out of range";
4228  return false;
4229  }
4230 
4231  bool IsA16 = false;
4232  if (ST.hasR128A16()) {
4233  const MachineOperand *R128A16 = getNamedOperand(MI, AMDGPU::OpName::r128);
4234  IsA16 = R128A16->getImm() != 0;
4235  } else if (ST.hasGFX10A16()) {
4236  const MachineOperand *A16 = getNamedOperand(MI, AMDGPU::OpName::a16);
4237  IsA16 = A16->getImm() != 0;
4238  }
4239 
4240  bool PackDerivatives = IsA16 || BaseOpcode->G16;
4241  bool IsNSA = SRsrcIdx - VAddr0Idx > 1;
4242 
4243  unsigned AddrWords = BaseOpcode->NumExtraArgs;
4244  unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
4245  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
4246  if (IsA16)
4247  AddrWords += (AddrComponents + 1) / 2;
4248  else
4249  AddrWords += AddrComponents;
4250 
4251  if (BaseOpcode->Gradients) {
4252  if (PackDerivatives)
4253  // There are two gradients per coordinate, we pack them separately.
4254  // For the 3d case, we get (dy/du, dx/du) (-, dz/du) (dy/dv, dx/dv) (-, dz/dv)
4255  AddrWords += (Dim->NumGradients / 2 + 1) / 2 * 2;
4256  else
4257  AddrWords += Dim->NumGradients;
4258  }
4259 
4260  unsigned VAddrWords;
4261  if (IsNSA) {
4262  VAddrWords = SRsrcIdx - VAddr0Idx;
4263  } else {
4264  const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
4265  VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
4266  if (AddrWords > 8)
4267  AddrWords = 16;
4268  else if (AddrWords > 4)
4269  AddrWords = 8;
4270  else if (AddrWords == 4)
4271  AddrWords = 4;
4272  else if (AddrWords == 3)
4273  AddrWords = 3;
4274  }
4275 
4276  if (VAddrWords != AddrWords) {
4277  LLVM_DEBUG(dbgs() << "bad vaddr size, expected " << AddrWords
4278  << " but got " << VAddrWords << "\n");
4279  ErrInfo = "bad vaddr size";
4280  return false;
4281  }
4282  }
4283  }
4284 
4285  const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
4286  if (DppCt) {
4287  using namespace AMDGPU::DPP;
4288 
4289  unsigned DC = DppCt->getImm();
4297  ErrInfo = "Invalid dpp_ctrl value";
4298  return false;
4299  }
4300  if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 &&
4301  ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4302  ErrInfo = "Invalid dpp_ctrl value: "
4303  "wavefront shifts are not supported on GFX10+";
4304  return false;
4305  }
4306  if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 &&
4307  ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4308  ErrInfo = "Invalid dpp_ctrl value: "
4309  "broadcasts are not supported on GFX10+";
4310  return false;
4311  }
4313  ST.getGeneration() < AMDGPUSubtarget::GFX10) {
4316  !ST.hasGFX90AInsts()) {
4317  ErrInfo = "Invalid dpp_ctrl value: "
4318  "row_newbroadcast/row_share is not supported before "
4319  "GFX90A/GFX10";
4320  return false;
4321  } else if (DC > DppCtrl::ROW_NEWBCAST_LAST || !ST.hasGFX90AInsts()) {
4322  ErrInfo = "Invalid dpp_ctrl value: "
4323  "row_share and row_xmask are not supported before GFX10";
4324  return false;
4325  }
4326  }
4327 
4328  int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
4329  int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
4330 
4331  if (Opcode != AMDGPU::V_MOV_B64_DPP_PSEUDO &&
4332  ((DstIdx >= 0 &&
4333  (Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64RegClassID ||
4334  Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64_Align2RegClassID)) ||
4335  ((Src0Idx >= 0 &&
4336  (Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID ||
4337  Desc.OpInfo[Src0Idx].RegClass ==
4338  AMDGPU::VReg_64_Align2RegClassID)))) &&
4340  ErrInfo = "Invalid dpp_ctrl value: "
4341  "64 bit dpp only support row_newbcast";
4342  return false;
4343  }
4344  }
4345 
4346  if ((MI.mayStore() || MI.mayLoad()) && !isVGPRSpill(MI)) {
4347  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
4348  uint16_t DataNameIdx = isDS(Opcode) ? AMDGPU::OpName::data0
4349  : AMDGPU::OpName::vdata;
4350  const MachineOperand *Data = getNamedOperand(MI, DataNameIdx);
4351  const MachineOperand *Data2 = getNamedOperand(MI, AMDGPU::OpName::data1);
4352  if (Data && !Data->isReg())
4353  Data = nullptr;
4354 
4355  if (ST.hasGFX90AInsts()) {
4356  if (Dst && Data &&
4357  (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) {
4358  ErrInfo = "Invalid register class: "
4359  "vdata and vdst should be both VGPR or AGPR";
4360  return false;
4361  }
4362  if (Data && Data2 &&
4363  (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) {
4364  ErrInfo = "Invalid register class: "
4365  "both data operands should be VGPR or AGPR";
4366  return false;
4367  }
4368  } else {
4369  if ((Dst && RI.isAGPR(MRI, Dst->getReg())) ||
4370  (Data && RI.isAGPR(MRI, Data->getReg())) ||
4371  (Data2 && RI.isAGPR(MRI, Data2->getReg()))) {
4372  ErrInfo = "Invalid register class: "
4373  "agpr loads and stores not supported on this GPU";
4374  return false;
4375  }
4376  }
4377  }
4378 
4379  return true;
4380 }
4381 
4382 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
4383  switch (MI.getOpcode()) {
4384  default: return AMDGPU::INSTRUCTION_LIST_END;
4385  case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
4386  case AMDGPU::COPY: return AMDGPU::COPY;
4387  case AMDGPU::PHI: return AMDGPU::PHI;
4388  case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
4389  case AMDGPU::WQM: return AMDGPU::WQM;
4390  case AMDGPU::SOFT_WQM: return AMDGPU::SOFT_WQM;
4391  case AMDGPU::STRICT_WWM: return AMDGPU::STRICT_WWM;
4392  case AMDGPU::STRICT_WQM: return AMDGPU::STRICT_WQM;
4393  case AMDGPU::S_MOV_B32: {
4394  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4395  return MI.getOperand(1).isReg() ||
4396  RI.isAGPR(MRI, MI.getOperand(0).getReg()) ?
4397  AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
4398  }
4399  case AMDGPU::S_ADD_I32:
4400  return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_CO_U32_e32;
4401  case AMDGPU::S_ADDC_U32:
4402  return AMDGPU::V_ADDC_U32_e32;
4403  case AMDGPU::S_SUB_I32:
4404  return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_CO_U32_e32;
4405  // FIXME: These are not consistently handled, and selected when the carry is
4406  // used.
4407  case AMDGPU::S_ADD_U32:
4408  return AMDGPU::V_ADD_CO_U32_e32;
4409  case AMDGPU::S_SUB_U32:
4410  return AMDGPU::V_SUB_CO_U32_e32;
4411  case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
4412  case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_U32_e64;
4413  case AMDGPU::S_MUL_HI_U32: return AMDGPU::V_MUL_HI_U32_e64;
4414  case AMDGPU::S_MUL_HI_I32: return AMDGPU::V_MUL_HI_I32_e64;
4415  case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
4416  case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
4417  case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e64;
4418  case AMDGPU::S_XNOR_B32:
4419  return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
4420  case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e64;
4421  case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e64;
4422  case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e64;
4423  case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e64;
4424  case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
4425  case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64_e64;
4426  case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
4427  case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64_e64;
4428  case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
4429  case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64_e64;
4430  case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32_e64;
4431  case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32_e64;
4432  case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32_e64;
4433  case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32_e64;
4434  case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
4435  case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
4436  case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
4437  case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
4438  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
4439  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
4440  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
4441  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
4442  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
4443  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
4444  case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32;
4445  case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32;
4446  case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32;
4447  case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
4448  case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
4449  case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
4450  case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32;
4451  case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32;
4452  case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
4453  case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
4454  case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
4455  case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
4456  case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
4457  case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
4458  }
4460  "Unexpected scalar opcode without corresponding vector one!");
4461 }
4462 
4463 static unsigned adjustAllocatableRegClass(const GCNSubtarget &ST,
4464  const MachineRegisterInfo &MRI,
4465  const MCInstrDesc &TID,
4466  unsigned RCID,
4467  bool IsAllocatable) {
4468  if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
4469  (TID.mayLoad() || TID.mayStore() ||
4471  switch (RCID) {
4472  case AMDGPU::AV_32RegClassID: return AMDGPU::VGPR_32RegClassID;
4473  case AMDGPU::AV_64RegClassID: return AMDGPU::VReg_64RegClassID;
4474  case AMDGPU::AV_96RegClassID: return AMDGPU::VReg_96RegClassID;
4475  case AMDGPU::AV_128RegClassID: return AMDGPU::VReg_128RegClassID;
4476  case AMDGPU::AV_160RegClassID: return AMDGPU::VReg_160RegClassID;
4477  default:
4478  break;
4479  }
4480  }
4481  return RCID;
4482 }
4483 
4485  unsigned OpNum, const TargetRegisterInfo *TRI,
4486  const MachineFunction &MF)
4487  const {
4488  if (OpNum >= TID.getNumOperands())
4489  return nullptr;
4490  auto RegClass = TID.OpInfo[OpNum].RegClass;
4491  bool IsAllocatable = false;
4493  // vdst and vdata should be both VGPR or AGPR, same for the DS instructions
4494  // with two data operands. Request register class constainted to VGPR only
4495  // of both operands present as Machine Copy Propagation can not check this
4496  // constraint and possibly other passes too.
4497  //
4498  // The check is limited to FLAT and DS because atomics in non-flat encoding
4499  // have their vdst and vdata tied to be the same register.
4500  const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
4501  AMDGPU::OpName::vdst);
4502  const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
4503  (TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
4504  : AMDGPU::OpName::vdata);
4505  if (DataIdx != -1) {
4506  IsAllocatable = VDstIdx != -1 ||
4508  AMDGPU::OpName::data1) != -1;
4509  }
4510  }
4511  RegClass = adjustAllocatableRegClass(ST, MF.getRegInfo(), TID, RegClass,
4512  IsAllocatable);
4513  return RI.getRegClass(RegClass);
4514 }
4515 
4517  unsigned OpNo) const {
4518  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4519  const MCInstrDesc &Desc = get(MI.getOpcode());
4520  if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
4521  Desc.OpInfo[OpNo].RegClass == -1) {
4522  Register Reg = MI.getOperand(OpNo).getReg();
4523 
4524  if (Reg.isVirtual())
4525  return MRI.getRegClass(Reg);
4526  return RI.getPhysRegClass(Reg);
4527  }
4528 
4529  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
4530  RCID = adjustAllocatableRegClass(ST, MRI, Desc, RCID, true);
4531  return RI.getRegClass(RCID);
4532 }
4533 
4534 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
4536  MachineBasicBlock *MBB = MI.getParent();
4537  MachineOperand &MO = MI.getOperand(OpIdx);
4539  unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
4540  const TargetRegisterClass *RC = RI.getRegClass(RCID);
4541  unsigned Size = RI.getRegSizeInBits(*RC);
4542  unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
4543  if (MO.isReg())
4544  Opcode = AMDGPU::COPY;
4545  else if (RI.isSGPRClass(RC))
4546  Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
4547 
4548  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
4549  const TargetRegisterClass *VRC64 = RI.getVGPR64Class();
4550  if (RI.getCommonSubClass(VRC64, VRC))
4551  VRC = VRC64;
4552  else
4553  VRC = &AMDGPU::VGPR_32RegClass;
4554 
4557  BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
4558  MO.ChangeToRegister(Reg, false);
4559 }
4560 
4563  MachineOperand &SuperReg,
4564  const TargetRegisterClass *SuperRC,
4565  unsigned SubIdx,
4566  const TargetRegisterClass *SubRC)
4567  const {
4568  MachineBasicBlock *MBB = MI->getParent();
4569  DebugLoc DL = MI->getDebugLoc();
4571 
4572  if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
4573  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4574  .addReg(SuperReg.getReg(), 0, SubIdx);
4575  return SubReg;
4576  }
4577 
4578  // Just in case the super register is itself a sub-register, copy it to a new
4579  // value so we don't need to worry about merging its subreg index with the
4580  // SubIdx passed to this function. The register coalescer should be able to
4581  // eliminate this extra copy.
4582  Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
4583 
4584  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
4585  .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
4586 
4587  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4588  .addReg(NewSuperReg, 0, SubIdx);
4589 
4590  return SubReg;
4591 }
4592 
4596  MachineOperand &Op,
4597  const TargetRegisterClass *SuperRC,
4598  unsigned SubIdx,
4599  const TargetRegisterClass *SubRC) const {
4600  if (Op.isImm()) {
4601  if (SubIdx == AMDGPU::sub0)
4602  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
4603  if (SubIdx == AMDGPU::sub1)
4604  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
4605 
4606  llvm_unreachable("Unhandled register index for immediate");
4607  }
4608 
4609  unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
4610  SubIdx, SubRC);
4611  return MachineOperand::CreateReg(SubReg, false);
4612 }
4613 
4614 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
4615 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
4616  assert(Inst.getNumExplicitOperands() == 3);
4617  MachineOperand Op1 = Inst.getOperand(1);
4618  Inst.RemoveOperand(1);
4619  Inst.addOperand(Op1);
4620 }
4621 
4623  const MCOperandInfo &OpInfo,
4624  const MachineOperand &MO) const {
4625  if (!MO.isReg())
4626  return false;
4627 
4628  Register Reg = MO.getReg();
4629 
4630  const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
4631  if (Reg.isPhysical())
4632  return DRC->contains(Reg);
4633 
4634  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
4635 
4636  if (MO.getSubReg()) {
4637  const MachineFunction *MF = MO.getParent()->getParent()->getParent();
4638  const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
4639  if (!SuperRC)
4640  return false;
4641 
4642  DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
4643  if (!DRC)
4644  return false;
4645  }
4646  return RC->hasSuperClassEq(DRC);
4647 }
4648 
4650  const MCOperandInfo &OpInfo,
4651  const MachineOperand &MO) const {
4652  if (MO.isReg())
4653  return isLegalRegOperand(MRI, OpInfo, MO);
4654 
4655  // Handle non-register types that are treated like immediates.
4656  assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
4657  return true;
4658 }
4659 
4660 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
4661  const MachineOperand *MO) const {
4662  const MachineFunction &MF = *MI.getParent()->getParent();
4663  const MachineRegisterInfo &MRI = MF.getRegInfo();
4664  const MCInstrDesc &InstDesc = MI.getDesc();
4665  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
4666  const TargetRegisterClass *DefinedRC =
4667  OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
4668  if (!MO)
4669  MO = &MI.getOperand(OpIdx);
4670 
4671  int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
4672  int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
4673  if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
4674  if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
4675  return false;
4676 
4677  SmallDenseSet<RegSubRegPair> SGPRsUsed;
4678  if (MO->isReg())
4679  SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
4680 
4681  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4682  if (i == OpIdx)
4683  continue;
4684  const MachineOperand &Op = MI.getOperand(i);
4685  if (Op.isReg()) {
4686  RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
4687  if (!SGPRsUsed.count(SGPR) &&
4688  usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
4689  if (--ConstantBusLimit <= 0)
4690  return false;
4691  SGPRsUsed.insert(SGPR);
4692  }
4693  } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
4694  if (--ConstantBusLimit <= 0)
4695  return false;
4696  } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
4697  isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
4698  if (!VOP3LiteralLimit--)
4699  return false;
4700  if (--ConstantBusLimit <= 0)
4701  return false;
4702  }
4703  }
4704  }
4705 
4706  if (MO->isReg()) {
4707  assert(DefinedRC);
4708  if (!isLegalRegOperand(MRI, OpInfo, *MO))
4709  return false;
4710  bool IsAGPR = RI.isAGPR(MRI, MO->getReg());
4711  if (IsAGPR && !ST.hasMAIInsts())
4712  return false;
4713  unsigned Opc = MI.getOpcode();
4714  if (IsAGPR &&
4715  (!ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
4716  (MI.mayLoad() || MI.mayStore() || isDS(Opc) || isMIMG(Opc)))
4717  return false;
4718  // Atomics should have both vdst and vdata either vgpr or agpr.
4719  const int VDstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
4720  const int DataIdx = AMDGPU::getNamedOperandIdx(Opc,
4721  isDS(Opc) ? AMDGPU::OpName::data0 : AMDGPU::OpName::vdata);
4722  if ((int)OpIdx == VDstIdx && DataIdx != -1 &&
4723  MI.getOperand(DataIdx).isReg() &&
4724  RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR)
4725  return false;
4726  if ((int)OpIdx == DataIdx) {
4727  if (VDstIdx != -1 &&
4728  RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR)
4729  return false;
4730  // DS instructions with 2 src operands also must have tied RC.
4731  const int Data1Idx = AMDGPU::getNamedOperandIdx(Opc,
4732  AMDGPU::OpName::data1);
4733  if (Data1Idx != -1 && MI.getOperand(Data1Idx).isReg() &&
4734  RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR)
4735  return false;
4736  }
4737  if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
4738  (int)OpIdx == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) &&
4739  RI.isSGPRReg(MRI, MO->getReg()))
4740  return false;
4741  return true;
4742  }
4743 
4744  // Handle non-register types that are treated like immediates.
4745  assert(MO->isImm() || MO->isTargetIndex() || MO->isFI() || MO->isGlobal());
4746 
4747  if (!DefinedRC) {
4748  // This operand expects an immediate.
4749  return true;
4750  }
4751 
4752  return isImmOperandLegal(MI, OpIdx, *MO);
4753 }
4754 
4756  MachineInstr &MI) const {
4757  unsigned Opc = MI.getOpcode();
4758  const MCInstrDesc &InstrDesc = get(Opc);
4759 
4760  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
4761  MachineOperand &Src0 = MI.getOperand(Src0Idx);
4762 
4763  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
4764  MachineOperand &Src1 = MI.getOperand(Src1Idx);
4765 
4766  // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
4767  // we need to only have one constant bus use before GFX10.
4768  bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister;
4769  if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 &&
4770  Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4771  isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4772  legalizeOpWithMove(MI, Src0Idx);
4773 
4774  // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for
4775  // both the value to write (src0) and lane select (src1). Fix up non-SGPR
4776  // src0/src1 with V_READFIRSTLANE.
4777  if (Opc == AMDGPU::V_WRITELANE_B32) {
4778  const DebugLoc &DL = MI.getDebugLoc();
4779  if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4780  Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4781  BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4782  .add(Src0);
4783  Src0.ChangeToRegister(Reg, false);
4784  }
4785  if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
4786  Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4787  const DebugLoc &DL = MI.getDebugLoc();
4788  BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4789  .add(Src1);
4790  Src1.ChangeToRegister(Reg, false);
4791  }
4792  return;
4793  }
4794 
4795  // No VOP2 instructions support AGPRs.
4796  if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4797  legalizeOpWithMove(MI, Src0Idx);
4798 
4799  if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg()))
4800  legalizeOpWithMove(MI, Src1Idx);
4801 
4802  // VOP2 src0 instructions support all operand types, so we don't need to check
4803  // their legality. If src1 is already legal, we don't need to do anything.