LLVM  14.0.0git
SIInstrInfo.cpp
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1 //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI Implementation of TargetInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SIInstrInfo.h"
15 #include "AMDGPU.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "GCNHazardRecognizer.h"
18 #include "GCNSubtarget.h"
20 #include "SIMachineFunctionInfo.h"
28 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/IR/IntrinsicsAMDGPU.h"
30 #include "llvm/MC/MCContext.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "si-instr-info"
37 
38 #define GET_INSTRINFO_CTOR_DTOR
39 #include "AMDGPUGenInstrInfo.inc"
40 
41 namespace llvm {
42 
43 class AAResults;
44 
45 namespace AMDGPU {
46 #define GET_D16ImageDimIntrinsics_IMPL
47 #define GET_ImageDimIntrinsicTable_IMPL
48 #define GET_RsrcIntrinsics_IMPL
49 #include "AMDGPUGenSearchableTables.inc"
50 }
51 }
52 
53 
54 // Must be at least 4 to be able to branch over minimum unconditional branch
55 // code. This is only for making it possible to write reasonably small tests for
56 // long branches.
57 static cl::opt<unsigned>
58 BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
59  cl::desc("Restrict range of branch instructions (DEBUG)"));
60 
62  "amdgpu-fix-16-bit-physreg-copies",
63  cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"),
64  cl::init(true),
66 
68  : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
69  RI(ST), ST(ST) {
70  SchedModel.init(&ST);
71 }
72 
73 //===----------------------------------------------------------------------===//
74 // TargetInstrInfo callbacks
75 //===----------------------------------------------------------------------===//
76 
77 static unsigned getNumOperandsNoGlue(SDNode *Node) {
78  unsigned N = Node->getNumOperands();
79  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
80  --N;
81  return N;
82 }
83 
84 /// Returns true if both nodes have the same value for the given
85 /// operand \p Op, or if both nodes do not have this operand.
86 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
87  unsigned Opc0 = N0->getMachineOpcode();
88  unsigned Opc1 = N1->getMachineOpcode();
89 
90  int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
91  int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
92 
93  if (Op0Idx == -1 && Op1Idx == -1)
94  return true;
95 
96 
97  if ((Op0Idx == -1 && Op1Idx != -1) ||
98  (Op1Idx == -1 && Op0Idx != -1))
99  return false;
100 
101  // getNamedOperandIdx returns the index for the MachineInstr's operands,
102  // which includes the result as the first operand. We are indexing into the
103  // MachineSDNode's operands, so we need to skip the result operand to get
104  // the real index.
105  --Op0Idx;
106  --Op1Idx;
107 
108  return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
109 }
110 
112  AAResults *AA) const {
113  if (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isSDWA(MI) || isSALU(MI)) {
114  // Normally VALU use of exec would block the rematerialization, but that
115  // is OK in this case to have an implicit exec read as all VALU do.
116  // We really want all of the generic logic for this except for this.
117 
118  // Another potential implicit use is mode register. The core logic of
119  // the RA will not attempt rematerialization if mode is set anywhere
120  // in the function, otherwise it is safe since mode is not changed.
121 
122  // There is difference to generic method which does not allow
123  // rematerialization if there are virtual register uses. We allow this,
124  // therefore this method includes SOP instructions as well.
125  return !MI.hasImplicitDef() &&
126  MI.getNumImplicitOperands() == MI.getDesc().getNumImplicitUses() &&
127  !MI.mayRaiseFPException();
128  }
129 
130  return false;
131 }
132 
133 static bool readsExecAsData(const MachineInstr &MI) {
134  if (MI.isCompare())
135  return true;
136 
137  switch (MI.getOpcode()) {
138  default:
139  break;
140  case AMDGPU::V_READFIRSTLANE_B32:
141  case AMDGPU::V_CNDMASK_B64_PSEUDO:
142  case AMDGPU::V_CNDMASK_B32_dpp:
143  case AMDGPU::V_CNDMASK_B32_e32:
144  case AMDGPU::V_CNDMASK_B32_e64:
145  case AMDGPU::V_CNDMASK_B32_sdwa:
146  return true;
147  }
148 
149  return false;
150 }
151 
153  // Any implicit use of exec by VALU is not a real register read.
154  return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
155  isVALU(*MO.getParent()) && !readsExecAsData(*MO.getParent());
156 }
157 
159  int64_t &Offset0,
160  int64_t &Offset1) const {
161  if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
162  return false;
163 
164  unsigned Opc0 = Load0->getMachineOpcode();
165  unsigned Opc1 = Load1->getMachineOpcode();
166 
167  // Make sure both are actually loads.
168  if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
169  return false;
170 
171  if (isDS(Opc0) && isDS(Opc1)) {
172 
173  // FIXME: Handle this case:
174  if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
175  return false;
176 
177  // Check base reg.
178  if (Load0->getOperand(0) != Load1->getOperand(0))
179  return false;
180 
181  // Skip read2 / write2 variants for simplicity.
182  // TODO: We should report true if the used offsets are adjacent (excluded
183  // st64 versions).
184  int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
185  int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
186  if (Offset0Idx == -1 || Offset1Idx == -1)
187  return false;
188 
189  // XXX - be careful of datalesss loads
190  // getNamedOperandIdx returns the index for MachineInstrs. Since they
191  // include the output in the operand list, but SDNodes don't, we need to
192  // subtract the index by one.
193  Offset0Idx -= get(Opc0).NumDefs;
194  Offset1Idx -= get(Opc1).NumDefs;
195  Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
196  Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
197  return true;
198  }
199 
200  if (isSMRD(Opc0) && isSMRD(Opc1)) {
201  // Skip time and cache invalidation instructions.
202  if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
203  AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
204  return false;
205 
207 
208  // Check base reg.
209  if (Load0->getOperand(0) != Load1->getOperand(0))
210  return false;
211 
212  const ConstantSDNode *Load0Offset =
213  dyn_cast<ConstantSDNode>(Load0->getOperand(1));
214  const ConstantSDNode *Load1Offset =
215  dyn_cast<ConstantSDNode>(Load1->getOperand(1));
216 
217  if (!Load0Offset || !Load1Offset)
218  return false;
219 
220  Offset0 = Load0Offset->getZExtValue();
221  Offset1 = Load1Offset->getZExtValue();
222  return true;
223  }
224 
225  // MUBUF and MTBUF can access the same addresses.
226  if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
227 
228  // MUBUF and MTBUF have vaddr at different indices.
229  if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
230  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
231  !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
232  return false;
233 
234  int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
235  int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
236 
237  if (OffIdx0 == -1 || OffIdx1 == -1)
238  return false;
239 
240  // getNamedOperandIdx returns the index for MachineInstrs. Since they
241  // include the output in the operand list, but SDNodes don't, we need to
242  // subtract the index by one.
243  OffIdx0 -= get(Opc0).NumDefs;
244  OffIdx1 -= get(Opc1).NumDefs;
245 
246  SDValue Off0 = Load0->getOperand(OffIdx0);
247  SDValue Off1 = Load1->getOperand(OffIdx1);
248 
249  // The offset might be a FrameIndexSDNode.
250  if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
251  return false;
252 
253  Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
254  Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
255  return true;
256  }
257 
258  return false;
259 }
260 
261 static bool isStride64(unsigned Opc) {
262  switch (Opc) {
263  case AMDGPU::DS_READ2ST64_B32:
264  case AMDGPU::DS_READ2ST64_B64:
265  case AMDGPU::DS_WRITE2ST64_B32:
266  case AMDGPU::DS_WRITE2ST64_B64:
267  return true;
268  default:
269  return false;
270  }
271 }
272 
275  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
276  const TargetRegisterInfo *TRI) const {
277  if (!LdSt.mayLoadOrStore())
278  return false;
279 
280  unsigned Opc = LdSt.getOpcode();
281  OffsetIsScalable = false;
282  const MachineOperand *BaseOp, *OffsetOp;
283  int DataOpIdx;
284 
285  if (isDS(LdSt)) {
286  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
287  OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
288  if (OffsetOp) {
289  // Normal, single offset LDS instruction.
290  if (!BaseOp) {
291  // DS_CONSUME/DS_APPEND use M0 for the base address.
292  // TODO: find the implicit use operand for M0 and use that as BaseOp?
293  return false;
294  }
295  BaseOps.push_back(BaseOp);
296  Offset = OffsetOp->getImm();
297  // Get appropriate operand, and compute width accordingly.
298  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
299  if (DataOpIdx == -1)
300  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
301  Width = getOpSize(LdSt, DataOpIdx);
302  } else {
303  // The 2 offset instructions use offset0 and offset1 instead. We can treat
304  // these as a load with a single offset if the 2 offsets are consecutive.
305  // We will use this for some partially aligned loads.
306  const MachineOperand *Offset0Op =
307  getNamedOperand(LdSt, AMDGPU::OpName::offset0);
308  const MachineOperand *Offset1Op =
309  getNamedOperand(LdSt, AMDGPU::OpName::offset1);
310 
311  unsigned Offset0 = Offset0Op->getImm();
312  unsigned Offset1 = Offset1Op->getImm();
313  if (Offset0 + 1 != Offset1)
314  return false;
315 
316  // Each of these offsets is in element sized units, so we need to convert
317  // to bytes of the individual reads.
318 
319  unsigned EltSize;
320  if (LdSt.mayLoad())
321  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
322  else {
323  assert(LdSt.mayStore());
324  int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
325  EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
326  }
327 
328  if (isStride64(Opc))
329  EltSize *= 64;
330 
331  BaseOps.push_back(BaseOp);
332  Offset = EltSize * Offset0;
333  // Get appropriate operand(s), and compute width accordingly.
334  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
335  if (DataOpIdx == -1) {
336  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
337  Width = getOpSize(LdSt, DataOpIdx);
338  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
339  Width += getOpSize(LdSt, DataOpIdx);
340  } else {
341  Width = getOpSize(LdSt, DataOpIdx);
342  }
343  }
344  return true;
345  }
346 
347  if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
348  const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
349  if (!RSrc) // e.g. BUFFER_WBINVL1_VOL
350  return false;
351  BaseOps.push_back(RSrc);
352  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
353  if (BaseOp && !BaseOp->isFI())
354  BaseOps.push_back(BaseOp);
355  const MachineOperand *OffsetImm =
356  getNamedOperand(LdSt, AMDGPU::OpName::offset);
357  Offset = OffsetImm->getImm();
358  const MachineOperand *SOffset =
359  getNamedOperand(LdSt, AMDGPU::OpName::soffset);
360  if (SOffset) {
361  if (SOffset->isReg())
362  BaseOps.push_back(SOffset);
363  else
364  Offset += SOffset->getImm();
365  }
366  // Get appropriate operand, and compute width accordingly.
367  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
368  if (DataOpIdx == -1)
369  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
370  Width = getOpSize(LdSt, DataOpIdx);
371  return true;
372  }
373 
374  if (isMIMG(LdSt)) {
375  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
376  BaseOps.push_back(&LdSt.getOperand(SRsrcIdx));
377  int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
378  if (VAddr0Idx >= 0) {
379  // GFX10 possible NSA encoding.
380  for (int I = VAddr0Idx; I < SRsrcIdx; ++I)
381  BaseOps.push_back(&LdSt.getOperand(I));
382  } else {
383  BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr));
384  }
385  Offset = 0;
386  // Get appropriate operand, and compute width accordingly.
387  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
388  Width = getOpSize(LdSt, DataOpIdx);
389  return true;
390  }
391 
392  if (isSMRD(LdSt)) {
393  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
394  if (!BaseOp) // e.g. S_MEMTIME
395  return false;
396  BaseOps.push_back(BaseOp);
397  OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset);
398  Offset = OffsetOp ? OffsetOp->getImm() : 0;
399  // Get appropriate operand, and compute width accordingly.
400  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
401  Width = getOpSize(LdSt, DataOpIdx);
402  return true;
403  }
404 
405  if (isFLAT(LdSt)) {
406  // Instructions have either vaddr or saddr or both or none.
407  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
408  if (BaseOp)
409  BaseOps.push_back(BaseOp);
410  BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
411  if (BaseOp)
412  BaseOps.push_back(BaseOp);
413  Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
414  // Get appropriate operand, and compute width accordingly.
415  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
416  if (DataOpIdx == -1)
417  DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
418  Width = getOpSize(LdSt, DataOpIdx);
419  return true;
420  }
421 
422  return false;
423 }
424 
425 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
427  const MachineInstr &MI2,
429  // Only examine the first "base" operand of each instruction, on the
430  // assumption that it represents the real base address of the memory access.
431  // Other operands are typically offsets or indices from this base address.
432  if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front()))
433  return true;
434 
435  if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
436  return false;
437 
438  auto MO1 = *MI1.memoperands_begin();
439  auto MO2 = *MI2.memoperands_begin();
440  if (MO1->getAddrSpace() != MO2->getAddrSpace())
441  return false;
442 
443  auto Base1 = MO1->getValue();
444  auto Base2 = MO2->getValue();
445  if (!Base1 || !Base2)
446  return false;
447  Base1 = getUnderlyingObject(Base1);
448  Base2 = getUnderlyingObject(Base2);
449 
450  if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
451  return false;
452 
453  return Base1 == Base2;
454 }
455 
458  unsigned NumLoads,
459  unsigned NumBytes) const {
460  // If the mem ops (to be clustered) do not have the same base ptr, then they
461  // should not be clustered
462  if (!BaseOps1.empty() && !BaseOps2.empty()) {
463  const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
464  const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
465  if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
466  return false;
467  } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
468  // If only one base op is empty, they do not have the same base ptr
469  return false;
470  }
471 
472  // In order to avoid regester pressure, on an average, the number of DWORDS
473  // loaded together by all clustered mem ops should not exceed 8. This is an
474  // empirical value based on certain observations and performance related
475  // experiments.
476  // The good thing about this heuristic is - it avoids clustering of too many
477  // sub-word loads, and also avoids clustering of wide loads. Below is the
478  // brief summary of how the heuristic behaves for various `LoadSize`.
479  // (1) 1 <= LoadSize <= 4: cluster at max 8 mem ops
480  // (2) 5 <= LoadSize <= 8: cluster at max 4 mem ops
481  // (3) 9 <= LoadSize <= 12: cluster at max 2 mem ops
482  // (4) 13 <= LoadSize <= 16: cluster at max 2 mem ops
483  // (5) LoadSize >= 17: do not cluster
484  const unsigned LoadSize = NumBytes / NumLoads;
485  const unsigned NumDWORDs = ((LoadSize + 3) / 4) * NumLoads;
486  return NumDWORDs <= 8;
487 }
488 
489 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
490 // the first 16 loads will be interleaved with the stores, and the next 16 will
491 // be clustered as expected. It should really split into 2 16 store batches.
492 //
493 // Loads are clustered until this returns false, rather than trying to schedule
494 // groups of stores. This also means we have to deal with saying different
495 // address space loads should be clustered, and ones which might cause bank
496 // conflicts.
497 //
498 // This might be deprecated so it might not be worth that much effort to fix.
500  int64_t Offset0, int64_t Offset1,
501  unsigned NumLoads) const {
502  assert(Offset1 > Offset0 &&
503  "Second offset should be larger than first offset!");
504  // If we have less than 16 loads in a row, and the offsets are within 64
505  // bytes, then schedule together.
506 
507  // A cacheline is 64 bytes (for global memory).
508  return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
509 }
510 
513  const DebugLoc &DL, MCRegister DestReg,
514  MCRegister SrcReg, bool KillSrc,
515  const char *Msg = "illegal SGPR to VGPR copy") {
516  MachineFunction *MF = MBB.getParent();
517  DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(), Msg, DL, DS_Error);
518  LLVMContext &C = MF->getFunction().getContext();
519  C.diagnose(IllegalCopy);
520 
521  BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
522  .addReg(SrcReg, getKillRegState(KillSrc));
523 }
524 
525 /// Handle copying from SGPR to AGPR, or from AGPR to AGPR. It is not possible
526 /// to directly copy, so an intermediate VGPR needs to be used.
527 static void indirectCopyToAGPR(const SIInstrInfo &TII,
530  const DebugLoc &DL, MCRegister DestReg,
531  MCRegister SrcReg, bool KillSrc,
532  RegScavenger &RS,
533  Register ImpDefSuperReg = Register(),
534  Register ImpUseSuperReg = Register()) {
535  const SIRegisterInfo &RI = TII.getRegisterInfo();
536 
537  assert(AMDGPU::SReg_32RegClass.contains(SrcReg) ||
538  AMDGPU::AGPR_32RegClass.contains(SrcReg));
539 
540  // First try to find defining accvgpr_write to avoid temporary registers.
541  for (auto Def = MI, E = MBB.begin(); Def != E; ) {
542  --Def;
543  if (!Def->definesRegister(SrcReg, &RI))
544  continue;
545  if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64)
546  break;
547 
548  MachineOperand &DefOp = Def->getOperand(1);
549  assert(DefOp.isReg() || DefOp.isImm());
550 
551  if (DefOp.isReg()) {
552  // Check that register source operand if not clobbered before MI.
553  // Immediate operands are always safe to propagate.
554  bool SafeToPropagate = true;
555  for (auto I = Def; I != MI && SafeToPropagate; ++I)
556  if (I->modifiesRegister(DefOp.getReg(), &RI))
557  SafeToPropagate = false;
558 
559  if (!SafeToPropagate)
560  break;
561 
562  DefOp.setIsKill(false);
563  }
564 
566  BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
567  .add(DefOp);
568  if (ImpDefSuperReg)
569  Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
570 
571  if (ImpUseSuperReg) {
572  Builder.addReg(ImpUseSuperReg,
574  }
575 
576  return;
577  }
578 
579  RS.enterBasicBlock(MBB);
580  RS.forward(MI);
581 
582  // Ideally we want to have three registers for a long reg_sequence copy
583  // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
584  unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
585  *MBB.getParent());
586 
587  // Registers in the sequence are allocated contiguously so we can just
588  // use register number to pick one of three round-robin temps.
589  unsigned RegNo = DestReg % 3;
590  Register Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
591  if (!Tmp)
592  report_fatal_error("Cannot scavenge VGPR to copy to AGPR");
593  RS.setRegUsed(Tmp);
594 
595  if (!TII.getSubtarget().hasGFX90AInsts()) {
596  // Only loop through if there are any free registers left, otherwise
597  // scavenger may report a fatal error without emergency spill slot
598  // or spill with the slot.
599  while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
600  Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
601  if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
602  break;
603  Tmp = Tmp2;
604  RS.setRegUsed(Tmp);
605  }
606  }
607 
608  // Insert copy to temporary VGPR.
609  unsigned TmpCopyOp = AMDGPU::V_MOV_B32_e32;
610  if (AMDGPU::AGPR_32RegClass.contains(SrcReg)) {
611  TmpCopyOp = AMDGPU::V_ACCVGPR_READ_B32_e64;
612  } else {
613  assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
614  }
615 
616  MachineInstrBuilder UseBuilder = BuildMI(MBB, MI, DL, TII.get(TmpCopyOp), Tmp)
617  .addReg(SrcReg, getKillRegState(KillSrc));
618  if (ImpUseSuperReg) {
619  UseBuilder.addReg(ImpUseSuperReg,
621  }
622 
623  MachineInstrBuilder DefBuilder
624  = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
625  .addReg(Tmp, RegState::Kill);
626 
627  if (ImpDefSuperReg)
628  DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
629 }
630 
633  MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
634  const TargetRegisterClass *RC, bool Forward) {
635  const SIRegisterInfo &RI = TII.getRegisterInfo();
636  ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4);
638  MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
639 
640  for (unsigned Idx = 0; Idx < BaseIndices.size(); ++Idx) {
641  int16_t SubIdx = BaseIndices[Idx];
642  Register Reg = RI.getSubReg(DestReg, SubIdx);
643  unsigned Opcode = AMDGPU::S_MOV_B32;
644 
645  // Is SGPR aligned? If so try to combine with next.
646  Register Src = RI.getSubReg(SrcReg, SubIdx);
647  bool AlignedDest = ((Reg - AMDGPU::SGPR0) % 2) == 0;
648  bool AlignedSrc = ((Src - AMDGPU::SGPR0) % 2) == 0;
649  if (AlignedDest && AlignedSrc && (Idx + 1 < BaseIndices.size())) {
650  // Can use SGPR64 copy
651  unsigned Channel = RI.getChannelFromSubReg(SubIdx);
652  SubIdx = RI.getSubRegFromChannel(Channel, 2);
653  Opcode = AMDGPU::S_MOV_B64;
654  Idx++;
655  }
656 
657  LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), RI.getSubReg(DestReg, SubIdx))
658  .addReg(RI.getSubReg(SrcReg, SubIdx))
659  .addReg(SrcReg, RegState::Implicit);
660 
661  if (!FirstMI)
662  FirstMI = LastMI;
663 
664  if (!Forward)
665  I--;
666  }
667 
668  assert(FirstMI && LastMI);
669  if (!Forward)
670  std::swap(FirstMI, LastMI);
671 
672  FirstMI->addOperand(
673  MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
674 
675  if (KillSrc)
676  LastMI->addRegisterKilled(SrcReg, &RI);
677 }
678 
681  const DebugLoc &DL, MCRegister DestReg,
682  MCRegister SrcReg, bool KillSrc) const {
683  const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
684 
685  // FIXME: This is hack to resolve copies between 16 bit and 32 bit
686  // registers until all patterns are fixed.
687  if (Fix16BitCopies &&
688  ((RI.getRegSizeInBits(*RC) == 16) ^
689  (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) {
690  MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg;
691  MCRegister Super = RI.get32BitRegister(RegToFix);
692  assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix);
693  RegToFix = Super;
694 
695  if (DestReg == SrcReg) {
696  // Insert empty bundle since ExpandPostRA expects an instruction here.
697  BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
698  return;
699  }
700 
701  RC = RI.getPhysRegClass(DestReg);
702  }
703 
704  if (RC == &AMDGPU::VGPR_32RegClass) {
705  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
706  AMDGPU::SReg_32RegClass.contains(SrcReg) ||
707  AMDGPU::AGPR_32RegClass.contains(SrcReg));
708  unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
709  AMDGPU::V_ACCVGPR_READ_B32_e64 : AMDGPU::V_MOV_B32_e32;
710  BuildMI(MBB, MI, DL, get(Opc), DestReg)
711  .addReg(SrcReg, getKillRegState(KillSrc));
712  return;
713  }
714 
715  if (RC == &AMDGPU::SReg_32_XM0RegClass ||
716  RC == &AMDGPU::SReg_32RegClass) {
717  if (SrcReg == AMDGPU::SCC) {
718  BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
719  .addImm(1)
720  .addImm(0);
721  return;
722  }
723 
724  if (DestReg == AMDGPU::VCC_LO) {
725  if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
726  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
727  .addReg(SrcReg, getKillRegState(KillSrc));
728  } else {
729  // FIXME: Hack until VReg_1 removed.
730  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
731  BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
732  .addImm(0)
733  .addReg(SrcReg, getKillRegState(KillSrc));
734  }
735 
736  return;
737  }
738 
739  if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
740  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
741  return;
742  }
743 
744  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
745  .addReg(SrcReg, getKillRegState(KillSrc));
746  return;
747  }
748 
749  if (RC == &AMDGPU::SReg_64RegClass) {
750  if (SrcReg == AMDGPU::SCC) {
751  BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg)
752  .addImm(1)
753  .addImm(0);
754  return;
755  }
756 
757  if (DestReg == AMDGPU::VCC) {
758  if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
759  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
760  .addReg(SrcReg, getKillRegState(KillSrc));
761  } else {
762  // FIXME: Hack until VReg_1 removed.
763  assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
764  BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
765  .addImm(0)
766  .addReg(SrcReg, getKillRegState(KillSrc));
767  }
768 
769  return;
770  }
771 
772  if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
773  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
774  return;
775  }
776 
777  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
778  .addReg(SrcReg, getKillRegState(KillSrc));
779  return;
780  }
781 
782  if (DestReg == AMDGPU::SCC) {
783  // Copying 64-bit or 32-bit sources to SCC barely makes sense,
784  // but SelectionDAG emits such copies for i1 sources.
785  if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
786  // This copy can only be produced by patterns
787  // with explicit SCC, which are known to be enabled
788  // only for subtargets with S_CMP_LG_U64 present.
790  BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U64))
791  .addReg(SrcReg, getKillRegState(KillSrc))
792  .addImm(0);
793  } else {
794  assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
795  BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
796  .addReg(SrcReg, getKillRegState(KillSrc))
797  .addImm(0);
798  }
799 
800  return;
801  }
802 
803  if (RC == &AMDGPU::AGPR_32RegClass) {
804  if (AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
805  BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
806  .addReg(SrcReg, getKillRegState(KillSrc));
807  return;
808  }
809 
810  if (AMDGPU::AGPR_32RegClass.contains(SrcReg) && ST.hasGFX90AInsts()) {
811  BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_MOV_B32), DestReg)
812  .addReg(SrcReg, getKillRegState(KillSrc));
813  return;
814  }
815 
816  // FIXME: Pass should maintain scavenger to avoid scan through the block on
817  // every AGPR spill.
818  RegScavenger RS;
819  indirectCopyToAGPR(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RS);
820  return;
821  }
822 
823  const unsigned Size = RI.getRegSizeInBits(*RC);
824  if (Size == 16) {
825  assert(AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
826  AMDGPU::VGPR_HI16RegClass.contains(SrcReg) ||
827  AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
828  AMDGPU::AGPR_LO16RegClass.contains(SrcReg));
829 
830  bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
831  bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
832  bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
833  bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
834  bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) ||
835  AMDGPU::SReg_LO16RegClass.contains(DestReg) ||
836  AMDGPU::AGPR_LO16RegClass.contains(DestReg);
837  bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
838  AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
839  AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
840  MCRegister NewDestReg = RI.get32BitRegister(DestReg);
841  MCRegister NewSrcReg = RI.get32BitRegister(SrcReg);
842 
843  if (IsSGPRDst) {
844  if (!IsSGPRSrc) {
845  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
846  return;
847  }
848 
849  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
850  .addReg(NewSrcReg, getKillRegState(KillSrc));
851  return;
852  }
853 
854  if (IsAGPRDst || IsAGPRSrc) {
855  if (!DstLow || !SrcLow) {
856  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
857  "Cannot use hi16 subreg with an AGPR!");
858  }
859 
860  copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
861  return;
862  }
863 
864  if (IsSGPRSrc && !ST.hasSDWAScalar()) {
865  if (!DstLow || !SrcLow) {
866  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
867  "Cannot use hi16 subreg on VI!");
868  }
869 
870  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
871  .addReg(NewSrcReg, getKillRegState(KillSrc));
872  return;
873  }
874 
875  auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
876  .addImm(0) // src0_modifiers
877  .addReg(NewSrcReg)
878  .addImm(0) // clamp
884  .addReg(NewDestReg, RegState::Implicit | RegState::Undef);
885  // First implicit operand is $exec.
886  MIB->tieOperands(0, MIB->getNumOperands() - 1);
887  return;
888  }
889 
890  const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg);
891  if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
892  if (ST.hasPackedFP32Ops()) {
893  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestReg)
895  .addReg(SrcReg)
897  .addReg(SrcReg)
898  .addImm(0) // op_sel_lo
899  .addImm(0) // op_sel_hi
900  .addImm(0) // neg_lo
901  .addImm(0) // neg_hi
902  .addImm(0) // clamp
903  .addReg(SrcReg, getKillRegState(KillSrc) | RegState::Implicit);
904  return;
905  }
906  }
907 
908  const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
909  if (RI.isSGPRClass(RC)) {
910  if (!RI.isSGPRClass(SrcRC)) {
911  reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
912  return;
913  }
914  expandSGPRCopy(*this, MBB, MI, DL, DestReg, SrcReg, KillSrc, RC, Forward);
915  return;
916  }
917 
918  unsigned EltSize = 4;
919  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
920  if (RI.isAGPRClass(RC)) {
921  if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC))
922  Opcode = AMDGPU::V_ACCVGPR_MOV_B32;
923  else if (RI.hasVGPRs(SrcRC))
924  Opcode = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
925  else
926  Opcode = AMDGPU::INSTRUCTION_LIST_END;
927  } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) {
928  Opcode = AMDGPU::V_ACCVGPR_READ_B32_e64;
929  } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) &&
930  (RI.isProperlyAlignedRC(*RC) &&
931  (SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
932  // TODO: In 96-bit case, could do a 64-bit mov and then a 32-bit mov.
933  if (ST.hasPackedFP32Ops()) {
934  Opcode = AMDGPU::V_PK_MOV_B32;
935  EltSize = 8;
936  }
937  }
938 
939  // For the cases where we need an intermediate instruction/temporary register
940  // (destination is an AGPR), we need a scavenger.
941  //
942  // FIXME: The pass should maintain this for us so we don't have to re-scan the
943  // whole block for every handled copy.
944  std::unique_ptr<RegScavenger> RS;
945  if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
946  RS.reset(new RegScavenger());
947 
948  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
949 
950  // If there is an overlap, we can't kill the super-register on the last
951  // instruction, since it will also kill the components made live by this def.
952  const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg);
953 
954  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
955  unsigned SubIdx;
956  if (Forward)
957  SubIdx = SubIndices[Idx];
958  else
959  SubIdx = SubIndices[SubIndices.size() - Idx - 1];
960 
961  bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
962 
963  if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
964  Register ImpDefSuper = Idx == 0 ? Register(DestReg) : Register();
965  Register ImpUseSuper = SrcReg;
966  indirectCopyToAGPR(*this, MBB, MI, DL, RI.getSubReg(DestReg, SubIdx),
967  RI.getSubReg(SrcReg, SubIdx), UseKill, *RS,
968  ImpDefSuper, ImpUseSuper);
969  } else if (Opcode == AMDGPU::V_PK_MOV_B32) {
970  Register DstSubReg = RI.getSubReg(DestReg, SubIdx);
971  Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
972  MachineInstrBuilder MIB =
973  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DstSubReg)
975  .addReg(SrcSubReg)
977  .addReg(SrcSubReg)
978  .addImm(0) // op_sel_lo
979  .addImm(0) // op_sel_hi
980  .addImm(0) // neg_lo
981  .addImm(0) // neg_hi
982  .addImm(0) // clamp
983  .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
984  if (Idx == 0)
986  } else {
988  BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx))
989  .addReg(RI.getSubReg(SrcReg, SubIdx));
990  if (Idx == 0)
991  Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
992 
993  Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
994  }
995  }
996 }
997 
998 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
999  int NewOpc;
1000 
1001  // Try to map original to commuted opcode
1002  NewOpc = AMDGPU::getCommuteRev(Opcode);
1003  if (NewOpc != -1)
1004  // Check if the commuted (REV) opcode exists on the target.
1005  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1006 
1007  // Try to map commuted to original opcode
1008  NewOpc = AMDGPU::getCommuteOrig(Opcode);
1009  if (NewOpc != -1)
1010  // Check if the original (non-REV) opcode exists on the target.
1011  return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
1012 
1013  return Opcode;
1014 }
1015 
1018  const DebugLoc &DL, unsigned DestReg,
1019  int64_t Value) const {
1021  const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1022  if (RegClass == &AMDGPU::SReg_32RegClass ||
1023  RegClass == &AMDGPU::SGPR_32RegClass ||
1024  RegClass == &AMDGPU::SReg_32_XM0RegClass ||
1025  RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
1026  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
1027  .addImm(Value);
1028  return;
1029  }
1030 
1031  if (RegClass == &AMDGPU::SReg_64RegClass ||
1032  RegClass == &AMDGPU::SGPR_64RegClass ||
1033  RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
1034  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
1035  .addImm(Value);
1036  return;
1037  }
1038 
1039  if (RegClass == &AMDGPU::VGPR_32RegClass) {
1040  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
1041  .addImm(Value);
1042  return;
1043  }
1044  if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {
1045  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
1046  .addImm(Value);
1047  return;
1048  }
1049 
1050  unsigned EltSize = 4;
1051  unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1052  if (RI.isSGPRClass(RegClass)) {
1053  if (RI.getRegSizeInBits(*RegClass) > 32) {
1054  Opcode = AMDGPU::S_MOV_B64;
1055  EltSize = 8;
1056  } else {
1057  Opcode = AMDGPU::S_MOV_B32;
1058  EltSize = 4;
1059  }
1060  }
1061 
1062  ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
1063  for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
1064  int64_t IdxValue = Idx == 0 ? Value : 0;
1065 
1067  get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx]));
1068  Builder.addImm(IdxValue);
1069  }
1070 }
1071 
1072 const TargetRegisterClass *
1074  return &AMDGPU::VGPR_32RegClass;
1075 }
1076 
1079  const DebugLoc &DL, Register DstReg,
1081  Register TrueReg,
1082  Register FalseReg) const {
1084  const TargetRegisterClass *BoolXExecRC =
1085  RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
1086  assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
1087  "Not a VGPR32 reg");
1088 
1089  if (Cond.size() == 1) {
1090  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1091  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1092  .add(Cond[0]);
1093  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1094  .addImm(0)
1095  .addReg(FalseReg)
1096  .addImm(0)
1097  .addReg(TrueReg)
1098  .addReg(SReg);
1099  } else if (Cond.size() == 2) {
1100  assert(Cond[0].isImm() && "Cond[0] is not an immediate");
1101  switch (Cond[0].getImm()) {
1102  case SIInstrInfo::SCC_TRUE: {
1103  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1104  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1105  : AMDGPU::S_CSELECT_B64), SReg)
1106  .addImm(1)
1107  .addImm(0);
1108  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1109  .addImm(0)
1110  .addReg(FalseReg)
1111  .addImm(0)
1112  .addReg(TrueReg)
1113  .addReg(SReg);
1114  break;
1115  }
1116  case SIInstrInfo::SCC_FALSE: {
1117  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1118  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1119  : AMDGPU::S_CSELECT_B64), SReg)
1120  .addImm(0)
1121  .addImm(1);
1122  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1123  .addImm(0)
1124  .addReg(FalseReg)
1125  .addImm(0)
1126  .addReg(TrueReg)
1127  .addReg(SReg);
1128  break;
1129  }
1130  case SIInstrInfo::VCCNZ: {
1131  MachineOperand RegOp = Cond[1];
1132  RegOp.setImplicit(false);
1133  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1134  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1135  .add(RegOp);
1136  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1137  .addImm(0)
1138  .addReg(FalseReg)
1139  .addImm(0)
1140  .addReg(TrueReg)
1141  .addReg(SReg);
1142  break;
1143  }
1144  case SIInstrInfo::VCCZ: {
1145  MachineOperand RegOp = Cond[1];
1146  RegOp.setImplicit(false);
1147  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1148  BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1149  .add(RegOp);
1150  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1151  .addImm(0)
1152  .addReg(TrueReg)
1153  .addImm(0)
1154  .addReg(FalseReg)
1155  .addReg(SReg);
1156  break;
1157  }
1158  case SIInstrInfo::EXECNZ: {
1159  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1161  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1162  : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1163  .addImm(0);
1164  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1165  : AMDGPU::S_CSELECT_B64), SReg)
1166  .addImm(1)
1167  .addImm(0);
1168  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1169  .addImm(0)
1170  .addReg(FalseReg)
1171  .addImm(0)
1172  .addReg(TrueReg)
1173  .addReg(SReg);
1174  break;
1175  }
1176  case SIInstrInfo::EXECZ: {
1177  Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1179  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1180  : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
1181  .addImm(0);
1182  BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1183  : AMDGPU::S_CSELECT_B64), SReg)
1184  .addImm(0)
1185  .addImm(1);
1186  BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1187  .addImm(0)
1188  .addReg(FalseReg)
1189  .addImm(0)
1190  .addReg(TrueReg)
1191  .addReg(SReg);
1192  llvm_unreachable("Unhandled branch predicate EXECZ");
1193  break;
1194  }
1195  default:
1196  llvm_unreachable("invalid branch predicate");
1197  }
1198  } else {
1199  llvm_unreachable("Can only handle Cond size 1 or 2");
1200  }
1201 }
1202 
1205  const DebugLoc &DL,
1206  Register SrcReg, int Value) const {
1209  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
1210  .addImm(Value)
1211  .addReg(SrcReg);
1212 
1213  return Reg;
1214 }
1215 
1218  const DebugLoc &DL,
1219  Register SrcReg, int Value) const {
1222  BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1223  .addImm(Value)
1224  .addReg(SrcReg);
1225 
1226  return Reg;
1227 }
1228 
1229 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
1230 
1231  if (RI.isAGPRClass(DstRC))
1232  return AMDGPU::COPY;
1233  if (RI.getRegSizeInBits(*DstRC) == 32) {
1234  return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1235  } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1236  return AMDGPU::S_MOV_B64;
1237  } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
1238  return AMDGPU::V_MOV_B64_PSEUDO;
1239  }
1240  return AMDGPU::COPY;
1241 }
1242 
1243 const MCInstrDesc &
1245  bool IsIndirectSrc) const {
1246  if (IsIndirectSrc) {
1247  if (VecSize <= 32) // 4 bytes
1248  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1);
1249  if (VecSize <= 64) // 8 bytes
1250  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2);
1251  if (VecSize <= 96) // 12 bytes
1252  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3);
1253  if (VecSize <= 128) // 16 bytes
1254  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4);
1255  if (VecSize <= 160) // 20 bytes
1256  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5);
1257  if (VecSize <= 256) // 32 bytes
1258  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8);
1259  if (VecSize <= 512) // 64 bytes
1260  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16);
1261  if (VecSize <= 1024) // 128 bytes
1262  return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32);
1263 
1264  llvm_unreachable("unsupported size for IndirectRegReadGPRIDX pseudos");
1265  }
1266 
1267  if (VecSize <= 32) // 4 bytes
1268  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1);
1269  if (VecSize <= 64) // 8 bytes
1270  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2);
1271  if (VecSize <= 96) // 12 bytes
1272  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3);
1273  if (VecSize <= 128) // 16 bytes
1274  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4);
1275  if (VecSize <= 160) // 20 bytes
1276  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5);
1277  if (VecSize <= 256) // 32 bytes
1278  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8);
1279  if (VecSize <= 512) // 64 bytes
1280  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16);
1281  if (VecSize <= 1024) // 128 bytes
1282  return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32);
1283 
1284  llvm_unreachable("unsupported size for IndirectRegWriteGPRIDX pseudos");
1285 }
1286 
1288  if (VecSize <= 32) // 4 bytes
1289  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1290  if (VecSize <= 64) // 8 bytes
1291  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1292  if (VecSize <= 96) // 12 bytes
1293  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1294  if (VecSize <= 128) // 16 bytes
1295  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1296  if (VecSize <= 160) // 20 bytes
1297  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1298  if (VecSize <= 256) // 32 bytes
1299  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1300  if (VecSize <= 512) // 64 bytes
1301  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1302  if (VecSize <= 1024) // 128 bytes
1303  return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1304 
1305  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1306 }
1307 
1308 static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
1309  if (VecSize <= 32) // 4 bytes
1310  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1;
1311  if (VecSize <= 64) // 8 bytes
1312  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2;
1313  if (VecSize <= 96) // 12 bytes
1314  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3;
1315  if (VecSize <= 128) // 16 bytes
1316  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
1317  if (VecSize <= 160) // 20 bytes
1318  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1319  if (VecSize <= 256) // 32 bytes
1320  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
1321  if (VecSize <= 512) // 64 bytes
1322  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16;
1323  if (VecSize <= 1024) // 128 bytes
1324  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32;
1325 
1326  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1327 }
1328 
1329 static unsigned getIndirectSGPRWriteMovRelPseudo64(unsigned VecSize) {
1330  if (VecSize <= 64) // 8 bytes
1331  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1;
1332  if (VecSize <= 128) // 16 bytes
1333  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2;
1334  if (VecSize <= 256) // 32 bytes
1335  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4;
1336  if (VecSize <= 512) // 64 bytes
1337  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8;
1338  if (VecSize <= 1024) // 128 bytes
1339  return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16;
1340 
1341  llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
1342 }
1343 
1344 const MCInstrDesc &
1346  bool IsSGPR) const {
1347  if (IsSGPR) {
1348  switch (EltSize) {
1349  case 32:
1351  case 64:
1353  default:
1354  llvm_unreachable("invalid reg indexing elt size");
1355  }
1356  }
1357 
1358  assert(EltSize == 32 && "invalid reg indexing elt size");
1360 }
1361 
1362 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
1363  switch (Size) {
1364  case 4:
1365  return AMDGPU::SI_SPILL_S32_SAVE;
1366  case 8:
1367  return AMDGPU::SI_SPILL_S64_SAVE;
1368  case 12:
1369  return AMDGPU::SI_SPILL_S96_SAVE;
1370  case 16:
1371  return AMDGPU::SI_SPILL_S128_SAVE;
1372  case 20:
1373  return AMDGPU::SI_SPILL_S160_SAVE;
1374  case 24:
1375  return AMDGPU::SI_SPILL_S192_SAVE;
1376  case 28:
1377  return AMDGPU::SI_SPILL_S224_SAVE;
1378  case 32:
1379  return AMDGPU::SI_SPILL_S256_SAVE;
1380  case 64:
1381  return AMDGPU::SI_SPILL_S512_SAVE;
1382  case 128:
1383  return AMDGPU::SI_SPILL_S1024_SAVE;
1384  default:
1385  llvm_unreachable("unknown register size");
1386  }
1387 }
1388 
1389 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
1390  switch (Size) {
1391  case 4:
1392  return AMDGPU::SI_SPILL_V32_SAVE;
1393  case 8:
1394  return AMDGPU::SI_SPILL_V64_SAVE;
1395  case 12:
1396  return AMDGPU::SI_SPILL_V96_SAVE;
1397  case 16:
1398  return AMDGPU::SI_SPILL_V128_SAVE;
1399  case 20:
1400  return AMDGPU::SI_SPILL_V160_SAVE;
1401  case 24:
1402  return AMDGPU::SI_SPILL_V192_SAVE;
1403  case 28:
1404  return AMDGPU::SI_SPILL_V224_SAVE;
1405  case 32:
1406  return AMDGPU::SI_SPILL_V256_SAVE;
1407  case 64:
1408  return AMDGPU::SI_SPILL_V512_SAVE;
1409  case 128:
1410  return AMDGPU::SI_SPILL_V1024_SAVE;
1411  default:
1412  llvm_unreachable("unknown register size");
1413  }
1414 }
1415 
1416 static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
1417  switch (Size) {
1418  case 4:
1419  return AMDGPU::SI_SPILL_A32_SAVE;
1420  case 8:
1421  return AMDGPU::SI_SPILL_A64_SAVE;
1422  case 12:
1423  return AMDGPU::SI_SPILL_A96_SAVE;
1424  case 16:
1425  return AMDGPU::SI_SPILL_A128_SAVE;
1426  case 20:
1427  return AMDGPU::SI_SPILL_A160_SAVE;
1428  case 24:
1429  return AMDGPU::SI_SPILL_A192_SAVE;
1430  case 28:
1431  return AMDGPU::SI_SPILL_A224_SAVE;
1432  case 32:
1433  return AMDGPU::SI_SPILL_A256_SAVE;
1434  case 64:
1435  return AMDGPU::SI_SPILL_A512_SAVE;
1436  case 128:
1437  return AMDGPU::SI_SPILL_A1024_SAVE;
1438  default:
1439  llvm_unreachable("unknown register size");
1440  }
1441 }
1442 
1443 static unsigned getAVSpillSaveOpcode(unsigned Size) {
1444  switch (Size) {
1445  case 4:
1446  return AMDGPU::SI_SPILL_AV32_SAVE;
1447  case 8:
1448  return AMDGPU::SI_SPILL_AV64_SAVE;
1449  case 12:
1450  return AMDGPU::SI_SPILL_AV96_SAVE;
1451  case 16:
1452  return AMDGPU::SI_SPILL_AV128_SAVE;
1453  case 20:
1454  return AMDGPU::SI_SPILL_AV160_SAVE;
1455  case 24:
1456  return AMDGPU::SI_SPILL_AV192_SAVE;
1457  case 28:
1458  return AMDGPU::SI_SPILL_AV224_SAVE;
1459  case 32:
1460  return AMDGPU::SI_SPILL_AV256_SAVE;
1461  case 64:
1462  return AMDGPU::SI_SPILL_AV512_SAVE;
1463  case 128:
1464  return AMDGPU::SI_SPILL_AV1024_SAVE;
1465  default:
1466  llvm_unreachable("unknown register size");
1467  }
1468 }
1469 
1472  Register SrcReg, bool isKill,
1473  int FrameIndex,
1474  const TargetRegisterClass *RC,
1475  const TargetRegisterInfo *TRI) const {
1476  MachineFunction *MF = MBB.getParent();
1478  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1479  const DebugLoc &DL = MBB.findDebugLoc(MI);
1480 
1481  MachinePointerInfo PtrInfo
1484  PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
1485  FrameInfo.getObjectAlign(FrameIndex));
1486  unsigned SpillSize = TRI->getSpillSize(*RC);
1487 
1489  if (RI.isSGPRClass(RC)) {
1490  MFI->setHasSpilledSGPRs();
1491  assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled");
1492  assert(SrcReg != AMDGPU::EXEC_LO && SrcReg != AMDGPU::EXEC_HI &&
1493  SrcReg != AMDGPU::EXEC && "exec should not be spilled");
1494 
1495  // We are only allowed to create one new instruction when spilling
1496  // registers, so we need to use pseudo instruction for spilling SGPRs.
1497  const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1498 
1499  // The SGPR spill/restore instructions only work on number sgprs, so we need
1500  // to make sure we are using the correct register class.
1501  if (SrcReg.isVirtual() && SpillSize == 4) {
1502  MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1503  }
1504 
1505  BuildMI(MBB, MI, DL, OpDesc)
1506  .addReg(SrcReg, getKillRegState(isKill)) // data
1507  .addFrameIndex(FrameIndex) // addr
1508  .addMemOperand(MMO)
1510 
1511  if (RI.spillSGPRToVGPR())
1512  FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1513  return;
1514  }
1515 
1516  unsigned Opcode = RI.isVectorSuperClass(RC) ? getAVSpillSaveOpcode(SpillSize)
1517  : RI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(SpillSize)
1518  : getVGPRSpillSaveOpcode(SpillSize);
1519  MFI->setHasSpilledVGPRs();
1520 
1521  BuildMI(MBB, MI, DL, get(Opcode))
1522  .addReg(SrcReg, getKillRegState(isKill)) // data
1523  .addFrameIndex(FrameIndex) // addr
1524  .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1525  .addImm(0) // offset
1526  .addMemOperand(MMO);
1527 }
1528 
1529 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
1530  switch (Size) {
1531  case 4:
1532  return AMDGPU::SI_SPILL_S32_RESTORE;
1533  case 8:
1534  return AMDGPU::SI_SPILL_S64_RESTORE;
1535  case 12:
1536  return AMDGPU::SI_SPILL_S96_RESTORE;
1537  case 16:
1538  return AMDGPU::SI_SPILL_S128_RESTORE;
1539  case 20:
1540  return AMDGPU::SI_SPILL_S160_RESTORE;
1541  case 24:
1542  return AMDGPU::SI_SPILL_S192_RESTORE;
1543  case 28:
1544  return AMDGPU::SI_SPILL_S224_RESTORE;
1545  case 32:
1546  return AMDGPU::SI_SPILL_S256_RESTORE;
1547  case 64:
1548  return AMDGPU::SI_SPILL_S512_RESTORE;
1549  case 128:
1550  return AMDGPU::SI_SPILL_S1024_RESTORE;
1551  default:
1552  llvm_unreachable("unknown register size");
1553  }
1554 }
1555 
1556 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
1557  switch (Size) {
1558  case 4:
1559  return AMDGPU::SI_SPILL_V32_RESTORE;
1560  case 8:
1561  return AMDGPU::SI_SPILL_V64_RESTORE;
1562  case 12:
1563  return AMDGPU::SI_SPILL_V96_RESTORE;
1564  case 16:
1565  return AMDGPU::SI_SPILL_V128_RESTORE;
1566  case 20:
1567  return AMDGPU::SI_SPILL_V160_RESTORE;
1568  case 24:
1569  return AMDGPU::SI_SPILL_V192_RESTORE;
1570  case 28:
1571  return AMDGPU::SI_SPILL_V224_RESTORE;
1572  case 32:
1573  return AMDGPU::SI_SPILL_V256_RESTORE;
1574  case 64:
1575  return AMDGPU::SI_SPILL_V512_RESTORE;
1576  case 128:
1577  return AMDGPU::SI_SPILL_V1024_RESTORE;
1578  default:
1579  llvm_unreachable("unknown register size");
1580  }
1581 }
1582 
1583 static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
1584  switch (Size) {
1585  case 4:
1586  return AMDGPU::SI_SPILL_A32_RESTORE;
1587  case 8:
1588  return AMDGPU::SI_SPILL_A64_RESTORE;
1589  case 12:
1590  return AMDGPU::SI_SPILL_A96_RESTORE;
1591  case 16:
1592  return AMDGPU::SI_SPILL_A128_RESTORE;
1593  case 20:
1594  return AMDGPU::SI_SPILL_A160_RESTORE;
1595  case 24:
1596  return AMDGPU::SI_SPILL_A192_RESTORE;
1597  case 28:
1598  return AMDGPU::SI_SPILL_A224_RESTORE;
1599  case 32:
1600  return AMDGPU::SI_SPILL_A256_RESTORE;
1601  case 64:
1602  return AMDGPU::SI_SPILL_A512_RESTORE;
1603  case 128:
1604  return AMDGPU::SI_SPILL_A1024_RESTORE;
1605  default:
1606  llvm_unreachable("unknown register size");
1607  }
1608 }
1609 
1610 static unsigned getAVSpillRestoreOpcode(unsigned Size) {
1611  switch (Size) {
1612  case 4:
1613  return AMDGPU::SI_SPILL_AV32_RESTORE;
1614  case 8:
1615  return AMDGPU::SI_SPILL_AV64_RESTORE;
1616  case 12:
1617  return AMDGPU::SI_SPILL_AV96_RESTORE;
1618  case 16:
1619  return AMDGPU::SI_SPILL_AV128_RESTORE;
1620  case 20:
1621  return AMDGPU::SI_SPILL_AV160_RESTORE;
1622  case 24:
1623  return AMDGPU::SI_SPILL_AV192_RESTORE;
1624  case 28:
1625  return AMDGPU::SI_SPILL_AV224_RESTORE;
1626  case 32:
1627  return AMDGPU::SI_SPILL_AV256_RESTORE;
1628  case 64:
1629  return AMDGPU::SI_SPILL_AV512_RESTORE;
1630  case 128:
1631  return AMDGPU::SI_SPILL_AV1024_RESTORE;
1632  default:
1633  llvm_unreachable("unknown register size");
1634  }
1635 }
1636 
1639  Register DestReg, int FrameIndex,
1640  const TargetRegisterClass *RC,
1641  const TargetRegisterInfo *TRI) const {
1642  MachineFunction *MF = MBB.getParent();
1644  MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1645  const DebugLoc &DL = MBB.findDebugLoc(MI);
1646  unsigned SpillSize = TRI->getSpillSize(*RC);
1647 
1648  MachinePointerInfo PtrInfo
1650 
1652  PtrInfo, MachineMemOperand::MOLoad, FrameInfo.getObjectSize(FrameIndex),
1653  FrameInfo.getObjectAlign(FrameIndex));
1654 
1655  if (RI.isSGPRClass(RC)) {
1656  MFI->setHasSpilledSGPRs();
1657  assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into");
1658  assert(DestReg != AMDGPU::EXEC_LO && DestReg != AMDGPU::EXEC_HI &&
1659  DestReg != AMDGPU::EXEC && "exec should not be spilled");
1660 
1661  // FIXME: Maybe this should not include a memoperand because it will be
1662  // lowered to non-memory instructions.
1663  const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1664  if (DestReg.isVirtual() && SpillSize == 4) {
1666  MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0_XEXECRegClass);
1667  }
1668 
1669  if (RI.spillSGPRToVGPR())
1670  FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1671  BuildMI(MBB, MI, DL, OpDesc, DestReg)
1672  .addFrameIndex(FrameIndex) // addr
1673  .addMemOperand(MMO)
1675 
1676  return;
1677  }
1678 
1679  unsigned Opcode = RI.isVectorSuperClass(RC)
1680  ? getAVSpillRestoreOpcode(SpillSize)
1681  : RI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
1682  : getVGPRSpillRestoreOpcode(SpillSize);
1683  BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1684  .addFrameIndex(FrameIndex) // vaddr
1685  .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1686  .addImm(0) // offset
1687  .addMemOperand(MMO);
1688 }
1689 
1692  insertNoops(MBB, MI, 1);
1693 }
1694 
1697  unsigned Quantity) const {
1699  while (Quantity > 0) {
1700  unsigned Arg = std::min(Quantity, 8u);
1701  Quantity -= Arg;
1702  BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)).addImm(Arg - 1);
1703  }
1704 }
1705 
1707  auto MF = MBB.getParent();
1709 
1710  assert(Info->isEntryFunction());
1711 
1712  if (MBB.succ_empty()) {
1713  bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
1714  if (HasNoTerminator) {
1715  if (Info->returnsVoid()) {
1716  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1717  } else {
1718  BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1719  }
1720  }
1721  }
1722 }
1723 
1725  switch (MI.getOpcode()) {
1726  default:
1727  if (MI.isMetaInstruction())
1728  return 0;
1729  return 1; // FIXME: Do wait states equal cycles?
1730 
1731  case AMDGPU::S_NOP:
1732  return MI.getOperand(0).getImm() + 1;
1733 
1734  // FIXME: Any other pseudo instruction?
1735  // SI_RETURN_TO_EPILOG is a fallthrough to code outside of the function. The
1736  // hazard, even if one exist, won't really be visible. Should we handle it?
1737  case AMDGPU::SI_MASKED_UNREACHABLE:
1738  case AMDGPU::WAVE_BARRIER:
1739  return 0;
1740  }
1741 }
1742 
1744  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1745  MachineBasicBlock &MBB = *MI.getParent();
1747  switch (MI.getOpcode()) {
1748  default: return TargetInstrInfo::expandPostRAPseudo(MI);
1749  case AMDGPU::S_MOV_B64_term:
1750  // This is only a terminator to get the correct spill code placement during
1751  // register allocation.
1752  MI.setDesc(get(AMDGPU::S_MOV_B64));
1753  break;
1754 
1755  case AMDGPU::S_MOV_B32_term:
1756  // This is only a terminator to get the correct spill code placement during
1757  // register allocation.
1758  MI.setDesc(get(AMDGPU::S_MOV_B32));
1759  break;
1760 
1761  case AMDGPU::S_XOR_B64_term:
1762  // This is only a terminator to get the correct spill code placement during
1763  // register allocation.
1764  MI.setDesc(get(AMDGPU::S_XOR_B64));
1765  break;
1766 
1767  case AMDGPU::S_XOR_B32_term:
1768  // This is only a terminator to get the correct spill code placement during
1769  // register allocation.
1770  MI.setDesc(get(AMDGPU::S_XOR_B32));
1771  break;
1772  case AMDGPU::S_OR_B64_term:
1773  // This is only a terminator to get the correct spill code placement during
1774  // register allocation.
1775  MI.setDesc(get(AMDGPU::S_OR_B64));
1776  break;
1777  case AMDGPU::S_OR_B32_term:
1778  // This is only a terminator to get the correct spill code placement during
1779  // register allocation.
1780  MI.setDesc(get(AMDGPU::S_OR_B32));
1781  break;
1782 
1783  case AMDGPU::S_ANDN2_B64_term:
1784  // This is only a terminator to get the correct spill code placement during
1785  // register allocation.
1786  MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1787  break;
1788 
1789  case AMDGPU::S_ANDN2_B32_term:
1790  // This is only a terminator to get the correct spill code placement during
1791  // register allocation.
1792  MI.setDesc(get(AMDGPU::S_ANDN2_B32));
1793  break;
1794 
1795  case AMDGPU::S_AND_B64_term:
1796  // This is only a terminator to get the correct spill code placement during
1797  // register allocation.
1798  MI.setDesc(get(AMDGPU::S_AND_B64));
1799  break;
1800 
1801  case AMDGPU::S_AND_B32_term:
1802  // This is only a terminator to get the correct spill code placement during
1803  // register allocation.
1804  MI.setDesc(get(AMDGPU::S_AND_B32));
1805  break;
1806 
1807  case AMDGPU::V_MOV_B64_PSEUDO: {
1808  Register Dst = MI.getOperand(0).getReg();
1809  Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1810  Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1811 
1812  const MachineOperand &SrcOp = MI.getOperand(1);
1813  // FIXME: Will this work for 64-bit floating point immediates?
1814  assert(!SrcOp.isFPImm());
1815  if (SrcOp.isImm()) {
1816  APInt Imm(64, SrcOp.getImm());
1817  APInt Lo(32, Imm.getLoBits(32).getZExtValue());
1818  APInt Hi(32, Imm.getHiBits(32).getZExtValue());
1819  if (ST.hasPackedFP32Ops() && Lo == Hi && isInlineConstant(Lo)) {
1820  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
1822  .addImm(Lo.getSExtValue())
1824  .addImm(Lo.getSExtValue())
1825  .addImm(0) // op_sel_lo
1826  .addImm(0) // op_sel_hi
1827  .addImm(0) // neg_lo
1828  .addImm(0) // neg_hi
1829  .addImm(0); // clamp
1830  } else {
1831  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1832  .addImm(Lo.getSExtValue())
1834  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1835  .addImm(Hi.getSExtValue())
1837  }
1838  } else {
1839  assert(SrcOp.isReg());
1840  if (ST.hasPackedFP32Ops() &&
1841  !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
1842  BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), Dst)
1843  .addImm(SISrcMods::OP_SEL_1) // src0_mod
1844  .addReg(SrcOp.getReg())
1846  .addReg(SrcOp.getReg())
1847  .addImm(0) // op_sel_lo
1848  .addImm(0) // op_sel_hi
1849  .addImm(0) // neg_lo
1850  .addImm(0) // neg_hi
1851  .addImm(0); // clamp
1852  } else {
1853  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1854  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1856  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1857  .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1859  }
1860  }
1861  MI.eraseFromParent();
1862  break;
1863  }
1864  case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
1865  expandMovDPP64(MI);
1866  break;
1867  }
1868  case AMDGPU::S_MOV_B64_IMM_PSEUDO: {
1869  const MachineOperand &SrcOp = MI.getOperand(1);
1870  assert(!SrcOp.isFPImm());
1871  APInt Imm(64, SrcOp.getImm());
1872  if (Imm.isIntN(32) || isInlineConstant(Imm)) {
1873  MI.setDesc(get(AMDGPU::S_MOV_B64));
1874  break;
1875  }
1876 
1877  Register Dst = MI.getOperand(0).getReg();
1878  Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1879  Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1880 
1881  APInt Lo(32, Imm.getLoBits(32).getZExtValue());
1882  APInt Hi(32, Imm.getHiBits(32).getZExtValue());
1883  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo)
1884  .addImm(Lo.getSExtValue())
1886  BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi)
1887  .addImm(Hi.getSExtValue())
1889  MI.eraseFromParent();
1890  break;
1891  }
1892  case AMDGPU::V_SET_INACTIVE_B32: {
1893  unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1894  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1895  auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1896  FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
1897  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1898  .add(MI.getOperand(2));
1899  BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1900  .addReg(Exec);
1901  MI.eraseFromParent();
1902  break;
1903  }
1904  case AMDGPU::V_SET_INACTIVE_B64: {
1905  unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1906  unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1907  auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec);
1908  FirstNot->addRegisterDead(AMDGPU::SCC, TRI); // SCC is overwritten
1909  MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1910  MI.getOperand(0).getReg())
1911  .add(MI.getOperand(2));
1912  expandPostRAPseudo(*Copy);
1913  BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1914  .addReg(Exec);
1915  MI.eraseFromParent();
1916  break;
1917  }
1918  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V1:
1919  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V2:
1920  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3:
1921  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4:
1922  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5:
1923  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8:
1924  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16:
1925  case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32:
1926  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1:
1927  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2:
1928  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
1929  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
1930  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
1931  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
1932  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16:
1933  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32:
1934  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1:
1935  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2:
1936  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4:
1937  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8:
1938  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16: {
1939  const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);
1940 
1941  unsigned Opc;
1942  if (RI.hasVGPRs(EltRC)) {
1943  Opc = AMDGPU::V_MOVRELD_B32_e32;
1944  } else {
1945  Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64
1946  : AMDGPU::S_MOVRELD_B32;
1947  }
1948 
1949  const MCInstrDesc &OpDesc = get(Opc);
1950  Register VecReg = MI.getOperand(0).getReg();
1951  bool IsUndef = MI.getOperand(1).isUndef();
1952  unsigned SubReg = MI.getOperand(3).getImm();
1953  assert(VecReg == MI.getOperand(1).getReg());
1954 
1955  MachineInstrBuilder MIB =
1956  BuildMI(MBB, MI, DL, OpDesc)
1957  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1958  .add(MI.getOperand(2))
1960  .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1961 
1962  const int ImpDefIdx =
1963  OpDesc.getNumOperands() + OpDesc.getNumImplicitUses();
1964  const int ImpUseIdx = ImpDefIdx + 1;
1965  MIB->tieOperands(ImpDefIdx, ImpUseIdx);
1966  MI.eraseFromParent();
1967  break;
1968  }
1969  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V1:
1970  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2:
1971  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3:
1972  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4:
1973  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5:
1974  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8:
1975  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V16:
1976  case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32: {
1977  assert(ST.useVGPRIndexMode());
1978  Register VecReg = MI.getOperand(0).getReg();
1979  bool IsUndef = MI.getOperand(1).isUndef();
1980  Register Idx = MI.getOperand(3).getReg();
1981  Register SubReg = MI.getOperand(4).getImm();
1982 
1983  MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
1984  .addReg(Idx)
1986  SetOn->getOperand(3).setIsUndef();
1987 
1988  const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write);
1989  MachineInstrBuilder MIB =
1990  BuildMI(MBB, MI, DL, OpDesc)
1991  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1992  .add(MI.getOperand(2))
1994  .addReg(VecReg,
1995  RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1996 
1997  const int ImpDefIdx = OpDesc.getNumOperands() + OpDesc.getNumImplicitUses();
1998  const int ImpUseIdx = ImpDefIdx + 1;
1999  MIB->tieOperands(ImpDefIdx, ImpUseIdx);
2000 
2001  MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2002 
2003  finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2004 
2005  MI.eraseFromParent();
2006  break;
2007  }
2008  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V1:
2009  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V2:
2010  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3:
2011  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4:
2012  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5:
2013  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8:
2014  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V16:
2015  case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V32: {
2016  assert(ST.useVGPRIndexMode());
2017  Register Dst = MI.getOperand(0).getReg();
2018  Register VecReg = MI.getOperand(1).getReg();
2019  bool IsUndef = MI.getOperand(1).isUndef();
2020  Register Idx = MI.getOperand(2).getReg();
2021  Register SubReg = MI.getOperand(3).getImm();
2022 
2023  MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))
2024  .addReg(Idx)
2026  SetOn->getOperand(3).setIsUndef();
2027 
2028  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read))
2029  .addDef(Dst)
2030  .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2031  .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2032 
2033  MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF));
2034 
2035  finalizeBundle(MBB, SetOn->getIterator(), std::next(SetOff->getIterator()));
2036 
2037  MI.eraseFromParent();
2038  break;
2039  }
2040  case AMDGPU::SI_PC_ADD_REL_OFFSET: {
2041  MachineFunction &MF = *MBB.getParent();
2042  Register Reg = MI.getOperand(0).getReg();
2043  Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
2044  Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
2045 
2046  // Create a bundle so these instructions won't be re-ordered by the
2047  // post-RA scheduler.
2048  MIBundleBuilder Bundler(MBB, MI);
2049  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
2050 
2051  // Add 32-bit offset from this instruction to the start of the
2052  // constant data.
2053  Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
2054  .addReg(RegLo)
2055  .add(MI.getOperand(1)));
2056 
2057  MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
2058  .addReg(RegHi);
2059  MIB.add(MI.getOperand(2));
2060 
2061  Bundler.append(MIB);
2062  finalizeBundle(MBB, Bundler.begin());
2063 
2064  MI.eraseFromParent();
2065  break;
2066  }
2067  case AMDGPU::ENTER_STRICT_WWM: {
2068  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2069  // Whole Wave Mode is entered.
2070  MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
2071  : AMDGPU::S_OR_SAVEEXEC_B64));
2072  break;
2073  }
2074  case AMDGPU::ENTER_STRICT_WQM: {
2075  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2076  // STRICT_WQM is entered.
2077  const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2078  const unsigned WQMOp = ST.isWave32() ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64;
2079  const unsigned MovOp = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
2080  BuildMI(MBB, MI, DL, get(MovOp), MI.getOperand(0).getReg()).addReg(Exec);
2081  BuildMI(MBB, MI, DL, get(WQMOp), Exec).addReg(Exec);
2082 
2083  MI.eraseFromParent();
2084  break;
2085  }
2086  case AMDGPU::EXIT_STRICT_WWM:
2087  case AMDGPU::EXIT_STRICT_WQM: {
2088  // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
2089  // WWM/STICT_WQM is exited.
2090  MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
2091  break;
2092  }
2093  }
2094  return true;
2095 }
2096 
2097 std::pair<MachineInstr*, MachineInstr*>
2099  assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
2100 
2101  MachineBasicBlock &MBB = *MI.getParent();
2103  MachineFunction *MF = MBB.getParent();
2105  Register Dst = MI.getOperand(0).getReg();
2106  unsigned Part = 0;
2107  MachineInstr *Split[2];
2108 
2109  for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
2110  auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
2111  if (Dst.isPhysical()) {
2112  MovDPP.addDef(RI.getSubReg(Dst, Sub));
2113  } else {
2114  assert(MRI.isSSA());
2115  auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2116  MovDPP.addDef(Tmp);
2117  }
2118 
2119  for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
2120  const MachineOperand &SrcOp = MI.getOperand(I);
2121  assert(!SrcOp.isFPImm());
2122  if (SrcOp.isImm()) {
2123  APInt Imm(64, SrcOp.getImm());
2124  Imm.ashrInPlace(Part * 32);
2125  MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
2126  } else {
2127  assert(SrcOp.isReg());
2128  Register Src = SrcOp.getReg();
2129  if (Src.isPhysical())
2130  MovDPP.addReg(RI.getSubReg(Src, Sub));
2131  else
2132  MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
2133  }
2134  }
2135 
2136  for (unsigned I = 3; I < MI.getNumExplicitOperands(); ++I)
2137  MovDPP.addImm(MI.getOperand(I).getImm());
2138 
2139  Split[Part] = MovDPP;
2140  ++Part;
2141  }
2142 
2143  if (Dst.isVirtual())
2144  BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
2145  .addReg(Split[0]->getOperand(0).getReg())
2146  .addImm(AMDGPU::sub0)
2147  .addReg(Split[1]->getOperand(0).getReg())
2148  .addImm(AMDGPU::sub1);
2149 
2150  MI.eraseFromParent();
2151  return std::make_pair(Split[0], Split[1]);
2152 }
2153 
2155  MachineOperand &Src0,
2156  unsigned Src0OpName,
2157  MachineOperand &Src1,
2158  unsigned Src1OpName) const {
2159  MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
2160  if (!Src0Mods)
2161  return false;
2162 
2163  MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
2164  assert(Src1Mods &&
2165  "All commutable instructions have both src0 and src1 modifiers");
2166 
2167  int Src0ModsVal = Src0Mods->getImm();
2168  int Src1ModsVal = Src1Mods->getImm();
2169 
2170  Src1Mods->setImm(Src0ModsVal);
2171  Src0Mods->setImm(Src1ModsVal);
2172  return true;
2173 }
2174 
2176  MachineOperand &RegOp,
2177  MachineOperand &NonRegOp) {
2178  Register Reg = RegOp.getReg();
2179  unsigned SubReg = RegOp.getSubReg();
2180  bool IsKill = RegOp.isKill();
2181  bool IsDead = RegOp.isDead();
2182  bool IsUndef = RegOp.isUndef();
2183  bool IsDebug = RegOp.isDebug();
2184 
2185  if (NonRegOp.isImm())
2186  RegOp.ChangeToImmediate(NonRegOp.getImm());
2187  else if (NonRegOp.isFI())
2188  RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
2189  else if (NonRegOp.isGlobal()) {
2190  RegOp.ChangeToGA(NonRegOp.getGlobal(), NonRegOp.getOffset(),
2191  NonRegOp.getTargetFlags());
2192  } else
2193  return nullptr;
2194 
2195  // Make sure we don't reinterpret a subreg index in the target flags.
2196  RegOp.setTargetFlags(NonRegOp.getTargetFlags());
2197 
2198  NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
2199  NonRegOp.setSubReg(SubReg);
2200 
2201  return &MI;
2202 }
2203 
2205  unsigned Src0Idx,
2206  unsigned Src1Idx) const {
2207  assert(!NewMI && "this should never be used");
2208 
2209  unsigned Opc = MI.getOpcode();
2210  int CommutedOpcode = commuteOpcode(Opc);
2211  if (CommutedOpcode == -1)
2212  return nullptr;
2213 
2214  assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
2215  static_cast<int>(Src0Idx) &&
2216  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
2217  static_cast<int>(Src1Idx) &&
2218  "inconsistency with findCommutedOpIndices");
2219 
2220  MachineOperand &Src0 = MI.getOperand(Src0Idx);
2221  MachineOperand &Src1 = MI.getOperand(Src1Idx);
2222 
2223  MachineInstr *CommutedMI = nullptr;
2224  if (Src0.isReg() && Src1.isReg()) {
2225  if (isOperandLegal(MI, Src1Idx, &Src0)) {
2226  // Be sure to copy the source modifiers to the right place.
2227  CommutedMI
2228  = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
2229  }
2230 
2231  } else if (Src0.isReg() && !Src1.isReg()) {
2232  // src0 should always be able to support any operand type, so no need to
2233  // check operand legality.
2234  CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2235  } else if (!Src0.isReg() && Src1.isReg()) {
2236  if (isOperandLegal(MI, Src1Idx, &Src0))
2237  CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2238  } else {
2239  // FIXME: Found two non registers to commute. This does happen.
2240  return nullptr;
2241  }
2242 
2243  if (CommutedMI) {
2244  swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2245  Src1, AMDGPU::OpName::src1_modifiers);
2246 
2247  CommutedMI->setDesc(get(CommutedOpcode));
2248  }
2249 
2250  return CommutedMI;
2251 }
2252 
2253 // This needs to be implemented because the source modifiers may be inserted
2254 // between the true commutable operands, and the base
2255 // TargetInstrInfo::commuteInstruction uses it.
2257  unsigned &SrcOpIdx0,
2258  unsigned &SrcOpIdx1) const {
2259  return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
2260 }
2261 
2262 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
2263  unsigned &SrcOpIdx1) const {
2264  if (!Desc.isCommutable())
2265  return false;
2266 
2267  unsigned Opc = Desc.getOpcode();
2268  int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
2269  if (Src0Idx == -1)
2270  return false;
2271 
2272  int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
2273  if (Src1Idx == -1)
2274  return false;
2275 
2276  return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
2277 }
2278 
2279 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
2280  int64_t BrOffset) const {
2281  // BranchRelaxation should never have to check s_setpc_b64 because its dest
2282  // block is unanalyzable.
2283  assert(BranchOp != AMDGPU::S_SETPC_B64);
2284 
2285  // Convert to dwords.
2286  BrOffset /= 4;
2287 
2288  // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
2289  // from the next instruction.
2290  BrOffset -= 1;
2291 
2292  return isIntN(BranchOffsetBits, BrOffset);
2293 }
2294 
2296  const MachineInstr &MI) const {
2297  if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
2298  // This would be a difficult analysis to perform, but can always be legal so
2299  // there's no need to analyze it.
2300  return nullptr;
2301  }
2302 
2303  return MI.getOperand(0).getMBB();
2304 }
2305 
2307  MachineBasicBlock &DestBB,
2308  MachineBasicBlock &RestoreBB,
2309  const DebugLoc &DL, int64_t BrOffset,
2310  RegScavenger *RS) const {
2311  assert(RS && "RegScavenger required for long branching");
2312  assert(MBB.empty() &&
2313  "new block should be inserted for expanding unconditional branch");
2314  assert(MBB.pred_size() == 1);
2315  assert(RestoreBB.empty() &&
2316  "restore block should be inserted for restoring clobbered registers");
2317 
2318  MachineFunction *MF = MBB.getParent();
2320 
2321  // FIXME: Virtual register workaround for RegScavenger not working with empty
2322  // blocks.
2323  Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2324 
2325  auto I = MBB.end();
2326 
2327  // We need to compute the offset relative to the instruction immediately after
2328  // s_getpc_b64. Insert pc arithmetic code before last terminator.
2329  MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2330 
2331  auto &MCCtx = MF->getContext();
2332  MCSymbol *PostGetPCLabel =
2333  MCCtx.createTempSymbol("post_getpc", /*AlwaysAddSuffix=*/true);
2334  GetPC->setPostInstrSymbol(*MF, PostGetPCLabel);
2335 
2336  MCSymbol *OffsetLo =
2337  MCCtx.createTempSymbol("offset_lo", /*AlwaysAddSuffix=*/true);
2338  MCSymbol *OffsetHi =
2339  MCCtx.createTempSymbol("offset_hi", /*AlwaysAddSuffix=*/true);
2340  BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
2341  .addReg(PCReg, RegState::Define, AMDGPU::sub0)
2342  .addReg(PCReg, 0, AMDGPU::sub0)
2343  .addSym(OffsetLo, MO_FAR_BRANCH_OFFSET);
2344  BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
2345  .addReg(PCReg, RegState::Define, AMDGPU::sub1)
2346  .addReg(PCReg, 0, AMDGPU::sub1)
2347  .addSym(OffsetHi, MO_FAR_BRANCH_OFFSET);
2348 
2349  // Insert the indirect branch after the other terminator.
2350  BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2351  .addReg(PCReg);
2352 
2353  // FIXME: If spilling is necessary, this will fail because this scavenger has
2354  // no emergency stack slots. It is non-trivial to spill in this situation,
2355  // because the restore code needs to be specially placed after the
2356  // jump. BranchRelaxation then needs to be made aware of the newly inserted
2357  // block.
2358  //
2359  // If a spill is needed for the pc register pair, we need to insert a spill
2360  // restore block right before the destination block, and insert a short branch
2361  // into the old destination block's fallthrough predecessor.
2362  // e.g.:
2363  //
2364  // s_cbranch_scc0 skip_long_branch:
2365  //
2366  // long_branch_bb:
2367  // spill s[8:9]
2368  // s_getpc_b64 s[8:9]
2369  // s_add_u32 s8, s8, restore_bb
2370  // s_addc_u32 s9, s9, 0
2371  // s_setpc_b64 s[8:9]
2372  //
2373  // skip_long_branch:
2374  // foo;
2375  //
2376  // .....
2377  //
2378  // dest_bb_fallthrough_predecessor:
2379  // bar;
2380  // s_branch dest_bb
2381  //
2382  // restore_bb:
2383  // restore s[8:9]
2384  // fallthrough dest_bb
2385  ///
2386  // dest_bb:
2387  // buzz;
2388 
2389  RS->enterBasicBlockEnd(MBB);
2391  AMDGPU::SReg_64RegClass, MachineBasicBlock::iterator(GetPC),
2392  /* RestoreAfter */ false, 0, /* AllowSpill */ false);
2393  if (Scav) {
2394  RS->setRegUsed(Scav);
2395  MRI.replaceRegWith(PCReg, Scav);
2396  MRI.clearVirtRegs();
2397  } else {
2398  // As SGPR needs VGPR to be spilled, we reuse the slot of temporary VGPR for
2399  // SGPR spill.
2400  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2401  const SIRegisterInfo *TRI = ST.getRegisterInfo();
2402  TRI->spillEmergencySGPR(GetPC, RestoreBB, AMDGPU::SGPR0_SGPR1, RS);
2403  MRI.replaceRegWith(PCReg, AMDGPU::SGPR0_SGPR1);
2404  MRI.clearVirtRegs();
2405  }
2406 
2407  MCSymbol *DestLabel = Scav ? DestBB.getSymbol() : RestoreBB.getSymbol();
2408  // Now, the distance could be defined.
2410  MCSymbolRefExpr::create(DestLabel, MCCtx),
2411  MCSymbolRefExpr::create(PostGetPCLabel, MCCtx), MCCtx);
2412  // Add offset assignments.
2413  auto *Mask = MCConstantExpr::create(0xFFFFFFFFULL, MCCtx);
2415  auto *ShAmt = MCConstantExpr::create(32, MCCtx);
2416  OffsetHi->setVariableValue(MCBinaryExpr::createAShr(Offset, ShAmt, MCCtx));
2417 }
2418 
2419 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
2420  switch (Cond) {
2421  case SIInstrInfo::SCC_TRUE:
2422  return AMDGPU::S_CBRANCH_SCC1;
2423  case SIInstrInfo::SCC_FALSE:
2424  return AMDGPU::S_CBRANCH_SCC0;
2425  case SIInstrInfo::VCCNZ:
2426  return AMDGPU::S_CBRANCH_VCCNZ;
2427  case SIInstrInfo::VCCZ:
2428  return AMDGPU::S_CBRANCH_VCCZ;
2429  case SIInstrInfo::EXECNZ:
2430  return AMDGPU::S_CBRANCH_EXECNZ;
2431  case SIInstrInfo::EXECZ:
2432  return AMDGPU::S_CBRANCH_EXECZ;
2433  default:
2434  llvm_unreachable("invalid branch predicate");
2435  }
2436 }
2437 
2438 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
2439  switch (Opcode) {
2440  case AMDGPU::S_CBRANCH_SCC0:
2441  return SCC_FALSE;
2442  case AMDGPU::S_CBRANCH_SCC1:
2443  return SCC_TRUE;
2444  case AMDGPU::S_CBRANCH_VCCNZ:
2445  return VCCNZ;
2446  case AMDGPU::S_CBRANCH_VCCZ:
2447  return VCCZ;
2448  case AMDGPU::S_CBRANCH_EXECNZ:
2449  return EXECNZ;
2450  case AMDGPU::S_CBRANCH_EXECZ:
2451  return EXECZ;
2452  default:
2453  return INVALID_BR;
2454  }
2455 }
2456 
2459  MachineBasicBlock *&TBB,
2460  MachineBasicBlock *&FBB,
2462  bool AllowModify) const {
2463  if (I->getOpcode() == AMDGPU::S_BRANCH) {
2464  // Unconditional Branch
2465  TBB = I->getOperand(0).getMBB();
2466  return false;
2467  }
2468 
2469  MachineBasicBlock *CondBB = nullptr;
2470 
2471  if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
2472  CondBB = I->getOperand(1).getMBB();
2473  Cond.push_back(I->getOperand(0));
2474  } else {
2475  BranchPredicate Pred = getBranchPredicate(I->getOpcode());
2476  if (Pred == INVALID_BR)
2477  return true;
2478 
2479  CondBB = I->getOperand(0).getMBB();
2480  Cond.push_back(MachineOperand::CreateImm(Pred));
2481  Cond.push_back(I->getOperand(1)); // Save the branch register.
2482  }
2483  ++I;
2484 
2485  if (I == MBB.end()) {
2486  // Conditional branch followed by fall-through.
2487  TBB = CondBB;
2488  return false;
2489  }
2490 
2491  if (I->getOpcode() == AMDGPU::S_BRANCH) {
2492  TBB = CondBB;
2493  FBB = I->getOperand(0).getMBB();
2494  return false;
2495  }
2496 
2497  return true;
2498 }
2499 
2501  MachineBasicBlock *&FBB,
2503  bool AllowModify) const {
2505  auto E = MBB.end();
2506  if (I == E)
2507  return false;
2508 
2509  // Skip over the instructions that are artificially terminators for special
2510  // exec management.
2511  while (I != E && !I->isBranch() && !I->isReturn()) {
2512  switch (I->getOpcode()) {
2513  case AMDGPU::S_MOV_B64_term:
2514  case AMDGPU::S_XOR_B64_term:
2515  case AMDGPU::S_OR_B64_term:
2516  case AMDGPU::S_ANDN2_B64_term:
2517  case AMDGPU::S_AND_B64_term:
2518  case AMDGPU::S_MOV_B32_term:
2519  case AMDGPU::S_XOR_B32_term:
2520  case AMDGPU::S_OR_B32_term:
2521  case AMDGPU::S_ANDN2_B32_term:
2522  case AMDGPU::S_AND_B32_term:
2523  break;
2524  case AMDGPU::SI_IF:
2525  case AMDGPU::SI_ELSE:
2526  case AMDGPU::SI_KILL_I1_TERMINATOR:
2527  case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
2528  // FIXME: It's messy that these need to be considered here at all.
2529  return true;
2530  default:
2531  llvm_unreachable("unexpected non-branch terminator inst");
2532  }
2533 
2534  ++I;
2535  }
2536 
2537  if (I == E)
2538  return false;
2539 
2540  return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
2541 }
2542 
2544  int *BytesRemoved) const {
2545  unsigned Count = 0;
2546  unsigned RemovedSize = 0;
2548  // Skip over artificial terminators when removing instructions.
2549  if (MI.isBranch() || MI.isReturn()) {
2550  RemovedSize += getInstSizeInBytes(MI);
2551  MI.eraseFromParent();
2552  ++Count;
2553  }
2554  }
2555 
2556  if (BytesRemoved)
2557  *BytesRemoved = RemovedSize;
2558 
2559  return Count;
2560 }
2561 
2562 // Copy the flags onto the implicit condition register operand.
2564  const MachineOperand &OrigCond) {
2565  CondReg.setIsUndef(OrigCond.isUndef());
2566  CondReg.setIsKill(OrigCond.isKill());
2567 }
2568 
2570  MachineBasicBlock *TBB,
2571  MachineBasicBlock *FBB,
2573  const DebugLoc &DL,
2574  int *BytesAdded) const {
2575  if (!FBB && Cond.empty()) {
2576  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2577  .addMBB(TBB);
2578  if (BytesAdded)
2579  *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
2580  return 1;
2581  }
2582 
2583  if(Cond.size() == 1 && Cond[0].isReg()) {
2584  BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2585  .add(Cond[0])
2586  .addMBB(TBB);
2587  return 1;
2588  }
2589 
2590  assert(TBB && Cond[0].isImm());
2591 
2592  unsigned Opcode
2593  = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
2594 
2595  if (!FBB) {
2596  Cond[1].isUndef();
2597  MachineInstr *CondBr =
2598  BuildMI(&MBB, DL, get(Opcode))
2599  .addMBB(TBB);
2600 
2601  // Copy the flags onto the implicit condition register operand.
2602  preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
2603  fixImplicitOperands(*CondBr);
2604 
2605  if (BytesAdded)
2606  *BytesAdded = ST.hasOffset3fBug() ? 8 : 4;
2607  return 1;
2608  }
2609 
2610  assert(TBB && FBB);
2611 
2612  MachineInstr *CondBr =
2613  BuildMI(&MBB, DL, get(Opcode))
2614  .addMBB(TBB);
2615  fixImplicitOperands(*CondBr);
2616  BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2617  .addMBB(FBB);
2618 
2619  MachineOperand &CondReg = CondBr->getOperand(1);
2620  CondReg.setIsUndef(Cond[1].isUndef());
2621  CondReg.setIsKill(Cond[1].isKill());
2622 
2623  if (BytesAdded)
2624  *BytesAdded = ST.hasOffset3fBug() ? 16 : 8;
2625 
2626  return 2;
2627 }
2628 
2631  if (Cond.size() != 2) {
2632  return true;
2633  }
2634 
2635  if (Cond[0].isImm()) {
2636  Cond[0].setImm(-Cond[0].getImm());
2637  return false;
2638  }
2639 
2640  return true;
2641 }
2642 
2645  Register DstReg, Register TrueReg,
2646  Register FalseReg, int &CondCycles,
2647  int &TrueCycles, int &FalseCycles) const {
2648  switch (Cond[0].getImm()) {
2649  case VCCNZ:
2650  case VCCZ: {
2652  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2653  if (MRI.getRegClass(FalseReg) != RC)
2654  return false;
2655 
2656  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2657  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2658 
2659  // Limit to equal cost for branch vs. N v_cndmask_b32s.
2660  return RI.hasVGPRs(RC) && NumInsts <= 6;
2661  }
2662  case SCC_TRUE:
2663  case SCC_FALSE: {
2664  // FIXME: We could insert for VGPRs if we could replace the original compare
2665  // with a vector one.
2667  const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2668  if (MRI.getRegClass(FalseReg) != RC)
2669  return false;
2670 
2671  int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2672 
2673  // Multiples of 8 can do s_cselect_b64
2674  if (NumInsts % 2 == 0)
2675  NumInsts /= 2;
2676 
2677  CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2678  return RI.isSGPRClass(RC);
2679  }
2680  default:
2681  return false;
2682  }
2683 }
2684 
2688  Register TrueReg, Register FalseReg) const {
2689  BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
2690  if (Pred == VCCZ || Pred == SCC_FALSE) {
2691  Pred = static_cast<BranchPredicate>(-Pred);
2692  std::swap(TrueReg, FalseReg);
2693  }
2694 
2696  const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2697  unsigned DstSize = RI.getRegSizeInBits(*DstRC);
2698 
2699  if (DstSize == 32) {
2701  if (Pred == SCC_TRUE) {
2702  Select = BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B32), DstReg)
2703  .addReg(TrueReg)
2704  .addReg(FalseReg);
2705  } else {
2706  // Instruction's operands are backwards from what is expected.
2707  Select = BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e32), DstReg)
2708  .addReg(FalseReg)
2709  .addReg(TrueReg);
2710  }
2711 
2712  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2713  return;
2714  }
2715 
2716  if (DstSize == 64 && Pred == SCC_TRUE) {
2717  MachineInstr *Select =
2718  BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2719  .addReg(TrueReg)
2720  .addReg(FalseReg);
2721 
2722  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2723  return;
2724  }
2725 
2726  static const int16_t Sub0_15[] = {
2727  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
2728  AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
2729  AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
2730  AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
2731  };
2732 
2733  static const int16_t Sub0_15_64[] = {
2734  AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
2735  AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
2736  AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
2737  AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
2738  };
2739 
2740  unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
2741  const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
2742  const int16_t *SubIndices = Sub0_15;
2743  int NElts = DstSize / 32;
2744 
2745  // 64-bit select is only available for SALU.
2746  // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
2747  if (Pred == SCC_TRUE) {
2748  if (NElts % 2) {
2749  SelOp = AMDGPU::S_CSELECT_B32;
2750  EltRC = &AMDGPU::SGPR_32RegClass;
2751  } else {
2752  SelOp = AMDGPU::S_CSELECT_B64;
2753  EltRC = &AMDGPU::SGPR_64RegClass;
2754  SubIndices = Sub0_15_64;
2755  NElts /= 2;
2756  }
2757  }
2758 
2760  MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
2761 
2762  I = MIB->getIterator();
2763 
2765  for (int Idx = 0; Idx != NElts; ++Idx) {
2766  Register DstElt = MRI.createVirtualRegister(EltRC);
2767  Regs.push_back(DstElt);
2768 
2769  unsigned SubIdx = SubIndices[Idx];
2770 
2772  if (SelOp == AMDGPU::V_CNDMASK_B32_e32) {
2773  Select =
2774  BuildMI(MBB, I, DL, get(SelOp), DstElt)
2775  .addReg(FalseReg, 0, SubIdx)
2776  .addReg(TrueReg, 0, SubIdx);
2777  } else {
2778  Select =
2779  BuildMI(MBB, I, DL, get(SelOp), DstElt)
2780  .addReg(TrueReg, 0, SubIdx)
2781  .addReg(FalseReg, 0, SubIdx);
2782  }
2783 
2784  preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2786 
2787  MIB.addReg(DstElt)
2788  .addImm(SubIdx);
2789  }
2790 }
2791 
2793  switch (MI.getOpcode()) {
2794  case AMDGPU::V_MOV_B32_e32:
2795  case AMDGPU::V_MOV_B32_e64:
2796  case AMDGPU::V_MOV_B64_PSEUDO:
2797  case AMDGPU::S_MOV_B32:
2798  case AMDGPU::S_MOV_B64:
2799  case AMDGPU::COPY:
2800  case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
2801  case AMDGPU::V_ACCVGPR_READ_B32_e64:
2802  case AMDGPU::V_ACCVGPR_MOV_B32:
2803  return true;
2804  default:
2805  return false;
2806  }
2807 }
2808 
2810  unsigned Kind) const {
2811  switch(Kind) {
2822  }
2823  return AMDGPUAS::FLAT_ADDRESS;
2824 }
2825 
2827  unsigned Opc = MI.getOpcode();
2828  int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2829  AMDGPU::OpName::src0_modifiers);
2830  int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2831  AMDGPU::OpName::src1_modifiers);
2832  int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2833  AMDGPU::OpName::src2_modifiers);
2834 
2835  MI.RemoveOperand(Src2ModIdx);
2836  MI.RemoveOperand(Src1ModIdx);
2837  MI.RemoveOperand(Src0ModIdx);
2838 }
2839 
2841  Register Reg, MachineRegisterInfo *MRI) const {
2842  if (!MRI->hasOneNonDBGUse(Reg))
2843  return false;
2844 
2845  switch (DefMI.getOpcode()) {
2846  default:
2847  return false;
2848  case AMDGPU::S_MOV_B64:
2849  // TODO: We could fold 64-bit immediates, but this get compilicated
2850  // when there are sub-registers.
2851  return false;
2852 
2853  case AMDGPU::V_MOV_B32_e32:
2854  case AMDGPU::S_MOV_B32:
2855  case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
2856  break;
2857  }
2858 
2859  const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2860  assert(ImmOp);
2861  // FIXME: We could handle FrameIndex values here.
2862  if (!ImmOp->isImm())
2863  return false;
2864 
2865  unsigned Opc = UseMI.getOpcode();
2866  if (Opc == AMDGPU::COPY) {
2867  Register DstReg = UseMI.getOperand(0).getReg();
2868  bool Is16Bit = getOpSize(UseMI, 0) == 2;
2869  bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
2870  unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2871  APInt Imm(32, ImmOp->getImm());
2872 
2873  if (UseMI.getOperand(1).getSubReg() == AMDGPU::hi16)
2874  Imm = Imm.ashr(16);
2875 
2876  if (RI.isAGPR(*MRI, DstReg)) {
2877  if (!isInlineConstant(Imm))
2878  return false;
2879  NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
2880  }
2881 
2882  if (Is16Bit) {
2883  if (isVGPRCopy)
2884  return false; // Do not clobber vgpr_hi16
2885 
2886  if (DstReg.isVirtual() && UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
2887  return false;
2888 
2889  UseMI.getOperand(0).setSubReg(0);
2890  if (DstReg.isPhysical()) {
2891  DstReg = RI.get32BitRegister(DstReg);
2892  UseMI.getOperand(0).setReg(DstReg);
2893  }
2894  assert(UseMI.getOperand(1).getReg().isVirtual());
2895  }
2896 
2897  UseMI.setDesc(get(NewOpc));
2898  UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
2899  UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2900  return true;
2901  }
2902 
2903  if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
2904  Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
2905  Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2906  Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64) {
2907  // Don't fold if we are using source or output modifiers. The new VOP2
2908  // instructions don't have them.
2910  return false;
2911 
2912  // If this is a free constant, there's no reason to do this.
2913  // TODO: We could fold this here instead of letting SIFoldOperands do it
2914  // later.
2915  MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2916 
2917  // Any src operand can be used for the legality check.
2918  if (isInlineConstant(UseMI, *Src0, *ImmOp))
2919  return false;
2920 
2921  bool IsF32 = Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
2922  Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64;
2923  bool IsFMA = Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2924  Opc == AMDGPU::V_FMA_F16_e64 || Opc == AMDGPU::V_FMAC_F16_e64;
2925  MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2926  MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2927 
2928  // Multiplied part is the constant: Use v_madmk_{f16, f32}.
2929  // We should only expect these to be on src0 due to canonicalizations.
2930  if (Src0->isReg() && Src0->getReg() == Reg) {
2931  if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2932  return false;
2933 
2934  if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2935  return false;
2936 
2937  unsigned NewOpc =
2938  IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32 : AMDGPU::V_FMAMK_F16)
2939  : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
2940  if (pseudoToMCOpcode(NewOpc) == -1)
2941  return false;
2942 
2943  // We need to swap operands 0 and 1 since madmk constant is at operand 1.
2944 
2945  const int64_t Imm = ImmOp->getImm();
2946 
2947  // FIXME: This would be a lot easier if we could return a new instruction
2948  // instead of having to modify in place.
2949 
2950  // Remove these first since they are at the end.
2951  UseMI.RemoveOperand(
2952  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2953  UseMI.RemoveOperand(
2954  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2955 
2956  Register Src1Reg = Src1->getReg();
2957  unsigned Src1SubReg = Src1->getSubReg();
2958  Src0->setReg(Src1Reg);
2959  Src0->setSubReg(Src1SubReg);
2960  Src0->setIsKill(Src1->isKill());
2961 
2962  if (Opc == AMDGPU::V_MAC_F32_e64 ||
2963  Opc == AMDGPU::V_MAC_F16_e64 ||
2964  Opc == AMDGPU::V_FMAC_F32_e64 ||
2965  Opc == AMDGPU::V_FMAC_F16_e64)
2966  UseMI.untieRegOperand(
2967  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2968 
2969  Src1->ChangeToImmediate(Imm);
2970 
2972  UseMI.setDesc(get(NewOpc));
2973 
2974  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2975  if (DeleteDef)
2976  DefMI.eraseFromParent();
2977 
2978  return true;
2979  }
2980 
2981  // Added part is the constant: Use v_madak_{f16, f32}.
2982  if (Src2->isReg() && Src2->getReg() == Reg) {
2983  // Not allowed to use constant bus for another operand.
2984  // We can however allow an inline immediate as src0.
2985  bool Src0Inlined = false;
2986  if (Src0->isReg()) {
2987  // Try to inline constant if possible.
2988  // If the Def moves immediate and the use is single
2989  // We are saving VGPR here.
2991  if (Def && Def->isMoveImmediate() &&
2992  isInlineConstant(Def->getOperand(1)) &&
2993  MRI->hasOneUse(Src0->getReg())) {
2994  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2995  Src0Inlined = true;
2996  } else if ((Src0->getReg().isPhysical() &&
2997  (ST.getConstantBusLimit(Opc) <= 1 &&
2998  RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2999  (Src0->getReg().isVirtual() &&
3000  (ST.getConstantBusLimit(Opc) <= 1 &&
3001  RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
3002  return false;
3003  // VGPR is okay as Src0 - fallthrough
3004  }
3005 
3006  if (Src1->isReg() && !Src0Inlined ) {
3007  // We have one slot for inlinable constant so far - try to fill it
3009  if (Def && Def->isMoveImmediate() &&
3010  isInlineConstant(Def->getOperand(1)) &&
3011  MRI->hasOneUse(Src1->getReg()) &&
3012  commuteInstruction(UseMI)) {
3013  Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3014  } else if ((Src1->getReg().isPhysical() &&
3015  RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
3016  (Src1->getReg().isVirtual() &&
3017  RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
3018  return false;
3019  // VGPR is okay as Src1 - fallthrough
3020  }
3021 
3022  unsigned NewOpc =
3023  IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32 : AMDGPU::V_FMAAK_F16)
3024  : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
3025  if (pseudoToMCOpcode(NewOpc) == -1)
3026  return false;
3027 
3028  const int64_t Imm = ImmOp->getImm();
3029 
3030  // FIXME: This would be a lot easier if we could return a new instruction
3031  // instead of having to modify in place.
3032 
3033  // Remove these first since they are at the end.
3034  UseMI.RemoveOperand(
3035  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
3036  UseMI.RemoveOperand(
3037  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
3038 
3039  if (Opc == AMDGPU::V_MAC_F32_e64 ||
3040  Opc == AMDGPU::V_MAC_F16_e64 ||
3041  Opc == AMDGPU::V_FMAC_F32_e64 ||
3042  Opc == AMDGPU::V_FMAC_F16_e64)
3043  UseMI.untieRegOperand(
3044  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
3045 
3046  // ChangingToImmediate adds Src2 back to the instruction.
3047  Src2->ChangeToImmediate(Imm);
3048 
3049  // These come before src2.
3051  UseMI.setDesc(get(NewOpc));
3052  // It might happen that UseMI was commuted
3053  // and we now have SGPR as SRC1. If so 2 inlined
3054  // constant and SGPR are illegal.
3056 
3057  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
3058  if (DeleteDef)
3059  DefMI.eraseFromParent();
3060 
3061  return true;
3062  }
3063  }
3064 
3065  return false;
3066 }
3067 
3068 static bool
3071  if (BaseOps1.size() != BaseOps2.size())
3072  return false;
3073  for (size_t I = 0, E = BaseOps1.size(); I < E; ++I) {
3074  if (!BaseOps1[I]->isIdenticalTo(*BaseOps2[I]))
3075  return false;
3076  }
3077  return true;
3078 }
3079 
3080 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
3081  int WidthB, int OffsetB) {
3082  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
3083  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
3084  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
3085  return LowOffset + LowWidth <= HighOffset;
3086 }
3087 
3088 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
3089  const MachineInstr &MIb) const {
3090  SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
3091  int64_t Offset0, Offset1;
3092  unsigned Dummy0, Dummy1;
3093  bool Offset0IsScalable, Offset1IsScalable;
3094  if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
3095  Dummy0, &RI) ||
3096  !getMemOperandsWithOffsetWidth(MIb, BaseOps1, Offset1, Offset1IsScalable,
3097  Dummy1, &RI))
3098  return false;
3099 
3100  if (!memOpsHaveSameBaseOperands(BaseOps0, BaseOps1))
3101  return false;
3102 
3103  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
3104  // FIXME: Handle ds_read2 / ds_write2.
3105  return false;
3106  }
3107  unsigned Width0 = MIa.memoperands().front()->getSize();
3108  unsigned Width1 = MIb.memoperands().front()->getSize();
3109  return offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1);
3110 }
3111 
3113  const MachineInstr &MIb) const {
3114  assert(MIa.mayLoadOrStore() &&
3115  "MIa must load from or modify a memory location");
3116  assert(MIb.mayLoadOrStore() &&
3117  "MIb must load from or modify a memory location");
3118 
3120  return false;
3121 
3122  // XXX - Can we relax this between address spaces?
3123  if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
3124  return false;
3125 
3126  // TODO: Should we check the address space from the MachineMemOperand? That
3127  // would allow us to distinguish objects we know don't alias based on the
3128  // underlying address space, even if it was lowered to a different one,
3129  // e.g. private accesses lowered to use MUBUF instructions on a scratch
3130  // buffer.
3131  if (isDS(MIa)) {
3132  if (isDS(MIb))
3133  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3134 
3135  return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
3136  }
3137 
3138  if (isMUBUF(MIa) || isMTBUF(MIa)) {
3139  if (isMUBUF(MIb) || isMTBUF(MIb))
3140  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3141 
3142  return !isFLAT(MIb) && !isSMRD(MIb);
3143  }
3144 
3145  if (isSMRD(MIa)) {
3146  if (isSMRD(MIb))
3147  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3148 
3149  return !isFLAT(MIb) && !isMUBUF(MIb) && !isMTBUF(MIb);
3150  }
3151 
3152  if (isFLAT(MIa)) {
3153  if (isFLAT(MIb))
3154  return checkInstOffsetsDoNotOverlap(MIa, MIb);
3155 
3156  return false;
3157  }
3158 
3159  return false;
3160 }
3161 
3163  int64_t &Imm, MachineInstr **DefMI = nullptr) {
3164  if (Reg.isPhysical())
3165  return false;
3166  auto *Def = MRI.getUniqueVRegDef(Reg);
3167  if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {
3168  Imm = Def->getOperand(1).getImm();
3169  if (DefMI)
3170  *DefMI = Def;
3171  return true;
3172  }
3173  return false;
3174 }
3175 
3176 static bool getFoldableImm(const MachineOperand *MO, int64_t &Imm,
3177  MachineInstr **DefMI = nullptr) {
3178  if (!MO->isReg())
3179  return false;
3180  const MachineFunction *MF = MO->getParent()->getParent()->getParent();
3181  const MachineRegisterInfo &MRI = MF->getRegInfo();
3182  return getFoldableImm(MO->getReg(), MRI, Imm, DefMI);
3183 }
3184 
3186  MachineInstr &NewMI) {
3187  if (LV) {
3188  unsigned NumOps = MI.getNumOperands();
3189  for (unsigned I = 1; I < NumOps; ++I) {
3190  MachineOperand &Op = MI.getOperand(I);
3191  if (Op.isReg() && Op.isKill())
3192  LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
3193  }
3194  }
3195 }
3196 
3198  LiveVariables *LV,
3199  LiveIntervals *LIS) const {
3200  unsigned Opc = MI.getOpcode();
3201  bool IsF16 = false;
3202  bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
3203  Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
3204  Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3205  bool IsF64 = Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
3206 
3207  switch (Opc) {
3208  default:
3209  return nullptr;
3210  case AMDGPU::V_MAC_F16_e64:
3211  case AMDGPU::V_FMAC_F16_e64:
3212  IsF16 = true;
3214  case AMDGPU::V_MAC_F32_e64:
3215  case AMDGPU::V_FMAC_F32_e64:
3216  case AMDGPU::V_FMAC_F64_e64:
3217  break;
3218  case AMDGPU::V_MAC_F16_e32:
3219  case AMDGPU::V_FMAC_F16_e32:
3220  IsF16 = true;
3222  case AMDGPU::V_MAC_F32_e32:
3223  case AMDGPU::V_FMAC_F32_e32:
3224  case AMDGPU::V_FMAC_F64_e32: {
3225  int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3226  AMDGPU::OpName::src0);
3227  const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3228  if (!Src0->isReg() && !Src0->isImm())
3229  return nullptr;
3230 
3231  if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
3232  return nullptr;
3233 
3234  break;
3235  }
3236  }
3237 
3238  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3239  const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
3240  const MachineOperand *Src0Mods =
3241  getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
3242  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3243  const MachineOperand *Src1Mods =
3244  getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
3245  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3246  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3247  const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
3248  MachineInstrBuilder MIB;
3249  MachineBasicBlock &MBB = *MI.getParent();
3250 
3251  if (!Src0Mods && !Src1Mods && !Clamp && !Omod && !IsF64 &&
3252  // If we have an SGPR input, we will violate the constant bus restriction.
3253  (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
3254  !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
3256  const auto killDef = [&DefMI, &MBB, this]() -> void {
3258  // The only user is the instruction which will be killed.
3260  return;
3261  // We cannot just remove the DefMI here, calling pass will crash.
3262  DefMI->setDesc(get(AMDGPU::IMPLICIT_DEF));
3263  for (unsigned I = DefMI->getNumOperands() - 1; I != 0; --I)
3264  DefMI->RemoveOperand(I);
3265  };
3266 
3267  int64_t Imm;
3268  if (getFoldableImm(Src2, Imm, &DefMI)) {
3269  unsigned NewOpc =
3270  IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
3271  : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
3272  if (pseudoToMCOpcode(NewOpc) != -1) {
3273  MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3274  .add(*Dst)
3275  .add(*Src0)
3276  .add(*Src1)
3277  .addImm(Imm);
3278  updateLiveVariables(LV, MI, *MIB);
3279  if (LIS)
3280  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3281  killDef();
3282  return MIB;
3283  }
3284  }
3285  unsigned NewOpc = IsFMA
3286  ? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
3287  : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
3288  if (getFoldableImm(Src1, Imm, &DefMI)) {
3289  if (pseudoToMCOpcode(NewOpc) != -1) {
3290  MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3291  .add(*Dst)
3292  .add(*Src0)
3293  .addImm(Imm)
3294  .add(*Src2);
3295  updateLiveVariables(LV, MI, *MIB);
3296  if (LIS)
3297  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3298  killDef();
3299  return MIB;
3300  }
3301  }
3302  if (getFoldableImm(Src0, Imm, &DefMI)) {
3303  if (pseudoToMCOpcode(NewOpc) != -1 &&
3305  MI, AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::src0),
3306  Src1)) {
3307  MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3308  .add(*Dst)
3309  .add(*Src1)
3310  .addImm(Imm)
3311  .add(*Src2);
3312  updateLiveVariables(LV, MI, *MIB);
3313  if (LIS)
3314  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3315  killDef();
3316  return MIB;
3317  }
3318  }
3319  }
3320 
3321  unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
3322  : IsF64 ? AMDGPU::V_FMA_F64_e64
3323  : AMDGPU::V_FMA_F32_e64)
3324  : (IsF16 ? AMDGPU::V_MAD_F16_e64 : AMDGPU::V_MAD_F32_e64);
3325  if (pseudoToMCOpcode(NewOpc) == -1)
3326  return nullptr;
3327 
3328  MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3329  .add(*Dst)
3330  .addImm(Src0Mods ? Src0Mods->getImm() : 0)
3331  .add(*Src0)
3332  .addImm(Src1Mods ? Src1Mods->getImm() : 0)
3333  .add(*Src1)
3334  .addImm(0) // Src mods
3335  .add(*Src2)
3336  .addImm(Clamp ? Clamp->getImm() : 0)
3337  .addImm(Omod ? Omod->getImm() : 0);
3338  updateLiveVariables(LV, MI, *MIB);
3339  if (LIS)
3340  LIS->ReplaceMachineInstrInMaps(MI, *MIB);
3341  return MIB;
3342 }
3343 
3344 // It's not generally safe to move VALU instructions across these since it will
3345 // start using the register as a base index rather than directly.
3346 // XXX - Why isn't hasSideEffects sufficient for these?
3348  switch (MI.getOpcode()) {
3349  case AMDGPU::S_SET_GPR_IDX_ON:
3350  case AMDGPU::S_SET_GPR_IDX_MODE:
3351  case AMDGPU::S_SET_GPR_IDX_OFF:
3352  return true;
3353  default:
3354  return false;
3355  }
3356 }
3357 
3359  const MachineBasicBlock *MBB,
3360  const MachineFunction &MF) const {
3361  // Skipping the check for SP writes in the base implementation. The reason it
3362  // was added was apparently due to compile time concerns.
3363  //
3364  // TODO: Do we really want this barrier? It triggers unnecessary hazard nops
3365  // but is probably avoidable.
3366 
3367  // Copied from base implementation.
3368  // Terminators and labels can't be scheduled around.
3369  if (MI.isTerminator() || MI.isPosition())
3370  return true;
3371 
3372  // INLINEASM_BR can jump to another block
3373  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
3374  return true;
3375 
3376  // Target-independent instructions do not have an implicit-use of EXEC, even
3377  // when they operate on VGPRs. Treating EXEC modifications as scheduling
3378  // boundaries prevents incorrect movements of such instructions.
3379  return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
3380  MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
3381  MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
3383 }
3384 
3386  return Opcode == AMDGPU::DS_ORDERED_COUNT ||
3387  Opcode == AMDGPU::DS_GWS_INIT ||
3388  Opcode == AMDGPU::DS_GWS_SEMA_V ||
3389  Opcode == AMDGPU::DS_GWS_SEMA_BR ||
3390  Opcode == AMDGPU::DS_GWS_SEMA_P ||
3391  Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
3392  Opcode == AMDGPU::DS_GWS_BARRIER;
3393 }
3394 
3396  // Skip the full operand and register alias search modifiesRegister
3397  // does. There's only a handful of instructions that touch this, it's only an
3398  // implicit def, and doesn't alias any other registers.
3399  if (const MCPhysReg *ImpDef = MI.getDesc().getImplicitDefs()) {
3400  for (; ImpDef && *ImpDef; ++ImpDef) {
3401  if (*ImpDef == AMDGPU::MODE)
3402  return true;
3403  }
3404  }
3405 
3406  return false;
3407 }
3408 
3410  unsigned Opcode = MI.getOpcode();
3411 
3412  if (MI.mayStore() && isSMRD(MI))
3413  return true; // scalar store or atomic
3414 
3415  // This will terminate the function when other lanes may need to continue.
3416  if (MI.isReturn())
3417  return true;
3418 
3419  // These instructions cause shader I/O that may cause hardware lockups
3420  // when executed with an empty EXEC mask.
3421  //
3422  // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
3423  // EXEC = 0, but checking for that case here seems not worth it
3424  // given the typical code patterns.
3425  if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
3426  isEXP(Opcode) ||
3427  Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
3428  Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
3429  return true;
3430 
3431  if (MI.isCall() || MI.isInlineAsm())
3432  return true; // conservative assumption
3433 
3434  // A mode change is a scalar operation that influences vector instructions.
3435  if (modifiesModeRegister(MI))
3436  return true;
3437 
3438  // These are like SALU instructions in terms of effects, so it's questionable
3439  // whether we should return true for those.
3440  //
3441  // However, executing them with EXEC = 0 causes them to operate on undefined
3442  // data, which we avoid by returning true here.
3443  if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
3444  Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32)
3445  return true;
3446 
3447  return false;
3448 }
3449 
3451  const MachineInstr &MI) const {
3452  if (MI.isMetaInstruction())
3453  return false;
3454 
3455  // This won't read exec if this is an SGPR->SGPR copy.
3456  if (MI.isCopyLike()) {
3457  if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
3458  return true;
3459 
3460  // Make sure this isn't copying exec as a normal operand
3461  return MI.readsRegister(AMDGPU::EXEC, &RI);
3462  }
3463 
3464  // Make a conservative assumption about the callee.
3465  if (MI.isCall())
3466  return true;
3467 
3468  // Be conservative with any unhandled generic opcodes.
3469  if (!isTargetSpecificOpcode(MI.getOpcode()))
3470  return true;
3471 
3472  return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
3473 }
3474 
3475 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
3476  switch (Imm.getBitWidth()) {
3477  case 1: // This likely will be a condition code mask.
3478  return true;
3479 
3480  case 32:
3482  ST.hasInv2PiInlineImm());
3483  case 64:
3485  ST.hasInv2PiInlineImm());
3486  case 16:
3487  return ST.has16BitInsts() &&
3489  ST.hasInv2PiInlineImm());
3490  default:
3491  llvm_unreachable("invalid bitwidth");
3492  }
3493 }
3494 
3496  uint8_t OperandType) const {
3497  if (!MO.isImm() ||
3500  return false;
3501 
3502  // MachineOperand provides no way to tell the true operand size, since it only
3503  // records a 64-bit value. We need to know the size to determine if a 32-bit
3504  // floating point immediate bit pattern is legal for an integer immediate. It
3505  // would be for any 32-bit integer operand, but would not be for a 64-bit one.
3506 
3507  int64_t Imm = MO.getImm();
3508  switch (OperandType) {
3520  int32_t Trunc = static_cast<int32_t>(Imm);
3522  }
3529  ST.hasInv2PiInlineImm());
3533  // We would expect inline immediates to not be concerned with an integer/fp
3534  // distinction. However, in the case of 16-bit integer operations, the
3535  // "floating point" values appear to not work. It seems read the low 16-bits
3536  // of 32-bit immediates, which happens to always work for the integer
3537  // values.
3538  //
3539  // See llvm bugzilla 46302.
3540  //
3541  // TODO: Theoretically we could use op-sel to use the high bits of the
3542  // 32-bit FP values.
3543  return AMDGPU::isInlinableIntLiteral(Imm);
3547  // This suffers the same problem as the scalar 16-bit cases.
3553  if (isInt<16>(Imm) || isUInt<16>(Imm)) {
3554  // A few special case instructions have 16-bit operands on subtargets
3555  // where 16-bit instructions are not legal.
3556  // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
3557  // constants in these cases
3558  int16_t Trunc = static_cast<int16_t>(Imm);
3559  return ST.has16BitInsts() &&
3561  }
3562 
3563  return false;
3564  }
3568  uint32_t Trunc = static_cast<uint32_t>(Imm);
3570  }
3573  return false;
3574  default:
3575  llvm_unreachable("invalid bitwidth");
3576  }
3577 }
3578 
3580  const MCOperandInfo &OpInfo) const {
3581  switch (MO.getType()) {
3583  return false;
3585  return !isInlineConstant(MO, OpInfo);
3591  return true;
3592  default:
3593  llvm_unreachable("unexpected operand type");
3594  }
3595 }
3596 
3597 static bool compareMachineOp(const MachineOperand &Op0,
3598  const MachineOperand &Op1) {
3599  if (Op0.getType() != Op1.getType())
3600  return false;
3601 
3602  switch (Op0.getType()) {
3604  return Op0.getReg() == Op1.getReg();
3606  return Op0.getImm() == Op1.getImm();
3607  default:
3608  llvm_unreachable("Didn't expect to be comparing these operand types");
3609  }
3610 }
3611 
3613  const MachineOperand &MO) const {
3614  const MCInstrDesc &InstDesc = MI.getDesc();
3615  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
3616 
3617  assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
3618 
3619  if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
3620  return true;
3621 
3622  if (OpInfo.RegClass < 0)
3623  return false;
3624 
3625  if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
3626  if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
3627  OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
3628  AMDGPU::OpName::src2))
3629  return false;
3630  return RI.opCanUseInlineConstant(OpInfo.OperandType);
3631  }
3632 
3633  if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
3634  return false;
3635 
3636  if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
3637  return true;
3638 
3639  return ST.hasVOP3Literal();
3640 }
3641 
3642 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
3643  // GFX90A does not have V_MUL_LEGACY_F32_e32.
3644  if (Opcode == AMDGPU::V_MUL_LEGACY_F32_e64 && ST.hasGFX90AInsts())
3645  return false;
3646 
3647  int Op32 = AMDGPU::getVOPe32(Opcode);
3648  if (Op32 == -1)
3649  return false;
3650 
3651  return pseudoToMCOpcode(Op32) != -1;
3652 }
3653 
3654 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
3655  // The src0_modifier operand is present on all instructions
3656  // that have modifiers.
3657 
3658  return AMDGPU::getNamedOperandIdx(Opcode,
3659  AMDGPU::OpName::src0_modifiers) != -1;
3660 }
3661 
3663  unsigned OpName) const {
3664  const MachineOperand *Mods = getNamedOperand(MI, OpName);
3665  return Mods && Mods->getImm();
3666 }
3667 
3669  return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
3670  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
3671  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
3672  hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
3673  hasModifiersSet(MI, AMDGPU::OpName::omod);
3674 }
3675 
3677  const MachineRegisterInfo &MRI) const {
3678  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3679  // Can't shrink instruction with three operands.
3680  if (Src2) {
3681  switch (MI.getOpcode()) {
3682  default: return false;
3683 
3684  case AMDGPU::V_ADDC_U32_e64:
3685  case AMDGPU::V_SUBB_U32_e64:
3686  case AMDGPU::V_SUBBREV_U32_e64: {
3687  const MachineOperand *Src1
3688  = getNamedOperand(MI, AMDGPU::OpName::src1);
3689  if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
3690  return false;
3691  // Additional verification is needed for sdst/src2.
3692  return true;
3693  }
3694  case AMDGPU::V_MAC_F16_e64:
3695  case AMDGPU::V_MAC_F32_e64:
3696  case AMDGPU::V_MAC_LEGACY_F32_e64:
3697  case AMDGPU::V_FMAC_F16_e64:
3698  case AMDGPU::V_FMAC_F32_e64:
3699  case AMDGPU::V_FMAC_F64_e64:
3700  case AMDGPU::V_FMAC_LEGACY_F32_e64:
3701  if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
3702  hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
3703  return false;
3704  break;
3705 
3706  case AMDGPU::V_CNDMASK_B32_e64:
3707  break;
3708  }
3709  }
3710 
3711  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3712  if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
3713  hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
3714  return false;
3715 
3716  // We don't need to check src0, all input types are legal, so just make sure
3717  // src0 isn't using any modifiers.
3718  if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
3719  return false;
3720 
3721  // Can it be shrunk to a valid 32 bit opcode?
3722  if (!hasVALU32BitEncoding(MI.getOpcode()))
3723  return false;
3724 
3725  // Check output modifiers
3726  return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
3727  !hasModifiersSet(MI, AMDGPU::OpName::clamp);
3728 }
3729 
3730 // Set VCC operand with all flags from \p Orig, except for setting it as
3731 // implicit.
3733  const MachineOperand &Orig) {
3734 
3735  for (MachineOperand &Use : MI.implicit_operands()) {
3736  if (Use.isUse() &&
3737  (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
3738  Use.setIsUndef(Orig.isUndef());
3739  Use.setIsKill(Orig.isKill());
3740  return;
3741  }
3742  }
3743 }
3744 
3746  unsigned Op32) const {
3747  MachineBasicBlock *MBB = MI.getParent();;
3748  MachineInstrBuilder Inst32 =
3749  BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32))
3750  .setMIFlags(MI.getFlags());
3751 
3752  // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
3753  // For VOPC instructions, this is replaced by an implicit def of vcc.
3754  int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
3755  if (Op32DstIdx != -1) {
3756  // dst
3757  Inst32.add(MI.getOperand(0));
3758  } else {
3759  assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3760  (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
3761  "Unexpected case");
3762  }
3763 
3764  Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
3765 
3766  const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3767  if (Src1)
3768  Inst32.add(*Src1);
3769 
3770  const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3771 
3772  if (Src2) {
3773  int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
3774  if (Op32Src2Idx != -1) {
3775  Inst32.add(*Src2);
3776  } else {
3777  // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
3778  // replaced with an implicit read of vcc or vcc_lo. The implicit read
3779  // of vcc was already added during the initial BuildMI, but we
3780  // 1) may need to change vcc to vcc_lo to preserve the original register
3781  // 2) have to preserve the original flags.
3782  fixImplicitOperands(*Inst32);
3783  copyFlagsToImplicitVCC(*Inst32, *Src2);
3784  }
3785  }
3786 
3787  return Inst32;
3788 }
3789 
3791  const MachineOperand &MO,
3792  const MCOperandInfo &OpInfo) const {
3793  // Literal constants use the constant bus.
3794  //if (isLiteralConstantLike(MO, OpInfo))
3795  // return true;
3796  if (MO.isImm())
3797  return !isInlineConstant(MO, OpInfo);
3798 
3799  if (!MO.isReg())
3800  return true; // Misc other operands like FrameIndex
3801 
3802  if (!MO.isUse())
3803  return false;
3804 
3805  if (MO.getReg().isVirtual())
3806  return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3807 
3808  // Null is free
3809  if (MO.getReg() == AMDGPU::SGPR_NULL)
3810  return false;
3811 
3812  // SGPRs use the constant bus
3813  if (MO.isImplicit()) {
3814  return MO.getReg() == AMDGPU::M0 ||
3815  MO.getReg() == AMDGPU::VCC ||
3816  MO.getReg() == AMDGPU::VCC_LO;
3817  } else {
3818  return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
3819  AMDGPU::SReg_64RegClass.contains(MO.getReg());
3820  }
3821 }
3822 
3824  for (const MachineOperand &MO : MI.implicit_operands()) {
3825  // We only care about reads.
3826  if (MO.isDef())
3827  continue;
3828 
3829  switch (MO.getReg()) {
3830  case AMDGPU::VCC:
3831  case AMDGPU::VCC_LO:
3832  case AMDGPU::VCC_HI:
3833  case AMDGPU::M0:
3834  case AMDGPU::FLAT_SCR:
3835  return MO.getReg();
3836 
3837  default:
3838  break;
3839  }
3840  }
3841 
3842  return AMDGPU::NoRegister;
3843 }
3844 
3845 static bool shouldReadExec(const MachineInstr &MI) {
3846  if (SIInstrInfo::isVALU(MI)) {
3847  switch (MI.getOpcode()) {
3848  case AMDGPU::V_READLANE_B32:
3849  case AMDGPU::V_WRITELANE_B32:
3850  return false;
3851  }
3852 
3853  return true;
3854  }
3855 
3856  if (MI.isPreISelOpcode() ||
3857  SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
3860  return false;
3861 
3862  return true;
3863 }
3864 
3865 static bool isSubRegOf(const SIRegisterInfo &TRI,
3866  const MachineOperand &SuperVec,
3867  const MachineOperand &SubReg) {
3868  if (SubReg.getReg().isPhysical())
3869  return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
3870 
3871  return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
3872  SubReg.getReg() == SuperVec.getReg();
3873 }
3874 
3876  StringRef &ErrInfo) const {
3877  uint16_t Opcode = MI.getOpcode();
3878  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
3879  return true;
3880 
3881  const MachineFunction *MF = MI.getParent()->getParent();
3882  const MachineRegisterInfo &MRI = MF->getRegInfo();
3883 
3884  int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
3885  int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
3886  int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
3887 
3888  // Make sure the number of operands is correct.
3889  const MCInstrDesc &Desc = get(Opcode);
3890  if (!Desc.isVariadic() &&
3891  Desc.getNumOperands() != MI.getNumExplicitOperands()) {
3892  ErrInfo = "Instruction has wrong number of operands.";
3893  return false;
3894  }
3895 
3896  if (MI.isInlineAsm()) {
3897  // Verify register classes for inlineasm constraints.
3898  for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
3899  I != E; ++I) {
3900  const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
3901  if (!RC)
3902  continue;
3903 
3904  const MachineOperand &Op = MI.getOperand(I);
3905  if (!Op.isReg())
3906  continue;
3907 
3908  Register Reg = Op.getReg();
3909  if (!Reg.isVirtual() && !RC->contains(Reg)) {
3910  ErrInfo = "inlineasm operand has incorrect register class.";
3911  return false;
3912  }
3913  }
3914 
3915  return true;
3916  }
3917 
3918  if (isMIMG(MI) && MI.memoperands_empty() && MI.mayLoadOrStore()) {
3919  ErrInfo = "missing memory operand from MIMG instruction.";
3920  return false;
3921  }
3922 
3923  // Make sure the register classes are correct.
3924  for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
3925  const MachineOperand &MO = MI.getOperand(i);
3926  if (MO.isFPImm()) {
3927  ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
3928  "all fp values to integers.";
3929  return false;
3930  }
3931 
3932  int RegClass = Desc.OpInfo[i].RegClass;
3933 
3934  switch (Desc.OpInfo[i].OperandType) {
3936  if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
3937  ErrInfo = "Illegal immediate value for operand.";
3938  return false;
3939  }
3940  break;
3944  break;
3956  if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
3957  ErrInfo = "Illegal immediate value for operand.";
3958  return false;
3959  }
3960  break;
3961  }
3964  // Check if this operand is an immediate.
3965  // FrameIndex operands will be replaced by immediates, so they are
3966  // allowed.
3967  if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
3968  ErrInfo = "Expected immediate, but got non-immediate";
3969  return false;
3970  }
3972  default:
3973  continue;
3974  }
3975 
3976  if (!MO.isReg())
3977  continue;
3978  Register Reg = MO.getReg();
3979  if (!Reg)
3980  continue;
3981 
3982  // FIXME: Ideally we would have separate instruction definitions with the
3983  // aligned register constraint.
3984  // FIXME: We do not verify inline asm operands, but custom inline asm
3985  // verification is broken anyway
3986  if (ST.needsAlignedVGPRs()) {
3987  const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg);
3988  if (RI.hasVectorRegisters(RC) && MO.getSubReg()) {
3989  const TargetRegisterClass *SubRC =
3990  RI.getSubRegClass(RC, MO.getSubReg());
3991  RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg());
3992  if (RC)
3993  RC = SubRC;
3994  }
3995 
3996  // Check that this is the aligned version of the class.
3997  if (!RC || !RI.isProperlyAlignedRC(*RC)) {
3998  ErrInfo = "Subtarget requires even aligned vector registers";
3999  return false;
4000  }
4001  }
4002 
4003  if (RegClass != -1) {
4004  if (Reg.isVirtual())
4005  continue;
4006 
4007  const TargetRegisterClass *RC = RI.getRegClass(RegClass);
4008  if (!RC->contains(Reg)) {
4009  ErrInfo = "Operand has incorrect register class.";
4010  return false;
4011  }
4012  }
4013  }
4014 
4015  // Verify SDWA
4016  if (isSDWA(MI)) {
4017  if (!ST.hasSDWA()) {
4018  ErrInfo = "SDWA is not supported on this target";
4019  return false;
4020  }
4021 
4022  int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
4023 
4024  const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
4025 
4026  for (int OpIdx: OpIndicies) {
4027  if (OpIdx == -1)
4028  continue;
4029  const MachineOperand &MO = MI.getOperand(OpIdx);
4030 
4031  if (!ST.hasSDWAScalar()) {
4032  // Only VGPRS on VI
4033  if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
4034  ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
4035  return false;
4036  }
4037  } else {
4038  // No immediates on GFX9
4039  if (!MO.isReg()) {
4040  ErrInfo =
4041  "Only reg allowed as operands in SDWA instructions on GFX9+";
4042  return false;
4043  }
4044  }
4045  }
4046 
4047  if (!ST.hasSDWAOmod()) {
4048  // No omod allowed on VI
4049  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
4050  if (OMod != nullptr &&
4051  (!OMod->isImm() || OMod->getImm() != 0)) {
4052  ErrInfo = "OMod not allowed in SDWA instructions on VI";
4053  return false;
4054  }
4055  }
4056 
4057  uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
4058  if (isVOPC(BasicOpcode)) {
4059  if (!ST.hasSDWASdst() && DstIdx != -1) {
4060  // Only vcc allowed as dst on VI for VOPC
4061  const MachineOperand &Dst = MI.getOperand(DstIdx);
4062  if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
4063  ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
4064  return false;
4065  }
4066  } else if (!ST.hasSDWAOutModsVOPC()) {
4067  // No clamp allowed on GFX9 for VOPC
4068  const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
4069  if (Clamp && (!Clamp->isImm() || Clamp->getImm() != 0)) {
4070  ErrInfo = "Clamp not allowed in VOPC SDWA instructions on VI";
4071  return false;
4072  }
4073 
4074  // No omod allowed on GFX9 for VOPC
4075  const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
4076  if (OMod && (!OMod->isImm() || OMod->getImm() != 0)) {
4077  ErrInfo = "OMod not allowed in VOPC SDWA instructions on VI";
4078  return false;
4079  }
4080  }
4081  }
4082 
4083  const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
4084  if (DstUnused && DstUnused->isImm() &&
4086  const MachineOperand &Dst = MI.getOperand(DstIdx);
4087  if (!Dst.isReg() || !Dst.isTied()) {
4088  ErrInfo = "Dst register should have tied register";
4089  return false;
4090  }
4091 
4092  const MachineOperand &TiedMO =
4093  MI.getOperand(MI.findTiedOperandIdx(DstIdx));
4094  if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
4095  ErrInfo =
4096  "Dst register should be tied to implicit use of preserved register";
4097  return false;
4098  } else if (TiedMO.getReg().isPhysical() &&
4099  Dst.getReg() != TiedMO.getReg()) {
4100  ErrInfo = "Dst register should use same physical register as preserved";
4101  return false;
4102  }
4103  }
4104  }
4105 
4106  // Verify MIMG
4107  if (isMIMG(MI.getOpcode()) && !MI.mayStore()) {
4108  // Ensure that the return type used is large enough for all the options
4109  // being used TFE/LWE require an extra result register.
4110  const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
4111  if (DMask) {
4112  uint64_t DMaskImm = DMask->getImm();
4113  uint32_t RegCount =
4114  isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm);
4115  const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
4116  const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
4117  const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
4118 
4119  // Adjust for packed 16 bit values
4120  if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
4121  RegCount >>= 1;
4122 
4123  // Adjust if using LWE or TFE
4124  if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
4125  RegCount += 1;
4126 
4127  const uint32_t DstIdx =
4128  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
4129  const MachineOperand &Dst = MI.getOperand(DstIdx);
4130  if (Dst.isReg()) {
4131  const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
4132  uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
4133  if (RegCount > DstSize) {
4134  ErrInfo = "MIMG instruction returns too many registers for dst "
4135  "register class";
4136  return false;
4137  }
4138  }
4139  }
4140  }
4141 
4142  // Verify VOP*. Ignore multiple sgpr operands on writelane.
4143  if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
4144  && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
4145  // Only look at the true operands. Only a real operand can use the constant
4146  // bus, and we don't want to check pseudo-operands like the source modifier
4147  // flags.
4148  const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
4149 
4150  unsigned ConstantBusCount = 0;
4151  bool UsesLiteral = false;
4152  const MachineOperand *LiteralVal = nullptr;
4153 
4154  if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
4155  ++ConstantBusCount;
4156 
4157  SmallVector<Register, 2> SGPRsUsed;
4158  Register SGPRUsed;
4159 
4160  for (int OpIdx : OpIndices) {
4161  if (OpIdx == -1)
4162  break;
4163  const MachineOperand &MO = MI.getOperand(OpIdx);
4164  if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
4165  if (MO.isReg()) {
4166  SGPRUsed = MO.getReg();
4167  if (llvm::all_of(SGPRsUsed, [SGPRUsed](unsigned SGPR) {
4168  return SGPRUsed != SGPR;
4169  })) {
4170  ++ConstantBusCount;
4171  SGPRsUsed.push_back(SGPRUsed);
4172  }
4173  } else {
4174  if (!UsesLiteral) {
4175  ++ConstantBusCount;
4176  UsesLiteral = true;
4177  LiteralVal = &MO;
4178  } else if (!MO.isIdenticalTo(*LiteralVal)) {
4179  assert(isVOP3(MI));
4180  ErrInfo = "VOP3 instruction uses more than one literal";
4181  return false;
4182  }
4183  }
4184  }
4185  }
4186 
4187  SGPRUsed = findImplicitSGPRRead(MI);
4188  if (SGPRUsed != AMDGPU::NoRegister) {
4189  // Implicit uses may safely overlap true overands
4190  if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
4191  return !RI.regsOverlap(SGPRUsed, SGPR);
4192  })) {
4193  ++ConstantBusCount;
4194  SGPRsUsed.push_back(SGPRUsed);
4195  }
4196  }
4197 
4198  // v_writelane_b32 is an exception from constant bus restriction:
4199  // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
4200  if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
4201  Opcode != AMDGPU::V_WRITELANE_B32) {
4202  ErrInfo = "VOP* instruction violates constant bus restriction";
4203  return false;
4204  }
4205 
4206  if (isVOP3(MI) && UsesLiteral && !ST.hasVOP3Literal()) {
4207  ErrInfo = "VOP3 instruction uses literal";
4208  return false;
4209  }
4210  }
4211 
4212  // Special case for writelane - this can break the multiple constant bus rule,
4213  // but still can't use more than one SGPR register
4214  if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
4215  unsigned SGPRCount = 0;
4216  Register SGPRUsed = AMDGPU::NoRegister;
4217 
4218  for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
4219  if (OpIdx == -1)
4220  break;
4221 
4222  const MachineOperand &MO = MI.getOperand(OpIdx);
4223 
4224  if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
4225  if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
4226  if (MO.getReg() != SGPRUsed)
4227  ++SGPRCount;
4228  SGPRUsed = MO.getReg();
4229  }
4230  }
4231  if (SGPRCount > ST.getConstantBusLimit(Opcode)) {
4232  ErrInfo = "WRITELANE instruction violates constant bus restriction";
4233  return false;
4234  }
4235  }
4236  }
4237 
4238  // Verify misc. restrictions on specific instructions.
4239  if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32_e64 ||
4240  Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64_e64) {
4241  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4242  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
4243  const MachineOperand &Src2 = MI.getOperand(Src2Idx);
4244  if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
4245  if (!compareMachineOp(Src0, Src1) &&
4246  !compareMachineOp(Src0, Src2)) {
4247  ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
4248  return false;
4249  }
4250  }
4251  if ((getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm() &
4252  SISrcMods::ABS) ||
4253  (getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm() &
4254  SISrcMods::ABS) ||
4255  (getNamedOperand(MI, AMDGPU::OpName::src2_modifiers)->getImm() &
4256  SISrcMods::ABS)) {
4257  ErrInfo = "ABS not allowed in VOP3B instructions";
4258  return false;
4259  }
4260  }
4261 
4262  if (isSOP2(MI) || isSOPC(MI)) {
4263  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4264  const MachineOperand &Src1 = MI.getOperand(Src1Idx);
4265  unsigned Immediates = 0;
4266 
4267  if (!Src0.isReg() &&
4268  !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
4269  Immediates++;
4270  if (!Src1.isReg() &&
4271  !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
4272  Immediates++;
4273 
4274  if (Immediates > 1) {
4275  ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
4276  return false;
4277  }
4278  }
4279 
4280  if (isSOPK(MI)) {
4281  auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
4282  if (Desc.isBranch()) {
4283  if (!Op->isMBB()) {
4284  ErrInfo = "invalid branch target for SOPK instruction";
4285  return false;
4286  }
4287  } else {
4288  uint64_t Imm = Op->getImm();
4289  if (sopkIsZext(MI)) {
4290  if (!isUInt<16>(Imm)) {
4291  ErrInfo = "invalid immediate for SOPK instruction";
4292  return false;
4293  }
4294  } else {
4295  if (!isInt<16>(Imm)) {
4296  ErrInfo = "invalid immediate for SOPK instruction";
4297  return false;
4298  }
4299  }
4300  }
4301  }
4302 
4303  if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
4304  Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
4305  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
4306  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
4307  const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
4308  Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;
4309 
4310  const unsigned StaticNumOps = Desc.getNumOperands() +
4311  Desc.getNumImplicitUses();
4312  const unsigned NumImplicitOps = IsDst ? 2 : 1;
4313 
4314  // Allow additional implicit operands. This allows a fixup done by the post
4315  // RA scheduler where the main implicit operand is killed and implicit-defs
4316  // are added for sub-registers that remain live after this instruction.
4317  if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
4318  ErrInfo = "missing implicit register operands";
4319  return false;
4320  }
4321 
4322  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
4323  if (IsDst) {
4324  if (!Dst->isUse()) {
4325  ErrInfo = "v_movreld_b32 vdst should be a use operand";
4326  return false;
4327  }
4328 
4329  unsigned UseOpIdx;
4330  if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) ||
4331  UseOpIdx != StaticNumOps + 1) {
4332  ErrInfo = "movrel implicit operands should be tied";
4333  return false;
4334  }
4335  }
4336 
4337  const MachineOperand &Src0 = MI.getOperand(Src0Idx);
4338  const MachineOperand &ImpUse
4339  = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
4340  if (!ImpUse.isReg() || !ImpUse.isUse() ||
4341  !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
4342  ErrInfo = "src0 should be subreg of implicit vector use";
4343  return false;
4344  }
4345  }
4346 
4347  // Make sure we aren't losing exec uses in the td files. This mostly requires
4348  // being careful when using let Uses to try to add other use registers.
4349  if (shouldReadExec(MI)) {
4350  if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
4351  ErrInfo = "VALU instruction does not implicitly read exec mask";
4352  return false;
4353  }
4354  }
4355 
4356  if (isSMRD(MI)) {
4357  if (MI.mayStore()) {
4358  // The register offset form of scalar stores may only use m0 as the
4359  // soffset register.
4360  const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
4361  if (Soff && Soff->getReg() != AMDGPU::M0) {
4362  ErrInfo = "scalar stores must use m0 as offset register";
4363  return false;
4364  }
4365  }
4366  }
4367 
4368  if (isFLAT(MI) && !ST.hasFlatInstOffsets()) {
4369  const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4370  if (Offset->getImm() != 0) {
4371  ErrInfo = "subtarget does not support offsets in flat instructions";
4372  return false;
4373  }
4374  }
4375 
4376  if (isMIMG(MI)) {
4377  const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
4378  if (DimOp) {
4379  int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode,
4380  AMDGPU::OpName::vaddr0);
4381  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
4382  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opcode);
4383  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
4384  AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
4385  const AMDGPU::MIMGDimInfo *Dim =
4387 
4388  if (!Dim) {
4389  ErrInfo = "dim is out of range";
4390  return false;
4391  }
4392 
4393  bool IsA16 = false;
4394  if (ST.hasR128A16()) {
4395  const MachineOperand *R128A16 = getNamedOperand(MI, AMDGPU::OpName::r128);
4396  IsA16 = R128A16->getImm() != 0;
4397  } else if (ST.hasGFX10A16()) {
4398  const MachineOperand *A16 = getNamedOperand(MI, AMDGPU::OpName::a16);
4399  IsA16 = A16->getImm() != 0;
4400  }
4401 
4402  bool IsNSA = SRsrcIdx - VAddr0Idx > 1;
4403 
4404  unsigned AddrWords =
4405  AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, ST.hasG16());
4406 
4407  unsigned VAddrWords;
4408  if (IsNSA) {
4409  VAddrWords = SRsrcIdx - VAddr0Idx;
4410  } else {
4411  const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
4412  VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
4413  if (AddrWords > 8)
4414  AddrWords = 16;
4415  }
4416 
4417  if (VAddrWords != AddrWords) {
4418  LLVM_DEBUG(dbgs() << "bad vaddr size, expected " << AddrWords
4419  << " but got " << VAddrWords << "\n");
4420  ErrInfo = "bad vaddr size";
4421  return false;
4422  }
4423  }
4424  }
4425 
4426  const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
4427  if (DppCt) {
4428  using namespace AMDGPU::DPP;
4429 
4430  unsigned DC = DppCt->getImm();
4438  ErrInfo = "Invalid dpp_ctrl value";
4439  return false;
4440  }
4441  if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 &&
4442  ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4443  ErrInfo = "Invalid dpp_ctrl value: "
4444  "wavefront shifts are not supported on GFX10+";
4445  return false;
4446  }
4447  if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 &&
4448  ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4449  ErrInfo = "Invalid dpp_ctrl value: "
4450  "broadcasts are not supported on GFX10+";
4451  return false;
4452  }
4454  ST.getGeneration() < AMDGPUSubtarget::GFX10) {
4457  !ST.hasGFX90AInsts()) {
4458  ErrInfo = "Invalid dpp_ctrl value: "
4459  "row_newbroadcast/row_share is not supported before "
4460  "GFX90A/GFX10";
4461  return false;
4462  } else if (DC > DppCtrl::ROW_NEWBCAST_LAST || !ST.hasGFX90AInsts()) {
4463  ErrInfo = "Invalid dpp_ctrl value: "
4464  "row_share and row_xmask are not supported before GFX10";
4465  return false;
4466  }
4467  }
4468 
4469  int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
4470  int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
4471 
4472  if (Opcode != AMDGPU::V_MOV_B64_DPP_PSEUDO &&
4473  ((DstIdx >= 0 &&
4474  (Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64RegClassID ||
4475  Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64_Align2RegClassID)) ||
4476  ((Src0Idx >= 0 &&
4477  (Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID ||
4478  Desc.OpInfo[Src0Idx].RegClass ==
4479  AMDGPU::VReg_64_Align2RegClassID)))) &&
4481  ErrInfo = "Invalid dpp_ctrl value: "
4482  "64 bit dpp only support row_newbcast";
4483  return false;
4484  }
4485  }
4486 
4487  if ((MI.mayStore() || MI.mayLoad()) && !isVGPRSpill(MI)) {
4488  const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
4489  uint16_t DataNameIdx = isDS(Opcode) ? AMDGPU::OpName::data0
4490  : AMDGPU::OpName::vdata;
4491  const MachineOperand *Data = getNamedOperand(MI, DataNameIdx);
4492  const MachineOperand *Data2 = getNamedOperand(MI, AMDGPU::OpName::data1);
4493  if (Data && !Data->isReg())
4494  Data = nullptr;
4495 
4496  if (ST.hasGFX90AInsts()) {
4497  if (Dst && Data &&
4498  (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) {
4499  ErrInfo = "Invalid register class: "
4500  "vdata and vdst should be both VGPR or AGPR";
4501  return false;
4502  }
4503  if (Data && Data2 &&
4504  (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) {
4505  ErrInfo = "Invalid register class: "
4506  "both data operands should be VGPR or AGPR";
4507  return false;
4508  }
4509  } else {
4510  if ((Dst && RI.isAGPR(MRI, Dst->getReg())) ||
4511  (Data && RI.isAGPR(MRI, Data->getReg())) ||
4512  (Data2 && RI.isAGPR(MRI, Data2->getReg()))) {
4513  ErrInfo = "Invalid register class: "
4514  "agpr loads and stores not supported on this GPU";
4515  return false;
4516  }
4517  }
4518  }
4519 
4520  if (ST.needsAlignedVGPRs() &&
4521  (MI.getOpcode() == AMDGPU::DS_GWS_INIT ||
4522  MI.getOpcode() == AMDGPU::DS_GWS_SEMA_BR ||
4523  MI.getOpcode() == AMDGPU::DS_GWS_BARRIER)) {
4524  const MachineOperand *Op = getNamedOperand(MI, AMDGPU::OpName::data0);
4525  Register Reg = Op->getReg();
4526  bool Aligned = true;
4527  if (Reg.isPhysical()) {
4528  Aligned = !(RI.getHWRegIndex(Reg) & 1);
4529  } else {
4530  const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
4531  Aligned = RI.getRegSizeInBits(RC) > 32 && RI.isProperlyAlignedRC(RC) &&
4532  !(RI.getChannelFromSubReg(Op->getSubReg()) & 1);
4533  }
4534 
4535  if (!Aligned) {
4536  ErrInfo = "Subtarget requires even aligned vector registers "
4537  "for DS_GWS instructions";
4538  return false;
4539  }
4540  }
4541 
4542  if (Desc.getOpcode() == AMDGPU::G_AMDGPU_WAVE_ADDRESS) {
4543  const MachineOperand &SrcOp = MI.getOperand(1);
4544  if (!SrcOp.isReg() || SrcOp.getReg().isVirtual()) {
4545  ErrInfo = "pseudo expects only physical SGPRs";
4546  return false;
4547  }
4548  }
4549 
4550  return true;
4551 }
4552 
4553 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
4554  switch (MI.getOpcode()) {
4555  default: return AMDGPU::INSTRUCTION_LIST_END;
4556  case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
4557  case AMDGPU::COPY: return AMDGPU::COPY;
4558  case AMDGPU::PHI: return AMDGPU::PHI;
4559  case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
4560  case AMDGPU::WQM: return AMDGPU::WQM;
4561  case AMDGPU::SOFT_WQM: return AMDGPU::SOFT_WQM;
4562  case AMDGPU::STRICT_WWM: return AMDGPU::STRICT_WWM;
4563  case AMDGPU::STRICT_WQM: return AMDGPU::STRICT_WQM;
4564  case AMDGPU::S_MOV_B32: {
4565  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4566  return MI.getOperand(1).isReg() ||
4567  RI.isAGPR(MRI, MI.getOperand(0).getReg()) ?
4568  AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
4569  }
4570  case AMDGPU::S_ADD_I32:
4571  return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_CO_U32_e32;
4572  case AMDGPU::S_ADDC_U32:
4573  return AMDGPU::V_ADDC_U32_e32;
4574  case AMDGPU::S_SUB_I32:
4575  return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_CO_U32_e32;
4576  // FIXME: These are not consistently handled, and selected when the carry is
4577  // used.
4578  case AMDGPU::S_ADD_U32:
4579  return AMDGPU::V_ADD_CO_U32_e32;
4580  case AMDGPU::S_SUB_U32:
4581  return AMDGPU::V_SUB_CO_U32_e32;
4582  case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
4583  case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_U32_e64;
4584  case AMDGPU::S_MUL_HI_U32: return AMDGPU::V_MUL_HI_U32_e64;
4585  case AMDGPU::S_MUL_HI_I32: return AMDGPU::V_MUL_HI_I32_e64;
4586  case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
4587  case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
4588  case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e64;
4589  case AMDGPU::S_XNOR_B32:
4590  return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
4591  case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e64;
4592  case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e64;
4593  case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e64;
4594  case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e64;
4595  case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
4596  case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64_e64;
4597  case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
4598  case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64_e64;
4599  case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
4600  case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64_e64;
4601  case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32_e64;
4602  case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32_e64;
4603  case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32_e64;
4604  case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32_e64;
4605  case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
4606  case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
4607  case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
4608  case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
4609  case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e64;
4610  case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e64;
4611  case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e64;
4612  case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e64;
4613  case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e64;
4614  case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e64;
4615  case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e64;
4616  case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e64;
4617  case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e64;
4618  case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e64;
4619  case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e64;
4620  case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e64;
4621  case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e64;
4622  case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e64;
4623  case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
4624  case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
4625  case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
4626  case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
4627  case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
4628  case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
4629  }
4631  "Unexpected scalar opcode without corresponding vector one!");
4632 }
4633 
4634 static unsigned adjustAllocatableRegClass(const GCNSubtarget &ST,
4635  const MachineRegisterInfo &MRI,
4636  const MCInstrDesc &TID,
4637  unsigned RCID,
4638  bool IsAllocatable) {
4639  if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
4640  (((TID.mayLoad() || TID.mayStore()) &&
4641  !(TID.TSFlags & SIInstrFlags::VGPRSpill)) ||
4643  switch (RCID) {
4644  case AMDGPU::AV_32RegClassID: return AMDGPU::VGPR_32RegClassID;
4645  case AMDGPU::AV_64RegClassID: return AMDGPU::VReg_64RegClassID;
4646  case AMDGPU::AV_96RegClassID: return AMDGPU::VReg_96RegClassID;
4647  case AMDGPU::AV_128RegClassID: return AMDGPU::VReg_128RegClassID;
4648  case AMDGPU::AV_160RegClassID: return AMDGPU::VReg_160RegClassID;
4649  default:
4650  break;
4651  }
4652  }
4653  return RCID;
4654 }
4655 
4657  unsigned OpNum, const TargetRegisterInfo *TRI,
4658  const MachineFunction &MF)
4659  const {
4660  if (OpNum >= TID.getNumOperands())
4661  return nullptr;
4662  auto RegClass = TID.OpInfo[OpNum].RegClass;
4663  bool IsAllocatable = false;
4665  // vdst and vdata should be both VGPR or AGPR, same for the DS instructions
4666  // with two data operands. Request register class constainted to VGPR only
4667  // of both operands present as Machine Copy Propagation can not check this
4668  // constraint and possibly other passes too.
4669  //
4670  // The check is limited to FLAT and DS because atomics in non-flat encoding
4671  // have their vdst and vdata tied to be the same register.
4672  const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
4673  AMDGPU::OpName::vdst);
4674  const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
4675  (TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
4676  : AMDGPU::OpName::vdata);
4677  if (DataIdx != -1) {
4678  IsAllocatable = VDstIdx != -1 ||
4680  AMDGPU::OpName::data1) != -1;
4681  }
4682  }
4683  RegClass = adjustAllocatableRegClass(ST, MF.getRegInfo(), TID, RegClass,
4684  IsAllocatable);
4685  return RI.getRegClass(RegClass);
4686 }
4687 
4689  unsigned OpNo) const {
4690  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4691  const MCInstrDesc &Desc = get(MI.getOpcode());
4692  if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
4693  Desc.OpInfo[OpNo].RegClass == -1) {
4694  Register Reg = MI.getOperand(OpNo).getReg();
4695 
4696  if (Reg.isVirtual())
4697  return MRI.getRegClass(Reg);
4698  return RI.getPhysRegClass(Reg);
4699  }
4700 
4701  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
4702  RCID = adjustAllocatableRegClass(ST, MRI, Desc, RCID, true);
4703  return RI.getRegClass(RCID);
4704 }
4705 
4706 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
4708  MachineBasicBlock *MBB = MI.getParent();
4709  MachineOperand &MO = MI.getOperand(OpIdx);
4711  unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
4712  const TargetRegisterClass *RC = RI.getRegClass(RCID);
4713  unsigned Size = RI.getRegSizeInBits(*RC);
4714  unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
4715  if (MO.isReg())
4716  Opcode = AMDGPU::COPY;
4717  else if (RI.isSGPRClass(RC))
4718  Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
4719 
4720  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
4721  const TargetRegisterClass *VRC64 = RI.getVGPR64Class();
4722  if (RI.getCommonSubClass(VRC64, VRC))
4723  VRC = VRC64;
4724  else
4725  VRC = &AMDGPU::VGPR_32RegClass;
4726 
4729  BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
4730  MO.ChangeToRegister(Reg, false);
4731 }
4732 
4735  MachineOperand &SuperReg,
4736  const TargetRegisterClass *SuperRC,
4737  unsigned SubIdx,
4738  const TargetRegisterClass *SubRC)
4739  const {
4740  MachineBasicBlock *MBB = MI->getParent();
4741  DebugLoc DL = MI->getDebugLoc();
4743 
4744  if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
4745  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4746  .addReg(SuperReg.getReg(), 0, SubIdx);
4747  return SubReg;
4748  }
4749 
4750  // Just in case the super register is itself a sub-register, copy it to a new
4751  // value so we don't need to worry about merging its subreg index with the
4752  // SubIdx passed to this function. The register coalescer should be able to
4753  // eliminate this extra copy.
4754  Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
4755 
4756  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
4757  .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
4758 
4759  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4760  .addReg(NewSuperReg, 0, SubIdx);
4761 
4762  return SubReg;
4763 }
4764 
4768  MachineOperand &Op,
4769  const TargetRegisterClass *SuperRC,
4770  unsigned SubIdx,
4771  const TargetRegisterClass *SubRC) const {
4772  if (Op.isImm()) {
4773  if (SubIdx == AMDGPU::sub0)
4774  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
4775  if (SubIdx == AMDGPU::sub1)
4776  return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
4777 
4778  llvm_unreachable("Unhandled register index for immediate");
4779  }
4780 
4781  unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
4782  SubIdx, SubRC);
4783  return MachineOperand::CreateReg(SubReg, false);
4784 }
4785 
4786 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
4787 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
4788  assert(Inst.getNumExplicitOperands() == 3);
4789  MachineOperand Op1 = Inst.getOperand(1);
4790  Inst.RemoveOperand(1);
4791  Inst.addOperand(Op1);
4792 }
4793 
4795  const MCOperandInfo &OpInfo,
4796  const MachineOperand &MO) const {
4797  if (!MO.isReg())
4798  return false;
4799 
4800  Register Reg = MO.getReg();
4801 
4802  const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
4803  if (Reg.isPhysical())
4804  return DRC->contains(Reg);
4805 
4806  const TargetRegisterClass *RC =