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ARMBaseRegisterInfo.h
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1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the base ARM implementation of TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include <cstdint>
23 
24 #define GET_REGINFO_HEADER
25 #include "ARMGenRegisterInfo.inc"
26 
27 namespace llvm {
28 
29 class LiveIntervals;
30 
31 /// Register allocation hints.
32 namespace ARMRI {
33 
34  enum {
35  // Used for LDRD register pairs
38  // Used to hint for lr in t2DoLoopStart
39  RegLR = 3
40  };
41 
42 } // end namespace ARMRI
43 
44 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
45 /// or a stack/pc register that we should push/pop.
46 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
47  using namespace ARM;
48 
49  switch (Reg) {
50  case R0: case R1: case R2: case R3:
51  case R4: case R5: case R6: case R7:
52  case LR: case SP: case PC:
53  return true;
54  case R8: case R9: case R10: case R11: case R12:
55  // For iOS we want r7 and lr to be next to each other.
56  return !isIOS;
57  default:
58  return false;
59  }
60 }
61 
62 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
63  using namespace ARM;
64 
65  switch (Reg) {
66  case R8: case R9: case R10: case R11: case R12:
67  // iOS has this second area.
68  return isIOS;
69  default:
70  return false;
71  }
72 }
73 
74 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
75  using namespace ARM;
76 
77  switch (Reg) {
78  case D15: case D14: case D13: case D12:
79  case D11: case D10: case D9: case D8:
80  case D7: case D6: case D5: case D4:
81  case D3: case D2: case D1: case D0:
82  case D31: case D30: case D29: case D28:
83  case D27: case D26: case D25: case D24:
84  case D23: case D22: case D21: case D20:
85  case D19: case D18: case D17: case D16:
86  return true;
87  default:
88  return false;
89  }
90 }
91 
92 static inline bool isCalleeSavedRegister(unsigned Reg,
93  const MCPhysReg *CSRegs) {
94  for (unsigned i = 0; CSRegs[i]; ++i)
95  if (Reg == CSRegs[i])
96  return true;
97  return false;
98 }
99 
101 protected:
102  /// BasePtr - ARM physical register used as a base ptr in complex stack
103  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
104  /// variable size stack objects.
105  unsigned BasePtr = ARM::R6;
106 
107  // Can be only subclassed.
108  explicit ARMBaseRegisterInfo();
109 
110  // Return the opcode that implements 'Op', or 0 if no opcode
111  unsigned getOpcode(int Op) const;
112 
113 public:
114  /// Code Generation virtual methods...
115  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
116  const MCPhysReg *
119  CallingConv::ID) const override;
120  const uint32_t *getNoPreservedMask() const override;
121  const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
122  const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
123 
124  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
125  /// case that 'returned' is on an i32 first argument if the calling convention
126  /// is one that can (partially) model this attribute with a preserved mask
127  /// (i.e. it is a calling convention that uses the same register for the first
128  /// i32 argument and an i32 return value)
129  ///
130  /// Should return NULL in the case that the calling convention does not have
131  /// this property
133  CallingConv::ID) const;
134 
136  getIntraCallClobberedRegs(const MachineFunction *MF) const override;
137 
138  BitVector getReservedRegs(const MachineFunction &MF) const override;
139  bool isAsmClobberable(const MachineFunction &MF,
140  MCRegister PhysReg) const override;
142  unsigned PhysReg) const override;
143 
144  const TargetRegisterClass *
146  unsigned Kind = 0) const override;
147  const TargetRegisterClass *
148  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
149 
150  const TargetRegisterClass *
152  const MachineFunction &MF) const override;
153 
154  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
155  MachineFunction &MF) const override;
156 
159  const MachineFunction &MF, const VirtRegMap *VRM,
160  const LiveRegMatrix *Matrix) const override;
161 
163  MachineFunction &MF) const override;
164 
165  bool hasBasePointer(const MachineFunction &MF) const;
166 
167  bool canRealignStack(const MachineFunction &MF) const override;
169  int Idx) const override;
170  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
172  int64_t Offset) const override;
173  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
174  int64_t Offset) const override;
175  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
176  int64_t Offset) const override;
177 
178  bool cannotEliminateFrame(const MachineFunction &MF) const;
179 
180  // Debug information queries.
181  Register getFrameRegister(const MachineFunction &MF) const override;
182  Register getBaseRegister() const { return BasePtr; }
183 
184  /// emitLoadConstPool - Emits a load from constpool to materialize the
185  /// specified immediate.
186  virtual void
188  const DebugLoc &dl, Register DestReg, unsigned SubIdx,
189  int Val, ARMCC::CondCodes Pred = ARMCC::AL,
190  Register PredReg = Register(),
191  unsigned MIFlags = MachineInstr::NoFlags) const;
192 
193  /// Code Generation virtual methods...
194  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
195 
196  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
197 
198  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
199 
201  int SPAdj, unsigned FIOperandNum,
202  RegScavenger *RS = nullptr) const override;
203 
204  /// SrcRC and DstRC will be morphed into NewRC if this returns true
206  const TargetRegisterClass *SrcRC,
207  unsigned SubReg,
208  const TargetRegisterClass *DstRC,
209  unsigned DstSubReg,
210  const TargetRegisterClass *NewRC,
211  LiveIntervals &LIS) const override;
212 
213  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
214  unsigned DefSubReg,
215  const TargetRegisterClass *SrcRC,
216  unsigned SrcSubReg) const override;
217 };
218 
219 } // end namespace llvm
220 
221 #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
i
i
Definition: README.txt:29
llvm::ARMBaseRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: ARMBaseRegisterInfo.cpp:63
llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
Definition: ARMBaseRegisterInfo.cpp:657
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: ARMBaseRegisterInfo.cpp:115
llvm::ARMBaseRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: ARMBaseRegisterInfo.cpp:926
llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
Definition: ARMBaseRegisterInfo.cpp:169
llvm::ARMBaseRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Definition: ARMBaseRegisterInfo.cpp:286
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::ARMBaseRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: ARMBaseRegisterInfo.cpp:280
MachineBasicBlock.h
llvm::isARMArea1Register
static bool isARMArea1Register(unsigned Reg, bool isIOS)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
Definition: ARMBaseRegisterInfo.h:46
R4
#define R4(n)
llvm::ARMBaseRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: ARMBaseRegisterInfo.cpp:713
llvm::isARMArea3Register
static bool isARMArea3Register(unsigned Reg, bool isIOS)
Definition: ARMBaseRegisterInfo.h:74
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::isARMArea2Register
static bool isARMArea2Register(unsigned Reg, bool isIOS)
Definition: ARMBaseRegisterInfo.h:62
llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: ARMBaseRegisterInfo.cpp:525
llvm::ARMBaseRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: ARMBaseRegisterInfo.h:182
llvm::ARMBaseRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
Definition: ARMBaseRegisterInfo.cpp:510
llvm::ARMBaseRegisterInfo::getOpcode
unsigned getOpcode(int Op) const
R2
#define R2(n)
ARMBaseInfo.h
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:479
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
ARMGenRegisterInfo
llvm::ARMBaseRegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: ARMBaseRegisterInfo.cpp:330
llvm::ARMBaseRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: ARMBaseRegisterInfo.cpp:125
llvm::ARMBaseRegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:470
llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:160
llvm::BitVector
Definition: BitVector.h:74
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::ARMBaseRegisterInfo::isInlineAsmReadOnlyReg
bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMBaseRegisterInfo.cpp:234
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::ARMRI::RegPairOdd
@ RegPairOdd
Definition: ARMBaseRegisterInfo.h:36
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegScavenger
Definition: RegisterScavenging.h:34
MCRegisterInfo.h
llvm::isCalleeSavedRegister
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
Definition: ARMBaseRegisterInfo.h:92
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::ARMBaseRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: ARMBaseRegisterInfo.cpp:148
llvm::ARMBaseRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: ARMBaseRegisterInfo.cpp:685
R6
#define R6(n)
llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:153
llvm::ARMBaseRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition: ARMBaseRegisterInfo.cpp:867
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMBaseRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: ARMBaseRegisterInfo.cpp:230
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::ARMBaseRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Definition: ARMBaseRegisterInfo.cpp:576
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
uint32_t
llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:250
llvm::ARMBaseRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:194
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:100
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMBaseRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:515
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ARMBaseRegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:447
llvm::ARMBaseRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:293
llvm::ARMBaseRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:520
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::ARMBaseRegisterInfo::BasePtr
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
Definition: ARMBaseRegisterInfo.h:105
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ARMBaseRegisterInfo::getIntraCallClobberedRegs
ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const override
Definition: ARMBaseRegisterInfo.cpp:187
llvm::ARMRI::RegPairEven
@ RegPairEven
Definition: ARMBaseRegisterInfo.h:37
llvm::SmallVectorImpl< MCPhysReg >
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:410
llvm::ARMRI::RegLR
@ RegLR
Definition: ARMBaseRegisterInfo.h:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::ARMBaseRegisterInfo::updateRegAllocHint
void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:385
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ARMBaseRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: ARMBaseRegisterInfo.cpp:780
TargetRegisterInfo.h
llvm::ARMBaseRegisterInfo::emitLoadConstPool
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
Definition: ARMBaseRegisterInfo.cpp:490
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::ARMBaseRegisterInfo::ARMBaseRegisterInfo
ARMBaseRegisterInfo()
Definition: ARMBaseRegisterInfo.cpp:57
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40