LLVM 18.0.0git
ARMInstPrinter.cpp
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1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an ARM MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMInstPrinter.h"
14#include "Utils/ARMBaseInfo.h"
17#include "llvm/MC/MCAsmInfo.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
29#include <algorithm>
30#include <cassert>
31#include <cstdint>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "asm-printer"
36
37#define PRINT_ALIAS_INSTR
38#include "ARMGenAsmWriter.inc"
39
40/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
41///
42/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
43static unsigned translateShiftImm(unsigned imm) {
44 // lsr #32 and asr #32 exist, but should be encoded as a 0.
45 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
46
47 if (imm == 0)
48 return 32;
49 return imm;
50}
51
53 unsigned ShImm, const ARMInstPrinter &printer) {
54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
55 return;
56 O << ", ";
57
58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
59 O << getShiftOpcStr(ShOpc);
60
61 if (ShOpc != ARM_AM::rrx) {
62 O << " ";
64 << "#" << translateShiftImm(ShImm);
65 }
66}
67
69 const MCRegisterInfo &MRI)
70 : MCInstPrinter(MAI, MII, MRI) {}
71
73 if (Opt == "reg-names-std") {
74 DefaultAltIdx = ARM::NoRegAltName;
75 return true;
76 }
77 if (Opt == "reg-names-raw") {
78 DefaultAltIdx = ARM::RegNamesRaw;
79 return true;
80 }
81 return false;
82}
83
85 markup(OS, Markup::Register) << getRegisterName(Reg, DefaultAltIdx);
86}
87
89 StringRef Annot, const MCSubtargetInfo &STI,
90 raw_ostream &O) {
91 unsigned Opcode = MI->getOpcode();
92
93 switch (Opcode) {
94 // Check for MOVs and print canonical forms, instead.
95 case ARM::MOVsr: {
96 // FIXME: Thumb variants?
97 const MCOperand &Dst = MI->getOperand(0);
98 const MCOperand &MO1 = MI->getOperand(1);
99 const MCOperand &MO2 = MI->getOperand(2);
100 const MCOperand &MO3 = MI->getOperand(3);
101
103 printSBitModifierOperand(MI, 6, STI, O);
104 printPredicateOperand(MI, 4, STI, O);
105
106 O << '\t';
107 printRegName(O, Dst.getReg());
108 O << ", ";
109 printRegName(O, MO1.getReg());
110
111 O << ", ";
112 printRegName(O, MO2.getReg());
114 printAnnotation(O, Annot);
115 return;
116 }
117
118 case ARM::MOVsi: {
119 // FIXME: Thumb variants?
120 const MCOperand &Dst = MI->getOperand(0);
121 const MCOperand &MO1 = MI->getOperand(1);
122 const MCOperand &MO2 = MI->getOperand(2);
123
125 printSBitModifierOperand(MI, 5, STI, O);
126 printPredicateOperand(MI, 3, STI, O);
127
128 O << '\t';
129 printRegName(O, Dst.getReg());
130 O << ", ";
131 printRegName(O, MO1.getReg());
132
134 printAnnotation(O, Annot);
135 return;
136 }
137
138 O << ", ";
141 printAnnotation(O, Annot);
142 return;
143 }
144
145 // A8.6.123 PUSH
146 case ARM::STMDB_UPD:
147 case ARM::t2STMDB_UPD:
148 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
149 // Should only print PUSH if there are at least two registers in the list.
150 O << '\t' << "push";
151 printPredicateOperand(MI, 2, STI, O);
152 if (Opcode == ARM::t2STMDB_UPD)
153 O << ".w";
154 O << '\t';
155 printRegisterList(MI, 4, STI, O);
156 printAnnotation(O, Annot);
157 return;
158 } else
159 break;
160
161 case ARM::STR_PRE_IMM:
162 if (MI->getOperand(2).getReg() == ARM::SP &&
163 MI->getOperand(3).getImm() == -4) {
164 O << '\t' << "push";
165 printPredicateOperand(MI, 4, STI, O);
166 O << "\t{";
167 printRegName(O, MI->getOperand(1).getReg());
168 O << "}";
169 printAnnotation(O, Annot);
170 return;
171 } else
172 break;
173
174 // A8.6.122 POP
175 case ARM::LDMIA_UPD:
176 case ARM::t2LDMIA_UPD:
177 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
178 // Should only print POP if there are at least two registers in the list.
179 O << '\t' << "pop";
180 printPredicateOperand(MI, 2, STI, O);
181 if (Opcode == ARM::t2LDMIA_UPD)
182 O << ".w";
183 O << '\t';
184 printRegisterList(MI, 4, STI, O);
185 printAnnotation(O, Annot);
186 return;
187 } else
188 break;
189
190 case ARM::LDR_POST_IMM:
191 if (MI->getOperand(2).getReg() == ARM::SP &&
192 MI->getOperand(4).getImm() == 4) {
193 O << '\t' << "pop";
194 printPredicateOperand(MI, 5, STI, O);
195 O << "\t{";
196 printRegName(O, MI->getOperand(0).getReg());
197 O << "}";
198 printAnnotation(O, Annot);
199 return;
200 } else
201 break;
202
203 // A8.6.355 VPUSH
204 case ARM::VSTMSDB_UPD:
205 case ARM::VSTMDDB_UPD:
206 if (MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, STI, O);
209 O << '\t';
210 printRegisterList(MI, 4, STI, O);
211 printAnnotation(O, Annot);
212 return;
213 } else
214 break;
215
216 // A8.6.354 VPOP
217 case ARM::VLDMSIA_UPD:
218 case ARM::VLDMDIA_UPD:
219 if (MI->getOperand(0).getReg() == ARM::SP) {
220 O << '\t' << "vpop";
221 printPredicateOperand(MI, 2, STI, O);
222 O << '\t';
223 printRegisterList(MI, 4, STI, O);
224 printAnnotation(O, Annot);
225 return;
226 } else
227 break;
228
229 case ARM::tLDMIA: {
230 bool Writeback = true;
231 unsigned BaseReg = MI->getOperand(0).getReg();
232 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
233 if (MI->getOperand(i).getReg() == BaseReg)
234 Writeback = false;
235 }
236
237 O << "\tldm";
238
239 printPredicateOperand(MI, 1, STI, O);
240 O << '\t';
241 printRegName(O, BaseReg);
242 if (Writeback)
243 O << "!";
244 O << ", ";
245 printRegisterList(MI, 3, STI, O);
246 printAnnotation(O, Annot);
247 return;
248 }
249
250 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
251 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
252 // a single GPRPair reg operand is used in the .td file to replace the two
253 // GPRs. However, when decoding them, the two GRPs cannot be automatically
254 // expressed as a GPRPair, so we have to manually merge them.
255 // FIXME: We would really like to be able to tablegen'erate this.
256 case ARM::LDREXD:
257 case ARM::STREXD:
258 case ARM::LDAEXD:
259 case ARM::STLEXD: {
260 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
261 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
262 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
263 if (MRC.contains(Reg)) {
264 MCInst NewMI;
265 MCOperand NewReg;
266 NewMI.setOpcode(Opcode);
267
268 if (isStore)
269 NewMI.addOperand(MI->getOperand(0));
271 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
272 NewMI.addOperand(NewReg);
273
274 // Copy the rest operands into NewMI.
275 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
276 NewMI.addOperand(MI->getOperand(i));
277 printInstruction(&NewMI, Address, STI, O);
278 return;
279 }
280 break;
281 }
282 case ARM::TSB:
283 case ARM::t2TSB:
284 O << "\ttsb\tcsync";
285 return;
286 case ARM::t2DSB:
287 switch (MI->getOperand(0).getImm()) {
288 default:
289 if (!printAliasInstr(MI, Address, STI, O))
290 printInstruction(MI, Address, STI, O);
291 break;
292 case 0:
293 O << "\tssbb";
294 break;
295 case 4:
296 O << "\tpssbb";
297 break;
298 }
299 printAnnotation(O, Annot);
300 return;
301 }
302
303 if (!printAliasInstr(MI, Address, STI, O))
304 printInstruction(MI, Address, STI, O);
305
306 printAnnotation(O, Annot);
307}
308
309void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
310 const MCSubtargetInfo &STI, raw_ostream &O) {
311 const MCOperand &Op = MI->getOperand(OpNo);
312 if (Op.isReg()) {
313 unsigned Reg = Op.getReg();
314 printRegName(O, Reg);
315 } else if (Op.isImm()) {
316 markup(O, Markup::Immediate) << '#' << formatImm(Op.getImm());
317 } else {
318 assert(Op.isExpr() && "unknown operand kind in printOperand");
319 const MCExpr *Expr = Op.getExpr();
320 switch (Expr->getKind()) {
321 case MCExpr::Binary:
322 O << '#';
323 Expr->print(O, &MAI);
324 break;
325 case MCExpr::Constant: {
326 // If a symbolic branch target was added as a constant expression then
327 // print that address in hex. And only print 32 unsigned bits for the
328 // address.
329 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
330 int64_t TargetAddress;
331 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
332 O << '#';
333 Expr->print(O, &MAI);
334 } else {
335 O << "0x";
336 O.write_hex(static_cast<uint32_t>(TargetAddress));
337 }
338 break;
339 }
340 default:
341 // FIXME: Should we always treat this as if it is a constant literal and
342 // prefix it with '#'?
343 Expr->print(O, &MAI);
344 break;
345 }
346 }
347}
348
350 unsigned OpNum, const MCSubtargetInfo &STI,
351 raw_ostream &O) {
352 const MCOperand &Op = MI->getOperand(OpNum);
353 if (!Op.isImm() || !PrintBranchImmAsAddress || getUseMarkup())
354 return printOperand(MI, OpNum, STI, O);
356 Address, Op.getImm());
357 Target &= 0xffffffff;
358 O << formatHex(Target);
359 if (CommentStream)
360 *CommentStream << "imm = #" << formatImm(Op.getImm()) << '\n';
361}
362
364 const MCSubtargetInfo &STI,
365 raw_ostream &O) {
366 const MCOperand &MO1 = MI->getOperand(OpNum);
367 if (MO1.isExpr()) {
368 MO1.getExpr()->print(O, &MAI);
369 return;
370 }
371
372 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
373 O << "[pc, ";
374
375 int32_t OffImm = (int32_t)MO1.getImm();
376 bool isSub = OffImm < 0;
377
378 // Special value for #-0. All others are normal.
379 if (OffImm == INT32_MIN)
380 OffImm = 0;
381 if (isSub) {
382 markup(O, Markup::Immediate) << "#-" << formatImm(-OffImm);
383 } else {
384 markup(O, Markup::Immediate) << "#" << formatImm(OffImm);
385 }
386 O << "]";
387}
388
389// so_reg is a 4-operand unit corresponding to register forms of the A5.1
390// "Addressing Mode 1 - Data-processing operands" forms. This includes:
391// REG 0 0 - e.g. R5
392// REG REG 0,SH_OPC - e.g. R5, ROR R3
393// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
395 const MCSubtargetInfo &STI,
396 raw_ostream &O) {
397 const MCOperand &MO1 = MI->getOperand(OpNum);
398 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
399 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
400
401 printRegName(O, MO1.getReg());
402
403 // Print the shift opc.
405 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
406 if (ShOpc == ARM_AM::rrx)
407 return;
408
409 O << ' ';
410 printRegName(O, MO2.getReg());
412}
413
415 const MCSubtargetInfo &STI,
416 raw_ostream &O) {
417 const MCOperand &MO1 = MI->getOperand(OpNum);
418 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
419
420 printRegName(O, MO1.getReg());
421
422 // Print the shift opc.
424 ARM_AM::getSORegOffset(MO2.getImm()), *this);
425}
426
427//===--------------------------------------------------------------------===//
428// Addressing Mode #2
429//===--------------------------------------------------------------------===//
430
432 const MCSubtargetInfo &STI,
433 raw_ostream &O) {
434 const MCOperand &MO1 = MI->getOperand(Op);
435 const MCOperand &MO2 = MI->getOperand(Op + 1);
436 const MCOperand &MO3 = MI->getOperand(Op + 2);
437
438 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
439 O << "[";
440 printRegName(O, MO1.getReg());
441
442 if (!MO2.getReg()) {
443 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
444 O << ", ";
448 }
449 O << "]";
450 return;
451 }
452
453 O << ", ";
455 printRegName(O, MO2.getReg());
456
458 ARM_AM::getAM2Offset(MO3.getImm()), *this);
459 O << "]";
460}
461
463 const MCSubtargetInfo &STI,
464 raw_ostream &O) {
465 const MCOperand &MO1 = MI->getOperand(Op);
466 const MCOperand &MO2 = MI->getOperand(Op + 1);
467
468 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
469 O << "[";
470 printRegName(O, MO1.getReg());
471 O << ", ";
472 printRegName(O, MO2.getReg());
473 O << "]";
474}
475
477 const MCSubtargetInfo &STI,
478 raw_ostream &O) {
479 const MCOperand &MO1 = MI->getOperand(Op);
480 const MCOperand &MO2 = MI->getOperand(Op + 1);
481 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
482 O << "[";
483 printRegName(O, MO1.getReg());
484 O << ", ";
485 printRegName(O, MO2.getReg());
486 O << ", lsl ";
487 markup(O, Markup::Immediate) << "#1";
488 O << "]";
489}
490
492 const MCSubtargetInfo &STI,
493 raw_ostream &O) {
494 const MCOperand &MO1 = MI->getOperand(Op);
495
496 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
497 printOperand(MI, Op, STI, O);
498 return;
499 }
500
501#ifndef NDEBUG
502 const MCOperand &MO3 = MI->getOperand(Op + 2);
503 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
504 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
505#endif
506
508}
509
511 unsigned OpNum,
512 const MCSubtargetInfo &STI,
513 raw_ostream &O) {
514 const MCOperand &MO1 = MI->getOperand(OpNum);
515 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
516
517 if (!MO1.getReg()) {
518 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
521 << ImmOffs;
522 return;
523 }
524
526 printRegName(O, MO1.getReg());
527
529 ARM_AM::getAM2Offset(MO2.getImm()), *this);
530}
531
532//===--------------------------------------------------------------------===//
533// Addressing Mode #3
534//===--------------------------------------------------------------------===//
535
537 raw_ostream &O,
538 bool AlwaysPrintImm0) {
539 const MCOperand &MO1 = MI->getOperand(Op);
540 const MCOperand &MO2 = MI->getOperand(Op + 1);
541 const MCOperand &MO3 = MI->getOperand(Op + 2);
542
543 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
544 O << '[';
545 printRegName(O, MO1.getReg());
546
547 if (MO2.getReg()) {
548 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
549 printRegName(O, MO2.getReg());
550 O << ']';
551 return;
552 }
553
554 // If the op is sub we have to print the immediate even if it is 0
555 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
557
558 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
559 O << ", ";
560 markup(O, Markup::Immediate) << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs;
561 }
562 O << ']';
563}
564
565template <bool AlwaysPrintImm0>
567 const MCSubtargetInfo &STI,
568 raw_ostream &O) {
569 const MCOperand &MO1 = MI->getOperand(Op);
570 if (!MO1.isReg()) { // For label symbolic references.
571 printOperand(MI, Op, STI, O);
572 return;
573 }
574
575 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
577 "unexpected idxmode");
578 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
579}
580
582 unsigned OpNum,
583 const MCSubtargetInfo &STI,
584 raw_ostream &O) {
585 const MCOperand &MO1 = MI->getOperand(OpNum);
586 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
587
588 if (MO1.getReg()) {
589 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
590 printRegName(O, MO1.getReg());
591 return;
592 }
593
594 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
597 << ImmOffs;
598}
599
601 const MCSubtargetInfo &STI,
602 raw_ostream &O) {
603 const MCOperand &MO = MI->getOperand(OpNum);
604 unsigned Imm = MO.getImm();
606 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
607}
608
610 const MCSubtargetInfo &STI,
611 raw_ostream &O) {
612 const MCOperand &MO1 = MI->getOperand(OpNum);
613 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
614
615 O << (MO2.getImm() ? "" : "-");
616 printRegName(O, MO1.getReg());
617}
618
620 const MCSubtargetInfo &STI,
621 raw_ostream &O) {
622 const MCOperand &MO = MI->getOperand(OpNum);
623 unsigned Imm = MO.getImm();
625 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
626}
627
628template<int shift>
630 const MCSubtargetInfo &STI,
631 raw_ostream &O) {
632 const MCOperand &MO1 = MI->getOperand(OpNum);
633 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
634
635 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
636 O << "[";
637 printRegName(O, MO1.getReg());
638 O << ", ";
639 printRegName(O, MO2.getReg());
640
641 if (shift > 0)
642 printRegImmShift(O, ARM_AM::uxtw, shift, *this);
643
644 O << "]";
645}
646
648 const MCSubtargetInfo &STI,
649 raw_ostream &O) {
650 ARM_AM::AMSubMode Mode =
651 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
652 O << ARM_AM::getAMSubModeStr(Mode);
653}
654
655template <bool AlwaysPrintImm0>
657 const MCSubtargetInfo &STI,
658 raw_ostream &O) {
659 const MCOperand &MO1 = MI->getOperand(OpNum);
660 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
661
662 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
663 printOperand(MI, OpNum, STI, O);
664 return;
665 }
666
667 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
668 O << "[";
669 printRegName(O, MO1.getReg());
670
671 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
673 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
674 O << ", ";
676 << "#" << ARM_AM::getAddrOpcStr(Op) << ImmOffs * 4;
677 }
678 O << "]";
679}
680
681template <bool AlwaysPrintImm0>
683 const MCSubtargetInfo &STI,
684 raw_ostream &O) {
685 const MCOperand &MO1 = MI->getOperand(OpNum);
686 const MCOperand &MO2 = MI->getOperand(OpNum+1);
687
688 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
689 printOperand(MI, OpNum, STI, O);
690 return;
691 }
692
693 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
694 O << "[";
695 printRegName(O, MO1.getReg());
696
697 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
698 unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
699 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
700 O << ", ";
703 << ImmOffs * 2;
704 }
705 O << "]";
706}
707
709 const MCSubtargetInfo &STI,
710 raw_ostream &O) {
711 const MCOperand &MO1 = MI->getOperand(OpNum);
712 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
713
714 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
715 O << "[";
716 printRegName(O, MO1.getReg());
717 if (MO2.getImm()) {
718 O << ":" << (MO2.getImm() << 3);
719 }
720 O << "]";
721}
722
724 const MCSubtargetInfo &STI,
725 raw_ostream &O) {
726 const MCOperand &MO1 = MI->getOperand(OpNum);
727 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
728 O << "[";
729 printRegName(O, MO1.getReg());
730 O << "]";
731}
732
734 unsigned OpNum,
735 const MCSubtargetInfo &STI,
736 raw_ostream &O) {
737 const MCOperand &MO = MI->getOperand(OpNum);
738 if (MO.getReg() == 0)
739 O << "!";
740 else {
741 O << ", ";
742 printRegName(O, MO.getReg());
743 }
744}
745
747 unsigned OpNum,
748 const MCSubtargetInfo &STI,
749 raw_ostream &O) {
750 const MCOperand &MO = MI->getOperand(OpNum);
751 uint32_t v = ~MO.getImm();
752 int32_t lsb = llvm::countr_zero(v);
753 int32_t width = llvm::bit_width(v) - lsb;
754 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
755 markup(O, Markup::Immediate) << '#' << lsb;
756 O << ", ";
757 markup(O, Markup::Immediate) << '#' << width;
758}
759
760void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
761 const MCSubtargetInfo &STI,
762 raw_ostream &O) {
763 unsigned val = MI->getOperand(OpNum).getImm();
764 O << ARM_MB::MemBOptToString(val, STI.hasFeature(ARM::HasV8Ops));
765}
766
768 const MCSubtargetInfo &STI,
769 raw_ostream &O) {
770 unsigned val = MI->getOperand(OpNum).getImm();
772}
773
775 const MCSubtargetInfo &STI,
776 raw_ostream &O) {
777 unsigned val = MI->getOperand(OpNum).getImm();
779}
780
782 const MCSubtargetInfo &STI,
783 raw_ostream &O) {
784 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
785 bool isASR = (ShiftOp & (1 << 5)) != 0;
786 unsigned Amt = ShiftOp & 0x1f;
787 if (isASR) {
788 O << ", asr ";
789 markup(O, Markup::Immediate) << "#" << (Amt == 0 ? 32 : Amt);
790 } else if (Amt) {
791 O << ", lsl ";
792 markup(O, Markup::Immediate) << "#" << Amt;
793 }
794}
795
797 const MCSubtargetInfo &STI,
798 raw_ostream &O) {
799 unsigned Imm = MI->getOperand(OpNum).getImm();
800 if (Imm == 0)
801 return;
802 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
803 O << ", lsl ";
804 markup(O, Markup::Immediate) << "#" << Imm;
805}
806
808 const MCSubtargetInfo &STI,
809 raw_ostream &O) {
810 unsigned Imm = MI->getOperand(OpNum).getImm();
811 // A shift amount of 32 is encoded as 0.
812 if (Imm == 0)
813 Imm = 32;
814 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
815 O << ", asr ";
816 markup(O, Markup::Immediate) << "#" << Imm;
817}
818
819void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
820 const MCSubtargetInfo &STI,
821 raw_ostream &O) {
822 if (MI->getOpcode() != ARM::t2CLRM) {
823 assert(is_sorted(drop_begin(*MI, OpNum),
824 [&](const MCOperand &LHS, const MCOperand &RHS) {
825 return MRI.getEncodingValue(LHS.getReg()) <
826 MRI.getEncodingValue(RHS.getReg());
827 }));
828 }
829
830 O << "{";
831 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
832 if (i != OpNum)
833 O << ", ";
834 printRegName(O, MI->getOperand(i).getReg());
835 }
836 O << "}";
837}
838
840 const MCSubtargetInfo &STI,
841 raw_ostream &O) {
842 unsigned Reg = MI->getOperand(OpNum).getReg();
843 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
844 O << ", ";
845 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
846}
847
848void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
849 const MCSubtargetInfo &STI,
850 raw_ostream &O) {
851 const MCOperand &Op = MI->getOperand(OpNum);
852 if (Op.getImm())
853 O << "be";
854 else
855 O << "le";
856}
857
858void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
859 const MCSubtargetInfo &STI, raw_ostream &O) {
860 const MCOperand &Op = MI->getOperand(OpNum);
861 O << ARM_PROC::IModToString(Op.getImm());
862}
863
864void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
865 const MCSubtargetInfo &STI, raw_ostream &O) {
866 const MCOperand &Op = MI->getOperand(OpNum);
867 unsigned IFlags = Op.getImm();
868 for (int i = 2; i >= 0; --i)
869 if (IFlags & (1 << i))
870 O << ARM_PROC::IFlagsToString(1 << i);
871
872 if (IFlags == 0)
873 O << "none";
874}
875
877 const MCSubtargetInfo &STI,
878 raw_ostream &O) {
879 const MCOperand &Op = MI->getOperand(OpNum);
880 const FeatureBitset &FeatureBits = STI.getFeatureBits();
881 if (FeatureBits[ARM::FeatureMClass]) {
882
883 unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
884 unsigned Opcode = MI->getOpcode();
885
886 // For writes, handle extended mask bits if the DSP extension is present.
887 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
889 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
890 O << TheReg->Name;
891 return;
892 }
893 }
894
895 // Handle the basic 8-bit mask.
896 SYSm &= 0xff;
897 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
898 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
899 // alias for MSR APSR_nzcvq.
901 if (TheReg) {
902 O << TheReg->Name;
903 return;
904 }
905 }
906
908 if (TheReg) {
909 O << TheReg->Name;
910 return;
911 }
912
913 O << SYSm;
914
915 return;
916 }
917
918 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
919 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
920 unsigned SpecRegRBit = Op.getImm() >> 4;
921 unsigned Mask = Op.getImm() & 0xf;
922
923 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
924 O << "APSR_";
925 switch (Mask) {
926 default:
927 llvm_unreachable("Unexpected mask value!");
928 case 4:
929 O << "g";
930 return;
931 case 8:
932 O << "nzcvq";
933 return;
934 case 12:
935 O << "nzcvqg";
936 return;
937 }
938 }
939
940 if (SpecRegRBit)
941 O << "SPSR";
942 else
943 O << "CPSR";
944
945 if (Mask) {
946 O << '_';
947 if (Mask & 8)
948 O << 'f';
949 if (Mask & 4)
950 O << 's';
951 if (Mask & 2)
952 O << 'x';
953 if (Mask & 1)
954 O << 'c';
955 }
956}
957
959 const MCSubtargetInfo &STI,
960 raw_ostream &O) {
961 uint32_t Banked = MI->getOperand(OpNum).getImm();
962 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
963 assert(TheReg && "invalid banked register operand");
964 std::string Name = TheReg->Name;
965
966 uint32_t isSPSR = (Banked & 0x20) >> 5;
967 if (isSPSR)
968 Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
969 O << Name;
970}
971
973 const MCSubtargetInfo &STI,
974 raw_ostream &O) {
975 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
976 // Handle the undefined 15 CC value here for printing so we don't abort().
977 if ((unsigned)CC == 15)
978 O << "<und>";
979 else if (CC != ARMCC::AL)
981}
982
984 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
985 raw_ostream &O) {
986 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
987 O << "cs";
988 else
989 printMandatoryPredicateOperand(MI, OpNum, STI, O);
990}
991
993 unsigned OpNum,
994 const MCSubtargetInfo &STI,
995 raw_ostream &O) {
996 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
998}
999
1001 unsigned OpNum,
1002 const MCSubtargetInfo &STI,
1003 raw_ostream &O) {
1004 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1006}
1007
1009 const MCSubtargetInfo &STI,
1010 raw_ostream &O) {
1011 if (MI->getOperand(OpNum).getReg()) {
1012 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1013 "Expect ARM CPSR register!");
1014 O << 's';
1015 }
1016}
1017
1019 const MCSubtargetInfo &STI,
1020 raw_ostream &O) {
1021 O << MI->getOperand(OpNum).getImm();
1022}
1023
1024void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1025 const MCSubtargetInfo &STI,
1026 raw_ostream &O) {
1027 O << "p" << MI->getOperand(OpNum).getImm();
1028}
1029
1030void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1031 const MCSubtargetInfo &STI,
1032 raw_ostream &O) {
1033 O << "c" << MI->getOperand(OpNum).getImm();
1034}
1035
1037 const MCSubtargetInfo &STI,
1038 raw_ostream &O) {
1039 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1040}
1041
1042void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1043 const MCSubtargetInfo &STI, raw_ostream &O) {
1044 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1045}
1046
1047template <unsigned scale>
1049 const MCSubtargetInfo &STI,
1050 raw_ostream &O) {
1051 const MCOperand &MO = MI->getOperand(OpNum);
1052
1053 if (MO.isExpr()) {
1054 MO.getExpr()->print(O, &MAI);
1055 return;
1056 }
1057
1058 int32_t OffImm = (int32_t)MO.getImm() << scale;
1059
1060 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1061 if (OffImm == INT32_MIN)
1062 O << "#-0";
1063 else if (OffImm < 0)
1064 O << "#-" << -OffImm;
1065 else
1066 O << "#" << OffImm;
1067}
1068
1070 const MCSubtargetInfo &STI,
1071 raw_ostream &O) {
1073 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);
1074}
1075
1076void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1077 const MCSubtargetInfo &STI,
1078 raw_ostream &O) {
1079 unsigned Imm = MI->getOperand(OpNum).getImm();
1080 markup(O, Markup::Immediate) << "#" << formatImm((Imm == 0 ? 32 : Imm));
1081}
1082
1083void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1084 const MCSubtargetInfo &STI,
1085 raw_ostream &O) {
1086 // (3 - the number of trailing zeros) is the number of then / else.
1087 unsigned Mask = MI->getOperand(OpNum).getImm();
1088 unsigned NumTZ = llvm::countr_zero(Mask);
1089 assert(NumTZ <= 3 && "Invalid IT mask!");
1090 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1091 if ((Mask >> Pos) & 1)
1092 O << 'e';
1093 else
1094 O << 't';
1095 }
1096}
1097
1099 const MCSubtargetInfo &STI,
1100 raw_ostream &O) {
1101 const MCOperand &MO1 = MI->getOperand(Op);
1102 const MCOperand &MO2 = MI->getOperand(Op + 1);
1103
1104 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1105 printOperand(MI, Op, STI, O);
1106 return;
1107 }
1108
1109 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1110 O << "[";
1111 printRegName(O, MO1.getReg());
1112 if (unsigned RegNum = MO2.getReg()) {
1113 O << ", ";
1114 printRegName(O, RegNum);
1115 }
1116 O << "]";
1117}
1118
1120 unsigned Op,
1121 const MCSubtargetInfo &STI,
1122 raw_ostream &O,
1123 unsigned Scale) {
1124 const MCOperand &MO1 = MI->getOperand(Op);
1125 const MCOperand &MO2 = MI->getOperand(Op + 1);
1126
1127 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1128 printOperand(MI, Op, STI, O);
1129 return;
1130 }
1131
1132 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1133 O << "[";
1134 printRegName(O, MO1.getReg());
1135 if (unsigned ImmOffs = MO2.getImm()) {
1136 O << ", ";
1137 markup(O, Markup::Immediate) << "#" << formatImm(ImmOffs * Scale);
1138 }
1139 O << "]";
1140}
1141
1143 unsigned Op,
1144 const MCSubtargetInfo &STI,
1145 raw_ostream &O) {
1147}
1148
1150 unsigned Op,
1151 const MCSubtargetInfo &STI,
1152 raw_ostream &O) {
1154}
1155
1157 unsigned Op,
1158 const MCSubtargetInfo &STI,
1159 raw_ostream &O) {
1161}
1162
1164 const MCSubtargetInfo &STI,
1165 raw_ostream &O) {
1167}
1168
1169// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1170// register with shift forms.
1171// REG 0 0 - e.g. R5
1172// REG IMM, SH_OPC - e.g. R5, LSL #3
1173void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1174 const MCSubtargetInfo &STI,
1175 raw_ostream &O) {
1176 const MCOperand &MO1 = MI->getOperand(OpNum);
1177 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1178
1179 unsigned Reg = MO1.getReg();
1180 printRegName(O, Reg);
1181
1182 // Print the shift opc.
1183 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1185 ARM_AM::getSORegOffset(MO2.getImm()), *this);
1186}
1187
1188template <bool AlwaysPrintImm0>
1190 const MCSubtargetInfo &STI,
1191 raw_ostream &O) {
1192 const MCOperand &MO1 = MI->getOperand(OpNum);
1193 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1194
1195 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1196 printOperand(MI, OpNum, STI, O);
1197 return;
1198 }
1199
1200 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1201 O << "[";
1202 printRegName(O, MO1.getReg());
1203
1204 int32_t OffImm = (int32_t)MO2.getImm();
1205 bool isSub = OffImm < 0;
1206 // Special value for #-0. All others are normal.
1207 if (OffImm == INT32_MIN)
1208 OffImm = 0;
1209 if (isSub) {
1210 O << ", ";
1211 markup(O, Markup::Immediate) << "#-" << formatImm(-OffImm);
1212 } else if (AlwaysPrintImm0 || OffImm > 0) {
1213 O << ", ";
1214 markup(O, Markup::Immediate) << "#" << formatImm(OffImm);
1215 }
1216 O << "]";
1217}
1218
1219template <bool AlwaysPrintImm0>
1221 unsigned OpNum,
1222 const MCSubtargetInfo &STI,
1223 raw_ostream &O) {
1224 const MCOperand &MO1 = MI->getOperand(OpNum);
1225 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1226
1227 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1228 O << "[";
1229 printRegName(O, MO1.getReg());
1230
1231 int32_t OffImm = (int32_t)MO2.getImm();
1232 bool isSub = OffImm < 0;
1233 // Don't print +0.
1234 if (OffImm == INT32_MIN)
1235 OffImm = 0;
1236 if (isSub) {
1237 O << ", ";
1238 markup(O, Markup::Immediate) << "#-" << -OffImm;
1239 } else if (AlwaysPrintImm0 || OffImm > 0) {
1240 O << ", ";
1241 markup(O, Markup::Immediate) << "#" << OffImm;
1242 }
1243 O << "]";
1244}
1245
1246template <bool AlwaysPrintImm0>
1248 unsigned OpNum,
1249 const MCSubtargetInfo &STI,
1250 raw_ostream &O) {
1251 const MCOperand &MO1 = MI->getOperand(OpNum);
1252 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1253
1254 if (!MO1.isReg()) { // For label symbolic references.
1255 printOperand(MI, OpNum, STI, O);
1256 return;
1257 }
1258
1259 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1260 O << "[";
1261 printRegName(O, MO1.getReg());
1262
1263 int32_t OffImm = (int32_t)MO2.getImm();
1264 bool isSub = OffImm < 0;
1265
1266 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1267
1268 // Don't print +0.
1269 if (OffImm == INT32_MIN)
1270 OffImm = 0;
1271 if (isSub) {
1272 O << ", ";
1273 markup(O, Markup::Immediate) << "#-" << -OffImm;
1274 } else if (AlwaysPrintImm0 || OffImm > 0) {
1275 O << ", ";
1276 markup(O, Markup::Immediate) << "#" << OffImm;
1277 }
1278 O << "]";
1279}
1280
1282 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1283 raw_ostream &O) {
1284 const MCOperand &MO1 = MI->getOperand(OpNum);
1285 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1286
1287 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1288 O << "[";
1289 printRegName(O, MO1.getReg());
1290 if (MO2.getImm()) {
1291 O << ", ";
1292 markup(O, Markup::Immediate) << "#" << formatImm(MO2.getImm() * 4);
1293 }
1294 O << "]";
1295}
1296
1298 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1299 raw_ostream &O) {
1300 const MCOperand &MO1 = MI->getOperand(OpNum);
1301 int32_t OffImm = (int32_t)MO1.getImm();
1302 O << ", ";
1303 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1304 if (OffImm == INT32_MIN)
1305 O << "#-0";
1306 else if (OffImm < 0)
1307 O << "#-" << -OffImm;
1308 else
1309 O << "#" << OffImm;
1310}
1311
1313 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1314 raw_ostream &O) {
1315 const MCOperand &MO1 = MI->getOperand(OpNum);
1316 int32_t OffImm = (int32_t)MO1.getImm();
1317
1318 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1319
1320 O << ", ";
1321 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1322 if (OffImm == INT32_MIN)
1323 O << "#-0";
1324 else if (OffImm < 0)
1325 O << "#-" << -OffImm;
1326 else
1327 O << "#" << OffImm;
1328}
1329
1331 unsigned OpNum,
1332 const MCSubtargetInfo &STI,
1333 raw_ostream &O) {
1334 const MCOperand &MO1 = MI->getOperand(OpNum);
1335 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1336 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1337
1338 WithMarkup ScopedMarkup = markup(O, Markup::Memory);
1339 O << "[";
1340 printRegName(O, MO1.getReg());
1341
1342 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1343 O << ", ";
1344 printRegName(O, MO2.getReg());
1345
1346 unsigned ShAmt = MO3.getImm();
1347 if (ShAmt) {
1348 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1349 O << ", lsl ";
1350 markup(O, Markup::Immediate) << "#" << ShAmt;
1351 }
1352 O << "]";
1353}
1354
1355void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1356 const MCSubtargetInfo &STI,
1357 raw_ostream &O) {
1358 const MCOperand &MO = MI->getOperand(OpNum);
1360}
1361
1363 const MCSubtargetInfo &STI,
1364 raw_ostream &O) {
1365 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1366 unsigned EltBits;
1367 uint64_t Val = ARM_AM::decodeVMOVModImm(EncodedImm, EltBits);
1368
1369 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
1370 O << "#0x";
1371 O.write_hex(Val);
1372}
1373
1375 const MCSubtargetInfo &STI,
1376 raw_ostream &O) {
1377 unsigned Imm = MI->getOperand(OpNum).getImm();
1378 markup(O, Markup::Immediate) << "#" << formatImm(Imm + 1);
1379}
1380
1382 const MCSubtargetInfo &STI,
1383 raw_ostream &O) {
1384 unsigned Imm = MI->getOperand(OpNum).getImm();
1385 if (Imm == 0)
1386 return;
1387 assert(Imm <= 3 && "illegal ror immediate!");
1388 O << ", ror ";
1389 markup(O, Markup::Immediate) << "#" << 8 * Imm;
1390}
1391
1393 const MCSubtargetInfo &STI,
1394 raw_ostream &O) {
1395 MCOperand Op = MI->getOperand(OpNum);
1396
1397 // Support for fixups (MCFixup)
1398 if (Op.isExpr())
1399 return printOperand(MI, OpNum, STI, O);
1400
1401 unsigned Bits = Op.getImm() & 0xFF;
1402 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1403
1404 bool PrintUnsigned = false;
1405 switch (MI->getOpcode()) {
1406 case ARM::MOVi:
1407 // Movs to PC should be treated unsigned
1408 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1409 break;
1410 case ARM::MSRi:
1411 // Movs to special registers should be treated unsigned
1412 PrintUnsigned = true;
1413 break;
1414 }
1415
1416 int32_t Rotated = llvm::rotr<uint32_t>(Bits, Rot);
1417 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1418 // #rot has the least possible value
1419 O << "#";
1420 if (PrintUnsigned)
1421 markup(O, Markup::Immediate) << static_cast<uint32_t>(Rotated);
1422 else
1423 markup(O, Markup::Immediate) << Rotated;
1424 return;
1425 }
1426
1427 // Explicit #bits, #rot implied
1428 O << "#";
1429 markup(O, Markup::Immediate) << Bits;
1430 O << ", #";
1431 markup(O, Markup::Immediate) << Rot;
1432}
1433
1434void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1435 const MCSubtargetInfo &STI, raw_ostream &O) {
1436 markup(O, Markup::Immediate) << "#" << 16 - MI->getOperand(OpNum).getImm();
1437}
1438
1439void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1440 const MCSubtargetInfo &STI, raw_ostream &O) {
1441 markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
1442}
1443
1444void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1445 const MCSubtargetInfo &STI,
1446 raw_ostream &O) {
1447 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1448}
1449
1451 const MCSubtargetInfo &STI,
1452 raw_ostream &O) {
1453 O << "{";
1454 printRegName(O, MI->getOperand(OpNum).getReg());
1455 O << "}";
1456}
1457
1459 const MCSubtargetInfo &STI,
1460 raw_ostream &O) {
1461 unsigned Reg = MI->getOperand(OpNum).getReg();
1462 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1463 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1464 O << "{";
1465 printRegName(O, Reg0);
1466 O << ", ";
1467 printRegName(O, Reg1);
1468 O << "}";
1469}
1470
1472 const MCSubtargetInfo &STI,
1473 raw_ostream &O) {
1474 unsigned Reg = MI->getOperand(OpNum).getReg();
1475 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1476 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1477 O << "{";
1478 printRegName(O, Reg0);
1479 O << ", ";
1480 printRegName(O, Reg1);
1481 O << "}";
1482}
1483
1485 const MCSubtargetInfo &STI,
1486 raw_ostream &O) {
1487 // Normally, it's not safe to use register enum values directly with
1488 // addition to get the next register, but for VFP registers, the
1489 // sort order is guaranteed because they're all of the form D<n>.
1490 O << "{";
1491 printRegName(O, MI->getOperand(OpNum).getReg());
1492 O << ", ";
1493 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1494 O << ", ";
1495 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1496 O << "}";
1497}
1498
1500 const MCSubtargetInfo &STI,
1501 raw_ostream &O) {
1502 // Normally, it's not safe to use register enum values directly with
1503 // addition to get the next register, but for VFP registers, the
1504 // sort order is guaranteed because they're all of the form D<n>.
1505 O << "{";
1506 printRegName(O, MI->getOperand(OpNum).getReg());
1507 O << ", ";
1508 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1509 O << ", ";
1510 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1511 O << ", ";
1512 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1513 O << "}";
1514}
1515
1517 unsigned OpNum,
1518 const MCSubtargetInfo &STI,
1519 raw_ostream &O) {
1520 O << "{";
1521 printRegName(O, MI->getOperand(OpNum).getReg());
1522 O << "[]}";
1523}
1524
1526 unsigned OpNum,
1527 const MCSubtargetInfo &STI,
1528 raw_ostream &O) {
1529 unsigned Reg = MI->getOperand(OpNum).getReg();
1530 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1531 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1532 O << "{";
1533 printRegName(O, Reg0);
1534 O << "[], ";
1535 printRegName(O, Reg1);
1536 O << "[]}";
1537}
1538
1540 unsigned OpNum,
1541 const MCSubtargetInfo &STI,
1542 raw_ostream &O) {
1543 // Normally, it's not safe to use register enum values directly with
1544 // addition to get the next register, but for VFP registers, the
1545 // sort order is guaranteed because they're all of the form D<n>.
1546 O << "{";
1547 printRegName(O, MI->getOperand(OpNum).getReg());
1548 O << "[], ";
1549 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1550 O << "[], ";
1551 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1552 O << "[]}";
1553}
1554
1556 unsigned OpNum,
1557 const MCSubtargetInfo &STI,
1558 raw_ostream &O) {
1559 // Normally, it's not safe to use register enum values directly with
1560 // addition to get the next register, but for VFP registers, the
1561 // sort order is guaranteed because they're all of the form D<n>.
1562 O << "{";
1563 printRegName(O, MI->getOperand(OpNum).getReg());
1564 O << "[], ";
1565 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1566 O << "[], ";
1567 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1568 O << "[], ";
1569 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1570 O << "[]}";
1571}
1572
1574 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1575 raw_ostream &O) {
1576 unsigned Reg = MI->getOperand(OpNum).getReg();
1577 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1578 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1579 O << "{";
1580 printRegName(O, Reg0);
1581 O << "[], ";
1582 printRegName(O, Reg1);
1583 O << "[]}";
1584}
1585
1587 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1588 raw_ostream &O) {
1589 // Normally, it's not safe to use register enum values directly with
1590 // addition to get the next register, but for VFP registers, the
1591 // sort order is guaranteed because they're all of the form D<n>.
1592 O << "{";
1593 printRegName(O, MI->getOperand(OpNum).getReg());
1594 O << "[], ";
1595 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1596 O << "[], ";
1597 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1598 O << "[]}";
1599}
1600
1602 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1603 raw_ostream &O) {
1604 // Normally, it's not safe to use register enum values directly with
1605 // addition to get the next register, but for VFP registers, the
1606 // sort order is guaranteed because they're all of the form D<n>.
1607 O << "{";
1608 printRegName(O, MI->getOperand(OpNum).getReg());
1609 O << "[], ";
1610 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1611 O << "[], ";
1612 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1613 O << "[], ";
1614 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1615 O << "[]}";
1616}
1617
1619 unsigned OpNum,
1620 const MCSubtargetInfo &STI,
1621 raw_ostream &O) {
1622 // Normally, it's not safe to use register enum values directly with
1623 // addition to get the next register, but for VFP registers, the
1624 // sort order is guaranteed because they're all of the form D<n>.
1625 O << "{";
1626 printRegName(O, MI->getOperand(OpNum).getReg());
1627 O << ", ";
1628 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1629 O << ", ";
1630 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1631 O << "}";
1632}
1633
1635 const MCSubtargetInfo &STI,
1636 raw_ostream &O) {
1637 // Normally, it's not safe to use register enum values directly with
1638 // addition to get the next register, but for VFP registers, the
1639 // sort order is guaranteed because they're all of the form D<n>.
1640 O << "{";
1641 printRegName(O, MI->getOperand(OpNum).getReg());
1642 O << ", ";
1643 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1644 O << ", ";
1645 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1646 O << ", ";
1647 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1648 O << "}";
1649}
1650
1651template<unsigned NumRegs>
1653 const MCSubtargetInfo &STI,
1654 raw_ostream &O) {
1655 unsigned Reg = MI->getOperand(OpNum).getReg();
1656 const char *Prefix = "{";
1657 for (unsigned i = 0; i < NumRegs; i++) {
1658 O << Prefix;
1659 printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1660 Prefix = ", ";
1661 }
1662 O << "}";
1663}
1664
1665template<int64_t Angle, int64_t Remainder>
1667 const MCSubtargetInfo &STI,
1668 raw_ostream &O) {
1669 unsigned Val = MI->getOperand(OpNo).getImm();
1670 O << "#" << (Val * Angle) + Remainder;
1671}
1672
1674 const MCSubtargetInfo &STI,
1675 raw_ostream &O) {
1676 ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1677 if (CC != ARMVCC::None)
1678 O << ARMVPTPredToString(CC);
1679}
1680
1681void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1682 const MCSubtargetInfo &STI,
1683 raw_ostream &O) {
1684 // (3 - the number of trailing zeroes) is the number of them / else.
1685 unsigned Mask = MI->getOperand(OpNum).getImm();
1686 unsigned NumTZ = llvm::countr_zero(Mask);
1687 assert(NumTZ <= 3 && "Invalid VPT mask!");
1688 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1689 bool T = ((Mask >> Pos) & 1) == 0;
1690 if (T)
1691 O << 't';
1692 else
1693 O << 'e';
1694 }
1695}
1696
1698 const MCSubtargetInfo &STI,
1699 raw_ostream &O) {
1700 uint32_t Val = MI->getOperand(OpNum).getImm();
1701 assert(Val <= 1 && "Invalid MVE saturate operand");
1702 O << "#" << (Val == 1 ? 48 : 64);
1703}
unsigned const MachineRegisterInfo * MRI
static bool isStore(int Opcode)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, const ARMInstPrinter &printer)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
dxil pretty printer
std::string Name
#define op(i)
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Value * RHS
Value * LHS
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMVEVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryRestrictedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
Container class for subtarget features.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ Constant
Constant expressions.
Definition: MCExpr.h:39
@ Binary
Binary expressions.
Definition: MCExpr.h:38
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
ExprKind getKind() const
Definition: MCExpr.h:81
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
format_object< int64_t > formatHex(int64_t Value) const
const MCInstrInfo & MII
Definition: MCInstPrinter.h:52
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:50
WithMarkup markup(raw_ostream &OS, Markup M) const
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:53
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:51
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
bool getUseMarkup() const
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:74
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:48
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:63
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:58
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:52
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...
unsigned getAM2IdxMode(unsigned AM2Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
unsigned getAM2Offset(unsigned AM2Opc)
const char * getAMSubModeStr(AMSubMode Mode)
float getFPImmFloat(unsigned Imm)
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
const char * getAddrOpcStr(AddrOpc Op)
const char * getShiftOpcStr(ShiftOpc Op)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
AMSubMode getAM4SubMode(unsigned Mode)
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:134
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:77
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:46
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:37
static const char * TraceSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:105
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:330
static const char * ARMVPTPredToString(ARMVCC::VPTCodes CC)
Definition: ARMBaseInfo.h:130
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
Definition: bit.h:281
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:179
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition: STLExtras.h:1907
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:146