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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <utility>
34 
35 namespace llvm {
36 
37 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
42 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
51 
52  namespace ARMISD {
53 
54  // ARM Specific DAG Nodes
55  enum NodeType : unsigned {
56  // Start the numbering where the builtin ops and target ops leave off.
58 
59  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
60  // TargetExternalSymbol, and TargetGlobalAddress.
61  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
62  // PIC mode.
63  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
64 
65  // Add pseudo op to model memcpy for struct byval.
67 
68  CALL, // Function call.
69  CALL_PRED, // Function call that's predicable.
70  CALL_NOLINK, // Function call with branch not branch-and-link.
71  tSECALL, // CMSE non-secure function call.
72  BRCOND, // Conditional branch.
73  BR_JT, // Jumptable branch.
74  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75  RET_FLAG, // Return with a flag operand.
76  SERET_FLAG, // CMSE Entry function return with a flag operand.
77  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
78 
79  PIC_ADD, // Add with a PC operand and a PIC label.
80 
81  ASRL, // MVE long arithmetic shift right.
82  LSRL, // MVE long shift right.
83  LSLL, // MVE long shift left.
84 
85  CMP, // ARM compare instructions.
86  CMN, // ARM CMN instructions.
87  CMPZ, // ARM compare that sets only Z flag.
88  CMPFP, // ARM VFP compare instruction, sets FPSCR.
89  CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
90  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
91  CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
92  // FPSCR.
93  FMSTAT, // ARM fmstat instruction.
94 
95  CMOV, // ARM conditional move instructions.
96  SUBS, // Flag-setting subtraction.
97 
98  SSAT, // Signed saturation
99  USAT, // Unsigned saturation
100 
102 
103  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
104  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
105  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
106 
107  ADDC, // Add with carry
108  ADDE, // Add using carry
109  SUBC, // Sub with carry
110  SUBE, // Sub using carry
111  LSLS, // Shift left producing carry
112 
113  VMOVRRD, // double to two gprs.
114  VMOVDRR, // Two gprs to double.
115  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
116 
117  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
118  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
119  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
120 
121  TC_RETURN, // Tail call return pseudo.
122 
124 
125  DYN_ALLOC, // Dynamic allocation on the stack.
126 
127  MEMBARRIER_MCR, // Memory barrier (MCR)
128 
129  PRELOAD, // Preload
130 
131  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
132  WIN__DBZCHK, // Windows' divide by zero check
133 
134  WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
135  WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
136  LOOP_DEC, // Really a part of LE, performs the sub
137  LE, // Low-overhead loops, Loop End
138 
139  PREDICATE_CAST, // Predicate cast for MVE i1 types
140  VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
141 
142  VCMP, // Vector compare.
143  VCMPZ, // Vector compare to zero.
144  VTST, // Vector test bits.
145 
146  // Vector shift by vector
147  VSHLs, // ...left/right by signed
148  VSHLu, // ...left/right by unsigned
149 
150  // Vector shift by immediate:
151  VSHLIMM, // ...left
152  VSHRsIMM, // ...right (signed)
153  VSHRuIMM, // ...right (unsigned)
154 
155  // Vector rounding shift by immediate:
156  VRSHRsIMM, // ...right (signed)
157  VRSHRuIMM, // ...right (unsigned)
158  VRSHRNIMM, // ...right narrow
159 
160  // Vector saturating shift by immediate:
161  VQSHLsIMM, // ...left (signed)
162  VQSHLuIMM, // ...left (unsigned)
163  VQSHLsuIMM, // ...left (signed to unsigned)
164  VQSHRNsIMM, // ...right narrow (signed)
165  VQSHRNuIMM, // ...right narrow (unsigned)
166  VQSHRNsuIMM, // ...right narrow (signed to unsigned)
167 
168  // Vector saturating rounding shift by immediate:
169  VQRSHRNsIMM, // ...right narrow (signed)
170  VQRSHRNuIMM, // ...right narrow (unsigned)
171  VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
172 
173  // Vector shift and insert:
174  VSLIIMM, // ...left
175  VSRIIMM, // ...right
176 
177  // Vector get lane (VMOV scalar to ARM core register)
178  // (These are used for 8- and 16-bit element types only.)
179  VGETLANEu, // zero-extend vector extract element
180  VGETLANEs, // sign-extend vector extract element
181 
182  // Vector move immediate and move negated immediate:
185 
186  // Vector move f32 immediate:
188 
189  // Move H <-> R, clearing top 16 bits
192 
193  // Vector duplicate:
196 
197  // Vector shuffles:
198  VEXT, // extract
199  VREV64, // reverse elements within 64-bit doublewords
200  VREV32, // reverse elements within 32-bit words
201  VREV16, // reverse elements within 16-bit halfwords
202  VZIP, // zip (interleave)
203  VUZP, // unzip (deinterleave)
204  VTRN, // transpose
205  VTBL1, // 1-register shuffle with mask
206  VTBL2, // 2-register shuffle with mask
207  VMOVN, // MVE vmovn
208 
209  // MVE Saturating truncates
210  VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
211  VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
212 
213  // MVE float <> half converts
214  VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
215  // lanes
216  VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
217 
218  // MVE VIDUP instruction, taking a start value and increment.
220 
221  // Vector multiply long:
222  VMULLs, // ...signed
223  VMULLu, // ...unsigned
224 
225  VQDMULH, // MVE vqdmulh instruction
226 
227  // MVE reductions
228  VADDVs, // sign- or zero-extend the elements of a vector to i32,
229  VADDVu, // add them all together, and return an i32 of their sum
230  VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
232  VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
233  VADDLVu, // the low and high 32-bit halves of the sum
234  VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
235  VADDLVAu, // provided as low and high halves
236  VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
238  VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
240  VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
241  // them
242  VMLAVu, // and add the results together, returning an i32 of their sum
243  VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
245  VMLALVs, // Same as VMLAV but with i64, returning the low and
246  VMLALVu, // high 32-bit halves of the sum
247  VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
249  VMLALVAs, // Same as VMLALV but also add an input accumulator
250  VMLALVAu, // provided as low and high halves
251  VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
253  VMINVu, // Find minimum unsigned value of a vector and register
254  VMINVs, // Find minimum signed value of a vector and register
255  VMAXVu, // Find maximum unsigned value of a vector and register
256  VMAXVs, // Find maximum signed value of a vector and register
257 
258  SMULWB, // Signed multiply word by half word, bottom
259  SMULWT, // Signed multiply word by half word, top
260  UMLAL, // 64bit Unsigned Accumulate Multiply
261  SMLAL, // 64bit Signed Accumulate Multiply
262  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
263  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
264  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
265  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
266  SMLALTT, // 64-bit signed accumulate multiply top, top 16
267  SMLALD, // Signed multiply accumulate long dual
268  SMLALDX, // Signed multiply accumulate long dual exchange
269  SMLSLD, // Signed multiply subtract long dual
270  SMLSLDX, // Signed multiply subtract long dual exchange
271  SMMLAR, // Signed multiply long, round and add
272  SMMLSR, // Signed multiply long, subtract and round
273 
274  // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
275  // stands for.
280 
281  // Operands of the standard BUILD_VECTOR node are not legalized, which
282  // is fine if BUILD_VECTORs are always lowered to shuffles or other
283  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
284  // operands need to be legalized. Define an ARM-specific version of
285  // BUILD_VECTOR for this purpose.
287 
288  // Bit-field insert
290 
291  // Vector OR with immediate
293  // Vector AND with NOT of immediate
295 
296  // Pseudo vector bitwise select
298 
299  // Pseudo-instruction representing a memory copy using ldm/stm
300  // instructions.
302 
303  // Pseudo-instruction representing a memory copy using a tail predicated
304  // loop
306  // Pseudo-instruction representing a memset using a tail predicated
307  // loop
309 
310  // V8.1MMainline condition select
311  CSINV, // Conditional select invert.
312  CSNEG, // Conditional select negate.
313  CSINC, // Conditional select increment.
314 
315  // Vector load N-element structure to all lanes:
320 
321  // NEON loads with post-increment base updates:
333 
334  // NEON stores with post-increment base updates:
342 
343  // Load/Store of dual registers
346  };
347 
348  } // end namespace ARMISD
349 
350  namespace ARM {
351  /// Possible values of current rounding mode, which is specified in bits
352  /// 23:22 of FPSCR.
353  enum Rounding {
354  RN = 0, // Round to Nearest
355  RP = 1, // Round towards Plus infinity
356  RM = 2, // Round towards Minus infinity
357  RZ = 3, // Round towards Zero
358  rmMask = 3 // Bit mask selecting rounding mode
359  };
360 
361  // Bit position of rounding mode bits in FPSCR.
362  const unsigned RoundingBitsPos = 22;
363  } // namespace ARM
364 
365  /// Define some predicates that are used for node matching.
366  namespace ARM {
367 
368  bool isBitFieldInvertedMask(unsigned v);
369 
370  } // end namespace ARM
371 
372  //===--------------------------------------------------------------------===//
373  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
374 
376  public:
377  explicit ARMTargetLowering(const TargetMachine &TM,
378  const ARMSubtarget &STI);
379 
380  unsigned getJumpTableEncoding() const override;
381  bool useSoftFloat() const override;
382 
383  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
384 
385  /// ReplaceNodeResults - Replace the results of node with an illegal result
386  /// type with new values built out of custom code.
388  SelectionDAG &DAG) const override;
389 
390  const char *getTargetNodeName(unsigned Opcode) const override;
391 
392  bool isSelectSupported(SelectSupportKind Kind) const override {
393  // ARM does not support scalar condition selects on vectors.
394  return (Kind != ScalarCondVectorVal);
395  }
396 
397  bool isReadOnly(const GlobalValue *GV) const;
398 
399  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
401  EVT VT) const override;
402 
405  MachineBasicBlock *MBB) const override;
406 
408  SDNode *Node) const override;
409 
413  SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
414  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
415 
417  const APInt &OriginalDemandedBits,
418  const APInt &OriginalDemandedElts,
419  KnownBits &Known,
420  TargetLoweringOpt &TLO,
421  unsigned Depth) const override;
422 
423  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
424 
425  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
426  /// unaligned memory accesses of the specified type. Returns whether it
427  /// is "fast" by reference in the second argument.
428  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
429  Align Alignment,
431  bool *Fast) const override;
432 
434  const AttributeList &FuncAttributes) const override;
435 
436  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
437  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
438  bool isZExtFree(SDValue Val, EVT VT2) const override;
440  SmallVectorImpl<Use *> &Ops) const override;
441  Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
442 
443  bool isFNegFree(EVT VT) const override;
444 
445  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
446 
447  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
448 
449 
450  /// isLegalAddressingMode - Return true if the addressing mode represented
451  /// by AM is legal for this target, for a load/store of the specified type.
452  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
453  Type *Ty, unsigned AS,
454  Instruction *I = nullptr) const override;
455 
456  /// getScalingFactorCost - Return the cost of the scaling used in
457  /// addressing mode represented by AM.
458  /// If the AM is supported, the return value must be >= 0.
459  /// If the AM is not supported, the return value must be negative.
461  const AddrMode &AM, Type *Ty,
462  unsigned AS) const override;
463 
464  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
465 
466  /// Returns true if the addressing mode representing by AM is legal
467  /// for the Thumb1 target, for a load/store of the specified type.
468  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
469 
470  /// isLegalICmpImmediate - Return true if the specified immediate is legal
471  /// icmp immediate, that is the target has icmp instructions which can
472  /// compare a register against the immediate without having to materialize
473  /// the immediate into a register.
474  bool isLegalICmpImmediate(int64_t Imm) const override;
475 
476  /// isLegalAddImmediate - Return true if the specified immediate is legal
477  /// add immediate, that is the target has add instructions which can
478  /// add a register and the immediate without having to materialize
479  /// the immediate into a register.
480  bool isLegalAddImmediate(int64_t Imm) const override;
481 
482  /// getPreIndexedAddressParts - returns true by value, base pointer and
483  /// offset pointer and addressing mode by reference if the node's address
484  /// can be legally represented as pre-indexed load / store address.
487  SelectionDAG &DAG) const override;
488 
489  /// getPostIndexedAddressParts - returns true by value, base pointer and
490  /// offset pointer and addressing mode by reference if this node can be
491  /// combined with a load / store to form a post-indexed load / store.
494  SelectionDAG &DAG) const override;
495 
497  const APInt &DemandedElts,
498  const SelectionDAG &DAG,
499  unsigned Depth) const override;
500 
502  const APInt &DemandedElts,
503  TargetLoweringOpt &TLO) const override;
504 
505  bool ExpandInlineAsm(CallInst *CI) const override;
506 
507  ConstraintType getConstraintType(StringRef Constraint) const override;
508 
509  /// Examine constraint string and operand type and determine a weight value.
510  /// The operand object must already have been set up with the operand type.
512  AsmOperandInfo &info, const char *constraint) const override;
513 
514  std::pair<unsigned, const TargetRegisterClass *>
516  StringRef Constraint, MVT VT) const override;
517 
518  const char *LowerXConstraint(EVT ConstraintVT) const override;
519 
520  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
521  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
522  /// true it means one of the asm constraint of the inline asm instruction
523  /// being processed is 'm'.
524  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
525  std::vector<SDValue> &Ops,
526  SelectionDAG &DAG) const override;
527 
528  unsigned
529  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
530  if (ConstraintCode == "Q")
532  else if (ConstraintCode.size() == 2) {
533  if (ConstraintCode[0] == 'U') {
534  switch(ConstraintCode[1]) {
535  default:
536  break;
537  case 'm':
539  case 'n':
541  case 'q':
543  case 's':
545  case 't':
547  case 'v':
549  case 'y':
551  }
552  }
553  }
554  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
555  }
556 
557  const ARMSubtarget* getSubtarget() const {
558  return Subtarget;
559  }
560 
561  /// getRegClassFor - Return the register class that should be used for the
562  /// specified value type.
563  const TargetRegisterClass *
564  getRegClassFor(MVT VT, bool isDivergent = false) const override;
565 
566  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
567  unsigned &PrefAlign) const override;
568 
569  /// createFastISel - This method returns a target specific FastISel object,
570  /// or null if the target does not support "fast" ISel.
572  const TargetLibraryInfo *libInfo) const override;
573 
575 
576  bool
577  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
578  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
579 
580  /// isFPImmLegal - Returns true if the target can instruction select the
581  /// specified FP immediate natively. If false, the legalizer will
582  /// materialize the FP immediate as a load from a constant pool.
583  bool isFPImmLegal(const APFloat &Imm, EVT VT,
584  bool ForCodeSize = false) const override;
585 
586  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
587  const CallInst &I,
588  MachineFunction &MF,
589  unsigned Intrinsic) const override;
590 
591  /// Returns true if it is beneficial to convert a load of a constant
592  /// to just the constant itself.
594  Type *Ty) const override;
595 
596  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
597  /// with this index.
598  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
599  unsigned Index) const override;
600 
601  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
602  bool MathUsed) const override {
603  // Using overflow ops for overflow checks only should beneficial on ARM.
604  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
605  }
606 
607  /// Returns true if an argument of type Ty needs to be passed in a
608  /// contiguous block of registers in calling convention CallConv.
610  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
611 
612  /// If a physical register, this returns the register that receives the
613  /// exception address on entry to an EH pad.
614  Register
615  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
616 
617  /// If a physical register, this returns the register that receives the
618  /// exception typeid on entry to a landing pad.
619  Register
620  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
621 
624  AtomicOrdering Ord) const override;
626  Value *Addr, AtomicOrdering Ord) const override;
627 
629 
631  AtomicOrdering Ord) const override;
633  AtomicOrdering Ord) const override;
634 
635  unsigned getMaxSupportedInterleaveFactor() const override;
636 
639  ArrayRef<unsigned> Indices,
640  unsigned Factor) const override;
642  unsigned Factor) const override;
643 
644  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
646  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
647  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
649  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
652 
653  bool useLoadStackGuardNode() const override;
654 
655  void insertSSPDeclarations(Module &M) const override;
656  Value *getSDagStackGuard(const Module &M) const override;
657  Function *getSSPStackGuardCheck(const Module &M) const override;
658 
659  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
660  unsigned &Cost) const override;
661 
662  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
663  const SelectionDAG &DAG) const override {
664  // Do not merge to larger than i32.
665  return (MemVT.getSizeInBits() <= 32);
666  }
667 
668  bool isCheapToSpeculateCttz() const override;
669  bool isCheapToSpeculateCtlz() const override;
670 
671  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
672  return VT.isScalarInteger();
673  }
674 
675  bool supportSwiftError() const override {
676  return true;
677  }
678 
679  bool hasStandaloneRem(EVT VT) const override {
680  return HasStandaloneRem;
681  }
682 
683  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
684 
685  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
686  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
687 
688  /// Returns true if \p VecTy is a legal interleaved access type. This
689  /// function checks the vector element type and the overall width of the
690  /// vector.
691  bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
692  Align Alignment,
693  const DataLayout &DL) const;
694 
695  bool alignLoopsWithOptSize() const override;
696 
697  /// Returns the number of interleaved accesses that will be generated when
698  /// lowering accesses of the given type.
699  unsigned getNumInterleavedAccesses(VectorType *VecTy,
700  const DataLayout &DL) const;
701 
702  void finalizeLowering(MachineFunction &MF) const override;
703 
704  /// Return the correct alignment for the current calling convention.
706  DataLayout DL) const override;
707 
709  CombineLevel Level) const override;
710 
712  CombineLevel Level) const override;
713 
714  bool preferIncOfAddToSubOfNot(EVT VT) const override;
715 
716  protected:
717  std::pair<const TargetRegisterClass *, uint8_t>
719  MVT VT) const override;
720 
721  private:
722  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
723  /// make the right decision when generating code for different targets.
724  const ARMSubtarget *Subtarget;
725 
727 
728  const InstrItineraryData *Itins;
729 
730  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
731  unsigned ARMPCLabelIndex;
732 
733  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
734  // check.
735  bool InsertFencesForAtomic;
736 
737  bool HasStandaloneRem = true;
738 
739  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
740  void addDRTypeForNEON(MVT VT);
741  void addQRTypeForNEON(MVT VT);
742  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
743 
744  using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
745 
746  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
747  SDValue &Arg, RegsToPassVector &RegsToPass,
748  CCValAssign &VA, CCValAssign &NextVA,
749  SDValue &StackPtr,
750  SmallVectorImpl<SDValue> &MemOpChains,
751  ISD::ArgFlagsTy Flags) const;
752  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
753  SDValue &Root, SelectionDAG &DAG,
754  const SDLoc &dl) const;
755 
756  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
757  bool isVarArg) const;
758  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
759  bool isVarArg) const;
760  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
761  const SDLoc &dl, SelectionDAG &DAG,
762  const CCValAssign &VA,
763  ISD::ArgFlagsTy Flags) const;
764  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
765  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
766  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
767  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
768  const ARMSubtarget *Subtarget) const;
769  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
770  const ARMSubtarget *Subtarget) const;
771  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
772  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
773  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
774  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
775  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
776  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
777  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
778  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
779  SelectionDAG &DAG) const;
780  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
781  SelectionDAG &DAG,
782  TLSModel::Model model) const;
783  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
784  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
785  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
786  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
787  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
788  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
789  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
790  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
791  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
792  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
793  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
794  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
795  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
796  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
797  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
798  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
799  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
800  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
801  const ARMSubtarget *ST) const;
802  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
803  const ARMSubtarget *ST) const;
804  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
805  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
806  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
807  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
808  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
810  SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
811  const ARMSubtarget *Subtarget) const;
812  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
813  SDValue &Chain) const;
814  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
815  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
816  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
817  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
818  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
819  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
820  SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
821  void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
822  SelectionDAG &DAG) const;
823  void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
824  SelectionDAG &DAG) const;
825 
826  Register getRegisterByName(const char* RegName, LLT VT,
827  const MachineFunction &MF) const override;
828 
829  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
830  SmallVectorImpl<SDNode *> &Created) const override;
831 
832  bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
833  EVT VT) const override;
834 
835  SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
836  SDValue Val) const;
837  SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
838  MVT ValVT, SDValue Val) const;
839 
840  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
841 
842  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
843  CallingConv::ID CallConv, bool isVarArg,
845  const SDLoc &dl, SelectionDAG &DAG,
846  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
847  SDValue ThisVal) const;
848 
849  bool supportSplitCSR(MachineFunction *MF) const override {
851  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
852  }
853 
854  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
855  void insertCopiesSplitCSR(
856  MachineBasicBlock *Entry,
857  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
858 
859  bool
860  splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
861  SDValue *Parts, unsigned NumParts, MVT PartVT,
862  Optional<CallingConv::ID> CC) const override;
863 
864  SDValue
865  joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
866  const SDValue *Parts, unsigned NumParts,
867  MVT PartVT, EVT ValueVT,
868  Optional<CallingConv::ID> CC) const override;
869 
870  SDValue
871  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
872  const SmallVectorImpl<ISD::InputArg> &Ins,
873  const SDLoc &dl, SelectionDAG &DAG,
874  SmallVectorImpl<SDValue> &InVals) const override;
875 
876  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
877  SDValue &Chain, const Value *OrigArg,
878  unsigned InRegsParamRecordIdx, int ArgOffset,
879  unsigned ArgSize) const;
880 
881  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
882  const SDLoc &dl, SDValue &Chain,
883  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
884  bool ForceMutable = false) const;
885 
886  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
887  SmallVectorImpl<SDValue> &InVals) const override;
888 
889  /// HandleByVal - Target-specific cleanup for ByVal support.
890  void HandleByVal(CCState *, unsigned &, Align) const override;
891 
892  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
893  /// for tail call optimization. Targets which want to do tail call
894  /// optimization should implement this function.
895  bool IsEligibleForTailCallOptimization(
896  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
897  bool isCalleeStructRet, bool isCallerStructRet,
898  const SmallVectorImpl<ISD::OutputArg> &Outs,
899  const SmallVectorImpl<SDValue> &OutVals,
900  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
901  const bool isIndirect) const;
902 
903  bool CanLowerReturn(CallingConv::ID CallConv,
904  MachineFunction &MF, bool isVarArg,
905  const SmallVectorImpl<ISD::OutputArg> &Outs,
906  LLVMContext &Context) const override;
907 
908  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
909  const SmallVectorImpl<ISD::OutputArg> &Outs,
910  const SmallVectorImpl<SDValue> &OutVals,
911  const SDLoc &dl, SelectionDAG &DAG) const override;
912 
913  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
914 
915  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
916 
917  bool shouldConsiderGEPOffsetSplit() const override { return true; }
918 
919  bool isUnsupportedFloatingType(EVT VT) const;
920 
921  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
922  SDValue ARMcc, SDValue CCR, SDValue Cmp,
923  SelectionDAG &DAG) const;
924  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
925  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
926  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
927  const SDLoc &dl, bool Signaling = false) const;
928  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
929 
930  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
931 
932  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
933  MachineBasicBlock *DispatchBB, int FI) const;
934 
935  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
936 
937  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
938 
939  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
940  MachineBasicBlock *MBB) const;
941 
942  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
943  MachineBasicBlock *MBB) const;
944  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
945  MachineBasicBlock *MBB) const;
946  void addMVEVectorTypes(bool HasMVEFP);
947  void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
948  void setAllExpand(MVT VT);
949  };
950 
956  };
957 
958  namespace ARM {
959 
960  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
961  const TargetLibraryInfo *libInfo);
962 
963  } // end namespace ARM
964 
965 } // end namespace llvm
966 
967 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
llvm::ARMTargetLowering::isLegalT1ScaledAddressingMode
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
Definition: ARMISelLowering.cpp:17672
llvm::ARMTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: ARMISelLowering.cpp:17244
llvm::ARMISD::VADDLVs
@ VADDLVs
Definition: ARMISelLowering.h:232
llvm::ARMISD::VLD3DUP_UPD
@ VLD3DUP_UPD
Definition: ARMISelLowering.h:331
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::ARMTargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: ARMISelLowering.cpp:18337
llvm::ARMTargetLowering::getRegClassFor
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
Definition: ARMISelLowering.cpp:1827
ValueTypes.h
llvm::ARMISD::VMOVN
@ VMOVN
Definition: ARMISelLowering.h:207
llvm::ARMISD::RRX
@ RRX
Definition: ARMISelLowering.h:105
llvm::ARMTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
Definition: ARMISelLowering.cpp:1812
llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: ARMISelLowering.cpp:19990
llvm::ARMISD::QSUB16b
@ QSUB16b
Definition: ARMISelLowering.h:279
llvm::ARMISD::VMLALVs
@ VMLALVs
Definition: ARMISelLowering.h:245
llvm::ARMISD::SMLAL
@ SMLAL
Definition: ARMISelLowering.h:261
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4544
llvm::ARMTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: ARMISelLowering.cpp:19405
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1290
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override
Definition: ARMISelLowering.cpp:19512
llvm::ARMISD::MEMSETLOOP
@ MEMSETLOOP
Definition: ARMISelLowering.h:308
llvm::ARMISD::BCC_i64
@ BCC_i64
Definition: ARMISelLowering.h:101
llvm::ARMTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: ARMISelLowering.cpp:17923
llvm::ARMISD::VQSHLsuIMM
@ VQSHLsuIMM
Definition: ARMISelLowering.h:163
llvm::ARMISD::VLD2_UPD
@ VLD2_UPD
Definition: ARMISelLowering.h:323
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:144
llvm::ARMISD::SMLALTT
@ SMLALTT
Definition: ARMISelLowering.h:266
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ARMISD::VMOVrh
@ VMOVrh
Definition: ARMISelLowering.h:190
llvm::ARMISD::CMP
@ CMP
Definition: ARMISelLowering.h:85
llvm::ARMISD::SMLALBB
@ SMLALBB
Definition: ARMISelLowering.h:263
llvm::VMOVModImm
@ VMOVModImm
Definition: ARMISelLowering.h:952
llvm::ARMISD::CMPZ
@ CMPZ
Definition: ARMISelLowering.h:87
llvm::ARMISD::VADDLVAu
@ VADDLVAu
Definition: ARMISelLowering.h:235
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4104
llvm::ARMTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: ARMISelLowering.cpp:12863
llvm::ARMISD::CALL_NOLINK
@ CALL_NOLINK
Definition: ARMISelLowering.h:70
llvm::ARMISD::VLD3LN_UPD
@ VLD3LN_UPD
Definition: ARMISelLowering.h:327
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::ARMTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: ARMISelLowering.cpp:19472
llvm::Function
Definition: Function.h:61
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
StringRef.h
llvm::ARMTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: ARMISelLowering.cpp:11245
llvm::ARMISD::WLS
@ WLS
Definition: ARMISelLowering.h:134
llvm::InlineAsm::Constraint_Us
@ Constraint_Us
Definition: InlineAsm.h:258
llvm::ARMTargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: ARMISelLowering.cpp:18306
llvm::ARMISD::VMOVIMM
@ VMOVIMM
Definition: ARMISelLowering.h:183
llvm::ARMISD::PRELOAD
@ PRELOAD
Definition: ARMISelLowering.h:129
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ARMISD::DYN_ALLOC
@ DYN_ALLOC
Definition: ARMISelLowering.h:125
InlineAsm.h
llvm::ARMTargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
Definition: ARMISelLowering.cpp:19621
llvm::ARMTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: ARMISelLowering.cpp:18360
llvm::ARMTargetLowering::PerformCMOVCombine
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
Definition: ARMISelLowering.cpp:16724
llvm::ARMTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: ARMISelLowering.cpp:3269
llvm::ARMISD::VIDUP
@ VIDUP
Definition: ARMISelLowering.h:219
llvm::ARM::RP
@ RP
Definition: ARMISelLowering.h:355
llvm::IRBuilder<>
llvm::ARMISD::VLD2DUP_UPD
@ VLD2DUP_UPD
Definition: ARMISelLowering.h:330
llvm::ARMTargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
Definition: ARMISelLowering.cpp:19774
llvm::ARM::rmMask
@ rmMask
Definition: ARMISelLowering.h:358
llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: ARMISelLowering.cpp:18272
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::ARMTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: ARMISelLowering.cpp:17689
llvm::ARMISD::LE
@ LE
Definition: ARMISelLowering.h:137
llvm::ARMISD::VBICIMM
@ VBICIMM
Definition: ARMISelLowering.h:294
llvm::ARMISD::VSHRsIMM
@ VSHRsIMM
Definition: ARMISelLowering.h:152
llvm::MemOp
Definition: TargetLowering.h:109
llvm::ARMISD::LDRD
@ LDRD
Definition: ARMISelLowering.h:344
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::ARMTargetLowering::alignLoopsWithOptSize
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Definition: ARMISelLowering.cpp:19554
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:19349
llvm::ARMTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2023
llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: ARMISelLowering.cpp:12852
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:375
llvm::AttributeList
Definition: Attributes.h:385
llvm::ARMISD::VQSHRNsuIMM
@ VQSHRNsuIMM
Definition: ARMISelLowering.h:166
llvm::ARMTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: ARMISelLowering.cpp:19010
llvm::ARMISD::CMPFPw0
@ CMPFPw0
Definition: ARMISelLowering.h:90
llvm::ARMISD::VDUP
@ VDUP
Definition: ARMISelLowering.h:194
llvm::ARMISD::VST1_UPD
@ VST1_UPD
Definition: ARMISelLowering.h:335
llvm::ARMISD::PIC_ADD
@ PIC_ADD
Definition: ARMISelLowering.h:79
llvm::ARMISD::FMSTAT
@ FMSTAT
Definition: ARMISelLowering.h:93
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:355
llvm::ARMTargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: ARMISelLowering.cpp:19520
llvm::ARMISD::MEMCPY
@ MEMCPY
Definition: ARMISelLowering.h:301
llvm::ARMISD::BFI
@ BFI
Definition: ARMISelLowering.h:289
llvm::ARMISD::USAT
@ USAT
Definition: ARMISelLowering.h:99
llvm::ARMTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: ARMISelLowering.cpp:1858
llvm::ARMTargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
Definition: ARMISelLowering.h:679
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ARMISD::VST4LN_UPD
@ VST4LN_UPD
Definition: ARMISelLowering.h:341
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:61
llvm::ARMISD::VZIP
@ VZIP
Definition: ARMISelLowering.h:202
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::ARMISD::WIN__CHKSTK
@ WIN__CHKSTK
Definition: ARMISelLowering.h:131
llvm::ARMISD::SSAT
@ SSAT
Definition: ARMISelLowering.h:98
llvm::ARMISD::WIN__DBZCHK
@ WIN__DBZCHK
Definition: ARMISelLowering.h:132
llvm::ARMISD::VTBL1
@ VTBL1
Definition: ARMISelLowering.h:205
llvm::ARMTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: ARMISelLowering.cpp:19241
llvm::ARMTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: ARMISelLowering.cpp:9839
llvm::ARMISD::ASRL
@ ASRL
Definition: ARMISelLowering.h:81
llvm::ARMISD::VQRSHRNsIMM
@ VQRSHRNsIMM
Definition: ARMISelLowering.h:169
llvm::ARMTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: ARMISelLowering.cpp:18498
VectorType
Definition: ItaniumDemangle.h:901
llvm::ARMISD::SERET_FLAG
@ SERET_FLAG
Definition: ARMISelLowering.h:76
llvm::ARMISD::SMLSLD
@ SMLSLD
Definition: ARMISelLowering.h:269
llvm::ARMTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: ARMISelLowering.cpp:18190
llvm::ARMISD::NodeType
NodeType
Definition: ARMISelLowering.h:55
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:193
llvm::ARMISD::VTST
@ VTST
Definition: ARMISelLowering.h:144
llvm::ARMTargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: ARMISelLowering.cpp:20066
llvm::ARMISD::VSHRuIMM
@ VSHRuIMM
Definition: ARMISelLowering.h:153
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:527
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ARMISD::VMVNIMM
@ VMVNIMM
Definition: ARMISelLowering.h:184
llvm::ARMTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Definition: ARMISelLowering.cpp:17983
llvm::ARMISD::PREDICATE_CAST
@ PREDICATE_CAST
Definition: ARMISelLowering.h:139
llvm::ARMISD::SMMLAR
@ SMMLAR
Definition: ARMISelLowering.h:271
llvm::ARMTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: ARMISelLowering.cpp:18974
llvm::ARMTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: ARMISelLowering.cpp:17122
llvm::ARMISD::UMLAL
@ UMLAL
Definition: ARMISelLowering.h:260
llvm::ARMTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: ARMISelLowering.cpp:1611
MachineValueType.h
llvm::ARMISD::WLSSETUP
@ WLSSETUP
Definition: ARMISelLowering.h:135
llvm::ARMISD::BR2_JT
@ BR2_JT
Definition: ARMISelLowering.h:74
llvm::ARMTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: ARMISelLowering.h:392
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ARMTargetLowering::PerformIntrinsicCombine
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
Definition: ARMISelLowering.cpp:15860
llvm::ARMISD::VST2LN_UPD
@ VST2LN_UPD
Definition: ARMISelLowering.h:339
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::ARMISD::QSUB8b
@ QSUB8b
Definition: ARMISelLowering.h:277
llvm::ARMTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: ARMISelLowering.cpp:19314
llvm::ARMISD::SMMLSR
@ SMMLSR
Definition: ARMISelLowering.h:272
TargetLowering.h
llvm::ARMISD::VQRSHRNsuIMM
@ VQRSHRNsuIMM
Definition: ARMISelLowering.h:171
llvm::ARMISD::VMULLs
@ VMULLs
Definition: ARMISelLowering.h:222
llvm::ARM::isBitFieldInvertedMask
bool isBitFieldInvertedMask(unsigned v)
Definition: ARMISelLowering.cpp:18979
llvm::ARMTargetLowering::shouldConvertSplatType
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Definition: ARMISelLowering.cpp:17417
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
ARMBaseInfo.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ARMISD::VMLALVAs
@ VMLALVAs
Definition: ARMISelLowering.h:249
llvm::ARMISD::LOOP_DEC
@ LOOP_DEC
Definition: ARMISelLowering.h:136
llvm::ARMISD::VMOVSR
@ VMOVSR
Definition: ARMISelLowering.h:115
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ARMISD::VQRSHRNuIMM
@ VQRSHRNuIMM
Definition: ARMISelLowering.h:170
llvm::ARMTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: ARMISelLowering.cpp:18070
llvm::ARMISD::VADDLVAs
@ VADDLVAs
Definition: ARMISelLowering.h:234
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3144
llvm::ARMTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: ARMISelLowering.cpp:19476
llvm::ARMTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: ARMISelLowering.cpp:19464
SI
@ SI
Definition: SIInstrInfo.cpp:7475
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InlineAsm::Constraint_Uy
@ Constraint_Uy
Definition: InlineAsm.h:261
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:660
llvm::ARMISD::VQSHRNuIMM
@ VQSHRNuIMM
Definition: ARMISelLowering.h:165
llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
Definition: ARMISelLowering.cpp:17127
llvm::ARMISD::SRL_FLAG
@ SRL_FLAG
Definition: ARMISelLowering.h:103
llvm::ARMISD::VREV16
@ VREV16
Definition: ARMISelLowering.h:201
llvm::ARMTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: ARMISelLowering.cpp:1559
llvm::ARMISD::VADDLVps
@ VADDLVps
Definition: ARMISelLowering.h:236
llvm::ARMISD::SMLALDX
@ SMLALDX
Definition: ARMISelLowering.h:268
llvm::ARMISD::VCMP
@ VCMP
Definition: ARMISelLowering.h:142
llvm::ARMISD::VMLALVAu
@ VMLALVAu
Definition: ARMISelLowering.h:250
llvm::Instruction
Definition: Instruction.h:45
llvm::ARMTargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: ARMISelLowering.h:662
llvm::ARMISD::VMULLu
@ VMULLu
Definition: ARMISelLowering.h:223
llvm::ARMISD::VMOVDRR
@ VMOVDRR
Definition: ARMISelLowering.h:114
llvm::ARMISD::VLD1DUP
@ VLD1DUP
Definition: ARMISelLowering.h:316
llvm::ARMISD::VQSHLuIMM
@ VQSHLuIMM
Definition: ARMISelLowering.h:162
llvm::ARM::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: ARMISelLowering.h:362
llvm::ARMISD::SUBC
@ SUBC
Definition: ARMISelLowering.h:109
llvm::ARMISD::VQMOVNu
@ VQMOVNu
Definition: ARMISelLowering.h:211
llvm::ARMISD::VMINVs
@ VMINVs
Definition: ARMISelLowering.h:254
llvm::InlineAsm::Constraint_Um
@ Constraint_Um
Definition: InlineAsm.h:255
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ARMTargetLowering::PerformCMOVToBFICombine
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
Definition: ARMISelLowering.cpp:16423
llvm::ARMISD::VST3_UPD
@ VST3_UPD
Definition: ARMISelLowering.h:337
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMISD::VLD1_UPD
@ VLD1_UPD
Definition: ARMISelLowering.h:322
llvm::ARMTargetLowering::isReadOnly
bool isReadOnly(const GlobalValue *GV) const
Definition: ARMISelLowering.cpp:3662
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMISD::SMLALD
@ SMLALD
Definition: ARMISelLowering.h:267
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARMTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: ARMISelLowering.cpp:18422
llvm::VMVNModImm
@ VMVNModImm
Definition: ARMISelLowering.h:953
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMISD::VADDLVu
@ VADDLVu
Definition: ARMISelLowering.h:233
llvm::ARMISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: ARMISelLowering.h:119
llvm::ARMTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: ARMISelLowering.cpp:12817
llvm::ARMISD::QADD8b
@ QADD8b
Definition: ARMISelLowering.h:276
llvm::ARMISD::WrapperPIC
@ WrapperPIC
Definition: ARMISelLowering.h:61
llvm::ARMTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: ARMISelLowering.cpp:16936
llvm::ARMTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: ARMISelLowering.h:601
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::ARMISD::LSRL
@ LSRL
Definition: ARMISelLowering.h:82
llvm::ARMISD::CSINC
@ CSINC
Definition: ARMISelLowering.h:313
llvm::ARMISD::CALL_PRED
@ CALL_PRED
Definition: ARMISelLowering.h:69
llvm::ARM::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: ARMFastISel.cpp:3073
llvm::ARMISD::VRSHRuIMM
@ VRSHRuIMM
Definition: ARMISelLowering.h:157
llvm::ARMISD::WrapperJT
@ WrapperJT
Definition: ARMISelLowering.h:63
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::ARMISD::VMLALVApu
@ VMLALVApu
Definition: ARMISelLowering.h:252
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ARMISD::SUBS
@ SUBS
Definition: ARMISelLowering.h:96
llvm::ARMISD::VBSP
@ VBSP
Definition: ARMISelLowering.h:297
llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: ARMISelLowering.cpp:19358
llvm::ARMISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: ARMISelLowering.h:117
llvm::APFloat
Definition: APFloat.h:701
llvm::ARMISD::VMLAVu
@ VMLAVu
Definition: ARMISelLowering.h:242
llvm::ARMISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: ARMISelLowering.h:118
llvm::ARMISD::VADDLVAps
@ VADDLVAps
Definition: ARMISelLowering.h:238
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::ARMISD::VEXT
@ VEXT
Definition: ARMISelLowering.h:198
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: ARMISelLowering.h:671
llvm::ARMISD::SMULWT
@ SMULWT
Definition: ARMISelLowering.h:259
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARMISD::LSLL
@ LSLL
Definition: ARMISelLowering.h:83
llvm::ARMISD::VLD2DUP
@ VLD2DUP
Definition: ARMISelLowering.h:317
llvm::ARMISD::MEMCPYLOOP
@ MEMCPYLOOP
Definition: ARMISelLowering.h:305
llvm::ARMTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: ARMISelLowering.cpp:17303
llvm::ARMISD::VUZP
@ VUZP
Definition: ARMISelLowering.h:203
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARMISD::CMPFPEw0
@ CMPFPEw0
Definition: ARMISelLowering.h:91
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ARMTargetLowering::shouldAlignPointerArgs
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
Definition: ARMISelLowering.cpp:1845
llvm::ARMISD::VQDMULH
@ VQDMULH
Definition: ARMISelLowering.h:225
llvm::ARMISD::VCMPZ
@ VCMPZ
Definition: ARMISelLowering.h:143
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ARMISD::RET_FLAG
@ RET_FLAG
Definition: ARMISelLowering.h:75
llvm::ARMISD::BRCOND
@ BRCOND
Definition: ARMISelLowering.h:72
llvm::ARMISD::VCVTL
@ VCVTL
Definition: ARMISelLowering.h:216
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:2766
llvm::ARMISD::VREV64
@ VREV64
Definition: ARMISelLowering.h:199
llvm::ARMISD::VLD2LN_UPD
@ VLD2LN_UPD
Definition: ARMISelLowering.h:326
llvm::ARMISD::VST4_UPD
@ VST4_UPD
Definition: ARMISelLowering.h:338
llvm::ARMISD::VMOVRRD
@ VMOVRRD
Definition: ARMISelLowering.h:113
llvm::ARMISD::COPY_STRUCT_BYVAL
@ COPY_STRUCT_BYVAL
Definition: ARMISelLowering.h:66
llvm::ARMISD::THREAD_POINTER
@ THREAD_POINTER
Definition: ARMISelLowering.h:123
llvm::ARMTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
Definition: ARMISelLowering.cpp:7953
llvm::ARMISD::STRD
@ STRD
Definition: ARMISelLowering.h:345
llvm::ARMTargetLowering::canCombineStoreAndExtract
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
Definition: ARMISelLowering.cpp:19435
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
IRBuilder.h
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ARMISD::VADDLVApu
@ VADDLVApu
Definition: ARMISelLowering.h:239
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::ARMISD::VMINVu
@ VMINVu
Definition: ARMISelLowering.h:253
llvm::ARMISD::VMLALVps
@ VMLALVps
Definition: ARMISelLowering.h:247
llvm::ARMISD::VSHLs
@ VSHLs
Definition: ARMISelLowering.h:147
llvm::ARMTargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: ARMISelLowering.cpp:1574
llvm::ARMTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: ARMISelLowering.cpp:19395
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::ARMISD::VECTOR_REG_CAST
@ VECTOR_REG_CAST
Definition: ARMISelLowering.h:140
llvm::ARMISD::VRSHRsIMM
@ VRSHRsIMM
Definition: ARMISelLowering.h:156
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::ARMISD::VADDLVpu
@ VADDLVpu
Definition: ARMISelLowering.h:237
llvm::ARM::RM
@ RM
Definition: ARMISelLowering.h:356
llvm::ARMISD::VST3LN_UPD
@ VST3LN_UPD
Definition: ARMISelLowering.h:340
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::ARMISD::VMOVFPIMM
@ VMOVFPIMM
Definition: ARMISelLowering.h:187
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::ARM::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
Definition: ARMISelLowering.h:353
llvm::ARMISD::VLD4_UPD
@ VLD4_UPD
Definition: ARMISelLowering.h:325
llvm::ARMISD::VADDVs
@ VADDVs
Definition: ARMISelLowering.h:228
llvm::ARMISD::VTBL2
@ VTBL2
Definition: ARMISelLowering.h:206
llvm::ARMISD::QADD16b
@ QADD16b
Definition: ARMISelLowering.h:278
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMISD::VREV32
@ VREV32
Definition: ARMISelLowering.h:200
llvm::ARMISD::VLD3_UPD
@ VLD3_UPD
Definition: ARMISelLowering.h:324
llvm::ARMISD::VSRIIMM
@ VSRIIMM
Definition: ARMISelLowering.h:175
llvm::ARMISD::VADDVu
@ VADDVu
Definition: ARMISelLowering.h:229
llvm::ARMTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: ARMISelLowering.cpp:19421
llvm::ArrayRef< int >
RegInfo
Definition: AMDGPUAsmParser.cpp:2362
llvm::ARMISD::VGETLANEu
@ VGETLANEu
Definition: ARMISelLowering.h:179
llvm::ARMISD::VMLAVps
@ VMLAVps
Definition: ARMISelLowering.h:243
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::ARMISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: ARMISelLowering.h:57
llvm::ARMISD::VADDVps
@ VADDVps
Definition: ARMISelLowering.h:230
llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:19380
llvm::ARMTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: ARMISelLowering.cpp:19468
llvm::ARMTargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: ARMISelLowering.cpp:17430
llvm::ARMISD::BUILD_VECTOR
@ BUILD_VECTOR
Definition: ARMISelLowering.h:286
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::ARMISD::VLD1DUP_UPD
@ VLD1DUP_UPD
Definition: ARMISelLowering.h:329
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: ARMISelLowering.cpp:17199
llvm::ARMISD::VMOVhr
@ VMOVhr
Definition: ARMISelLowering.h:191
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMISD::CMPFPE
@ CMPFPE
Definition: ARMISelLowering.h:89
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
Node
Definition: ItaniumDemangle.h:114
llvm::ARMISD::VRSHRNIMM
@ VRSHRNIMM
Definition: ARMISelLowering.h:158
llvm::ARMISD::VST2_UPD
@ VST2_UPD
Definition: ARMISelLowering.h:336
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::ARMISD::SMLSLDX
@ SMLSLDX
Definition: ARMISelLowering.h:270
llvm::OtherModImm
@ OtherModImm
Definition: ARMISelLowering.h:955
llvm::ARMISD::VMLAVs
@ VMLAVs
Definition: ARMISelLowering.h:240
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
llvm::ARMTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: ARMISelLowering.cpp:17227
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMISD::VSLIIMM
@ VSLIIMM
Definition: ARMISelLowering.h:174
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMISD::CSNEG
@ CSNEG
Definition: ARMISelLowering.h:312
Attributes.h
llvm::ARMTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: ARMISelLowering.cpp:18390
llvm::ARMISD::VMLALVAps
@ VMLALVAps
Definition: ARMISelLowering.h:251
llvm::ARMISD::VSHLIMM
@ VSHLIMM
Definition: ARMISelLowering.h:151
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::ARMTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: ARMISelLowering.cpp:17755
llvm::ARMISD::SMULWB
@ SMULWB
Definition: ARMISelLowering.h:258
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1688
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::ARMISD::VGETLANEs
@ VGETLANEs
Definition: ARMISelLowering.h:180
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:247
llvm::ARMISD::SRA_FLAG
@ SRA_FLAG
Definition: ARMISelLowering.h:104
CallingConvLower.h
llvm::ARMISD::VMAXVu
@ VMAXVu
Definition: ARMISelLowering.h:255
llvm::InlineAsm::Constraint_Uv
@ Constraint_Uv
Definition: InlineAsm.h:260
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::InlineAsm::Constraint_Un
@ Constraint_Un
Definition: InlineAsm.h:256
llvm::ARMISD::VQMOVNs
@ VQMOVNs
Definition: ARMISelLowering.h:210
llvm::ARMISD::VLD4DUP_UPD
@ VLD4DUP_UPD
Definition: ARMISelLowering.h:332
llvm::ARMTargetLowering::getSubtarget
const ARMSubtarget * getSubtarget() const
Definition: ARMISelLowering.h:557
llvm::ARMISD::VADDVpu
@ VADDVpu
Definition: ARMISelLowering.h:231
llvm::ARMTargetLowering::PerformBRCONDCombine
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
Definition: ARMISelLowering.cpp:16684
llvm::ARM::RZ
@ RZ
Definition: ARMISelLowering.h:357
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4113
llvm::ARMISD::VMLALVu
@ VMLALVu
Definition: ARMISelLowering.h:246
ISDOpcodes.h
llvm::ARMISD::UMAAL
@ UMAAL
Definition: ARMISelLowering.h:262
Function.h
llvm::ARMISD::VDUPLANE
@ VDUPLANE
Definition: ARMISelLowering.h:195
llvm::ARMISD::tSECALL
@ tSECALL
Definition: ARMISelLowering.h:71
llvm::ARMISD::CMN
@ CMN
Definition: ARMISelLowering.h:86
llvm::ARMISD::VMLALVpu
@ VMLALVpu
Definition: ARMISelLowering.h:248
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:208
llvm::ARMISD::INTRET_FLAG
@ INTRET_FLAG
Definition: ARMISelLowering.h:77
llvm::ARMTargetLowering::makeDMB
Instruction * makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const
Definition: ARMISelLowering.cpp:19259
llvm::ARMISD::ADDE
@ ADDE
Definition: ARMISelLowering.h:108
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::InlineAsm::Constraint_Uq
@ Constraint_Uq
Definition: InlineAsm.h:257
llvm::ARMTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: ARMISelLowering.cpp:17460
llvm::ARMISD::CSINV
@ CSINV
Definition: ARMISelLowering.h:311
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:827
llvm::ARMISD::VQSHRNsIMM
@ VQSHRNsIMM
Definition: ARMISelLowering.h:164
llvm::ARMTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: ARMISelLowering.cpp:18991
CodeGen.h
llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
Definition: ARMISelLowering.cpp:19336
llvm::ARMISD::VQSHLsIMM
@ VQSHLsIMM
Definition: ARMISelLowering.h:161
llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: ARMISelLowering.cpp:19602
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:1986
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
SmallVector.h
llvm::ARMISD::VLD4DUP
@ VLD4DUP
Definition: ARMISelLowering.h:319
llvm::ARMISD::VCVTN
@ VCVTN
Definition: ARMISelLowering.h:214
llvm::TargetLoweringBase::ScalarCondVectorVal
@ ScalarCondVectorVal
Definition: TargetLowering.h:237
llvm::ARMTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: ARMISelLowering.cpp:19251
llvm::ARMTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: ARMISelLowering.cpp:11654
llvm::ARMTargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: ARMISelLowering.cpp:19428
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1247
llvm::ARMTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2028
N
#define N
llvm::ARMTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: ARMISelLowering.h:675
llvm::ARMISD::MEMBARRIER_MCR
@ MEMBARRIER_MCR
Definition: ARMISelLowering.h:127
llvm::ARMISD::VMLAVpu
@ VMLAVpu
Definition: ARMISelLowering.h:244
llvm::ARMTargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: ARMISelLowering.cpp:19561
llvm::ARMTargetLowering::isFNegFree
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition: ARMISelLowering.cpp:17265
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4205
llvm::ARMISD::CMPFP
@ CMPFP
Definition: ARMISelLowering.h:88
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::ARMISD::VLD3DUP
@ VLD3DUP
Definition: ARMISelLowering.h:318
llvm::ARMTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: ARMISelLowering.cpp:20005
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::ARMISD::TC_RETURN
@ TC_RETURN
Definition: ARMISelLowering.h:121
RegName
#define RegName(no)
llvm::ARMTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: ARMISelLowering.h:529
llvm::ARM_MB::MemBOpt
MemBOpt
Definition: ARMBaseInfo.h:58
llvm::InlineAsm::Constraint_Ut
@ Constraint_Ut
Definition: InlineAsm.h:259
llvm::ARMISD::VSHLu
@ VSHLu
Definition: ARMISelLowering.h:148
llvm::ARMTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: ARMISelLowering.cpp:9983
llvm::ARMISD::Wrapper
@ Wrapper
Definition: ARMISelLowering.h:59
llvm::ARMISD::SMLALBT
@ SMLALBT
Definition: ARMISelLowering.h:264
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::ARMTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: ARMISelLowering.cpp:17771
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MVEVMVNModImm
@ MVEVMVNModImm
Definition: ARMISelLowering.h:954
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::ARMISD::SUBE
@ SUBE
Definition: ARMISelLowering.h:110
llvm::ARMISD::CMOV
@ CMOV
Definition: ARMISelLowering.h:95
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:97
llvm::ARMTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
Definition: ARMISelLowering.cpp:19976
llvm::ARMTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: ARMISelLowering.cpp:19289
llvm::ARMISD::BR_JT
@ BR_JT
Definition: ARMISelLowering.h:73
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
MachineFunction.h
model
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from where P can be anything The alignment inference code cannot handle loads from globals in static non mode because it doesn t look through the extra dyld stub load If you try vec_align ll without relocation model
Definition: README-SSE.txt:414
llvm::ARMISD::CALL
@ CALL
Definition: ARMISelLowering.h:68
llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Definition: ARMISelLowering.cpp:17634
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:61
llvm::ARMTargetLowering::ARMTargetLowering
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
Definition: ARMISelLowering.cpp:455
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::ARMISD::ADDC
@ ADDC
Definition: ARMISelLowering.h:107
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMISD::SMLALTB
@ SMLALTB
Definition: ARMISelLowering.h:265
llvm::ARMISD::VLD4LN_UPD
@ VLD4LN_UPD
Definition: ARMISelLowering.h:328
llvm::ARMTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: ARMISelLowering.cpp:19401
llvm::ARMTargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
Definition: ARMISelLowering.cpp:17474
llvm::ARM::RN
@ RN
Definition: ARMISelLowering.h:354
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:235
llvm::VMOVModImmType
VMOVModImmType
Definition: ARMISelLowering.h:951
llvm::ARMISD::VORRIMM
@ VORRIMM
Definition: ARMISelLowering.h:292
llvm::ARMISD::VMAXVs
@ VMAXVs
Definition: ARMISelLowering.h:256
llvm::ARMTargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Definition: ARMISelLowering.cpp:19566
llvm::ARMISD::VTRN
@ VTRN
Definition: ARMISelLowering.h:204
llvm::ARMTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: ARMISelLowering.cpp:20012
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::ARMISD::LSLS
@ LSLS
Definition: ARMISelLowering.h:111