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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <utility>
34 
35 namespace llvm {
36 
37 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
42 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
51 
52  namespace ARMISD {
53 
54  // ARM Specific DAG Nodes
55  enum NodeType : unsigned {
56  // Start the numbering where the builtin ops and target ops leave off.
58 
59  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
60  // TargetExternalSymbol, and TargetGlobalAddress.
61  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
62  // PIC mode.
63  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
64 
65  // Add pseudo op to model memcpy for struct byval.
67 
68  CALL, // Function call.
69  CALL_PRED, // Function call that's predicable.
70  CALL_NOLINK, // Function call with branch not branch-and-link.
71  tSECALL, // CMSE non-secure function call.
72  BRCOND, // Conditional branch.
73  BR_JT, // Jumptable branch.
74  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75  RET_FLAG, // Return with a flag operand.
76  SERET_FLAG, // CMSE Entry function return with a flag operand.
77  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
78 
79  PIC_ADD, // Add with a PC operand and a PIC label.
80 
81  ASRL, // MVE long arithmetic shift right.
82  LSRL, // MVE long shift right.
83  LSLL, // MVE long shift left.
84 
85  CMP, // ARM compare instructions.
86  CMN, // ARM CMN instructions.
87  CMPZ, // ARM compare that sets only Z flag.
88  CMPFP, // ARM VFP compare instruction, sets FPSCR.
89  CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
90  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
91  CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
92  // FPSCR.
93  FMSTAT, // ARM fmstat instruction.
94 
95  CMOV, // ARM conditional move instructions.
96  SUBS, // Flag-setting subtraction.
97 
98  SSAT, // Signed saturation
99  USAT, // Unsigned saturation
100 
102 
103  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
104  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
105  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
106 
107  ADDC, // Add with carry
108  ADDE, // Add using carry
109  SUBC, // Sub with carry
110  SUBE, // Sub using carry
111  LSLS, // Shift left producing carry
112 
113  VMOVRRD, // double to two gprs.
114  VMOVDRR, // Two gprs to double.
115  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
116 
117  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
118  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
119  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
120 
121  TC_RETURN, // Tail call return pseudo.
122 
124 
125  DYN_ALLOC, // Dynamic allocation on the stack.
126 
127  MEMBARRIER_MCR, // Memory barrier (MCR)
128 
129  PRELOAD, // Preload
130 
131  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
132  WIN__DBZCHK, // Windows' divide by zero check
133 
134  WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
135  WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
136  LOOP_DEC, // Really a part of LE, performs the sub
137  LE, // Low-overhead loops, Loop End
138 
139  PREDICATE_CAST, // Predicate cast for MVE i1 types
140  VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
141 
142  MVESEXT, // Legalization aids for extending a vector into two/four vectors.
143  MVEZEXT, // or truncating two/four vectors into one. Eventually becomes
144  MVETRUNC, // stack store/load sequence, if not optimized to anything else.
145 
146  VCMP, // Vector compare.
147  VCMPZ, // Vector compare to zero.
148  VTST, // Vector test bits.
149 
150  // Vector shift by vector
151  VSHLs, // ...left/right by signed
152  VSHLu, // ...left/right by unsigned
153 
154  // Vector shift by immediate:
155  VSHLIMM, // ...left
156  VSHRsIMM, // ...right (signed)
157  VSHRuIMM, // ...right (unsigned)
158 
159  // Vector rounding shift by immediate:
160  VRSHRsIMM, // ...right (signed)
161  VRSHRuIMM, // ...right (unsigned)
162  VRSHRNIMM, // ...right narrow
163 
164  // Vector saturating shift by immediate:
165  VQSHLsIMM, // ...left (signed)
166  VQSHLuIMM, // ...left (unsigned)
167  VQSHLsuIMM, // ...left (signed to unsigned)
168  VQSHRNsIMM, // ...right narrow (signed)
169  VQSHRNuIMM, // ...right narrow (unsigned)
170  VQSHRNsuIMM, // ...right narrow (signed to unsigned)
171 
172  // Vector saturating rounding shift by immediate:
173  VQRSHRNsIMM, // ...right narrow (signed)
174  VQRSHRNuIMM, // ...right narrow (unsigned)
175  VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
176 
177  // Vector shift and insert:
178  VSLIIMM, // ...left
179  VSRIIMM, // ...right
180 
181  // Vector get lane (VMOV scalar to ARM core register)
182  // (These are used for 8- and 16-bit element types only.)
183  VGETLANEu, // zero-extend vector extract element
184  VGETLANEs, // sign-extend vector extract element
185 
186  // Vector move immediate and move negated immediate:
189 
190  // Vector move f32 immediate:
192 
193  // Move H <-> R, clearing top 16 bits
196 
197  // Vector duplicate:
200 
201  // Vector shuffles:
202  VEXT, // extract
203  VREV64, // reverse elements within 64-bit doublewords
204  VREV32, // reverse elements within 32-bit words
205  VREV16, // reverse elements within 16-bit halfwords
206  VZIP, // zip (interleave)
207  VUZP, // unzip (deinterleave)
208  VTRN, // transpose
209  VTBL1, // 1-register shuffle with mask
210  VTBL2, // 2-register shuffle with mask
211  VMOVN, // MVE vmovn
212 
213  // MVE Saturating truncates
214  VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
215  VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
216 
217  // MVE float <> half converts
218  VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
219  // lanes
220  VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
221 
222  // MVE VIDUP instruction, taking a start value and increment.
224 
225  // Vector multiply long:
226  VMULLs, // ...signed
227  VMULLu, // ...unsigned
228 
229  VQDMULH, // MVE vqdmulh instruction
230 
231  // MVE reductions
232  VADDVs, // sign- or zero-extend the elements of a vector to i32,
233  VADDVu, // add them all together, and return an i32 of their sum
234  VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
236  VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
237  VADDLVu, // the low and high 32-bit halves of the sum
238  VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
239  VADDLVAu, // provided as low and high halves
240  VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
242  VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
244  VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
245  // them
246  VMLAVu, // and add the results together, returning an i32 of their sum
247  VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
249  VMLALVs, // Same as VMLAV but with i64, returning the low and
250  VMLALVu, // high 32-bit halves of the sum
251  VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
253  VMLALVAs, // Same as VMLALV but also add an input accumulator
254  VMLALVAu, // provided as low and high halves
255  VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
257  VMINVu, // Find minimum unsigned value of a vector and register
258  VMINVs, // Find minimum signed value of a vector and register
259  VMAXVu, // Find maximum unsigned value of a vector and register
260  VMAXVs, // Find maximum signed value of a vector and register
261 
262  SMULWB, // Signed multiply word by half word, bottom
263  SMULWT, // Signed multiply word by half word, top
264  UMLAL, // 64bit Unsigned Accumulate Multiply
265  SMLAL, // 64bit Signed Accumulate Multiply
266  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
267  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
268  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
269  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
270  SMLALTT, // 64-bit signed accumulate multiply top, top 16
271  SMLALD, // Signed multiply accumulate long dual
272  SMLALDX, // Signed multiply accumulate long dual exchange
273  SMLSLD, // Signed multiply subtract long dual
274  SMLSLDX, // Signed multiply subtract long dual exchange
275  SMMLAR, // Signed multiply long, round and add
276  SMMLSR, // Signed multiply long, subtract and round
277 
278  // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
279  // stands for.
288 
289  // Operands of the standard BUILD_VECTOR node are not legalized, which
290  // is fine if BUILD_VECTORs are always lowered to shuffles or other
291  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
292  // operands need to be legalized. Define an ARM-specific version of
293  // BUILD_VECTOR for this purpose.
295 
296  // Bit-field insert
298 
299  // Vector OR with immediate
301  // Vector AND with NOT of immediate
303 
304  // Pseudo vector bitwise select
306 
307  // Pseudo-instruction representing a memory copy using ldm/stm
308  // instructions.
310 
311  // Pseudo-instruction representing a memory copy using a tail predicated
312  // loop
314  // Pseudo-instruction representing a memset using a tail predicated
315  // loop
317 
318  // V8.1MMainline condition select
319  CSINV, // Conditional select invert.
320  CSNEG, // Conditional select negate.
321  CSINC, // Conditional select increment.
322 
323  // Vector load N-element structure to all lanes:
328 
329  // NEON loads with post-increment base updates:
344 
345  // NEON stores with post-increment base updates:
356 
357  // Load/Store of dual registers
360  };
361 
362  } // end namespace ARMISD
363 
364  namespace ARM {
365  /// Possible values of current rounding mode, which is specified in bits
366  /// 23:22 of FPSCR.
367  enum Rounding {
368  RN = 0, // Round to Nearest
369  RP = 1, // Round towards Plus infinity
370  RM = 2, // Round towards Minus infinity
371  RZ = 3, // Round towards Zero
372  rmMask = 3 // Bit mask selecting rounding mode
373  };
374 
375  // Bit position of rounding mode bits in FPSCR.
376  const unsigned RoundingBitsPos = 22;
377  } // namespace ARM
378 
379  /// Define some predicates that are used for node matching.
380  namespace ARM {
381 
382  bool isBitFieldInvertedMask(unsigned v);
383 
384  } // end namespace ARM
385 
386  //===--------------------------------------------------------------------===//
387  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
388 
390  public:
391  explicit ARMTargetLowering(const TargetMachine &TM,
392  const ARMSubtarget &STI);
393 
394  unsigned getJumpTableEncoding() const override;
395  bool useSoftFloat() const override;
396 
397  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
398 
399  /// ReplaceNodeResults - Replace the results of node with an illegal result
400  /// type with new values built out of custom code.
402  SelectionDAG &DAG) const override;
403 
404  const char *getTargetNodeName(unsigned Opcode) const override;
405 
406  bool isSelectSupported(SelectSupportKind Kind) const override {
407  // ARM does not support scalar condition selects on vectors.
408  return (Kind != ScalarCondVectorVal);
409  }
410 
411  bool isReadOnly(const GlobalValue *GV) const;
412 
413  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
415  EVT VT) const override;
416 
419  MachineBasicBlock *MBB) const override;
420 
422  SDNode *Node) const override;
423 
427  SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
428  SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
429  SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
430  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
431 
433  const APInt &OriginalDemandedBits,
434  const APInt &OriginalDemandedElts,
435  KnownBits &Known,
436  TargetLoweringOpt &TLO,
437  unsigned Depth) const override;
438 
439  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
440 
441  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
442  /// unaligned memory accesses of the specified type. Returns whether it
443  /// is "fast" by reference in the second argument.
444  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
445  Align Alignment,
447  bool *Fast) const override;
448 
450  const AttributeList &FuncAttributes) const override;
451 
452  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
453  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
454  bool isZExtFree(SDValue Val, EVT VT2) const override;
456  SmallVectorImpl<Use *> &Ops) const override;
457  Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
458 
459  bool isFNegFree(EVT VT) const override;
460 
461  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
462 
463  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
464 
465 
466  /// isLegalAddressingMode - Return true if the addressing mode represented
467  /// by AM is legal for this target, for a load/store of the specified type.
468  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
469  Type *Ty, unsigned AS,
470  Instruction *I = nullptr) const override;
471 
472  /// getScalingFactorCost - Return the cost of the scaling used in
473  /// addressing mode represented by AM.
474  /// If the AM is supported, the return value must be >= 0.
475  /// If the AM is not supported, the return value must be negative.
477  const AddrMode &AM, Type *Ty,
478  unsigned AS) const override;
479 
480  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
481 
482  /// Returns true if the addressing mode representing by AM is legal
483  /// for the Thumb1 target, for a load/store of the specified type.
484  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
485 
486  /// isLegalICmpImmediate - Return true if the specified immediate is legal
487  /// icmp immediate, that is the target has icmp instructions which can
488  /// compare a register against the immediate without having to materialize
489  /// the immediate into a register.
490  bool isLegalICmpImmediate(int64_t Imm) const override;
491 
492  /// isLegalAddImmediate - Return true if the specified immediate is legal
493  /// add immediate, that is the target has add instructions which can
494  /// add a register and the immediate without having to materialize
495  /// the immediate into a register.
496  bool isLegalAddImmediate(int64_t Imm) const override;
497 
498  /// getPreIndexedAddressParts - returns true by value, base pointer and
499  /// offset pointer and addressing mode by reference if the node's address
500  /// can be legally represented as pre-indexed load / store address.
503  SelectionDAG &DAG) const override;
504 
505  /// getPostIndexedAddressParts - returns true by value, base pointer and
506  /// offset pointer and addressing mode by reference if this node can be
507  /// combined with a load / store to form a post-indexed load / store.
510  SelectionDAG &DAG) const override;
511 
513  const APInt &DemandedElts,
514  const SelectionDAG &DAG,
515  unsigned Depth) const override;
516 
518  const APInt &DemandedElts,
519  TargetLoweringOpt &TLO) const override;
520 
521  bool ExpandInlineAsm(CallInst *CI) const override;
522 
523  ConstraintType getConstraintType(StringRef Constraint) const override;
524 
525  /// Examine constraint string and operand type and determine a weight value.
526  /// The operand object must already have been set up with the operand type.
528  AsmOperandInfo &info, const char *constraint) const override;
529 
530  std::pair<unsigned, const TargetRegisterClass *>
532  StringRef Constraint, MVT VT) const override;
533 
534  const char *LowerXConstraint(EVT ConstraintVT) const override;
535 
536  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
537  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
538  /// true it means one of the asm constraint of the inline asm instruction
539  /// being processed is 'm'.
540  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
541  std::vector<SDValue> &Ops,
542  SelectionDAG &DAG) const override;
543 
544  unsigned
545  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
546  if (ConstraintCode == "Q")
548  else if (ConstraintCode.size() == 2) {
549  if (ConstraintCode[0] == 'U') {
550  switch(ConstraintCode[1]) {
551  default:
552  break;
553  case 'm':
555  case 'n':
557  case 'q':
559  case 's':
561  case 't':
563  case 'v':
565  case 'y':
567  }
568  }
569  }
570  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
571  }
572 
573  const ARMSubtarget* getSubtarget() const {
574  return Subtarget;
575  }
576 
577  /// getRegClassFor - Return the register class that should be used for the
578  /// specified value type.
579  const TargetRegisterClass *
580  getRegClassFor(MVT VT, bool isDivergent = false) const override;
581 
582  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
583  unsigned &PrefAlign) const override;
584 
585  /// createFastISel - This method returns a target specific FastISel object,
586  /// or null if the target does not support "fast" ISel.
588  const TargetLibraryInfo *libInfo) const override;
589 
591 
592  bool preferZeroCompareBranch() const override { return true; }
593 
594  bool
595  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
596  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
597 
598  /// isFPImmLegal - Returns true if the target can instruction select the
599  /// specified FP immediate natively. If false, the legalizer will
600  /// materialize the FP immediate as a load from a constant pool.
601  bool isFPImmLegal(const APFloat &Imm, EVT VT,
602  bool ForCodeSize = false) const override;
603 
604  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
605  const CallInst &I,
606  MachineFunction &MF,
607  unsigned Intrinsic) const override;
608 
609  /// Returns true if it is beneficial to convert a load of a constant
610  /// to just the constant itself.
612  Type *Ty) const override;
613 
614  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
615  /// with this index.
616  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
617  unsigned Index) const override;
618 
619  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
620  bool MathUsed) const override {
621  // Using overflow ops for overflow checks only should beneficial on ARM.
622  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
623  }
624 
625  /// Returns true if an argument of type Ty needs to be passed in a
626  /// contiguous block of registers in calling convention CallConv.
628  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
629  const DataLayout &DL) const override;
630 
631  /// If a physical register, this returns the register that receives the
632  /// exception address on entry to an EH pad.
633  Register
634  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
635 
636  /// If a physical register, this returns the register that receives the
637  /// exception typeid on entry to a landing pad.
638  Register
639  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
640 
643  AtomicOrdering Ord) const override;
645  AtomicOrdering Ord) const override;
646 
647  void
649 
651  AtomicOrdering Ord) const override;
653  AtomicOrdering Ord) const override;
654 
655  unsigned getMaxSupportedInterleaveFactor() const override;
656 
659  ArrayRef<unsigned> Indices,
660  unsigned Factor) const override;
662  unsigned Factor) const override;
663 
664  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
666  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
667  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
669  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
672 
673  bool useLoadStackGuardNode() const override;
674 
675  void insertSSPDeclarations(Module &M) const override;
676  Value *getSDagStackGuard(const Module &M) const override;
677  Function *getSSPStackGuardCheck(const Module &M) const override;
678 
679  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
680  unsigned &Cost) const override;
681 
682  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
683  const MachineFunction &MF) const override {
684  // Do not merge to larger than i32.
685  return (MemVT.getSizeInBits() <= 32);
686  }
687 
688  bool isCheapToSpeculateCttz() const override;
689  bool isCheapToSpeculateCtlz() const override;
690 
691  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
692  return VT.isScalarInteger();
693  }
694 
695  bool supportSwiftError() const override {
696  return true;
697  }
698 
699  bool hasStandaloneRem(EVT VT) const override {
700  return HasStandaloneRem;
701  }
702 
703  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
704 
705  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
706  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
707 
708  /// Returns true if \p VecTy is a legal interleaved access type. This
709  /// function checks the vector element type and the overall width of the
710  /// vector.
711  bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
712  Align Alignment,
713  const DataLayout &DL) const;
714 
715  bool isMulAddWithConstProfitable(const SDValue &AddNode,
716  const SDValue &ConstNode) const override;
717 
718  bool alignLoopsWithOptSize() const override;
719 
720  /// Returns the number of interleaved accesses that will be generated when
721  /// lowering accesses of the given type.
722  unsigned getNumInterleavedAccesses(VectorType *VecTy,
723  const DataLayout &DL) const;
724 
725  void finalizeLowering(MachineFunction &MF) const override;
726 
727  /// Return the correct alignment for the current calling convention.
729  const DataLayout &DL) const override;
730 
732  CombineLevel Level) const override;
733 
735  CombineLevel Level) const override;
736 
737  bool preferIncOfAddToSubOfNot(EVT VT) const override;
738 
739  protected:
740  std::pair<const TargetRegisterClass *, uint8_t>
742  MVT VT) const override;
743 
744  private:
745  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
746  /// make the right decision when generating code for different targets.
747  const ARMSubtarget *Subtarget;
748 
750 
751  const InstrItineraryData *Itins;
752 
753  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
754  unsigned ARMPCLabelIndex;
755 
756  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
757  // check.
758  bool InsertFencesForAtomic;
759 
760  bool HasStandaloneRem = true;
761 
762  void addTypeForNEON(MVT VT, MVT PromotedLdStVT);
763  void addDRTypeForNEON(MVT VT);
764  void addQRTypeForNEON(MVT VT);
765  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
766 
767  using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
768 
769  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
770  SDValue &Arg, RegsToPassVector &RegsToPass,
771  CCValAssign &VA, CCValAssign &NextVA,
772  SDValue &StackPtr,
773  SmallVectorImpl<SDValue> &MemOpChains,
774  bool IsTailCall,
775  int SPDiff) const;
776  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
777  SDValue &Root, SelectionDAG &DAG,
778  const SDLoc &dl) const;
779 
780  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
781  bool isVarArg) const;
782  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
783  bool isVarArg) const;
784  std::pair<SDValue, MachinePointerInfo>
785  computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG,
786  const CCValAssign &VA, SDValue StackPtr,
787  bool IsTailCall, int SPDiff) const;
788  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
789  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
790  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
791  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
792  const ARMSubtarget *Subtarget) const;
793  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
794  const ARMSubtarget *Subtarget) const;
795  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
796  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
797  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
798  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
799  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
800  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
801  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
802  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
803  SelectionDAG &DAG) const;
804  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
805  SelectionDAG &DAG,
806  TLSModel::Model model) const;
807  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
808  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
809  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
810  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
811  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
812  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
813  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
814  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
815  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
816  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
817  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
818  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
819  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
820  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
821  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
822  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
823  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
824  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
825  const ARMSubtarget *ST) const;
826  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
827  const ARMSubtarget *ST) const;
828  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
829  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
830  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
831  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
832  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
834  SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
835  const ARMSubtarget *Subtarget) const;
836  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
837  SDValue &Chain) const;
838  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
839  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
840  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
841  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
842  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
843  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
844  SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
845  void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
846  SelectionDAG &DAG) const;
847  void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
848  SelectionDAG &DAG) const;
849 
850  Register getRegisterByName(const char* RegName, LLT VT,
851  const MachineFunction &MF) const override;
852 
853  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
854  SmallVectorImpl<SDNode *> &Created) const override;
855 
856  bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
857  EVT VT) const override;
858 
859  SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
860  SDValue Val) const;
861  SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
862  MVT ValVT, SDValue Val) const;
863 
864  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
865 
866  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
867  CallingConv::ID CallConv, bool isVarArg,
869  const SDLoc &dl, SelectionDAG &DAG,
870  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
871  SDValue ThisVal) const;
872 
873  bool supportSplitCSR(MachineFunction *MF) const override {
875  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
876  }
877 
878  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
879  void insertCopiesSplitCSR(
880  MachineBasicBlock *Entry,
881  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
882 
883  bool
884  splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
885  SDValue *Parts, unsigned NumParts, MVT PartVT,
886  Optional<CallingConv::ID> CC) const override;
887 
888  SDValue
889  joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
890  const SDValue *Parts, unsigned NumParts,
891  MVT PartVT, EVT ValueVT,
892  Optional<CallingConv::ID> CC) const override;
893 
894  SDValue
895  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
896  const SmallVectorImpl<ISD::InputArg> &Ins,
897  const SDLoc &dl, SelectionDAG &DAG,
898  SmallVectorImpl<SDValue> &InVals) const override;
899 
900  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
901  SDValue &Chain, const Value *OrigArg,
902  unsigned InRegsParamRecordIdx, int ArgOffset,
903  unsigned ArgSize) const;
904 
905  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
906  const SDLoc &dl, SDValue &Chain,
907  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
908  bool ForceMutable = false) const;
909 
910  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
911  SmallVectorImpl<SDValue> &InVals) const override;
912 
913  /// HandleByVal - Target-specific cleanup for ByVal support.
914  void HandleByVal(CCState *, unsigned &, Align) const override;
915 
916  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
917  /// for tail call optimization. Targets which want to do tail call
918  /// optimization should implement this function.
919  bool IsEligibleForTailCallOptimization(
920  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
921  bool isCalleeStructRet, bool isCallerStructRet,
922  const SmallVectorImpl<ISD::OutputArg> &Outs,
923  const SmallVectorImpl<SDValue> &OutVals,
924  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
925  const bool isIndirect) const;
926 
927  bool CanLowerReturn(CallingConv::ID CallConv,
928  MachineFunction &MF, bool isVarArg,
929  const SmallVectorImpl<ISD::OutputArg> &Outs,
930  LLVMContext &Context) const override;
931 
932  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
933  const SmallVectorImpl<ISD::OutputArg> &Outs,
934  const SmallVectorImpl<SDValue> &OutVals,
935  const SDLoc &dl, SelectionDAG &DAG) const override;
936 
937  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
938 
939  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
940 
941  bool shouldConsiderGEPOffsetSplit() const override { return true; }
942 
943  bool isUnsupportedFloatingType(EVT VT) const;
944 
945  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
946  SDValue ARMcc, SDValue CCR, SDValue Cmp,
947  SelectionDAG &DAG) const;
948  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
949  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
950  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
951  const SDLoc &dl, bool Signaling = false) const;
952  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
953 
954  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
955 
956  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
957  MachineBasicBlock *DispatchBB, int FI) const;
958 
959  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
960 
961  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
962 
963  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
964  MachineBasicBlock *MBB) const;
965 
966  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
967  MachineBasicBlock *MBB) const;
968  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
969  MachineBasicBlock *MBB) const;
970  void addMVEVectorTypes(bool HasMVEFP);
971  void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
972  void setAllExpand(MVT VT);
973  };
974 
980  };
981 
982  namespace ARM {
983 
984  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
985  const TargetLibraryInfo *libInfo);
986 
987  } // end namespace ARM
988 
989 } // end namespace llvm
990 
991 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
llvm::ARMTargetLowering::isLegalT1ScaledAddressingMode
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
Definition: ARMISelLowering.cpp:18688
llvm::ARMTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: ARMISelLowering.cpp:18260
llvm::ARMISD::VADDLVs
@ VADDLVs
Definition: ARMISelLowering.h:236
llvm::ARMISD::VLD3DUP_UPD
@ VLD3DUP_UPD
Definition: ARMISelLowering.h:339
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::ARMTargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: ARMISelLowering.cpp:19380
llvm::ARMTargetLowering::getRegClassFor
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
Definition: ARMISelLowering.cpp:1861
ValueTypes.h
llvm::ARMISD::VMOVN
@ VMOVN
Definition: ARMISelLowering.h:211
llvm::ARMISD::RRX
@ RRX
Definition: ARMISelLowering.h:105
llvm::ARMTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
Definition: ARMISelLowering.cpp:1845
llvm::ARMISD::QSUB16b
@ QSUB16b
Definition: ARMISelLowering.h:283
llvm::ARMISD::VMLALVs
@ VMLALVs
Definition: ARMISelLowering.h:249
llvm::ARMISD::SMLAL
@ SMLAL
Definition: ARMISelLowering.h:265
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4636
llvm::ARMTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: ARMISelLowering.cpp:20448
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1304
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ARMISD::MEMSETLOOP
@ MEMSETLOOP
Definition: ARMISelLowering.h:316
llvm::ARMISD::BCC_i64
@ BCC_i64
Definition: ARMISelLowering.h:101
llvm::ARMTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: ARMISelLowering.cpp:18964
llvm::ARMISD::VQSHLsuIMM
@ VQSHLsuIMM
Definition: ARMISelLowering.h:167
llvm::ARMISD::VLD2_UPD
@ VLD2_UPD
Definition: ARMISelLowering.h:331
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::ARMISD::SMLALTT
@ SMLALTT
Definition: ARMISelLowering.h:270
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ARMISD::VMOVrh
@ VMOVrh
Definition: ARMISelLowering.h:194
llvm::ARMISD::CMP
@ CMP
Definition: ARMISelLowering.h:85
llvm::ARMISD::SMLALBB
@ SMLALBB
Definition: ARMISelLowering.h:267
llvm::VMOVModImm
@ VMOVModImm
Definition: ARMISelLowering.h:976
llvm::ARMISD::CMPZ
@ CMPZ
Definition: ARMISelLowering.h:87
llvm::ARMISD::VADDLVAu
@ VADDLVAu
Definition: ARMISelLowering.h:239
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4157
llvm::ARMTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: ARMISelLowering.cpp:13433
llvm::ARMISD::CALL_NOLINK
@ CALL_NOLINK
Definition: ARMISelLowering.h:70
llvm::ARMISD::VLD3LN_UPD
@ VLD3LN_UPD
Definition: ARMISelLowering.h:335
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::ARMTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: ARMISelLowering.cpp:20515
llvm::Function
Definition: Function.h:61
StringRef.h
llvm::ARMTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: ARMISelLowering.cpp:11618
llvm::ARMISD::WLS
@ WLS
Definition: ARMISelLowering.h:134
llvm::ARMTargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: ARMISelLowering.cpp:19349
llvm::ARMISD::VMOVIMM
@ VMOVIMM
Definition: ARMISelLowering.h:187
llvm::ARMISD::PRELOAD
@ PRELOAD
Definition: ARMISelLowering.h:129
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ARMISD::DYN_ALLOC
@ DYN_ALLOC
Definition: ARMISelLowering.h:125
InlineAsm.h
llvm::ARMTargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
Definition: ARMISelLowering.cpp:20662
llvm::ARMTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: ARMISelLowering.cpp:19403
llvm::ARMTargetLowering::PerformCMOVCombine
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
Definition: ARMISelLowering.cpp:17455
llvm::ARMTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: ARMISelLowering.cpp:3409
llvm::ARMISD::VIDUP
@ VIDUP
Definition: ARMISelLowering.h:223
llvm::ARM::RP
@ RP
Definition: ARMISelLowering.h:369
llvm::ARMISD::VLD1x3_UPD
@ VLD1x3_UPD
Definition: ARMISelLowering.h:342
llvm::ARMISD::VLD2DUP_UPD
@ VLD2DUP_UPD
Definition: ARMISelLowering.h:338
llvm::ARMTargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
Definition: ARMISelLowering.cpp:20815
llvm::ARM::rmMask
@ rmMask
Definition: ARMISelLowering.h:372
llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: ARMISelLowering.cpp:19315
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::ARMTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: ARMISelLowering.cpp:18705
llvm::ARMISD::LE
@ LE
Definition: ARMISelLowering.h:137
llvm::ARMISD::VBICIMM
@ VBICIMM
Definition: ARMISelLowering.h:302
llvm::ARMISD::VSHRsIMM
@ VSHRsIMM
Definition: ARMISelLowering.h:156
llvm::MemOp
Definition: TargetLowering.h:112
llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Definition: ARMISelLowering.cpp:20553
llvm::ARMISD::LDRD
@ LDRD
Definition: ARMISelLowering.h:358
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::InlineAsm::Constraint_Uy
@ Constraint_Uy
Definition: InlineAsm.h:261
llvm::ARMTargetLowering::alignLoopsWithOptSize
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Definition: ARMISelLowering.cpp:20595
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:20392
llvm::ARMTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2065
llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: ARMISelLowering.cpp:13422
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:389
llvm::AttributeList
Definition: Attributes.h:398
llvm::ARMISD::VQSHRNsuIMM
@ VQSHRNsuIMM
Definition: ARMISelLowering.h:170
llvm::ARMTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: ARMISelLowering.cpp:20053
llvm::ARMISD::CMPFPw0
@ CMPFPw0
Definition: ARMISelLowering.h:90
llvm::ARMISD::VDUP
@ VDUP
Definition: ARMISelLowering.h:198
llvm::ARMISD::VST1_UPD
@ VST1_UPD
Definition: ARMISelLowering.h:346
llvm::ARMISD::PIC_ADD
@ PIC_ADD
Definition: ARMISelLowering.h:79
llvm::ARMISD::FMSTAT
@ FMSTAT
Definition: ARMISelLowering.h:93
llvm::ARMISD::MEMCPY
@ MEMCPY
Definition: ARMISelLowering.h:309
llvm::ARMISD::BFI
@ BFI
Definition: ARMISelLowering.h:297
llvm::ARMISD::USAT
@ USAT
Definition: ARMISelLowering.h:99
llvm::ARMTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: ARMISelLowering.cpp:1898
llvm::ARMTargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
Definition: ARMISelLowering.h:699
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ARMISD::VST4LN_UPD
@ VST4LN_UPD
Definition: ARMISelLowering.h:352
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:61
llvm::ARMISD::VZIP
@ VZIP
Definition: ARMISelLowering.h:206
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::ARMISD::WIN__CHKSTK
@ WIN__CHKSTK
Definition: ARMISelLowering.h:131
llvm::ARMISD::SSAT
@ SSAT
Definition: ARMISelLowering.h:98
llvm::ARMISD::WIN__DBZCHK
@ WIN__DBZCHK
Definition: ARMISelLowering.h:132
llvm::ARMISD::VTBL1
@ VTBL1
Definition: ARMISelLowering.h:209
llvm::ARMTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: ARMISelLowering.cpp:20284
llvm::ARMTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: ARMISelLowering.cpp:10193
llvm::ARMISD::ASRL
@ ASRL
Definition: ARMISelLowering.h:81
llvm::ARMISD::VQRSHRNsIMM
@ VQRSHRNsIMM
Definition: ARMISelLowering.h:173
llvm::ARMTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: ARMISelLowering.cpp:19541
VectorType
Definition: ItaniumDemangle.h:1041
llvm::ARMISD::SERET_FLAG
@ SERET_FLAG
Definition: ARMISelLowering.h:76
llvm::ARMISD::SMLSLD
@ SMLSLD
Definition: ARMISelLowering.h:273
llvm::ARMTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: ARMISelLowering.cpp:19233
llvm::ARMISD::NodeType
NodeType
Definition: ARMISelLowering.h:55
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:196
llvm::ARMISD::VTST
@ VTST
Definition: ARMISelLowering.h:148
llvm::ARMTargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: ARMISelLowering.cpp:21108
llvm::ARMISD::VSHRuIMM
@ VSHRuIMM
Definition: ARMISelLowering.h:157
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:525
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ARMISD::VMVNIMM
@ VMVNIMM
Definition: ARMISelLowering.h:188
llvm::ARMTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Definition: ARMISelLowering.cpp:19024
llvm::ARMTargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: ARMISelLowering.cpp:20561
llvm::ARMISD::PREDICATE_CAST
@ PREDICATE_CAST
Definition: ARMISelLowering.h:139
llvm::ARMISD::SMMLAR
@ SMMLAR
Definition: ARMISelLowering.h:275
llvm::ARMTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: ARMISelLowering.cpp:20017
llvm::ARMISD::MVESEXT
@ MVESEXT
Definition: ARMISelLowering.h:142
llvm::ARMTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: ARMISelLowering.cpp:20519
llvm::ARMTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: ARMISelLowering.cpp:18138
llvm::ARMISD::UMLAL
@ UMLAL
Definition: ARMISelLowering.h:264
llvm::ARMTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: ARMISelLowering.cpp:1631
MachineValueType.h
llvm::ARMISD::WLSSETUP
@ WLSSETUP
Definition: ARMISelLowering.h:135
llvm::ARMISD::BR2_JT
@ BR2_JT
Definition: ARMISelLowering.h:74
llvm::ARMTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: ARMISelLowering.h:406
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ARMTargetLowering::PerformIntrinsicCombine
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
Definition: ARMISelLowering.cpp:16593
llvm::ARMISD::VST2LN_UPD
@ VST2LN_UPD
Definition: ARMISelLowering.h:350
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::ARMISD::QSUB8b
@ QSUB8b
Definition: ARMISelLowering.h:281
llvm::ARMISD::SMMLSR
@ SMMLSR
Definition: ARMISelLowering.h:276
TargetLowering.h
llvm::ARMISD::VQRSHRNsuIMM
@ VQRSHRNsuIMM
Definition: ARMISelLowering.h:175
llvm::ARMISD::VMULLs
@ VMULLs
Definition: ARMISelLowering.h:226
llvm::ARM::isBitFieldInvertedMask
bool isBitFieldInvertedMask(unsigned v)
Definition: ARMISelLowering.cpp:20022
llvm::ARMTargetLowering::shouldConvertSplatType
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Definition: ARMISelLowering.cpp:18433
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
ARMBaseInfo.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ARMISD::VMLALVAs
@ VMLALVAs
Definition: ARMISelLowering.h:253
llvm::ARMISD::LOOP_DEC
@ LOOP_DEC
Definition: ARMISelLowering.h:136
llvm::ARMISD::VMOVSR
@ VMOVSR
Definition: ARMISelLowering.h:115
llvm::ARMTargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: ARMISelLowering.h:682
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ARMISD::VQRSHRNuIMM
@ VQRSHRNuIMM
Definition: ARMISelLowering.h:174
llvm::ARMTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: ARMISelLowering.cpp:19113
llvm::ARMISD::VADDLVAs
@ VADDLVAs
Definition: ARMISelLowering.h:238
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::ARMTargetLowering::PerformMVEExtCombine
SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:17838
llvm::ARMTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: ARMISelLowering.cpp:20507
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:685
llvm::ARMISD::VQSHRNuIMM
@ VQSHRNuIMM
Definition: ARMISelLowering.h:169
llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
Definition: ARMISelLowering.cpp:18143
llvm::ARMISD::SRL_FLAG
@ SRL_FLAG
Definition: ARMISelLowering.h:103
llvm::ARMISD::VREV16
@ VREV16
Definition: ARMISelLowering.h:205
llvm::ARMTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: ARMISelLowering.cpp:1579
llvm::ARMISD::VADDLVps
@ VADDLVps
Definition: ARMISelLowering.h:240
llvm::ARMISD::SMLALDX
@ SMLALDX
Definition: ARMISelLowering.h:272
llvm::ARMISD::VCMP
@ VCMP
Definition: ARMISelLowering.h:146
llvm::ARMISD::VMLALVAu
@ VMLALVAu
Definition: ARMISelLowering.h:254
llvm::Instruction
Definition: Instruction.h:45
llvm::ARMISD::VMULLu
@ VMULLu
Definition: ARMISelLowering.h:227
llvm::ARMISD::VMOVDRR
@ VMOVDRR
Definition: ARMISelLowering.h:114
llvm::InlineAsm::Constraint_Us
@ Constraint_Us
Definition: InlineAsm.h:258
llvm::ARMISD::VLD1DUP
@ VLD1DUP
Definition: ARMISelLowering.h:324
llvm::ARMISD::VQSHLuIMM
@ VQSHLuIMM
Definition: ARMISelLowering.h:166
llvm::ARM::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: ARMISelLowering.h:376
llvm::ARMISD::SUBC
@ SUBC
Definition: ARMISelLowering.h:109
llvm::ARMISD::VQMOVNu
@ VQMOVNu
Definition: ARMISelLowering.h:215
llvm::ARMISD::VMINVs
@ VMINVs
Definition: ARMISelLowering.h:258
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ARMTargetLowering::PerformCMOVToBFICombine
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
Definition: ARMISelLowering.cpp:17154
llvm::ARMISD::VST3_UPD
@ VST3_UPD
Definition: ARMISelLowering.h:348
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMISD::VLD1_UPD
@ VLD1_UPD
Definition: ARMISelLowering.h:330
llvm::ARMTargetLowering::isReadOnly
bool isReadOnly(const GlobalValue *GV) const
Definition: ARMISelLowering.cpp:3802
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMISD::SMLALD
@ SMLALD
Definition: ARMISelLowering.h:271
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARMTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: ARMISelLowering.cpp:19465
llvm::ARMISD::UQADD8b
@ UQADD8b
Definition: ARMISelLowering.h:284
llvm::VMVNModImm
@ VMVNModImm
Definition: ARMISelLowering.h:977
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMISD::VADDLVu
@ VADDLVu
Definition: ARMISelLowering.h:237
llvm::ARMISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: ARMISelLowering.h:119
llvm::ARMTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: ARMISelLowering.cpp:13387
llvm::ARMISD::QADD8b
@ QADD8b
Definition: ARMISelLowering.h:280
llvm::ARMISD::WrapperPIC
@ WrapperPIC
Definition: ARMISelLowering.h:61
llvm::ARMTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: ARMISelLowering.cpp:17942
llvm::ARMTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: ARMISelLowering.h:619
llvm::InlineAsm::Constraint_Un
@ Constraint_Un
Definition: InlineAsm.h:256
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::ARMISD::LSRL
@ LSRL
Definition: ARMISelLowering.h:82
llvm::ARMISD::CSINC
@ CSINC
Definition: ARMISelLowering.h:321
llvm::ARMISD::CALL_PRED
@ CALL_PRED
Definition: ARMISelLowering.h:69
llvm::ARM::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: ARMFastISel.cpp:3076
llvm::ARMISD::VRSHRuIMM
@ VRSHRuIMM
Definition: ARMISelLowering.h:161
llvm::ARMISD::WrapperJT
@ WrapperJT
Definition: ARMISelLowering.h:63
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::ARMISD::VMLALVApu
@ VMLALVApu
Definition: ARMISelLowering.h:256
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ARMISD::SUBS
@ SUBS
Definition: ARMISelLowering.h:96
llvm::ARMISD::VBSP
@ VBSP
Definition: ARMISelLowering.h:305
llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: ARMISelLowering.cpp:20401
llvm::ARMISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: ARMISelLowering.h:117
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::APFloat
Definition: APFloat.h:701
llvm::ARMISD::VMLAVu
@ VMLAVu
Definition: ARMISelLowering.h:246
llvm::ARMISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: ARMISelLowering.h:118
llvm::ARMISD::VADDLVAps
@ VADDLVAps
Definition: ARMISelLowering.h:242
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::ARMISD::VEXT
@ VEXT
Definition: ARMISelLowering.h:202
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: ARMISelLowering.h:691
llvm::ARMISD::SMULWT
@ SMULWT
Definition: ARMISelLowering.h:263
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARMISD::LSLL
@ LSLL
Definition: ARMISelLowering.h:83
llvm::ARMISD::VLD2DUP
@ VLD2DUP
Definition: ARMISelLowering.h:325
llvm::ARMISD::MEMCPYLOOP
@ MEMCPYLOOP
Definition: ARMISelLowering.h:313
llvm::ARMTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: ARMISelLowering.cpp:18319
llvm::ARMISD::VUZP
@ VUZP
Definition: ARMISelLowering.h:207
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
llvm::ARMISD::CMPFPEw0
@ CMPFPEw0
Definition: ARMISelLowering.h:91
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ARMTargetLowering::shouldAlignPointerArgs
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
Definition: ARMISelLowering.cpp:1885
llvm::ARMISD::VQDMULH
@ VQDMULH
Definition: ARMISelLowering.h:229
llvm::ARMISD::VCMPZ
@ VCMPZ
Definition: ARMISelLowering.h:147
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ARMISD::RET_FLAG
@ RET_FLAG
Definition: ARMISelLowering.h:75
llvm::ARMISD::BRCOND
@ BRCOND
Definition: ARMISelLowering.h:72
llvm::ARMISD::VCVTL
@ VCVTL
Definition: ARMISelLowering.h:220
llvm::ARMTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: ARMISelLowering.h:592
llvm::ARMISD::UQSUB16b
@ UQSUB16b
Definition: ARMISelLowering.h:287
llvm::DemandedBits
Definition: DemandedBits.h:40
llvm::InlineAsm::Constraint_Ut
@ Constraint_Ut
Definition: InlineAsm.h:259
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:2811
llvm::ARMISD::VREV64
@ VREV64
Definition: ARMISelLowering.h:203
llvm::ARMISD::VLD2LN_UPD
@ VLD2LN_UPD
Definition: ARMISelLowering.h:334
llvm::ARMISD::VST4_UPD
@ VST4_UPD
Definition: ARMISelLowering.h:349
llvm::ARMISD::VMOVRRD
@ VMOVRRD
Definition: ARMISelLowering.h:113
llvm::ARMISD::COPY_STRUCT_BYVAL
@ COPY_STRUCT_BYVAL
Definition: ARMISelLowering.h:66
llvm::ARMISD::THREAD_POINTER
@ THREAD_POINTER
Definition: ARMISelLowering.h:123
llvm::ARMTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
Definition: ARMISelLowering.cpp:8197
llvm::ARMISD::STRD
@ STRD
Definition: ARMISelLowering.h:359
llvm::ARMISD::VST1x4_UPD
@ VST1x4_UPD
Definition: ARMISelLowering.h:355
llvm::ARMTargetLowering::canCombineStoreAndExtract
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
Definition: ARMISelLowering.cpp:20478
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
IRBuilder.h
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::ARMISD::VADDLVApu
@ VADDLVApu
Definition: ARMISelLowering.h:243
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::ARMISD::VMINVu
@ VMINVu
Definition: ARMISelLowering.h:257
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::ARMISD::VMLALVps
@ VMLALVps
Definition: ARMISelLowering.h:251
llvm::ARMISD::VSHLs
@ VSHLs
Definition: ARMISelLowering.h:151
llvm::ARMTargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: ARMISelLowering.cpp:1594
llvm::ARMTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: ARMISelLowering.cpp:20438
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1355
llvm::ARMISD::VECTOR_REG_CAST
@ VECTOR_REG_CAST
Definition: ARMISelLowering.h:140
llvm::ARMISD::VRSHRsIMM
@ VRSHRsIMM
Definition: ARMISelLowering.h:160
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ARMISD::VADDLVpu
@ VADDLVpu
Definition: ARMISelLowering.h:241
llvm::ARM::RM
@ RM
Definition: ARMISelLowering.h:370
llvm::ARMISD::VST3LN_UPD
@ VST3LN_UPD
Definition: ARMISelLowering.h:351
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::ARMISD::VMOVFPIMM
@ VMOVFPIMM
Definition: ARMISelLowering.h:191
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::ARM::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
Definition: ARMISelLowering.h:367
llvm::ARMTargetLowering::PerformMVETruncCombine
SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:17669
llvm::ARMISD::VLD4_UPD
@ VLD4_UPD
Definition: ARMISelLowering.h:333
llvm::ARMTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: ARMISelLowering.cpp:20357
llvm::ARMISD::VADDVs
@ VADDVs
Definition: ARMISelLowering.h:232
llvm::ARMISD::VTBL2
@ VTBL2
Definition: ARMISelLowering.h:210
llvm::ARMISD::QADD16b
@ QADD16b
Definition: ARMISelLowering.h:282
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMISD::VREV32
@ VREV32
Definition: ARMISelLowering.h:204
llvm::ARMISD::VLD3_UPD
@ VLD3_UPD
Definition: ARMISelLowering.h:332
llvm::ARMISD::VSRIIMM
@ VSRIIMM
Definition: ARMISelLowering.h:179
llvm::ARMISD::VADDVu
@ VADDVu
Definition: ARMISelLowering.h:233
llvm::ARMTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: ARMISelLowering.cpp:20464
llvm::ARMISD::MVEZEXT
@ MVEZEXT
Definition: ARMISelLowering.h:143
llvm::ArrayRef< int >
RegInfo
Definition: AMDGPUAsmParser.cpp:2366
llvm::ARMISD::VGETLANEu
@ VGETLANEu
Definition: ARMISelLowering.h:183
llvm::ARMISD::VMLAVps
@ VMLAVps
Definition: ARMISelLowering.h:247
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::ARMISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: ARMISelLowering.h:57
llvm::ARMISD::VST1x2_UPD
@ VST1x2_UPD
Definition: ARMISelLowering.h:353
llvm::ARMISD::VADDVps
@ VADDVps
Definition: ARMISelLowering.h:234
llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:20423
llvm::ARMISD::VLD1x4_UPD
@ VLD1x4_UPD
Definition: ARMISelLowering.h:343
llvm::ARMTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: ARMISelLowering.cpp:20511
llvm::ARMTargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: ARMISelLowering.cpp:18446
llvm::ARMISD::BUILD_VECTOR
@ BUILD_VECTOR
Definition: ARMISelLowering.h:294
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
llvm::ARMISD::VLD1DUP_UPD
@ VLD1DUP_UPD
Definition: ARMISelLowering.h:337
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: ARMISelLowering.cpp:18215
llvm::ARMISD::VMOVhr
@ VMOVhr
Definition: ARMISelLowering.h:195
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMISD::CMPFPE
@ CMPFPE
Definition: ARMISelLowering.h:89
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
Node
Definition: ItaniumDemangle.h:235
llvm::ARMISD::VRSHRNIMM
@ VRSHRNIMM
Definition: ARMISelLowering.h:162
llvm::ARMISD::MVETRUNC
@ MVETRUNC
Definition: ARMISelLowering.h:144
llvm::ARMISD::VST2_UPD
@ VST2_UPD
Definition: ARMISelLowering.h:347
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::ARMISD::SMLSLDX
@ SMLSLDX
Definition: ARMISelLowering.h:274
llvm::OtherModImm
@ OtherModImm
Definition: ARMISelLowering.h:979
llvm::ARMISD::VMLAVs
@ VMLAVs
Definition: ARMISelLowering.h:244
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::ARMTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: ARMISelLowering.cpp:18243
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: ARMISelLowering.cpp:21031
llvm::ARMISD::VSLIIMM
@ VSLIIMM
Definition: ARMISelLowering.h:178
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMISD::CSNEG
@ CSNEG
Definition: ARMISelLowering.h:320
Attributes.h
llvm::ARMTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: ARMISelLowering.cpp:19433
llvm::ARMISD::UQSUB8b
@ UQSUB8b
Definition: ARMISelLowering.h:285
llvm::ARMISD::VMLALVAps
@ VMLALVAps
Definition: ARMISelLowering.h:255
llvm::ARMISD::VLD1x2_UPD
@ VLD1x2_UPD
Definition: ARMISelLowering.h:341
llvm::ARMISD::VST1x3_UPD
@ VST1x3_UPD
Definition: ARMISelLowering.h:354
llvm::ARMISD::VSHLIMM
@ VSHLIMM
Definition: ARMISelLowering.h:155
llvm::ARMTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: ARMISelLowering.cpp:18771
llvm::ARMISD::SMULWB
@ SMULWB
Definition: ARMISelLowering.h:262
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::ARMISD::VGETLANEs
@ VGETLANEs
Definition: ARMISelLowering.h:184
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
llvm::ARMISD::SRA_FLAG
@ SRA_FLAG
Definition: ARMISelLowering.h:104
CallingConvLower.h
llvm::ARMTargetLowering::makeDMB
Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const
Definition: ARMISelLowering.cpp:20302
llvm::ARMISD::VMAXVu
@ VMAXVu
Definition: ARMISelLowering.h:259
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::ARMISD::VQMOVNs
@ VQMOVNs
Definition: ARMISelLowering.h:214
llvm::ARMISD::VLD4DUP_UPD
@ VLD4DUP_UPD
Definition: ARMISelLowering.h:340
llvm::ARMTargetLowering::getSubtarget
const ARMSubtarget * getSubtarget() const
Definition: ARMISelLowering.h:573
llvm::ARMISD::VADDVpu
@ VADDVpu
Definition: ARMISelLowering.h:235
llvm::ARMTargetLowering::PerformBRCONDCombine
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
Definition: ARMISelLowering.cpp:17415
llvm::ARM::RZ
@ RZ
Definition: ARMISelLowering.h:371
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4166
llvm::ARMISD::VMLALVu
@ VMLALVu
Definition: ARMISelLowering.h:250
ISDOpcodes.h
llvm::ARMISD::UMAAL
@ UMAAL
Definition: ARMISelLowering.h:266
Function.h
llvm::ARMISD::VDUPLANE
@ VDUPLANE
Definition: ARMISelLowering.h:199
llvm::ARMISD::tSECALL
@ tSECALL
Definition: ARMISelLowering.h:71
llvm::ARMISD::CMN
@ CMN
Definition: ARMISelLowering.h:86
llvm::ARMISD::VMLALVpu
@ VMLALVpu
Definition: ARMISelLowering.h:252
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::ARMISD::INTRET_FLAG
@ INTRET_FLAG
Definition: ARMISelLowering.h:77
llvm::ARMTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: ARMISelLowering.cpp:20332
llvm::ARMISD::ADDE
@ ADDE
Definition: ARMISelLowering.h:108
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ARMTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: ARMISelLowering.cpp:18476
llvm::ARMISD::CSINV
@ CSINV
Definition: ARMISelLowering.h:319
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:839
llvm::ARMTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(const SDValue &AddNode, const SDValue &ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: ARMISelLowering.cpp:18801
llvm::ARMTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Definition: ARMISelLowering.cpp:21017
llvm::ARMISD::VQSHRNsIMM
@ VQSHRNsIMM
Definition: ARMISelLowering.h:168
llvm::ARMTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: ARMISelLowering.cpp:20034
CodeGen.h
llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
Definition: ARMISelLowering.cpp:20379
llvm::ARMISD::VQSHLsIMM
@ VQSHLsIMM
Definition: ARMISelLowering.h:165
llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: ARMISelLowering.cpp:20643
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2009
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
SmallVector.h
llvm::ARMISD::VLD4DUP
@ VLD4DUP
Definition: ARMISelLowering.h:327
llvm::ARMISD::VCVTN
@ VCVTN
Definition: ARMISelLowering.h:218
llvm::TargetLoweringBase::ScalarCondVectorVal
@ ScalarCondVectorVal
Definition: TargetLowering.h:240
llvm::ARMTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: ARMISelLowering.cpp:20294
llvm::ARMTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: ARMISelLowering.cpp:12027
llvm::ARMTargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: ARMISelLowering.cpp:20471
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
llvm::ARMTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2070
llvm::InlineAsm::Constraint_Uv
@ Constraint_Uv
Definition: InlineAsm.h:260
N
#define N
llvm::ARMTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: ARMISelLowering.h:695
llvm::ARMISD::MEMBARRIER_MCR
@ MEMBARRIER_MCR
Definition: ARMISelLowering.h:127
llvm::ARMISD::VMLAVpu
@ VMLAVpu
Definition: ARMISelLowering.h:248
llvm::ARMTargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: ARMISelLowering.cpp:20602
llvm::ARMTargetLowering::isFNegFree
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition: ARMISelLowering.cpp:18281
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4258
llvm::ARMISD::CMPFP
@ CMPFP
Definition: ARMISelLowering.h:88
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::ARMISD::VLD3DUP
@ VLD3DUP
Definition: ARMISelLowering.h:326
llvm::ARMTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: ARMISelLowering.cpp:21047
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::ARMISD::TC_RETURN
@ TC_RETURN
Definition: ARMISelLowering.h:121
RegName
#define RegName(no)
llvm::ARMTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: ARMISelLowering.h:545
llvm::ARM_MB::MemBOpt
MemBOpt
Definition: ARMBaseInfo.h:58
llvm::ARMISD::VSHLu
@ VSHLu
Definition: ARMISelLowering.h:152
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: ARMISelLowering.cpp:10343
llvm::ARMISD::Wrapper
@ Wrapper
Definition: ARMISelLowering.h:59
llvm::ARMISD::SMLALBT
@ SMLALBT
Definition: ARMISelLowering.h:268
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::ARMTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: ARMISelLowering.cpp:18787
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MVEVMVNModImm
@ MVEVMVNModImm
Definition: ARMISelLowering.h:978
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::ARMISD::SUBE
@ SUBE
Definition: ARMISelLowering.h:110
llvm::ARMISD::CMOV
@ CMOV
Definition: ARMISelLowering.h:95
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:98
llvm::InlineAsm::Constraint_Uq
@ Constraint_Uq
Definition: InlineAsm.h:257
llvm::ARMISD::BR_JT
@ BR_JT
Definition: ARMISelLowering.h:73
llvm::ARMISD::UQADD16b
@ UQADD16b
Definition: ARMISelLowering.h:286
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
MachineFunction.h
model
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from where P can be anything The alignment inference code cannot handle loads from globals in static non mode because it doesn t look through the extra dyld stub load If you try vec_align ll without relocation model
Definition: README-SSE.txt:414
llvm::ARMISD::CALL
@ CALL
Definition: ARMISelLowering.h:68
llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Definition: ARMISelLowering.cpp:18650
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:61
llvm::InlineAsm::Constraint_Um
@ Constraint_Um
Definition: InlineAsm.h:255
llvm::ARMTargetLowering::ARMTargetLowering
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
Definition: ARMISelLowering.cpp:458
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
llvm::ARMISD::ADDC
@ ADDC
Definition: ARMISelLowering.h:107
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMISD::SMLALTB
@ SMLALTB
Definition: ARMISelLowering.h:269
llvm::ARMISD::VLD4LN_UPD
@ VLD4LN_UPD
Definition: ARMISelLowering.h:336
llvm::ARMTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: ARMISelLowering.cpp:20444
llvm::ARMTargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
Definition: ARMISelLowering.cpp:18490
llvm::ARM::RN
@ RN
Definition: ARMISelLowering.h:368
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:238
llvm::VMOVModImmType
VMOVModImmType
Definition: ARMISelLowering.h:975
llvm::ARMISD::VORRIMM
@ VORRIMM
Definition: ARMISelLowering.h:300
llvm::ARMISD::VMAXVs
@ VMAXVs
Definition: ARMISelLowering.h:260
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ARMTargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Definition: ARMISelLowering.cpp:20607
llvm::ARMISD::VTRN
@ VTRN
Definition: ARMISelLowering.h:208
llvm::ARMTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: ARMISelLowering.cpp:21054
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::ARMISD::LSLS
@ LSLS
Definition: ARMISelLowering.h:111