LLVM 19.0.0git
ARMISelLowering.h
Go to the documentation of this file.
1//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16
19#include "llvm/ADT/StringRef.h"
27#include "llvm/IR/Attributes.h"
28#include "llvm/IR/CallingConv.h"
29#include "llvm/IR/Function.h"
30#include "llvm/IR/InlineAsm.h"
32#include <optional>
33#include <utility>
34
35namespace llvm {
36
37class ARMSubtarget;
38class DataLayout;
39class FastISel;
40class FunctionLoweringInfo;
41class GlobalValue;
42class InstrItineraryData;
43class Instruction;
44class IRBuilderBase;
45class MachineBasicBlock;
46class MachineInstr;
47class SelectionDAG;
48class TargetLibraryInfo;
49class TargetMachine;
50class TargetRegisterInfo;
51class VectorType;
52
53 namespace ARMISD {
54
55 // ARM Specific DAG Nodes
56 enum NodeType : unsigned {
57 // Start the numbering where the builtin ops and target ops leave off.
59
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61 // TargetExternalSymbol, and TargetGlobalAddress.
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63 // PIC mode.
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65
66 // Add pseudo op to model memcpy for struct byval.
68
69 CALL, // Function call.
70 CALL_PRED, // Function call that's predicable.
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
73 t2CALL_BTI, // Thumb function call followed by BTI instruction.
74 BRCOND, // Conditional branch.
75 BR_JT, // Jumptable branch.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
77 RET_GLUE, // Return with a flag operand.
78 SERET_GLUE, // CMSE Entry function return with a flag operand.
79 INTRET_GLUE, // Interrupt return with an LR-offset and a flag operand.
80
81 PIC_ADD, // Add with a PC operand and a PIC label.
82
83 ASRL, // MVE long arithmetic shift right.
84 LSRL, // MVE long shift right.
85 LSLL, // MVE long shift left.
86
87 CMP, // ARM compare instructions.
88 CMN, // ARM CMN instructions.
89 CMPZ, // ARM compare that sets only Z flag.
90 CMPFP, // ARM VFP compare instruction, sets FPSCR.
91 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
92 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
93 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
94 // FPSCR.
95 FMSTAT, // ARM fmstat instruction.
96
97 CMOV, // ARM conditional move instructions.
98 SUBS, // Flag-setting subtraction.
99
100 SSAT, // Signed saturation
101 USAT, // Unsigned saturation
102
104
105 SRL_GLUE, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
106 SRA_GLUE, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
107 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
108
109 ADDC, // Add with carry
110 ADDE, // Add using carry
111 SUBC, // Sub with carry
112 SUBE, // Sub using carry
113 LSLS, // Shift left producing carry
114
115 VMOVRRD, // double to two gprs.
116 VMOVDRR, // Two gprs to double.
117 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
118
119 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
120 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
121 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
122
123 TC_RETURN, // Tail call return pseudo.
124
126
127 DYN_ALLOC, // Dynamic allocation on the stack.
128
129 MEMBARRIER_MCR, // Memory barrier (MCR)
130
131 PRELOAD, // Preload
132
133 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
134 WIN__DBZCHK, // Windows' divide by zero check
135
136 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
137 WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
138 LOOP_DEC, // Really a part of LE, performs the sub
139 LE, // Low-overhead loops, Loop End
140
141 PREDICATE_CAST, // Predicate cast for MVE i1 types
142 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
143
144 MVESEXT, // Legalization aids for extending a vector into two/four vectors.
145 MVEZEXT, // or truncating two/four vectors into one. Eventually becomes
146 MVETRUNC, // stack store/load sequence, if not optimized to anything else.
147
148 VCMP, // Vector compare.
149 VCMPZ, // Vector compare to zero.
150 VTST, // Vector test bits.
151
152 // Vector shift by vector
153 VSHLs, // ...left/right by signed
154 VSHLu, // ...left/right by unsigned
155
156 // Vector shift by immediate:
157 VSHLIMM, // ...left
158 VSHRsIMM, // ...right (signed)
159 VSHRuIMM, // ...right (unsigned)
160
161 // Vector rounding shift by immediate:
162 VRSHRsIMM, // ...right (signed)
163 VRSHRuIMM, // ...right (unsigned)
164 VRSHRNIMM, // ...right narrow
165
166 // Vector saturating shift by immediate:
167 VQSHLsIMM, // ...left (signed)
168 VQSHLuIMM, // ...left (unsigned)
169 VQSHLsuIMM, // ...left (signed to unsigned)
170 VQSHRNsIMM, // ...right narrow (signed)
171 VQSHRNuIMM, // ...right narrow (unsigned)
172 VQSHRNsuIMM, // ...right narrow (signed to unsigned)
173
174 // Vector saturating rounding shift by immediate:
175 VQRSHRNsIMM, // ...right narrow (signed)
176 VQRSHRNuIMM, // ...right narrow (unsigned)
177 VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
178
179 // Vector shift and insert:
180 VSLIIMM, // ...left
181 VSRIIMM, // ...right
182
183 // Vector get lane (VMOV scalar to ARM core register)
184 // (These are used for 8- and 16-bit element types only.)
185 VGETLANEu, // zero-extend vector extract element
186 VGETLANEs, // sign-extend vector extract element
187
188 // Vector move immediate and move negated immediate:
191
192 // Vector move f32 immediate:
194
195 // Move H <-> R, clearing top 16 bits
198
199 // Vector duplicate:
202
203 // Vector shuffles:
204 VEXT, // extract
205 VREV64, // reverse elements within 64-bit doublewords
206 VREV32, // reverse elements within 32-bit words
207 VREV16, // reverse elements within 16-bit halfwords
208 VZIP, // zip (interleave)
209 VUZP, // unzip (deinterleave)
210 VTRN, // transpose
211 VTBL1, // 1-register shuffle with mask
212 VTBL2, // 2-register shuffle with mask
213 VMOVN, // MVE vmovn
214
215 // MVE Saturating truncates
216 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
217 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
218
219 // MVE float <> half converts
220 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
221 // lanes
222 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
223
224 // MVE VIDUP instruction, taking a start value and increment.
226
227 // Vector multiply long:
228 VMULLs, // ...signed
229 VMULLu, // ...unsigned
230
231 VQDMULH, // MVE vqdmulh instruction
232
233 // MVE reductions
234 VADDVs, // sign- or zero-extend the elements of a vector to i32,
235 VADDVu, // add them all together, and return an i32 of their sum
236 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
238 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
239 VADDLVu, // the low and high 32-bit halves of the sum
240 VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
241 VADDLVAu, // provided as low and high halves
242 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
244 VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
246 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
247 VMLAVu, // them and add the results together, returning an i32 of their sum
248 VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
250 VMLALVs, // Same as VMLAV but with i64, returning the low and
251 VMLALVu, // high 32-bit halves of the sum
252 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
254 VMLALVAs, // Same as VMLALV but also add an input accumulator
255 VMLALVAu, // provided as low and high halves
256 VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
258 VMINVu, // Find minimum unsigned value of a vector and register
259 VMINVs, // Find minimum signed value of a vector and register
260 VMAXVu, // Find maximum unsigned value of a vector and register
261 VMAXVs, // Find maximum signed value of a vector and register
262
263 SMULWB, // Signed multiply word by half word, bottom
264 SMULWT, // Signed multiply word by half word, top
265 UMLAL, // 64bit Unsigned Accumulate Multiply
266 SMLAL, // 64bit Signed Accumulate Multiply
267 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
268 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
269 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
270 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
271 SMLALTT, // 64-bit signed accumulate multiply top, top 16
272 SMLALD, // Signed multiply accumulate long dual
273 SMLALDX, // Signed multiply accumulate long dual exchange
274 SMLSLD, // Signed multiply subtract long dual
275 SMLSLDX, // Signed multiply subtract long dual exchange
276 SMMLAR, // Signed multiply long, round and add
277 SMMLSR, // Signed multiply long, subtract and round
278
279 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
280 // stands for.
289
290 // Operands of the standard BUILD_VECTOR node are not legalized, which
291 // is fine if BUILD_VECTORs are always lowered to shuffles or other
292 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
293 // operands need to be legalized. Define an ARM-specific version of
294 // BUILD_VECTOR for this purpose.
296
297 // Bit-field insert
299
300 // Vector OR with immediate
302 // Vector AND with NOT of immediate
304
305 // Pseudo vector bitwise select
307
308 // Pseudo-instruction representing a memory copy using ldm/stm
309 // instructions.
311
312 // Pseudo-instruction representing a memory copy using a tail predicated
313 // loop
315 // Pseudo-instruction representing a memset using a tail predicated
316 // loop
318
319 // V8.1MMainline condition select
320 CSINV, // Conditional select invert.
321 CSNEG, // Conditional select negate.
322 CSINC, // Conditional select increment.
323
324 // Vector load N-element structure to all lanes:
329
330 // NEON loads with post-increment base updates:
345
346 // NEON stores with post-increment base updates:
357
358 // Load/Store of dual registers
360 STRD
361 };
362
363 } // end namespace ARMISD
364
365 namespace ARM {
366 /// Possible values of current rounding mode, which is specified in bits
367 /// 23:22 of FPSCR.
368 enum Rounding {
369 RN = 0, // Round to Nearest
370 RP = 1, // Round towards Plus infinity
371 RM = 2, // Round towards Minus infinity
372 RZ = 3, // Round towards Zero
373 rmMask = 3 // Bit mask selecting rounding mode
374 };
375
376 // Bit position of rounding mode bits in FPSCR.
377 const unsigned RoundingBitsPos = 22;
378
379 // Bits of floating-point status. These are NZCV flags, QC bit and cumulative
380 // FP exception bits.
381 const unsigned FPStatusBits = 0xf800009f;
382
383 // Some bits in the FPSCR are not yet defined. They must be preserved when
384 // modifying the contents.
385 const unsigned FPReservedBits = 0x00006060;
386 } // namespace ARM
387
388 /// Define some predicates that are used for node matching.
389 namespace ARM {
390
391 bool isBitFieldInvertedMask(unsigned v);
392
393 } // end namespace ARM
394
395 //===--------------------------------------------------------------------===//
396 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
397
399 public:
400 explicit ARMTargetLowering(const TargetMachine &TM,
401 const ARMSubtarget &STI);
402
403 unsigned getJumpTableEncoding() const override;
404 bool useSoftFloat() const override;
405
406 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
407
408 /// ReplaceNodeResults - Replace the results of node with an illegal result
409 /// type with new values built out of custom code.
411 SelectionDAG &DAG) const override;
412
413 const char *getTargetNodeName(unsigned Opcode) const override;
414
415 bool isSelectSupported(SelectSupportKind Kind) const override {
416 // ARM does not support scalar condition selects on vectors.
417 return (Kind != ScalarCondVectorVal);
418 }
419
420 bool isReadOnly(const GlobalValue *GV) const;
421
422 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
424 EVT VT) const override;
425
428 MachineBasicBlock *MBB) const override;
429
431 SDNode *Node) const override;
432
436 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
437 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
438 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
439 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
440
442 const APInt &OriginalDemandedBits,
443 const APInt &OriginalDemandedElts,
444 KnownBits &Known,
445 TargetLoweringOpt &TLO,
446 unsigned Depth) const override;
447
448 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
449
450 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
451 /// unaligned memory accesses of the specified type. Returns whether it
452 /// is "fast" by reference in the second argument.
453 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
454 Align Alignment,
456 unsigned *Fast) const override;
457
459 const AttributeList &FuncAttributes) const override;
460
461 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
462 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
463 bool isZExtFree(SDValue Val, EVT VT2) const override;
465 SmallVectorImpl<Use *> &Ops) const override;
466 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
467
468 bool isFNegFree(EVT VT) const override;
469
470 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
471
472 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
473
474
475 /// isLegalAddressingMode - Return true if the addressing mode represented
476 /// by AM is legal for this target, for a load/store of the specified type.
477 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
478 Type *Ty, unsigned AS,
479 Instruction *I = nullptr) const override;
480
481 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
482
483 /// Returns true if the addressing mode representing by AM is legal
484 /// for the Thumb1 target, for a load/store of the specified type.
485 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
486
487 /// isLegalICmpImmediate - Return true if the specified immediate is legal
488 /// icmp immediate, that is the target has icmp instructions which can
489 /// compare a register against the immediate without having to materialize
490 /// the immediate into a register.
491 bool isLegalICmpImmediate(int64_t Imm) const override;
492
493 /// isLegalAddImmediate - Return true if the specified immediate is legal
494 /// add immediate, that is the target has add instructions which can
495 /// add a register and the immediate without having to materialize
496 /// the immediate into a register.
497 bool isLegalAddImmediate(int64_t Imm) const override;
498
499 /// getPreIndexedAddressParts - returns true by value, base pointer and
500 /// offset pointer and addressing mode by reference if the node's address
501 /// can be legally represented as pre-indexed load / store address.
504 SelectionDAG &DAG) const override;
505
506 /// getPostIndexedAddressParts - returns true by value, base pointer and
507 /// offset pointer and addressing mode by reference if this node can be
508 /// combined with a load / store to form a post-indexed load / store.
511 SelectionDAG &DAG) const override;
512
514 const APInt &DemandedElts,
515 const SelectionDAG &DAG,
516 unsigned Depth) const override;
517
519 const APInt &DemandedElts,
520 TargetLoweringOpt &TLO) const override;
521
522 bool ExpandInlineAsm(CallInst *CI) const override;
523
524 ConstraintType getConstraintType(StringRef Constraint) const override;
525
526 /// Examine constraint string and operand type and determine a weight value.
527 /// The operand object must already have been set up with the operand type.
529 AsmOperandInfo &info, const char *constraint) const override;
530
531 std::pair<unsigned, const TargetRegisterClass *>
533 StringRef Constraint, MVT VT) const override;
534
535 const char *LowerXConstraint(EVT ConstraintVT) const override;
536
537 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
538 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
539 /// true it means one of the asm constraint of the inline asm instruction
540 /// being processed is 'm'.
542 std::vector<SDValue> &Ops,
543 SelectionDAG &DAG) const override;
544
546 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
547 if (ConstraintCode == "Q")
549 if (ConstraintCode.size() == 2) {
550 if (ConstraintCode[0] == 'U') {
551 switch(ConstraintCode[1]) {
552 default:
553 break;
554 case 'm':
556 case 'n':
558 case 'q':
560 case 's':
562 case 't':
564 case 'v':
566 case 'y':
568 }
569 }
570 }
571 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
572 }
573
574 const ARMSubtarget* getSubtarget() const {
575 return Subtarget;
576 }
577
578 /// getRegClassFor - Return the register class that should be used for the
579 /// specified value type.
580 const TargetRegisterClass *
581 getRegClassFor(MVT VT, bool isDivergent = false) const override;
582
583 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
584 Align &PrefAlign) const override;
585
586 /// createFastISel - This method returns a target specific FastISel object,
587 /// or null if the target does not support "fast" ISel.
589 const TargetLibraryInfo *libInfo) const override;
590
592
593 bool preferZeroCompareBranch() const override { return true; }
594
595 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
596
597 bool
598 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
599 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
600
601 /// isFPImmLegal - Returns true if the target can instruction select the
602 /// specified FP immediate natively. If false, the legalizer will
603 /// materialize the FP immediate as a load from a constant pool.
604 bool isFPImmLegal(const APFloat &Imm, EVT VT,
605 bool ForCodeSize = false) const override;
606
607 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
608 const CallInst &I,
609 MachineFunction &MF,
610 unsigned Intrinsic) const override;
611
612 /// Returns true if it is beneficial to convert a load of a constant
613 /// to just the constant itself.
615 Type *Ty) const override;
616
617 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
618 /// with this index.
619 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
620 unsigned Index) const override;
621
622 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
623 bool MathUsed) const override {
624 // Using overflow ops for overflow checks only should beneficial on ARM.
625 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
626 }
627
628 bool shouldReassociateReduction(unsigned Opc, EVT VT) const override {
629 return Opc != ISD::VECREDUCE_ADD;
630 }
631
632 /// Returns true if an argument of type Ty needs to be passed in a
633 /// contiguous block of registers in calling convention CallConv.
635 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
636 const DataLayout &DL) const override;
637
638 /// If a physical register, this returns the register that receives the
639 /// exception address on entry to an EH pad.
641 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
642
643 /// If a physical register, this returns the register that receives the
644 /// exception typeid on entry to a landing pad.
646 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
647
649 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
650 AtomicOrdering Ord) const override;
652 AtomicOrdering Ord) const override;
653
654 void
655 emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
656
658 AtomicOrdering Ord) const override;
660 AtomicOrdering Ord) const override;
661
662 unsigned getMaxSupportedInterleaveFactor() const override;
663
666 ArrayRef<unsigned> Indices,
667 unsigned Factor) const override;
669 unsigned Factor) const override;
670
671 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
673 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
675 shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
677 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
680
681 bool useLoadStackGuardNode() const override;
682
683 void insertSSPDeclarations(Module &M) const override;
684 Value *getSDagStackGuard(const Module &M) const override;
685 Function *getSSPStackGuardCheck(const Module &M) const override;
686
687 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
688 unsigned &Cost) const override;
689
690 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
691 const MachineFunction &MF) const override {
692 // Do not merge to larger than i32.
693 return (MemVT.getSizeInBits() <= 32);
694 }
695
696 bool isCheapToSpeculateCttz(Type *Ty) const override;
697 bool isCheapToSpeculateCtlz(Type *Ty) const override;
698
699 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
700 return VT.isScalarInteger();
701 }
702
703 bool supportSwiftError() const override {
704 return true;
705 }
706
707 bool hasStandaloneRem(EVT VT) const override {
708 return HasStandaloneRem;
709 }
710
713 unsigned ExpansionFactor) const override;
714
715 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
716 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
717
718 /// Returns true if \p VecTy is a legal interleaved access type. This
719 /// function checks the vector element type and the overall width of the
720 /// vector.
721 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
722 Align Alignment,
723 const DataLayout &DL) const;
724
726 SDValue ConstNode) const override;
727
728 bool alignLoopsWithOptSize() const override;
729
730 /// Returns the number of interleaved accesses that will be generated when
731 /// lowering accesses of the given type.
733 const DataLayout &DL) const;
734
735 void finalizeLowering(MachineFunction &MF) const override;
736
737 /// Return the correct alignment for the current calling convention.
739 const DataLayout &DL) const override;
740
742 CombineLevel Level) const override;
743
744 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
745
747 CombineLevel Level) const override;
748
749 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
750 EVT VT) const override;
751
752 bool preferIncOfAddToSubOfNot(EVT VT) const override;
753
754 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
755
756 bool isComplexDeinterleavingSupported() const override;
758 ComplexDeinterleavingOperation Operation, Type *Ty) const override;
759
762 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
763 Value *Accumulator = nullptr) const override;
764
765 bool softPromoteHalfType() const override { return true; }
766
767 bool useFPRegsForHalfType() const override { return true; }
768
769 protected:
770 std::pair<const TargetRegisterClass *, uint8_t>
772 MVT VT) const override;
773
774 private:
775 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
776 /// make the right decision when generating code for different targets.
777 const ARMSubtarget *Subtarget;
778
780
781 const InstrItineraryData *Itins;
782
783 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
784 // check.
785 bool InsertFencesForAtomic;
786
787 bool HasStandaloneRem = true;
788
789 void addTypeForNEON(MVT VT, MVT PromotedLdStVT);
790 void addDRTypeForNEON(MVT VT);
791 void addQRTypeForNEON(MVT VT);
792 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
793
794 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
795
796 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
797 SDValue &Arg, RegsToPassVector &RegsToPass,
798 CCValAssign &VA, CCValAssign &NextVA,
799 SDValue &StackPtr,
800 SmallVectorImpl<SDValue> &MemOpChains,
801 bool IsTailCall,
802 int SPDiff) const;
803 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
804 SDValue &Root, SelectionDAG &DAG,
805 const SDLoc &dl) const;
806
807 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
808 bool isVarArg) const;
809 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
810 bool isVarArg) const;
811 std::pair<SDValue, MachinePointerInfo>
812 computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG,
813 const CCValAssign &VA, SDValue StackPtr,
814 bool IsTailCall, int SPDiff) const;
815 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
819 const ARMSubtarget *Subtarget) const;
820 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
821 const ARMSubtarget *Subtarget) const;
822 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
830 SelectionDAG &DAG) const;
831 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
832 SelectionDAG &DAG,
833 TLSModel::Model model) const;
834 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
837 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
840 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
841 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
842 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
843 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
844 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
845 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
846 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
847 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
848 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
849 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
850 SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
851 SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
852 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
853 const ARMSubtarget *ST) const;
854 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
855 const ARMSubtarget *ST) const;
856 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
857 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
858 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
859 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
860 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
862 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
863 const ARMSubtarget *Subtarget) const;
864 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
865 SDValue &Chain) const;
866 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
867 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
868 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
869 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
870 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
871 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
872 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
873 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
874 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
875 SelectionDAG &DAG) const;
876
877 Register getRegisterByName(const char* RegName, LLT VT,
878 const MachineFunction &MF) const override;
879
880 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
881 SmallVectorImpl<SDNode *> &Created) const override;
882
883 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
884 EVT VT) const override;
885
886 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
887 SDValue Val) const;
888 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
889 MVT ValVT, SDValue Val) const;
890
891 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
892
893 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
894 CallingConv::ID CallConv, bool isVarArg,
896 const SDLoc &dl, SelectionDAG &DAG,
897 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
898 SDValue ThisVal) const;
899
900 bool supportSplitCSR(MachineFunction *MF) const override {
902 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
903 }
904
905 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
906 void insertCopiesSplitCSR(
907 MachineBasicBlock *Entry,
908 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
909
910 bool splitValueIntoRegisterParts(
911 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
912 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
913 const override;
914
915 SDValue joinRegisterPartsIntoValue(
916 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
917 unsigned NumParts, MVT PartVT, EVT ValueVT,
918 std::optional<CallingConv::ID> CC) const override;
919
920 SDValue
921 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
922 const SmallVectorImpl<ISD::InputArg> &Ins,
923 const SDLoc &dl, SelectionDAG &DAG,
924 SmallVectorImpl<SDValue> &InVals) const override;
925
926 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
927 SDValue &Chain, const Value *OrigArg,
928 unsigned InRegsParamRecordIdx, int ArgOffset,
929 unsigned ArgSize) const;
930
931 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
932 const SDLoc &dl, SDValue &Chain,
933 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
934 bool ForceMutable = false) const;
935
936 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
937 SmallVectorImpl<SDValue> &InVals) const override;
938
939 /// HandleByVal - Target-specific cleanup for ByVal support.
940 void HandleByVal(CCState *, unsigned &, Align) const override;
941
942 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
943 /// for tail call optimization. Targets which want to do tail call
944 /// optimization should implement this function.
945 bool IsEligibleForTailCallOptimization(
946 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo,
947 SmallVectorImpl<CCValAssign> &ArgLocs, const bool isIndirect) const;
948
949 bool CanLowerReturn(CallingConv::ID CallConv,
950 MachineFunction &MF, bool isVarArg,
951 const SmallVectorImpl<ISD::OutputArg> &Outs,
952 LLVMContext &Context) const override;
953
954 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
955 const SmallVectorImpl<ISD::OutputArg> &Outs,
956 const SmallVectorImpl<SDValue> &OutVals,
957 const SDLoc &dl, SelectionDAG &DAG) const override;
958
959 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
960
961 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
962
963 bool shouldConsiderGEPOffsetSplit() const override { return true; }
964
965 bool isUnsupportedFloatingType(EVT VT) const;
966
967 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
968 SDValue ARMcc, SDValue CCR, SDValue Cmp,
969 SelectionDAG &DAG) const;
970 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
971 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
972 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
973 const SDLoc &dl, bool Signaling = false) const;
974 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
975
976 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
977
978 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
979 MachineBasicBlock *DispatchBB, int FI) const;
980
981 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
982
983 MachineBasicBlock *EmitStructByval(MachineInstr &MI,
984 MachineBasicBlock *MBB) const;
985
986 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
987 MachineBasicBlock *MBB) const;
988 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
989 MachineBasicBlock *MBB) const;
990 void addMVEVectorTypes(bool HasMVEFP);
991 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
992 void setAllExpand(MVT VT);
993 };
994
1001
1002 namespace ARM {
1003
1004 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1005 const TargetLibraryInfo *libInfo);
1006
1007 } // end namespace ARM
1008
1009} // end namespace llvm
1010
1011#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
This file contains the simple types necessary to represent the attributes associated with functions a...
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
PowerPC Reduce CR logical Operation
const char LLVMTargetMachineRef TM
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:77
bool isReadOnly(const GlobalValue *GV) const
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
const ARMSubtarget * getSubtarget() const
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, Align &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
bool useFPRegsForHalfType() const override
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT...
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
bool isSelectSupported(SelectSupportKind Kind) const override
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldReassociateReduction(unsigned Opc, EVT VT) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool useSoftFloat() const override
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool softPromoteHalfType() const override
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:540
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:749
CCValAssign - Represent assignment of one arg/retval to a location.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:539
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:680
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
Itinerary data supplied by a subtarget to be used by a target.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
Machine Value Type.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:318
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
Provides information about what library functions are available for the current target.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
SelectSupportKind
Enum that describes what type of support for selects the target has.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
bool isBitFieldInvertedMask(unsigned v)
const unsigned FPStatusBits
const unsigned FPReservedBits
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
const unsigned RoundingBitsPos
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1419
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1373
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1431
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1491
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1542
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
AddressSpace
Definition: NVPTXBaseInfo.h:21
@ MVEVMVNModImm
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
DWARFExpression::Operation Op
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:156