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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <optional>
34 #include <utility>
35 
36 namespace llvm {
37 
38 class ARMSubtarget;
39 class DataLayout;
40 class FastISel;
41 class FunctionLoweringInfo;
42 class GlobalValue;
43 class InstrItineraryData;
44 class Instruction;
45 class MachineBasicBlock;
46 class MachineInstr;
47 class SelectionDAG;
48 class TargetLibraryInfo;
49 class TargetMachine;
50 class TargetRegisterInfo;
51 class VectorType;
52 
53  namespace ARMISD {
54 
55  // ARM Specific DAG Nodes
56  enum NodeType : unsigned {
57  // Start the numbering where the builtin ops and target ops leave off.
59 
60  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61  // TargetExternalSymbol, and TargetGlobalAddress.
62  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63  // PIC mode.
64  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65 
66  // Add pseudo op to model memcpy for struct byval.
68 
69  CALL, // Function call.
70  CALL_PRED, // Function call that's predicable.
71  CALL_NOLINK, // Function call with branch not branch-and-link.
72  tSECALL, // CMSE non-secure function call.
73  t2CALL_BTI, // Thumb function call followed by BTI instruction.
74  BRCOND, // Conditional branch.
75  BR_JT, // Jumptable branch.
76  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
77  RET_FLAG, // Return with a flag operand.
78  SERET_FLAG, // CMSE Entry function return with a flag operand.
79  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
80 
81  PIC_ADD, // Add with a PC operand and a PIC label.
82 
83  ASRL, // MVE long arithmetic shift right.
84  LSRL, // MVE long shift right.
85  LSLL, // MVE long shift left.
86 
87  CMP, // ARM compare instructions.
88  CMN, // ARM CMN instructions.
89  CMPZ, // ARM compare that sets only Z flag.
90  CMPFP, // ARM VFP compare instruction, sets FPSCR.
91  CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
92  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
93  CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
94  // FPSCR.
95  FMSTAT, // ARM fmstat instruction.
96 
97  CMOV, // ARM conditional move instructions.
98  SUBS, // Flag-setting subtraction.
99 
100  SSAT, // Signed saturation
101  USAT, // Unsigned saturation
102 
104 
105  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
106  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
107  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
108 
109  ADDC, // Add with carry
110  ADDE, // Add using carry
111  SUBC, // Sub with carry
112  SUBE, // Sub using carry
113  LSLS, // Shift left producing carry
114 
115  VMOVRRD, // double to two gprs.
116  VMOVDRR, // Two gprs to double.
117  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
118 
119  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
120  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
121  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
122 
123  TC_RETURN, // Tail call return pseudo.
124 
126 
127  DYN_ALLOC, // Dynamic allocation on the stack.
128 
129  MEMBARRIER_MCR, // Memory barrier (MCR)
130 
131  PRELOAD, // Preload
132 
133  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
134  WIN__DBZCHK, // Windows' divide by zero check
135 
136  WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
137  WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
138  LOOP_DEC, // Really a part of LE, performs the sub
139  LE, // Low-overhead loops, Loop End
140 
141  PREDICATE_CAST, // Predicate cast for MVE i1 types
142  VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
143 
144  MVESEXT, // Legalization aids for extending a vector into two/four vectors.
145  MVEZEXT, // or truncating two/four vectors into one. Eventually becomes
146  MVETRUNC, // stack store/load sequence, if not optimized to anything else.
147 
148  VCMP, // Vector compare.
149  VCMPZ, // Vector compare to zero.
150  VTST, // Vector test bits.
151 
152  // Vector shift by vector
153  VSHLs, // ...left/right by signed
154  VSHLu, // ...left/right by unsigned
155 
156  // Vector shift by immediate:
157  VSHLIMM, // ...left
158  VSHRsIMM, // ...right (signed)
159  VSHRuIMM, // ...right (unsigned)
160 
161  // Vector rounding shift by immediate:
162  VRSHRsIMM, // ...right (signed)
163  VRSHRuIMM, // ...right (unsigned)
164  VRSHRNIMM, // ...right narrow
165 
166  // Vector saturating shift by immediate:
167  VQSHLsIMM, // ...left (signed)
168  VQSHLuIMM, // ...left (unsigned)
169  VQSHLsuIMM, // ...left (signed to unsigned)
170  VQSHRNsIMM, // ...right narrow (signed)
171  VQSHRNuIMM, // ...right narrow (unsigned)
172  VQSHRNsuIMM, // ...right narrow (signed to unsigned)
173 
174  // Vector saturating rounding shift by immediate:
175  VQRSHRNsIMM, // ...right narrow (signed)
176  VQRSHRNuIMM, // ...right narrow (unsigned)
177  VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
178 
179  // Vector shift and insert:
180  VSLIIMM, // ...left
181  VSRIIMM, // ...right
182 
183  // Vector get lane (VMOV scalar to ARM core register)
184  // (These are used for 8- and 16-bit element types only.)
185  VGETLANEu, // zero-extend vector extract element
186  VGETLANEs, // sign-extend vector extract element
187 
188  // Vector move immediate and move negated immediate:
191 
192  // Vector move f32 immediate:
194 
195  // Move H <-> R, clearing top 16 bits
198 
199  // Vector duplicate:
202 
203  // Vector shuffles:
204  VEXT, // extract
205  VREV64, // reverse elements within 64-bit doublewords
206  VREV32, // reverse elements within 32-bit words
207  VREV16, // reverse elements within 16-bit halfwords
208  VZIP, // zip (interleave)
209  VUZP, // unzip (deinterleave)
210  VTRN, // transpose
211  VTBL1, // 1-register shuffle with mask
212  VTBL2, // 2-register shuffle with mask
213  VMOVN, // MVE vmovn
214 
215  // MVE Saturating truncates
216  VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
217  VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
218 
219  // MVE float <> half converts
220  VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
221  // lanes
222  VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
223 
224  // MVE VIDUP instruction, taking a start value and increment.
226 
227  // Vector multiply long:
228  VMULLs, // ...signed
229  VMULLu, // ...unsigned
230 
231  VQDMULH, // MVE vqdmulh instruction
232 
233  // MVE reductions
234  VADDVs, // sign- or zero-extend the elements of a vector to i32,
235  VADDVu, // add them all together, and return an i32 of their sum
236  VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
238  VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
239  VADDLVu, // the low and high 32-bit halves of the sum
240  VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
241  VADDLVAu, // provided as low and high halves
242  VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
244  VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
246  VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
247  // them
248  VMLAVu, // and add the results together, returning an i32 of their sum
249  VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
251  VMLALVs, // Same as VMLAV but with i64, returning the low and
252  VMLALVu, // high 32-bit halves of the sum
253  VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
255  VMLALVAs, // Same as VMLALV but also add an input accumulator
256  VMLALVAu, // provided as low and high halves
257  VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
259  VMINVu, // Find minimum unsigned value of a vector and register
260  VMINVs, // Find minimum signed value of a vector and register
261  VMAXVu, // Find maximum unsigned value of a vector and register
262  VMAXVs, // Find maximum signed value of a vector and register
263 
264  SMULWB, // Signed multiply word by half word, bottom
265  SMULWT, // Signed multiply word by half word, top
266  UMLAL, // 64bit Unsigned Accumulate Multiply
267  SMLAL, // 64bit Signed Accumulate Multiply
268  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
269  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
270  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
271  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
272  SMLALTT, // 64-bit signed accumulate multiply top, top 16
273  SMLALD, // Signed multiply accumulate long dual
274  SMLALDX, // Signed multiply accumulate long dual exchange
275  SMLSLD, // Signed multiply subtract long dual
276  SMLSLDX, // Signed multiply subtract long dual exchange
277  SMMLAR, // Signed multiply long, round and add
278  SMMLSR, // Signed multiply long, subtract and round
279 
280  // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
281  // stands for.
290 
291  // Operands of the standard BUILD_VECTOR node are not legalized, which
292  // is fine if BUILD_VECTORs are always lowered to shuffles or other
293  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
294  // operands need to be legalized. Define an ARM-specific version of
295  // BUILD_VECTOR for this purpose.
297 
298  // Bit-field insert
300 
301  // Vector OR with immediate
303  // Vector AND with NOT of immediate
305 
306  // Pseudo vector bitwise select
308 
309  // Pseudo-instruction representing a memory copy using ldm/stm
310  // instructions.
312 
313  // Pseudo-instruction representing a memory copy using a tail predicated
314  // loop
316  // Pseudo-instruction representing a memset using a tail predicated
317  // loop
319 
320  // V8.1MMainline condition select
321  CSINV, // Conditional select invert.
322  CSNEG, // Conditional select negate.
323  CSINC, // Conditional select increment.
324 
325  // Vector load N-element structure to all lanes:
330 
331  // NEON loads with post-increment base updates:
346 
347  // NEON stores with post-increment base updates:
358 
359  // Load/Store of dual registers
362  };
363 
364  } // end namespace ARMISD
365 
366  namespace ARM {
367  /// Possible values of current rounding mode, which is specified in bits
368  /// 23:22 of FPSCR.
369  enum Rounding {
370  RN = 0, // Round to Nearest
371  RP = 1, // Round towards Plus infinity
372  RM = 2, // Round towards Minus infinity
373  RZ = 3, // Round towards Zero
374  rmMask = 3 // Bit mask selecting rounding mode
375  };
376 
377  // Bit position of rounding mode bits in FPSCR.
378  const unsigned RoundingBitsPos = 22;
379  } // namespace ARM
380 
381  /// Define some predicates that are used for node matching.
382  namespace ARM {
383 
384  bool isBitFieldInvertedMask(unsigned v);
385 
386  } // end namespace ARM
387 
388  //===--------------------------------------------------------------------===//
389  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
390 
392  public:
393  explicit ARMTargetLowering(const TargetMachine &TM,
394  const ARMSubtarget &STI);
395 
396  unsigned getJumpTableEncoding() const override;
397  bool useSoftFloat() const override;
398 
399  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
400 
401  /// ReplaceNodeResults - Replace the results of node with an illegal result
402  /// type with new values built out of custom code.
404  SelectionDAG &DAG) const override;
405 
406  const char *getTargetNodeName(unsigned Opcode) const override;
407 
408  bool isSelectSupported(SelectSupportKind Kind) const override {
409  // ARM does not support scalar condition selects on vectors.
410  return (Kind != ScalarCondVectorVal);
411  }
412 
413  bool isReadOnly(const GlobalValue *GV) const;
414 
415  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
417  EVT VT) const override;
418 
421  MachineBasicBlock *MBB) const override;
422 
424  SDNode *Node) const override;
425 
429  SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
430  SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
431  SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
432  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
433 
435  const APInt &OriginalDemandedBits,
436  const APInt &OriginalDemandedElts,
437  KnownBits &Known,
438  TargetLoweringOpt &TLO,
439  unsigned Depth) const override;
440 
441  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
442 
443  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
444  /// unaligned memory accesses of the specified type. Returns whether it
445  /// is "fast" by reference in the second argument.
446  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
447  Align Alignment,
449  unsigned *Fast) const override;
450 
452  const AttributeList &FuncAttributes) const override;
453 
454  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
455  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
456  bool isZExtFree(SDValue Val, EVT VT2) const override;
458  SmallVectorImpl<Use *> &Ops) const override;
459  Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
460 
461  bool isFNegFree(EVT VT) const override;
462 
463  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
464 
465  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
466 
467 
468  /// isLegalAddressingMode - Return true if the addressing mode represented
469  /// by AM is legal for this target, for a load/store of the specified type.
470  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
471  Type *Ty, unsigned AS,
472  Instruction *I = nullptr) const override;
473 
474  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
475 
476  /// Returns true if the addressing mode representing by AM is legal
477  /// for the Thumb1 target, for a load/store of the specified type.
478  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
479 
480  /// isLegalICmpImmediate - Return true if the specified immediate is legal
481  /// icmp immediate, that is the target has icmp instructions which can
482  /// compare a register against the immediate without having to materialize
483  /// the immediate into a register.
484  bool isLegalICmpImmediate(int64_t Imm) const override;
485 
486  /// isLegalAddImmediate - Return true if the specified immediate is legal
487  /// add immediate, that is the target has add instructions which can
488  /// add a register and the immediate without having to materialize
489  /// the immediate into a register.
490  bool isLegalAddImmediate(int64_t Imm) const override;
491 
492  /// getPreIndexedAddressParts - returns true by value, base pointer and
493  /// offset pointer and addressing mode by reference if the node's address
494  /// can be legally represented as pre-indexed load / store address.
495  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
497  SelectionDAG &DAG) const override;
498 
499  /// getPostIndexedAddressParts - returns true by value, base pointer and
500  /// offset pointer and addressing mode by reference if this node can be
501  /// combined with a load / store to form a post-indexed load / store.
503  SDValue &Offset, ISD::MemIndexedMode &AM,
504  SelectionDAG &DAG) const override;
505 
507  const APInt &DemandedElts,
508  const SelectionDAG &DAG,
509  unsigned Depth) const override;
510 
512  const APInt &DemandedElts,
513  TargetLoweringOpt &TLO) const override;
514 
515  bool ExpandInlineAsm(CallInst *CI) const override;
516 
517  ConstraintType getConstraintType(StringRef Constraint) const override;
518 
519  /// Examine constraint string and operand type and determine a weight value.
520  /// The operand object must already have been set up with the operand type.
522  AsmOperandInfo &info, const char *constraint) const override;
523 
524  std::pair<unsigned, const TargetRegisterClass *>
526  StringRef Constraint, MVT VT) const override;
527 
528  const char *LowerXConstraint(EVT ConstraintVT) const override;
529 
530  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
531  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
532  /// true it means one of the asm constraint of the inline asm instruction
533  /// being processed is 'm'.
534  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
535  std::vector<SDValue> &Ops,
536  SelectionDAG &DAG) const override;
537 
538  unsigned
539  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
540  if (ConstraintCode == "Q")
542  else if (ConstraintCode.size() == 2) {
543  if (ConstraintCode[0] == 'U') {
544  switch(ConstraintCode[1]) {
545  default:
546  break;
547  case 'm':
549  case 'n':
551  case 'q':
553  case 's':
555  case 't':
557  case 'v':
559  case 'y':
561  }
562  }
563  }
564  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
565  }
566 
567  const ARMSubtarget* getSubtarget() const {
568  return Subtarget;
569  }
570 
571  /// getRegClassFor - Return the register class that should be used for the
572  /// specified value type.
573  const TargetRegisterClass *
574  getRegClassFor(MVT VT, bool isDivergent = false) const override;
575 
576  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
577  Align &PrefAlign) const override;
578 
579  /// createFastISel - This method returns a target specific FastISel object,
580  /// or null if the target does not support "fast" ISel.
582  const TargetLibraryInfo *libInfo) const override;
583 
585 
586  bool preferZeroCompareBranch() const override { return true; }
587 
588  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
589 
590  bool
591  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
592  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
593 
594  /// isFPImmLegal - Returns true if the target can instruction select the
595  /// specified FP immediate natively. If false, the legalizer will
596  /// materialize the FP immediate as a load from a constant pool.
597  bool isFPImmLegal(const APFloat &Imm, EVT VT,
598  bool ForCodeSize = false) const override;
599 
600  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
601  const CallInst &I,
602  MachineFunction &MF,
603  unsigned Intrinsic) const override;
604 
605  /// Returns true if it is beneficial to convert a load of a constant
606  /// to just the constant itself.
608  Type *Ty) const override;
609 
610  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
611  /// with this index.
612  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
613  unsigned Index) const override;
614 
615  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
616  bool MathUsed) const override {
617  // Using overflow ops for overflow checks only should beneficial on ARM.
618  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
619  }
620 
621  /// Returns true if an argument of type Ty needs to be passed in a
622  /// contiguous block of registers in calling convention CallConv.
624  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
625  const DataLayout &DL) const override;
626 
627  /// If a physical register, this returns the register that receives the
628  /// exception address on entry to an EH pad.
629  Register
630  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
631 
632  /// If a physical register, this returns the register that receives the
633  /// exception typeid on entry to a landing pad.
634  Register
635  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
636 
639  AtomicOrdering Ord) const override;
641  AtomicOrdering Ord) const override;
642 
643  void
645 
647  AtomicOrdering Ord) const override;
649  AtomicOrdering Ord) const override;
650 
651  unsigned getMaxSupportedInterleaveFactor() const override;
652 
655  ArrayRef<unsigned> Indices,
656  unsigned Factor) const override;
658  unsigned Factor) const override;
659 
660  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
662  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
664  shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
666  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
669 
670  bool useLoadStackGuardNode() const override;
671 
672  void insertSSPDeclarations(Module &M) const override;
673  Value *getSDagStackGuard(const Module &M) const override;
674  Function *getSSPStackGuardCheck(const Module &M) const override;
675 
676  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
677  unsigned &Cost) const override;
678 
679  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
680  const MachineFunction &MF) const override {
681  // Do not merge to larger than i32.
682  return (MemVT.getSizeInBits() <= 32);
683  }
684 
685  bool isCheapToSpeculateCttz(Type *Ty) const override;
686  bool isCheapToSpeculateCtlz(Type *Ty) const override;
687 
688  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
689  return VT.isScalarInteger();
690  }
691 
692  bool supportSwiftError() const override {
693  return true;
694  }
695 
696  bool hasStandaloneRem(EVT VT) const override {
697  return HasStandaloneRem;
698  }
699 
700  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
701 
702  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
703  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
704 
705  /// Returns true if \p VecTy is a legal interleaved access type. This
706  /// function checks the vector element type and the overall width of the
707  /// vector.
708  bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
709  Align Alignment,
710  const DataLayout &DL) const;
711 
713  SDValue ConstNode) const override;
714 
715  bool alignLoopsWithOptSize() const override;
716 
717  /// Returns the number of interleaved accesses that will be generated when
718  /// lowering accesses of the given type.
719  unsigned getNumInterleavedAccesses(VectorType *VecTy,
720  const DataLayout &DL) const;
721 
722  void finalizeLowering(MachineFunction &MF) const override;
723 
724  /// Return the correct alignment for the current calling convention.
726  const DataLayout &DL) const override;
727 
729  CombineLevel Level) const override;
730 
731  bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
732 
734  CombineLevel Level) const override;
735 
736  bool preferIncOfAddToSubOfNot(EVT VT) const override;
737 
738  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
739 
740  bool isComplexDeinterleavingSupported() const override;
742  ComplexDeinterleavingOperation Operation, Type *Ty) const override;
743 
746  ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
747  Value *Accumulator = nullptr) const override;
748 
749  protected:
750  std::pair<const TargetRegisterClass *, uint8_t>
752  MVT VT) const override;
753 
754  private:
755  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
756  /// make the right decision when generating code for different targets.
757  const ARMSubtarget *Subtarget;
758 
760 
761  const InstrItineraryData *Itins;
762 
763  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
764  unsigned ARMPCLabelIndex;
765 
766  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
767  // check.
768  bool InsertFencesForAtomic;
769 
770  bool HasStandaloneRem = true;
771 
772  void addTypeForNEON(MVT VT, MVT PromotedLdStVT);
773  void addDRTypeForNEON(MVT VT);
774  void addQRTypeForNEON(MVT VT);
775  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
776 
777  using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
778 
779  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
780  SDValue &Arg, RegsToPassVector &RegsToPass,
781  CCValAssign &VA, CCValAssign &NextVA,
782  SDValue &StackPtr,
783  SmallVectorImpl<SDValue> &MemOpChains,
784  bool IsTailCall,
785  int SPDiff) const;
786  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
787  SDValue &Root, SelectionDAG &DAG,
788  const SDLoc &dl) const;
789 
790  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
791  bool isVarArg) const;
792  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
793  bool isVarArg) const;
794  std::pair<SDValue, MachinePointerInfo>
795  computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG,
796  const CCValAssign &VA, SDValue StackPtr,
797  bool IsTailCall, int SPDiff) const;
798  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
799  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
800  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
801  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
802  const ARMSubtarget *Subtarget) const;
803  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
804  const ARMSubtarget *Subtarget) const;
805  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
806  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
807  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
808  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
809  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
810  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
811  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
812  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
813  SelectionDAG &DAG) const;
814  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
815  SelectionDAG &DAG,
816  TLSModel::Model model) const;
817  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
818  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
819  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
820  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
821  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
822  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
823  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
824  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
825  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
826  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
827  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
828  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
829  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
830  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
831  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
832  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
833  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
834  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
835  const ARMSubtarget *ST) const;
836  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
837  const ARMSubtarget *ST) const;
838  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
839  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
840  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
841  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
842  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
844  SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
845  const ARMSubtarget *Subtarget) const;
846  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
847  SDValue &Chain) const;
848  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
849  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
850  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
851  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
852  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
853  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
854  SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
855  SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
856  void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
857  SelectionDAG &DAG) const;
858 
859  Register getRegisterByName(const char* RegName, LLT VT,
860  const MachineFunction &MF) const override;
861 
862  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
863  SmallVectorImpl<SDNode *> &Created) const override;
864 
865  bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
866  EVT VT) const override;
867 
868  SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
869  SDValue Val) const;
870  SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
871  MVT ValVT, SDValue Val) const;
872 
873  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
874 
875  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
876  CallingConv::ID CallConv, bool isVarArg,
878  const SDLoc &dl, SelectionDAG &DAG,
879  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
880  SDValue ThisVal) const;
881 
882  bool supportSplitCSR(MachineFunction *MF) const override {
884  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
885  }
886 
887  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
888  void insertCopiesSplitCSR(
889  MachineBasicBlock *Entry,
890  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
891 
892  bool splitValueIntoRegisterParts(
893  SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
894  unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
895  const override;
896 
897  SDValue joinRegisterPartsIntoValue(
898  SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
899  unsigned NumParts, MVT PartVT, EVT ValueVT,
900  std::optional<CallingConv::ID> CC) const override;
901 
902  SDValue
903  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
904  const SmallVectorImpl<ISD::InputArg> &Ins,
905  const SDLoc &dl, SelectionDAG &DAG,
906  SmallVectorImpl<SDValue> &InVals) const override;
907 
908  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
909  SDValue &Chain, const Value *OrigArg,
910  unsigned InRegsParamRecordIdx, int ArgOffset,
911  unsigned ArgSize) const;
912 
913  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
914  const SDLoc &dl, SDValue &Chain,
915  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
916  bool ForceMutable = false) const;
917 
918  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
919  SmallVectorImpl<SDValue> &InVals) const override;
920 
921  /// HandleByVal - Target-specific cleanup for ByVal support.
922  void HandleByVal(CCState *, unsigned &, Align) const override;
923 
924  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
925  /// for tail call optimization. Targets which want to do tail call
926  /// optimization should implement this function.
927  bool IsEligibleForTailCallOptimization(
928  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
929  bool isCalleeStructRet, bool isCallerStructRet,
930  const SmallVectorImpl<ISD::OutputArg> &Outs,
931  const SmallVectorImpl<SDValue> &OutVals,
932  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
933  const bool isIndirect) const;
934 
935  bool CanLowerReturn(CallingConv::ID CallConv,
936  MachineFunction &MF, bool isVarArg,
937  const SmallVectorImpl<ISD::OutputArg> &Outs,
938  LLVMContext &Context) const override;
939 
940  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
941  const SmallVectorImpl<ISD::OutputArg> &Outs,
942  const SmallVectorImpl<SDValue> &OutVals,
943  const SDLoc &dl, SelectionDAG &DAG) const override;
944 
945  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
946 
947  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
948 
949  bool shouldConsiderGEPOffsetSplit() const override { return true; }
950 
951  bool isUnsupportedFloatingType(EVT VT) const;
952 
953  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
954  SDValue ARMcc, SDValue CCR, SDValue Cmp,
955  SelectionDAG &DAG) const;
956  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
957  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
958  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
959  const SDLoc &dl, bool Signaling = false) const;
960  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
961 
962  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
963 
964  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
965  MachineBasicBlock *DispatchBB, int FI) const;
966 
967  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
968 
969  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
970 
971  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
972  MachineBasicBlock *MBB) const;
973 
974  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
975  MachineBasicBlock *MBB) const;
976  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
977  MachineBasicBlock *MBB) const;
978  void addMVEVectorTypes(bool HasMVEFP);
979  void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
980  void setAllExpand(MVT VT);
981  };
982 
988  };
989 
990  namespace ARM {
991 
992  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
993  const TargetLibraryInfo *libInfo);
994 
995  } // end namespace ARM
996 
997 } // end namespace llvm
998 
999 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
llvm::InlineAsm::Constraint_Uy
@ Constraint_Uy
Definition: InlineAsm.h:273
llvm::ARMTargetLowering::isLegalT1ScaledAddressingMode
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
Definition: ARMISelLowering.cpp:19364
llvm::ARMTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: ARMISelLowering.cpp:18939
llvm::ARMISD::VADDLVs
@ VADDLVs
Definition: ARMISelLowering.h:238
llvm::ARMISD::VLD3DUP_UPD
@ VLD3DUP_UPD
Definition: ARMISelLowering.h:341
llvm::ARMTargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: ARMISelLowering.cpp:20064
llvm::ARMTargetLowering::shouldAlignPointerArgs
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, Align &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
Definition: ARMISelLowering.cpp:1923
llvm::ARMTargetLowering::getRegClassFor
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
Definition: ARMISelLowering.cpp:1899
ValueTypes.h
llvm::ARMISD::VMOVN
@ VMOVN
Definition: ARMISelLowering.h:213
llvm::InlineAsm::Constraint_Un
@ Constraint_Un
Definition: InlineAsm.h:268
llvm::ARMISD::RRX
@ RRX
Definition: ARMISelLowering.h:107
llvm::ARMTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
Definition: ARMISelLowering.cpp:1881
llvm::ARMISD::QSUB16b
@ QSUB16b
Definition: ARMISelLowering.h:285
llvm::ARMISD::VMLALVs
@ VMLALVs
Definition: ARMISelLowering.h:251
llvm::ARMISD::SMLAL
@ SMLAL
Definition: ARMISelLowering.h:267
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
llvm::ARMTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: ARMISelLowering.cpp:21155
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1373
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ARMISD::MEMSETLOOP
@ MEMSETLOOP
Definition: ARMISelLowering.h:318
llvm::ARMISD::BCC_i64
@ BCC_i64
Definition: ARMISelLowering.h:103
llvm::ARMTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: ARMISelLowering.cpp:19640
llvm::ARMISD::VQSHLsuIMM
@ VQSHLsuIMM
Definition: ARMISelLowering.h:169
llvm::ARMISD::VLD2_UPD
@ VLD2_UPD
Definition: ARMISelLowering.h:333
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported
bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override
Does this target support complex deinterleaving with the given operation and type.
Definition: ARMISelLowering.cpp:21845
llvm::ARMISD::SMLALTT
@ SMLALTT
Definition: ARMISelLowering.h:272
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ARMISD::VMOVrh
@ VMOVrh
Definition: ARMISelLowering.h:196
llvm::ARMISD::CMP
@ CMP
Definition: ARMISelLowering.h:87
llvm::ARMTargetLowering::isDesirableToCommuteXorWithShift
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override
Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT...
Definition: ARMISelLowering.cpp:13637
llvm::ARMISD::SMLALBB
@ SMLALBB
Definition: ARMISelLowering.h:269
llvm::VMOVModImm
@ VMOVModImm
Definition: ARMISelLowering.h:984
llvm::ARMISD::CMPZ
@ CMPZ
Definition: ARMISelLowering.h:89
llvm::ARMISD::VADDLVAu
@ VADDLVAu
Definition: ARMISelLowering.h:241
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4569
llvm::ARMTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: ARMISelLowering.cpp:13678
llvm::ARMISD::CALL_NOLINK
@ CALL_NOLINK
Definition: ARMISelLowering.h:71
llvm::ARMISD::VLD3LN_UPD
@ VLD3LN_UPD
Definition: ARMISelLowering.h:337
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: ARMISelLowering.cpp:21237
llvm::Function
Definition: Function.h:60
StringRef.h
llvm::ARMTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: ARMISelLowering.cpp:11774
llvm::ARMISD::WLS
@ WLS
Definition: ARMISelLowering.h:136
llvm::ARMTargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: ARMISelLowering.cpp:20033
llvm::ARMISD::VMOVIMM
@ VMOVIMM
Definition: ARMISelLowering.h:189
llvm::ARMISD::PRELOAD
@ PRELOAD
Definition: ARMISelLowering.h:131
llvm::InlineAsm::Constraint_Ut
@ Constraint_Ut
Definition: InlineAsm.h:271
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::ARMISD::DYN_ALLOC
@ DYN_ALLOC
Definition: ARMISelLowering.h:127
InlineAsm.h
llvm::ARMTargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
Definition: ARMISelLowering.cpp:21390
llvm::ARMTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: ARMISelLowering.cpp:20087
llvm::ARMTargetLowering::PerformCMOVCombine
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
Definition: ARMISelLowering.cpp:18104
llvm::ARMTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: ARMISelLowering.cpp:3483
llvm::ARMISD::VIDUP
@ VIDUP
Definition: ARMISelLowering.h:225
llvm::ARM::RP
@ RP
Definition: ARMISelLowering.h:371
llvm::ARMISD::VLD1x3_UPD
@ VLD1x3_UPD
Definition: ARMISelLowering.h:344
llvm::ARMISD::VLD2DUP_UPD
@ VLD2DUP_UPD
Definition: ARMISelLowering.h:340
llvm::ARMTargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
Definition: ARMISelLowering.cpp:21543
llvm::ARM::rmMask
@ rmMask
Definition: ARMISelLowering.h:374
llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: ARMISelLowering.cpp:19991
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::ARMTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: ARMISelLowering.cpp:19381
llvm::ARMISD::LE
@ LE
Definition: ARMISelLowering.h:139
llvm::ARMISD::VBICIMM
@ VBICIMM
Definition: ARMISelLowering.h:304
llvm::ARMISD::VSHRsIMM
@ VSHRsIMM
Definition: ARMISelLowering.h:158
llvm::MemOp
Definition: TargetLowering.h:111
llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Definition: ARMISelLowering.cpp:21278
llvm::ARMISD::LDRD
@ LDRD
Definition: ARMISelLowering.h:360
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::ARMTargetLowering::alignLoopsWithOptSize
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Definition: ARMISelLowering.cpp:21323
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:21080
llvm::ARMTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2104
llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: ARMISelLowering.cpp:13661
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:391
llvm::AttributeList
Definition: Attributes.h:432
llvm::ARMISD::VQSHRNsuIMM
@ VQSHRNsuIMM
Definition: ARMISelLowering.h:172
llvm::ARMTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: ARMISelLowering.cpp:20731
llvm::ARMISD::CMPFPw0
@ CMPFPw0
Definition: ARMISelLowering.h:92
llvm::ARMISD::VDUP
@ VDUP
Definition: ARMISelLowering.h:200
llvm::ARMISD::VST1_UPD
@ VST1_UPD
Definition: ARMISelLowering.h:348
llvm::ARMISD::PIC_ADD
@ PIC_ADD
Definition: ARMISelLowering.h:81
llvm::ARMISD::FMSTAT
@ FMSTAT
Definition: ARMISelLowering.h:95
llvm::ARMISD::MEMCPY
@ MEMCPY
Definition: ARMISelLowering.h:311
llvm::ARMISD::BFI
@ BFI
Definition: ARMISelLowering.h:299
llvm::ARMISD::USAT
@ USAT
Definition: ARMISelLowering.h:101
llvm::ARMTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: ARMISelLowering.cpp:1937
llvm::ARMTargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
Definition: ARMISelLowering.h:696
llvm::ARMISD::VST4LN_UPD
@ VST4LN_UPD
Definition: ARMISelLowering.h:354
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:62
llvm::ARMISD::VZIP
@ VZIP
Definition: ARMISelLowering.h:208
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::ARMISD::WIN__CHKSTK
@ WIN__CHKSTK
Definition: ARMISelLowering.h:133
llvm::ARMISD::SSAT
@ SSAT
Definition: ARMISelLowering.h:100
llvm::ARMISD::WIN__DBZCHK
@ WIN__DBZCHK
Definition: ARMISelLowering.h:134
llvm::ARMISD::VTBL1
@ VTBL1
Definition: ARMISelLowering.h:211
llvm::ARMTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: ARMISelLowering.cpp:20962
llvm::ARMTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: ARMISelLowering.cpp:10361
llvm::ARMISD::ASRL
@ ASRL
Definition: ARMISelLowering.h:83
llvm::ARMISD::VQRSHRNsIMM
@ VQRSHRNsIMM
Definition: ARMISelLowering.h:175
llvm::ARMTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: ARMISelLowering.cpp:20229
llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: ARMISelLowering.cpp:21058
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
VectorType
Definition: ItaniumDemangle.h:1075
llvm::ARMISD::SERET_FLAG
@ SERET_FLAG
Definition: ARMISelLowering.h:78
llvm::ARMISD::SMLSLD
@ SMLSLD
Definition: ARMISelLowering.h:275
llvm::ARMTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: ARMISelLowering.cpp:19909
llvm::ARMISD::NodeType
NodeType
Definition: ARMISelLowering.h:56
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::ARMISD::VTST
@ VTST
Definition: ARMISelLowering.h:150
llvm::ARMTargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: ARMISelLowering.cpp:21836
llvm::ARMISD::VSHRuIMM
@ VSHRuIMM
Definition: ARMISelLowering.h:159
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:525
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ARMISD::VMVNIMM
@ VMVNIMM
Definition: ARMISelLowering.h:190
llvm::ARMTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Definition: ARMISelLowering.cpp:19700
llvm::ARMTargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: ARMISelLowering.cpp:21286
llvm::ARMTargetLowering::isComplexDeinterleavingSupported
bool isComplexDeinterleavingSupported() const override
Does this target support complex deinterleaving.
Definition: ARMISelLowering.cpp:21841
llvm::ARMISD::PREDICATE_CAST
@ PREDICATE_CAST
Definition: ARMISelLowering.h:141
llvm::ARMISD::SMMLAR
@ SMMLAR
Definition: ARMISelLowering.h:277
llvm::ARMTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: ARMISelLowering.cpp:21218
llvm::ARMTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: ARMISelLowering.cpp:20695
llvm::ARMISD::MVESEXT
@ MVESEXT
Definition: ARMISelLowering.h:144
llvm::ARMTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: ARMISelLowering.cpp:21241
llvm::ComplexDeinterleavingOperation
ComplexDeinterleavingOperation
Definition: ComplexDeinterleavingPass.h:36
llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
Definition: ARMISelLowering.cpp:18821
llvm::ARMTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: ARMISelLowering.cpp:18816
llvm::ARMISD::UMLAL
@ UMLAL
Definition: ARMISelLowering.h:266
llvm::ARMTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: ARMISelLowering.cpp:1666
MachineValueType.h
llvm::ARMISD::WLSSETUP
@ WLSSETUP
Definition: ARMISelLowering.h:137
llvm::ARMISD::BR2_JT
@ BR2_JT
Definition: ARMISelLowering.h:76
llvm::ARMTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: ARMISelLowering.h:408
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ARMTargetLowering::PerformIntrinsicCombine
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
Definition: ARMISelLowering.cpp:17209
llvm::ARMISD::VST2LN_UPD
@ VST2LN_UPD
Definition: ARMISelLowering.h:352
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::ARMISD::QSUB8b
@ QSUB8b
Definition: ARMISelLowering.h:283
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ARMISD::SMMLSR
@ SMMLSR
Definition: ARMISelLowering.h:278
TargetLowering.h
llvm::ARMISD::VQRSHRNsuIMM
@ VQRSHRNsuIMM
Definition: ARMISelLowering.h:177
llvm::ARMISD::VMULLs
@ VMULLs
Definition: ARMISelLowering.h:228
llvm::ARM::isBitFieldInvertedMask
bool isBitFieldInvertedMask(unsigned v)
Definition: ARMISelLowering.cpp:20700
llvm::ARMTargetLowering::shouldConvertSplatType
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Definition: ARMISelLowering.cpp:19121
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
ARMBaseInfo.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
SelectionDAGNodes.h
llvm::ARMISD::VMLALVAs
@ VMLALVAs
Definition: ARMISelLowering.h:255
llvm::ARMISD::LOOP_DEC
@ LOOP_DEC
Definition: ARMISelLowering.h:138
llvm::ARMISD::VMOVSR
@ VMOVSR
Definition: ARMISelLowering.h:117
Operation
PowerPC Reduce CR logical Operation
Definition: PPCReduceCRLogicals.cpp:735
llvm::ARMTargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: ARMISelLowering.h:679
llvm::ARMISD::t2CALL_BTI
@ t2CALL_BTI
Definition: ARMISelLowering.h:73
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::ARMISD::VQRSHRNuIMM
@ VQRSHRNuIMM
Definition: ARMISelLowering.h:176
llvm::ARMTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: ARMISelLowering.cpp:19789
llvm::ARMISD::VADDLVAs
@ VADDLVAs
Definition: ARMISelLowering.h:240
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3506
llvm::ARMTargetLowering::PerformMVEExtCombine
SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:18504
SI
@ SI
Definition: SIInstrInfo.cpp:7982
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:708
llvm::ARMISD::VQSHRNuIMM
@ VQSHRNuIMM
Definition: ARMISelLowering.h:171
llvm::ARMTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: ARMISelLowering.cpp:21222
llvm::ARMISD::SRL_FLAG
@ SRL_FLAG
Definition: ARMISelLowering.h:105
llvm::ARMISD::VREV16
@ VREV16
Definition: ARMISelLowering.h:207
llvm::dwarf::Index
Index
Definition: Dwarf.h:490
llvm::ARMTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: ARMISelLowering.cpp:1614
llvm::ARMISD::VADDLVps
@ VADDLVps
Definition: ARMISelLowering.h:242
llvm::ARMISD::SMLALDX
@ SMLALDX
Definition: ARMISelLowering.h:274
llvm::ARMISD::VCMP
@ VCMP
Definition: ARMISelLowering.h:148
llvm::ARMISD::VMLALVAu
@ VMLALVAu
Definition: ARMISelLowering.h:256
llvm::Instruction
Definition: Instruction.h:42
llvm::ARMISD::VMULLu
@ VMULLu
Definition: ARMISelLowering.h:229
llvm::ARMISD::VMOVDRR
@ VMOVDRR
Definition: ARMISelLowering.h:116
llvm::ARMISD::VLD1DUP
@ VLD1DUP
Definition: ARMISelLowering.h:326
llvm::ARMISD::VQSHLuIMM
@ VQSHLuIMM
Definition: ARMISelLowering.h:168
llvm::ARM::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: ARMISelLowering.h:378
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
llvm::ARMISD::SUBC
@ SUBC
Definition: ARMISelLowering.h:111
llvm::ARMISD::VQMOVNu
@ VQMOVNu
Definition: ARMISelLowering.h:217
llvm::ARMISD::VMINVs
@ VMINVs
Definition: ARMISelLowering.h:260
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ARMTargetLowering::PerformCMOVToBFICombine
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
Definition: ARMISelLowering.cpp:17803
llvm::ARMISD::VST3_UPD
@ VST3_UPD
Definition: ARMISelLowering.h:350
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMISD::VLD1_UPD
@ VLD1_UPD
Definition: ARMISelLowering.h:332
llvm::ARMTargetLowering::isReadOnly
bool isReadOnly(const GlobalValue *GV) const
Definition: ARMISelLowering.cpp:3876
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMISD::SMLALD
@ SMLALD
Definition: ARMISelLowering.h:273
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARMTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: ARMISelLowering.cpp:20149
llvm::ARMISD::UQADD8b
@ UQADD8b
Definition: ARMISelLowering.h:286
llvm::VMVNModImm
@ VMVNModImm
Definition: ARMISelLowering.h:985
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ARMISD::VADDLVu
@ VADDLVu
Definition: ARMISelLowering.h:239
llvm::ARMISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: ARMISelLowering.h:121
llvm::ARMTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
Definition: ARMISelLowering.cpp:13598
llvm::ARMISD::QADD8b
@ QADD8b
Definition: ARMISelLowering.h:282
llvm::ARMISD::WrapperPIC
@ WrapperPIC
Definition: ARMISelLowering.h:62
llvm::ARMTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: ARMISelLowering.cpp:18608
llvm::ARMTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: ARMISelLowering.cpp:21214
llvm::ARMTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: ARMISelLowering.h:615
llvm::ComplexDeinterleavingRotation
ComplexDeinterleavingRotation
Definition: ComplexDeinterleavingPass.h:44
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::ARMISD::LSRL
@ LSRL
Definition: ARMISelLowering.h:84
llvm::ARMISD::CSINC
@ CSINC
Definition: ARMISelLowering.h:323
llvm::ARMISD::CALL_PRED
@ CALL_PRED
Definition: ARMISelLowering.h:70
llvm::ARM::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: ARMFastISel.cpp:3079
llvm::ARMISD::VRSHRuIMM
@ VRSHRuIMM
Definition: ARMISelLowering.h:163
llvm::ARMISD::WrapperJT
@ WrapperJT
Definition: ARMISelLowering.h:64
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::ARMISD::VMLALVApu
@ VMLALVApu
Definition: ARMISelLowering.h:258
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ARMISD::SUBS
@ SUBS
Definition: ARMISelLowering.h:98
llvm::ARMISD::VBSP
@ VBSP
Definition: ARMISelLowering.h:307
llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: ARMISelLowering.cpp:21097
llvm::ARMISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: ARMISelLowering.h:119
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::APFloat
Definition: APFloat.h:716
llvm::ARMISD::VMLAVu
@ VMLAVu
Definition: ARMISelLowering.h:248
llvm::ARMISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: ARMISelLowering.h:120
llvm::ARMISD::VADDLVAps
@ VADDLVAps
Definition: ARMISelLowering.h:244
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::ARMTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: ARMISelLowering.cpp:19477
llvm::ARMISD::VEXT
@ VEXT
Definition: ARMISelLowering.h:204
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: ARMISelLowering.h:688
llvm::ARMISD::SMULWT
@ SMULWT
Definition: ARMISelLowering.h:265
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ARMISD::LSLL
@ LSLL
Definition: ARMISelLowering.h:85
llvm::ARMISD::VLD2DUP
@ VLD2DUP
Definition: ARMISelLowering.h:327
llvm::ARMISD::MEMCPYLOOP
@ MEMCPYLOOP
Definition: ARMISelLowering.h:315
llvm::ARMTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: ARMISelLowering.cpp:18998
llvm::ARMISD::VUZP
@ VUZP
Definition: ARMISelLowering.h:209
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARMISD::CMPFPEw0
@ CMPFPEw0
Definition: ARMISelLowering.h:93
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::ARMISD::VQDMULH
@ VQDMULH
Definition: ARMISelLowering.h:231
llvm::ARMISD::VCMPZ
@ VCMPZ
Definition: ARMISelLowering.h:149
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::ARMISD::RET_FLAG
@ RET_FLAG
Definition: ARMISelLowering.h:77
llvm::ARMISD::BRCOND
@ BRCOND
Definition: ARMISelLowering.h:74
llvm::ARMISD::VCVTL
@ VCVTL
Definition: ARMISelLowering.h:222
llvm::ARMTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: ARMISelLowering.h:586
llvm::ARMISD::UQSUB16b
@ UQSUB16b
Definition: ARMISelLowering.h:289
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:3090
llvm::ARMISD::VREV64
@ VREV64
Definition: ARMISelLowering.h:205
llvm::ARMISD::VLD2LN_UPD
@ VLD2LN_UPD
Definition: ARMISelLowering.h:336
llvm::ARMISD::VST4_UPD
@ VST4_UPD
Definition: ARMISelLowering.h:351
llvm::ARMISD::VMOVRRD
@ VMOVRRD
Definition: ARMISelLowering.h:115
llvm::ARMISD::COPY_STRUCT_BYVAL
@ COPY_STRUCT_BYVAL
Definition: ARMISelLowering.h:67
llvm::ARMISD::THREAD_POINTER
@ THREAD_POINTER
Definition: ARMISelLowering.h:125
llvm::ARMTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
Definition: ARMISelLowering.cpp:8325
llvm::ARMISD::STRD
@ STRD
Definition: ARMISelLowering.h:361
llvm::ARMISD::VST1x4_UPD
@ VST1x4_UPD
Definition: ARMISelLowering.h:357
llvm::ARMTargetLowering::canCombineStoreAndExtract
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
Definition: ARMISelLowering.cpp:21185
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
IRBuilder.h
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::ARMISD::VADDLVApu
@ VADDLVApu
Definition: ARMISelLowering.h:245
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::ARMISD::VMINVu
@ VMINVu
Definition: ARMISelLowering.h:259
llvm::ARMISD::VMLALVps
@ VMLALVps
Definition: ARMISelLowering.h:253
llvm::ARMISD::VSHLs
@ VSHLs
Definition: ARMISelLowering.h:153
llvm::ARMTargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: ARMISelLowering.cpp:1629
llvm::ARMTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: ARMISelLowering.cpp:21145
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::ARMISD::VECTOR_REG_CAST
@ VECTOR_REG_CAST
Definition: ARMISelLowering.h:142
llvm::ARMISD::VRSHRsIMM
@ VRSHRsIMM
Definition: ARMISelLowering.h:162
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ARMISD::VADDLVpu
@ VADDLVpu
Definition: ARMISelLowering.h:243
llvm::ARM::RM
@ RM
Definition: ARMISelLowering.h:372
llvm::ARMISD::VST3LN_UPD
@ VST3LN_UPD
Definition: ARMISelLowering.h:353
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
llvm::ARMISD::VMOVFPIMM
@ VMOVFPIMM
Definition: ARMISelLowering.h:193
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ARM::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
Definition: ARMISelLowering.h:369
llvm::ARMTargetLowering::PerformMVETruncCombine
SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:18335
llvm::ARMISD::VLD4_UPD
@ VLD4_UPD
Definition: ARMISelLowering.h:335
llvm::ARMTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: ARMISelLowering.cpp:21035
llvm::ARMISD::VADDVs
@ VADDVs
Definition: ARMISelLowering.h:234
llvm::ARMISD::VTBL2
@ VTBL2
Definition: ARMISelLowering.h:212
llvm::ARMISD::QADD16b
@ QADD16b
Definition: ARMISelLowering.h:284
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMISD::VREV32
@ VREV32
Definition: ARMISelLowering.h:206
llvm::ARMISD::VLD3_UPD
@ VLD3_UPD
Definition: ARMISelLowering.h:334
llvm::ARMISD::VSRIIMM
@ VSRIIMM
Definition: ARMISelLowering.h:181
llvm::ARMISD::VADDVu
@ VADDVu
Definition: ARMISelLowering.h:235
llvm::ARMTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: ARMISelLowering.cpp:21171
llvm::ARMISD::MVEZEXT
@ MVEZEXT
Definition: ARMISelLowering.h:145
llvm::ArrayRef< int >
llvm::ARMTargetLowering::createComplexDeinterleavingIR
Value * createComplexDeinterleavingIR(Instruction *I, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override
Create the IR node for the given complex deinterleaving operation.
Definition: ARMISelLowering.cpp:21862
RegInfo
Definition: AMDGPUAsmParser.cpp:2578
llvm::ARMISD::VGETLANEu
@ VGETLANEu
Definition: ARMISelLowering.h:185
llvm::ARMISD::VMLAVps
@ VMLAVps
Definition: ARMISelLowering.h:249
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::ARMISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: ARMISelLowering.h:58
llvm::ARMISD::VST1x2_UPD
@ VST1x2_UPD
Definition: ARMISelLowering.h:355
llvm::ARMISD::VADDVps
@ VADDVps
Definition: ARMISelLowering.h:236
llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:21125
llvm::ARMISD::VLD1x4_UPD
@ VLD1x4_UPD
Definition: ARMISelLowering.h:345
llvm::ARMTargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: ARMISelLowering.cpp:19134
llvm::ARMISD::BUILD_VECTOR
@ BUILD_VECTOR
Definition: ARMISelLowering.h:296
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
llvm::ARMISD::VLD1DUP_UPD
@ VLD1DUP_UPD
Definition: ARMISelLowering.h:339
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: ARMISelLowering.cpp:18894
llvm::ARMISD::VMOVhr
@ VMOVhr
Definition: ARMISelLowering.h:197
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMISD::CMPFPE
@ CMPFPE
Definition: ARMISelLowering.h:91
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
Node
Definition: ItaniumDemangle.h:156
llvm::ARMISD::VRSHRNIMM
@ VRSHRNIMM
Definition: ARMISelLowering.h:164
llvm::ARMISD::MVETRUNC
@ MVETRUNC
Definition: ARMISelLowering.h:146
llvm::ARMISD::VST2_UPD
@ VST2_UPD
Definition: ARMISelLowering.h:349
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::ARMISD::SMLSLDX
@ SMLSLDX
Definition: ARMISelLowering.h:276
llvm::OtherModImm
@ OtherModImm
Definition: ARMISelLowering.h:987
llvm::ARMISD::VMLAVs
@ VMLAVs
Definition: ARMISelLowering.h:246
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::ARMTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: ARMISelLowering.cpp:18922
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: ARMISelLowering.cpp:21759
llvm::ARMISD::VSLIIMM
@ VSLIIMM
Definition: ARMISelLowering.h:180
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMISD::CSNEG
@ CSNEG
Definition: ARMISelLowering.h:322
Attributes.h
llvm::ARMTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: ARMISelLowering.cpp:20117
llvm::ARMISD::UQSUB8b
@ UQSUB8b
Definition: ARMISelLowering.h:287
llvm::ARMISD::VMLALVAps
@ VMLALVAps
Definition: ARMISelLowering.h:257
llvm::ARMISD::VLD1x2_UPD
@ VLD1x2_UPD
Definition: ARMISelLowering.h:343
llvm::ARMISD::VST1x3_UPD
@ VST1x3_UPD
Definition: ARMISelLowering.h:356
llvm::ARMISD::VSHLIMM
@ VSHLIMM
Definition: ARMISelLowering.h:157
llvm::InlineAsm::Constraint_Uv
@ Constraint_Uv
Definition: InlineAsm.h:272
llvm::ARMTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: ARMISelLowering.cpp:19447
llvm::ARMISD::SMULWB
@ SMULWB
Definition: ARMISelLowering.h:264
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:626
llvm::ARMISD::VGETLANEs
@ VGETLANEs
Definition: ARMISelLowering.h:186
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::ARMISD::SRA_FLAG
@ SRA_FLAG
Definition: ARMISelLowering.h:106
CallingConvLower.h
llvm::ARMTargetLowering::makeDMB
Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const
Definition: ARMISelLowering.cpp:20980
llvm::ARMISD::VMAXVu
@ VMAXVu
Definition: ARMISelLowering.h:261
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::ARMISD::VQMOVNs
@ VQMOVNs
Definition: ARMISelLowering.h:216
llvm::ARMISD::VLD4DUP_UPD
@ VLD4DUP_UPD
Definition: ARMISelLowering.h:342
llvm::ARMTargetLowering::getSubtarget
const ARMSubtarget * getSubtarget() const
Definition: ARMISelLowering.h:567
llvm::ARMISD::VADDVpu
@ VADDVpu
Definition: ARMISelLowering.h:237
llvm::ARMTargetLowering::PerformBRCONDCombine
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
Definition: ARMISelLowering.cpp:18064
llvm::ARM::RZ
@ RZ
Definition: ARMISelLowering.h:373
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4579
llvm::ARMISD::VMLALVu
@ VMLALVu
Definition: ARMISelLowering.h:252
ISDOpcodes.h
llvm::ARMISD::UMAAL
@ UMAAL
Definition: ARMISelLowering.h:268
Function.h
llvm::ARMISD::VDUPLANE
@ VDUPLANE
Definition: ARMISelLowering.h:201
llvm::ARMISD::tSECALL
@ tSECALL
Definition: ARMISelLowering.h:72
llvm::ARMISD::CMN
@ CMN
Definition: ARMISelLowering.h:88
llvm::ARMISD::VMLALVpu
@ VMLALVpu
Definition: ARMISelLowering.h:254
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::InlineAsm::Constraint_Uq
@ Constraint_Uq
Definition: InlineAsm.h:269
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:226
llvm::ARMISD::INTRET_FLAG
@ INTRET_FLAG
Definition: ARMISelLowering.h:79
llvm::ARMTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: ARMISelLowering.cpp:21010
llvm::ARMISD::ADDE
@ ADDE
Definition: ARMISelLowering.h:110
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ARMTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: ARMISelLowering.cpp:19164
llvm::ARMISD::CSINV
@ CSINV
Definition: ARMISelLowering.h:321
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:883
llvm::ARMTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Definition: ARMISelLowering.cpp:21745
llvm::ARMISD::VQSHRNsIMM
@ VQSHRNsIMM
Definition: ARMISelLowering.h:170
llvm::InlineAsm::Constraint_Us
@ Constraint_Us
Definition: InlineAsm.h:270
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ARMTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: ARMISelLowering.cpp:20712
CodeGen.h
llvm::ARMISD::VQSHLsIMM
@ VQSHLsIMM
Definition: ARMISelLowering.h:167
llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: ARMISelLowering.cpp:21371
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2006
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::InlineAsm::Constraint_Um
@ Constraint_Um
Definition: InlineAsm.h:267
llvm::ARMTargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: ARMISelLowering.cpp:13687
SmallVector.h
llvm::ARMISD::VLD4DUP
@ VLD4DUP
Definition: ARMISelLowering.h:329
llvm::ARMISD::VCVTN
@ VCVTN
Definition: ARMISelLowering.h:220
llvm::TargetLoweringBase::ScalarCondVectorVal
@ ScalarCondVectorVal
Definition: TargetLowering.h:239
llvm::ARMTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: ARMISelLowering.cpp:20972
llvm::ARMTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: ARMISelLowering.cpp:12183
llvm::ARMTargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: ARMISelLowering.cpp:21178
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1319
llvm::ARMTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2109
N
#define N
llvm::ARMTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: ARMISelLowering.h:692
llvm::ARMISD::MEMBARRIER_MCR
@ MEMBARRIER_MCR
Definition: ARMISelLowering.h:129
llvm::ARMISD::VMLAVpu
@ VMLAVpu
Definition: ARMISelLowering.h:250
llvm::ARMTargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: ARMISelLowering.cpp:21330
llvm::ARMTargetLowering::isFNegFree
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition: ARMISelLowering.cpp:18960
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4671
llvm::ARMISD::CMPFP
@ CMPFP
Definition: ARMISelLowering.h:90
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::ARMISD::VLD3DUP
@ VLD3DUP
Definition: ARMISelLowering.h:328
llvm::ARMTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: ARMISelLowering.cpp:21775
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::ARMISD::TC_RETURN
@ TC_RETURN
Definition: ARMISelLowering.h:123
RegName
#define RegName(no)
llvm::ARMTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: ARMISelLowering.h:539
llvm::ARM_MB::MemBOpt
MemBOpt
Definition: ARMBaseInfo.h:58
llvm::ARMISD::VSHLu
@ VSHLu
Definition: ARMISelLowering.h:154
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: ARMISelLowering.cpp:10513
llvm::ARMISD::Wrapper
@ Wrapper
Definition: ARMISelLowering.h:60
llvm::ARMISD::SMLALBT
@ SMLALBT
Definition: ARMISelLowering.h:270
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::ARMTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: ARMISelLowering.cpp:19463
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MVEVMVNModImm
@ MVEVMVNModImm
Definition: ARMISelLowering.h:986
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::ARMISD::SUBE
@ SUBE
Definition: ARMISelLowering.h:112
llvm::ARMISD::CMOV
@ CMOV
Definition: ARMISelLowering.h:97
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:97
llvm::ARMISD::BR_JT
@ BR_JT
Definition: ARMISelLowering.h:75
llvm::ARMISD::UQADD16b
@ UQADD16b
Definition: ARMISelLowering.h:288
MachineFunction.h
model
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from where P can be anything The alignment inference code cannot handle loads from globals in static non mode because it doesn t look through the extra dyld stub load If you try vec_align ll without relocation model
Definition: README-SSE.txt:414
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:263
llvm::ARMISD::CALL
@ CALL
Definition: ARMISelLowering.h:69
llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Definition: ARMISelLowering.cpp:19326
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:62
llvm::ARMTargetLowering::ARMTargetLowering
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
Definition: ARMISelLowering.cpp:483
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
llvm::ARMISD::ADDC
@ ADDC
Definition: ARMISelLowering.h:109
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMISD::SMLALTB
@ SMLALTB
Definition: ARMISelLowering.h:271
llvm::ARMISD::VLD4LN_UPD
@ VLD4LN_UPD
Definition: ARMISelLowering.h:338
llvm::ARMTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: ARMISelLowering.cpp:21150
llvm::ARM::RN
@ RN
Definition: ARMISelLowering.h:370
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:237
llvm::VMOVModImmType
VMOVModImmType
Definition: ARMISelLowering.h:983
llvm::ARMISD::VORRIMM
@ VORRIMM
Definition: ARMISelLowering.h:302
llvm::ARMISD::VMAXVs
@ VMAXVs
Definition: ARMISelLowering.h:262
llvm::ARMTargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Definition: ARMISelLowering.cpp:21335
llvm::ARMISD::VTRN
@ VTRN
Definition: ARMISelLowering.h:210
llvm::ARMTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: ARMISelLowering.cpp:21782
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::ARMISD::LSLS
@ LSLS
Definition: ARMISelLowering.h:113