Go to the documentation of this file.
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
40 class FunctionLoweringInfo;
42 class InstrItineraryData;
44 class MachineBasicBlock;
47 class TargetLibraryInfo;
49 class TargetRegisterInfo;
416 EVT VT)
const override;
434 const APInt &OriginalDemandedBits,
435 const APInt &OriginalDemandedElts,
437 TargetLoweringOpt &TLO,
438 unsigned Depth)
const override;
448 bool *Fast)
const override;
470 Type *Ty,
unsigned AS,
479 unsigned AS)
const override;
514 const APInt &DemandedElts,
516 unsigned Depth)
const override;
519 const APInt &DemandedElts,
520 TargetLoweringOpt &TLO)
const override;
529 AsmOperandInfo &
info,
const char *constraint)
const override;
531 std::pair<unsigned, const TargetRegisterClass *>
542 std::vector<SDValue> &Ops,
547 if (ConstraintCode ==
"Q")
549 else if (ConstraintCode.
size() == 2) {
550 if (ConstraintCode[0] ==
'U') {
551 switch(ConstraintCode[1]) {
584 Align &PrefAlign)
const override;
603 bool ForCodeSize =
false)
const override;
608 unsigned Intrinsic)
const override;
613 Type *Ty)
const override;
618 unsigned Index)
const override;
621 bool MathUsed)
const override {
661 unsigned Factor)
const override;
663 unsigned Factor)
const override;
682 unsigned &Cost)
const override;
702 return HasStandaloneRem;
718 SDValue ConstNode)
const override;
744 std::pair<const TargetRegisterClass *, uint8_t>
746 MVT VT)
const override;
758 unsigned ARMPCLabelIndex;
762 bool InsertFencesForAtomic;
764 bool HasStandaloneRem =
true;
766 void addTypeForNEON(
MVT VT,
MVT PromotedLdStVT);
767 void addDRTypeForNEON(
MVT VT);
768 void addQRTypeForNEON(
MVT VT);
782 const SDLoc &dl)
const;
785 bool isVarArg)
const;
787 bool isVarArg)
const;
788 std::pair<SDValue, MachinePointerInfo>
791 bool IsTailCall,
int SPDiff)
const;
860 EVT VT)
const override;
881 void initializeSplitCSR(MachineBasicBlock *Entry)
const override;
882 void insertCopiesSplitCSR(
883 MachineBasicBlock *Entry,
884 const SmallVectorImpl<MachineBasicBlock *> &Exits)
const override;
887 splitValueIntoRegisterParts(SelectionDAG &DAG,
const SDLoc &
DL, SDValue Val,
888 SDValue *Parts,
unsigned NumParts, MVT PartVT,
889 Optional<CallingConv::ID> CC)
const override;
892 joinRegisterPartsIntoValue(SelectionDAG &DAG,
const SDLoc &
DL,
893 const SDValue *Parts,
unsigned NumParts,
894 MVT PartVT, EVT ValueVT,
895 Optional<CallingConv::ID> CC)
const override;
898 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
899 const SmallVectorImpl<ISD::InputArg> &
Ins,
900 const SDLoc &dl, SelectionDAG &DAG,
901 SmallVectorImpl<SDValue> &InVals)
const override;
903 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
const SDLoc &dl,
904 SDValue &Chain,
const Value *OrigArg,
905 unsigned InRegsParamRecordIdx,
int ArgOffset,
906 unsigned ArgSize)
const;
908 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
909 const SDLoc &dl, SDValue &Chain,
910 unsigned ArgOffset,
unsigned TotalArgRegsSaveSize,
911 bool ForceMutable =
false)
const;
913 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
914 SmallVectorImpl<SDValue> &InVals)
const override;
917 void HandleByVal(CCState *,
unsigned &,
Align)
const override;
922 bool IsEligibleForTailCallOptimization(
924 bool isCalleeStructRet,
bool isCallerStructRet,
925 const SmallVectorImpl<ISD::OutputArg> &Outs,
926 const SmallVectorImpl<SDValue> &OutVals,
927 const SmallVectorImpl<ISD::InputArg> &
Ins, SelectionDAG &DAG,
928 const bool isIndirect)
const;
931 MachineFunction &MF,
bool isVarArg,
932 const SmallVectorImpl<ISD::OutputArg> &Outs,
933 LLVMContext &
Context)
const override;
935 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
936 const SmallVectorImpl<ISD::OutputArg> &Outs,
937 const SmallVectorImpl<SDValue> &OutVals,
938 const SDLoc &dl, SelectionDAG &DAG)
const override;
940 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
942 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
944 bool shouldConsiderGEPOffsetSplit()
const override {
return true; }
946 bool isUnsupportedFloatingType(EVT VT)
const;
948 SDValue getCMOV(
const SDLoc &dl, EVT VT, SDValue
FalseVal, SDValue
TrueVal,
949 SDValue ARMcc, SDValue CCR, SDValue Cmp,
950 SelectionDAG &DAG)
const;
952 SDValue &ARMcc, SelectionDAG &DAG,
const SDLoc &dl)
const;
953 SDValue getVFPCmp(SDValue
LHS, SDValue
RHS, SelectionDAG &DAG,
954 const SDLoc &dl,
bool Signaling =
false)
const;
955 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG)
const;
957 SDValue OptimizeVFPBrcond(SDValue
Op, SelectionDAG &DAG)
const;
959 void SetupEntryBlockForSjLj(MachineInstr &
MI, MachineBasicBlock *
MBB,
960 MachineBasicBlock *DispatchBB,
int FI)
const;
962 void EmitSjLjDispatchBlock(MachineInstr &
MI, MachineBasicBlock *
MBB)
const;
964 bool RemapAddSubWithFlags(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
966 MachineBasicBlock *EmitStructByval(MachineInstr &
MI,
967 MachineBasicBlock *
MBB)
const;
969 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &
MI,
970 MachineBasicBlock *
MBB)
const;
971 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &
MI,
972 MachineBasicBlock *
MBB)
const;
973 void addMVEVectorTypes(
bool HasMVEFP);
975 void setAllExpand(MVT VT);
988 const TargetLibraryInfo *libInfo);
994 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, Align &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
This is an optimization pass for GlobalISel generic memory operations.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Represents one node in the SelectionDAG.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
The instances of the Type class are immutable: once they are created, they are never changed.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
Function Alias Analysis Results
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Class to represent fixed width SIMD vectors.
unsigned const TargetRegisterInfo * TRI
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isSelectSupported(SelectSupportKind Kind) const override
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
bool isBitFieldInvertedMask(unsigned v)
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
CCValAssign - Represent assignment of one arg/retval to a location.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
bool useSoftFloat() const override
const unsigned RoundingBitsPos
Analysis containing CSE Info
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isReadOnly(const GlobalValue *GV) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Base class of all SIMD vector types.
AtomicOrdering
Atomic ordering for LLVM's memory model.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
An instruction for storing to memory.
This is an important base class in LLVM.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Representation of each machine instruction.
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
This is an important class for using LLVM in a threaded context.
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
Flags
Flags values. These may be or'd together.
Primary interface to the complete machine description for the target machine.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
StandardInstrumentations SI(Debug, VerifyEach)
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
A Module instance is used to store all the information related to an LLVM module.
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Class for arbitrary precision integers.
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
StringRef - Represent a constant reference to a string, i.e.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Common base class shared among various IRBuilders.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
An instruction for reading from memory.
an instruction that atomically reads a memory location, combines it with another value,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Wrapper class representing virtual and physical registers.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Function & getFunction()
Return the LLVM function that this machine code represents.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const
const ARMSubtarget * getSubtarget() const
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
Provides information about what library functions are available for the current target.
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
This instruction constructs a fixed permutation of two input vectors.
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
const char LLVMTargetMachineRef TM
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
This class represents a function call, abstracting a target machine's calling convention.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
BlockVerifier::State From
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from where P can be anything The alignment inference code cannot handle loads from globals in static non mode because it doesn t look through the extra dyld stub load If you try vec_align ll without relocation model
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
LLVM Value Representation.
An instruction that atomically checks whether a specified value is in a memory location,...
Itinerary data supplied by a subtarget to be used by a target.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
SelectSupportKind
Enum that describes what type of support for selects the target has.
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...