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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <utility>
34 
35 namespace llvm {
36 
37 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
42 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
51 
52  namespace ARMISD {
53 
54  // ARM Specific DAG Nodes
55  enum NodeType : unsigned {
56  // Start the numbering where the builtin ops and target ops leave off.
58 
59  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
60  // TargetExternalSymbol, and TargetGlobalAddress.
61  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
62  // PIC mode.
63  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
64 
65  // Add pseudo op to model memcpy for struct byval.
67 
68  CALL, // Function call.
69  CALL_PRED, // Function call that's predicable.
70  CALL_NOLINK, // Function call with branch not branch-and-link.
71  tSECALL, // CMSE non-secure function call.
72  t2CALL_BTI, // Thumb function call followed by BTI instruction.
73  BRCOND, // Conditional branch.
74  BR_JT, // Jumptable branch.
75  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
76  RET_FLAG, // Return with a flag operand.
77  SERET_FLAG, // CMSE Entry function return with a flag operand.
78  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
79 
80  PIC_ADD, // Add with a PC operand and a PIC label.
81 
82  ASRL, // MVE long arithmetic shift right.
83  LSRL, // MVE long shift right.
84  LSLL, // MVE long shift left.
85 
86  CMP, // ARM compare instructions.
87  CMN, // ARM CMN instructions.
88  CMPZ, // ARM compare that sets only Z flag.
89  CMPFP, // ARM VFP compare instruction, sets FPSCR.
90  CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
91  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
92  CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets
93  // FPSCR.
94  FMSTAT, // ARM fmstat instruction.
95 
96  CMOV, // ARM conditional move instructions.
97  SUBS, // Flag-setting subtraction.
98 
99  SSAT, // Signed saturation
100  USAT, // Unsigned saturation
101 
103 
104  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
105  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
106  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
107 
108  ADDC, // Add with carry
109  ADDE, // Add using carry
110  SUBC, // Sub with carry
111  SUBE, // Sub using carry
112  LSLS, // Shift left producing carry
113 
114  VMOVRRD, // double to two gprs.
115  VMOVDRR, // Two gprs to double.
116  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
117 
118  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
119  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
120  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
121 
122  TC_RETURN, // Tail call return pseudo.
123 
125 
126  DYN_ALLOC, // Dynamic allocation on the stack.
127 
128  MEMBARRIER_MCR, // Memory barrier (MCR)
129 
130  PRELOAD, // Preload
131 
132  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
133  WIN__DBZCHK, // Windows' divide by zero check
134 
135  WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
136  WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup.
137  LOOP_DEC, // Really a part of LE, performs the sub
138  LE, // Low-overhead loops, Loop End
139 
140  PREDICATE_CAST, // Predicate cast for MVE i1 types
141  VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
142 
143  MVESEXT, // Legalization aids for extending a vector into two/four vectors.
144  MVEZEXT, // or truncating two/four vectors into one. Eventually becomes
145  MVETRUNC, // stack store/load sequence, if not optimized to anything else.
146 
147  VCMP, // Vector compare.
148  VCMPZ, // Vector compare to zero.
149  VTST, // Vector test bits.
150 
151  // Vector shift by vector
152  VSHLs, // ...left/right by signed
153  VSHLu, // ...left/right by unsigned
154 
155  // Vector shift by immediate:
156  VSHLIMM, // ...left
157  VSHRsIMM, // ...right (signed)
158  VSHRuIMM, // ...right (unsigned)
159 
160  // Vector rounding shift by immediate:
161  VRSHRsIMM, // ...right (signed)
162  VRSHRuIMM, // ...right (unsigned)
163  VRSHRNIMM, // ...right narrow
164 
165  // Vector saturating shift by immediate:
166  VQSHLsIMM, // ...left (signed)
167  VQSHLuIMM, // ...left (unsigned)
168  VQSHLsuIMM, // ...left (signed to unsigned)
169  VQSHRNsIMM, // ...right narrow (signed)
170  VQSHRNuIMM, // ...right narrow (unsigned)
171  VQSHRNsuIMM, // ...right narrow (signed to unsigned)
172 
173  // Vector saturating rounding shift by immediate:
174  VQRSHRNsIMM, // ...right narrow (signed)
175  VQRSHRNuIMM, // ...right narrow (unsigned)
176  VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
177 
178  // Vector shift and insert:
179  VSLIIMM, // ...left
180  VSRIIMM, // ...right
181 
182  // Vector get lane (VMOV scalar to ARM core register)
183  // (These are used for 8- and 16-bit element types only.)
184  VGETLANEu, // zero-extend vector extract element
185  VGETLANEs, // sign-extend vector extract element
186 
187  // Vector move immediate and move negated immediate:
190 
191  // Vector move f32 immediate:
193 
194  // Move H <-> R, clearing top 16 bits
197 
198  // Vector duplicate:
201 
202  // Vector shuffles:
203  VEXT, // extract
204  VREV64, // reverse elements within 64-bit doublewords
205  VREV32, // reverse elements within 32-bit words
206  VREV16, // reverse elements within 16-bit halfwords
207  VZIP, // zip (interleave)
208  VUZP, // unzip (deinterleave)
209  VTRN, // transpose
210  VTBL1, // 1-register shuffle with mask
211  VTBL2, // 2-register shuffle with mask
212  VMOVN, // MVE vmovn
213 
214  // MVE Saturating truncates
215  VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
216  VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
217 
218  // MVE float <> half converts
219  VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
220  // lanes
221  VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
222 
223  // MVE VIDUP instruction, taking a start value and increment.
225 
226  // Vector multiply long:
227  VMULLs, // ...signed
228  VMULLu, // ...unsigned
229 
230  VQDMULH, // MVE vqdmulh instruction
231 
232  // MVE reductions
233  VADDVs, // sign- or zero-extend the elements of a vector to i32,
234  VADDVu, // add them all together, and return an i32 of their sum
235  VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
237  VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
238  VADDLVu, // the low and high 32-bit halves of the sum
239  VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
240  VADDLVAu, // provided as low and high halves
241  VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
243  VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
245  VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
246  // them
247  VMLAVu, // and add the results together, returning an i32 of their sum
248  VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
250  VMLALVs, // Same as VMLAV but with i64, returning the low and
251  VMLALVu, // high 32-bit halves of the sum
252  VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
254  VMLALVAs, // Same as VMLALV but also add an input accumulator
255  VMLALVAu, // provided as low and high halves
256  VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
258  VMINVu, // Find minimum unsigned value of a vector and register
259  VMINVs, // Find minimum signed value of a vector and register
260  VMAXVu, // Find maximum unsigned value of a vector and register
261  VMAXVs, // Find maximum signed value of a vector and register
262 
263  SMULWB, // Signed multiply word by half word, bottom
264  SMULWT, // Signed multiply word by half word, top
265  UMLAL, // 64bit Unsigned Accumulate Multiply
266  SMLAL, // 64bit Signed Accumulate Multiply
267  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
268  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
269  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
270  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
271  SMLALTT, // 64-bit signed accumulate multiply top, top 16
272  SMLALD, // Signed multiply accumulate long dual
273  SMLALDX, // Signed multiply accumulate long dual exchange
274  SMLSLD, // Signed multiply subtract long dual
275  SMLSLDX, // Signed multiply subtract long dual exchange
276  SMMLAR, // Signed multiply long, round and add
277  SMMLSR, // Signed multiply long, subtract and round
278 
279  // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b
280  // stands for.
289 
290  // Operands of the standard BUILD_VECTOR node are not legalized, which
291  // is fine if BUILD_VECTORs are always lowered to shuffles or other
292  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
293  // operands need to be legalized. Define an ARM-specific version of
294  // BUILD_VECTOR for this purpose.
296 
297  // Bit-field insert
299 
300  // Vector OR with immediate
302  // Vector AND with NOT of immediate
304 
305  // Pseudo vector bitwise select
307 
308  // Pseudo-instruction representing a memory copy using ldm/stm
309  // instructions.
311 
312  // Pseudo-instruction representing a memory copy using a tail predicated
313  // loop
315  // Pseudo-instruction representing a memset using a tail predicated
316  // loop
318 
319  // V8.1MMainline condition select
320  CSINV, // Conditional select invert.
321  CSNEG, // Conditional select negate.
322  CSINC, // Conditional select increment.
323 
324  // Vector load N-element structure to all lanes:
329 
330  // NEON loads with post-increment base updates:
345 
346  // NEON stores with post-increment base updates:
357 
358  // Load/Store of dual registers
361  };
362 
363  } // end namespace ARMISD
364 
365  namespace ARM {
366  /// Possible values of current rounding mode, which is specified in bits
367  /// 23:22 of FPSCR.
368  enum Rounding {
369  RN = 0, // Round to Nearest
370  RP = 1, // Round towards Plus infinity
371  RM = 2, // Round towards Minus infinity
372  RZ = 3, // Round towards Zero
373  rmMask = 3 // Bit mask selecting rounding mode
374  };
375 
376  // Bit position of rounding mode bits in FPSCR.
377  const unsigned RoundingBitsPos = 22;
378  } // namespace ARM
379 
380  /// Define some predicates that are used for node matching.
381  namespace ARM {
382 
383  bool isBitFieldInvertedMask(unsigned v);
384 
385  } // end namespace ARM
386 
387  //===--------------------------------------------------------------------===//
388  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
389 
391  public:
392  explicit ARMTargetLowering(const TargetMachine &TM,
393  const ARMSubtarget &STI);
394 
395  unsigned getJumpTableEncoding() const override;
396  bool useSoftFloat() const override;
397 
398  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
399 
400  /// ReplaceNodeResults - Replace the results of node with an illegal result
401  /// type with new values built out of custom code.
403  SelectionDAG &DAG) const override;
404 
405  const char *getTargetNodeName(unsigned Opcode) const override;
406 
407  bool isSelectSupported(SelectSupportKind Kind) const override {
408  // ARM does not support scalar condition selects on vectors.
409  return (Kind != ScalarCondVectorVal);
410  }
411 
412  bool isReadOnly(const GlobalValue *GV) const;
413 
414  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
416  EVT VT) const override;
417 
420  MachineBasicBlock *MBB) const override;
421 
423  SDNode *Node) const override;
424 
428  SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
429  SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
430  SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
431  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
432 
434  const APInt &OriginalDemandedBits,
435  const APInt &OriginalDemandedElts,
436  KnownBits &Known,
437  TargetLoweringOpt &TLO,
438  unsigned Depth) const override;
439 
440  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
441 
442  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
443  /// unaligned memory accesses of the specified type. Returns whether it
444  /// is "fast" by reference in the second argument.
445  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
446  Align Alignment,
448  bool *Fast) const override;
449 
451  const AttributeList &FuncAttributes) const override;
452 
453  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
454  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
455  bool isZExtFree(SDValue Val, EVT VT2) const override;
457  SmallVectorImpl<Use *> &Ops) const override;
458  Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
459 
460  bool isFNegFree(EVT VT) const override;
461 
462  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
463 
464  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
465 
466 
467  /// isLegalAddressingMode - Return true if the addressing mode represented
468  /// by AM is legal for this target, for a load/store of the specified type.
469  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
470  Type *Ty, unsigned AS,
471  Instruction *I = nullptr) const override;
472 
473  /// getScalingFactorCost - Return the cost of the scaling used in
474  /// addressing mode represented by AM.
475  /// If the AM is supported, the return value must be >= 0.
476  /// If the AM is not supported, the return value must be negative.
478  const AddrMode &AM, Type *Ty,
479  unsigned AS) const override;
480 
481  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
482 
483  /// Returns true if the addressing mode representing by AM is legal
484  /// for the Thumb1 target, for a load/store of the specified type.
485  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
486 
487  /// isLegalICmpImmediate - Return true if the specified immediate is legal
488  /// icmp immediate, that is the target has icmp instructions which can
489  /// compare a register against the immediate without having to materialize
490  /// the immediate into a register.
491  bool isLegalICmpImmediate(int64_t Imm) const override;
492 
493  /// isLegalAddImmediate - Return true if the specified immediate is legal
494  /// add immediate, that is the target has add instructions which can
495  /// add a register and the immediate without having to materialize
496  /// the immediate into a register.
497  bool isLegalAddImmediate(int64_t Imm) const override;
498 
499  /// getPreIndexedAddressParts - returns true by value, base pointer and
500  /// offset pointer and addressing mode by reference if the node's address
501  /// can be legally represented as pre-indexed load / store address.
504  SelectionDAG &DAG) const override;
505 
506  /// getPostIndexedAddressParts - returns true by value, base pointer and
507  /// offset pointer and addressing mode by reference if this node can be
508  /// combined with a load / store to form a post-indexed load / store.
511  SelectionDAG &DAG) const override;
512 
514  const APInt &DemandedElts,
515  const SelectionDAG &DAG,
516  unsigned Depth) const override;
517 
519  const APInt &DemandedElts,
520  TargetLoweringOpt &TLO) const override;
521 
522  bool ExpandInlineAsm(CallInst *CI) const override;
523 
524  ConstraintType getConstraintType(StringRef Constraint) const override;
525 
526  /// Examine constraint string and operand type and determine a weight value.
527  /// The operand object must already have been set up with the operand type.
529  AsmOperandInfo &info, const char *constraint) const override;
530 
531  std::pair<unsigned, const TargetRegisterClass *>
533  StringRef Constraint, MVT VT) const override;
534 
535  const char *LowerXConstraint(EVT ConstraintVT) const override;
536 
537  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
538  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
539  /// true it means one of the asm constraint of the inline asm instruction
540  /// being processed is 'm'.
541  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
542  std::vector<SDValue> &Ops,
543  SelectionDAG &DAG) const override;
544 
545  unsigned
546  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
547  if (ConstraintCode == "Q")
549  else if (ConstraintCode.size() == 2) {
550  if (ConstraintCode[0] == 'U') {
551  switch(ConstraintCode[1]) {
552  default:
553  break;
554  case 'm':
556  case 'n':
558  case 'q':
560  case 's':
562  case 't':
564  case 'v':
566  case 'y':
568  }
569  }
570  }
571  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
572  }
573 
574  const ARMSubtarget* getSubtarget() const {
575  return Subtarget;
576  }
577 
578  /// getRegClassFor - Return the register class that should be used for the
579  /// specified value type.
580  const TargetRegisterClass *
581  getRegClassFor(MVT VT, bool isDivergent = false) const override;
582 
583  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
584  unsigned &PrefAlign) const override;
585 
586  /// createFastISel - This method returns a target specific FastISel object,
587  /// or null if the target does not support "fast" ISel.
589  const TargetLibraryInfo *libInfo) const override;
590 
592 
593  bool preferZeroCompareBranch() const override { return true; }
594 
595  bool
596  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
597  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
598 
599  /// isFPImmLegal - Returns true if the target can instruction select the
600  /// specified FP immediate natively. If false, the legalizer will
601  /// materialize the FP immediate as a load from a constant pool.
602  bool isFPImmLegal(const APFloat &Imm, EVT VT,
603  bool ForCodeSize = false) const override;
604 
605  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
606  const CallInst &I,
607  MachineFunction &MF,
608  unsigned Intrinsic) const override;
609 
610  /// Returns true if it is beneficial to convert a load of a constant
611  /// to just the constant itself.
613  Type *Ty) const override;
614 
615  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
616  /// with this index.
617  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
618  unsigned Index) const override;
619 
620  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
621  bool MathUsed) const override {
622  // Using overflow ops for overflow checks only should beneficial on ARM.
623  return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
624  }
625 
626  /// Returns true if an argument of type Ty needs to be passed in a
627  /// contiguous block of registers in calling convention CallConv.
629  Type *Ty, CallingConv::ID CallConv, bool isVarArg,
630  const DataLayout &DL) const override;
631 
632  /// If a physical register, this returns the register that receives the
633  /// exception address on entry to an EH pad.
634  Register
635  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
636 
637  /// If a physical register, this returns the register that receives the
638  /// exception typeid on entry to a landing pad.
639  Register
640  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
641 
644  AtomicOrdering Ord) const override;
646  AtomicOrdering Ord) const override;
647 
648  void
650 
652  AtomicOrdering Ord) const override;
654  AtomicOrdering Ord) const override;
655 
656  unsigned getMaxSupportedInterleaveFactor() const override;
657 
660  ArrayRef<unsigned> Indices,
661  unsigned Factor) const override;
663  unsigned Factor) const override;
664 
665  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
667  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
668  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
670  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
673 
674  bool useLoadStackGuardNode() const override;
675 
676  void insertSSPDeclarations(Module &M) const override;
677  Value *getSDagStackGuard(const Module &M) const override;
678  Function *getSSPStackGuardCheck(const Module &M) const override;
679 
680  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
681  unsigned &Cost) const override;
682 
683  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
684  const MachineFunction &MF) const override {
685  // Do not merge to larger than i32.
686  return (MemVT.getSizeInBits() <= 32);
687  }
688 
689  bool isCheapToSpeculateCttz() const override;
690  bool isCheapToSpeculateCtlz() const override;
691 
692  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
693  return VT.isScalarInteger();
694  }
695 
696  bool supportSwiftError() const override {
697  return true;
698  }
699 
700  bool hasStandaloneRem(EVT VT) const override {
701  return HasStandaloneRem;
702  }
703 
704  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
705 
706  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
707  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
708 
709  /// Returns true if \p VecTy is a legal interleaved access type. This
710  /// function checks the vector element type and the overall width of the
711  /// vector.
712  bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
713  Align Alignment,
714  const DataLayout &DL) const;
715 
716  bool isMulAddWithConstProfitable(const SDValue &AddNode,
717  const SDValue &ConstNode) const override;
718 
719  bool alignLoopsWithOptSize() const override;
720 
721  /// Returns the number of interleaved accesses that will be generated when
722  /// lowering accesses of the given type.
723  unsigned getNumInterleavedAccesses(VectorType *VecTy,
724  const DataLayout &DL) const;
725 
726  void finalizeLowering(MachineFunction &MF) const override;
727 
728  /// Return the correct alignment for the current calling convention.
730  const DataLayout &DL) const override;
731 
733  CombineLevel Level) const override;
734 
736  CombineLevel Level) const override;
737 
738  bool preferIncOfAddToSubOfNot(EVT VT) const override;
739 
740  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
741 
742  protected:
743  std::pair<const TargetRegisterClass *, uint8_t>
745  MVT VT) const override;
746 
747  private:
748  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
749  /// make the right decision when generating code for different targets.
750  const ARMSubtarget *Subtarget;
751 
753 
754  const InstrItineraryData *Itins;
755 
756  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
757  unsigned ARMPCLabelIndex;
758 
759  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
760  // check.
761  bool InsertFencesForAtomic;
762 
763  bool HasStandaloneRem = true;
764 
765  void addTypeForNEON(MVT VT, MVT PromotedLdStVT);
766  void addDRTypeForNEON(MVT VT);
767  void addQRTypeForNEON(MVT VT);
768  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
769 
770  using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
771 
772  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
773  SDValue &Arg, RegsToPassVector &RegsToPass,
774  CCValAssign &VA, CCValAssign &NextVA,
775  SDValue &StackPtr,
776  SmallVectorImpl<SDValue> &MemOpChains,
777  bool IsTailCall,
778  int SPDiff) const;
779  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
780  SDValue &Root, SelectionDAG &DAG,
781  const SDLoc &dl) const;
782 
783  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
784  bool isVarArg) const;
785  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
786  bool isVarArg) const;
787  std::pair<SDValue, MachinePointerInfo>
788  computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG,
789  const CCValAssign &VA, SDValue StackPtr,
790  bool IsTailCall, int SPDiff) const;
791  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
792  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
793  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
794  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
795  const ARMSubtarget *Subtarget) const;
796  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
797  const ARMSubtarget *Subtarget) const;
798  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
799  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
800  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
801  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
802  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
803  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
804  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
805  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
806  SelectionDAG &DAG) const;
807  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
808  SelectionDAG &DAG,
809  TLSModel::Model model) const;
810  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
811  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
812  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
813  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
814  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
815  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
816  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
817  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
818  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
819  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
820  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
821  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
822  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
823  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
824  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
825  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
826  SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
827  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
828  const ARMSubtarget *ST) const;
829  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
830  const ARMSubtarget *ST) const;
831  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
832  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
833  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
834  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
835  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
837  SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
838  const ARMSubtarget *Subtarget) const;
839  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
840  SDValue &Chain) const;
841  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
842  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
843  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
844  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
845  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
846  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
847  SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
848  void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
849  SelectionDAG &DAG) const;
850  void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
851  SelectionDAG &DAG) const;
852 
853  Register getRegisterByName(const char* RegName, LLT VT,
854  const MachineFunction &MF) const override;
855 
856  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
857  SmallVectorImpl<SDNode *> &Created) const override;
858 
859  bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
860  EVT VT) const override;
861 
862  SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
863  SDValue Val) const;
864  SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
865  MVT ValVT, SDValue Val) const;
866 
867  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
868 
869  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
870  CallingConv::ID CallConv, bool isVarArg,
872  const SDLoc &dl, SelectionDAG &DAG,
873  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
874  SDValue ThisVal) const;
875 
876  bool supportSplitCSR(MachineFunction *MF) const override {
878  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
879  }
880 
881  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
882  void insertCopiesSplitCSR(
883  MachineBasicBlock *Entry,
884  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
885 
886  bool
887  splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
888  SDValue *Parts, unsigned NumParts, MVT PartVT,
889  Optional<CallingConv::ID> CC) const override;
890 
891  SDValue
892  joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
893  const SDValue *Parts, unsigned NumParts,
894  MVT PartVT, EVT ValueVT,
895  Optional<CallingConv::ID> CC) const override;
896 
897  SDValue
898  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
899  const SmallVectorImpl<ISD::InputArg> &Ins,
900  const SDLoc &dl, SelectionDAG &DAG,
901  SmallVectorImpl<SDValue> &InVals) const override;
902 
903  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
904  SDValue &Chain, const Value *OrigArg,
905  unsigned InRegsParamRecordIdx, int ArgOffset,
906  unsigned ArgSize) const;
907 
908  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
909  const SDLoc &dl, SDValue &Chain,
910  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
911  bool ForceMutable = false) const;
912 
913  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
914  SmallVectorImpl<SDValue> &InVals) const override;
915 
916  /// HandleByVal - Target-specific cleanup for ByVal support.
917  void HandleByVal(CCState *, unsigned &, Align) const override;
918 
919  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
920  /// for tail call optimization. Targets which want to do tail call
921  /// optimization should implement this function.
922  bool IsEligibleForTailCallOptimization(
923  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
924  bool isCalleeStructRet, bool isCallerStructRet,
925  const SmallVectorImpl<ISD::OutputArg> &Outs,
926  const SmallVectorImpl<SDValue> &OutVals,
927  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
928  const bool isIndirect) const;
929 
930  bool CanLowerReturn(CallingConv::ID CallConv,
931  MachineFunction &MF, bool isVarArg,
932  const SmallVectorImpl<ISD::OutputArg> &Outs,
933  LLVMContext &Context) const override;
934 
935  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
936  const SmallVectorImpl<ISD::OutputArg> &Outs,
937  const SmallVectorImpl<SDValue> &OutVals,
938  const SDLoc &dl, SelectionDAG &DAG) const override;
939 
940  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
941 
942  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
943 
944  bool shouldConsiderGEPOffsetSplit() const override { return true; }
945 
946  bool isUnsupportedFloatingType(EVT VT) const;
947 
948  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
949  SDValue ARMcc, SDValue CCR, SDValue Cmp,
950  SelectionDAG &DAG) const;
951  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
952  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
953  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
954  const SDLoc &dl, bool Signaling = false) const;
955  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
956 
957  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
958 
959  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
960  MachineBasicBlock *DispatchBB, int FI) const;
961 
962  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
963 
964  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
965 
966  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
967  MachineBasicBlock *MBB) const;
968 
969  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
970  MachineBasicBlock *MBB) const;
971  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
972  MachineBasicBlock *MBB) const;
973  void addMVEVectorTypes(bool HasMVEFP);
974  void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
975  void setAllExpand(MVT VT);
976  };
977 
983  };
984 
985  namespace ARM {
986 
987  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
988  const TargetLibraryInfo *libInfo);
989 
990  } // end namespace ARM
991 
992 } // end namespace llvm
993 
994 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
llvm::ARMTargetLowering::isLegalT1ScaledAddressingMode
bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...
Definition: ARMISelLowering.cpp:19244
llvm::ARMTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: ARMISelLowering.cpp:18807
llvm::ARMISD::VADDLVs
@ VADDLVs
Definition: ARMISelLowering.h:237
llvm::ARMISD::VLD3DUP_UPD
@ VLD3DUP_UPD
Definition: ARMISelLowering.h:340
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::ARMTargetLowering::LowerXConstraint
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
Definition: ARMISelLowering.cpp:19936
llvm::InlineAsm::Constraint_Ut
@ Constraint_Ut
Definition: InlineAsm.h:264
llvm::ARMTargetLowering::getRegClassFor
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override
getRegClassFor - Return the register class that should be used for the specified value type.
Definition: ARMISelLowering.cpp:1879
ValueTypes.h
llvm::ARMISD::VMOVN
@ VMOVN
Definition: ARMISelLowering.h:212
llvm::ARMISD::RRX
@ RRX
Definition: ARMISelLowering.h:106
llvm::ARMTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
Definition: ARMISelLowering.cpp:1861
llvm::ARMISD::QSUB16b
@ QSUB16b
Definition: ARMISelLowering.h:284
llvm::ARMISD::VMLALVs
@ VMLALVs
Definition: ARMISelLowering.h:250
llvm::ARMISD::SMLAL
@ SMLAL
Definition: ARMISelLowering.h:266
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4644
llvm::ARMTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: ARMISelLowering.cpp:21001
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1319
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::ARMISD::MEMSETLOOP
@ MEMSETLOOP
Definition: ARMISelLowering.h:317
llvm::ARMISD::BCC_i64
@ BCC_i64
Definition: ARMISelLowering.h:102
llvm::ARMTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Definition: ARMISelLowering.cpp:19520
llvm::ARMISD::VQSHLsuIMM
@ VQSHLsuIMM
Definition: ARMISelLowering.h:168
llvm::ARMISD::VLD2_UPD
@ VLD2_UPD
Definition: ARMISelLowering.h:332
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::ARMISD::SMLALTT
@ SMLALTT
Definition: ARMISelLowering.h:271
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1088
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ARMISD::VMOVrh
@ VMOVrh
Definition: ARMISelLowering.h:195
llvm::ARMISD::CMP
@ CMP
Definition: ARMISelLowering.h:86
llvm::ARMISD::SMLALBB
@ SMLALBB
Definition: ARMISelLowering.h:268
llvm::VMOVModImm
@ VMOVModImm
Definition: ARMISelLowering.h:979
llvm::ARMISD::CMPZ
@ CMPZ
Definition: ARMISelLowering.h:88
llvm::ARMISD::VADDLVAu
@ VADDLVAu
Definition: ARMISelLowering.h:240
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4252
llvm::ARMTargetLowering::preferIncOfAddToSubOfNot
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
Definition: ARMISelLowering.cpp:13598
llvm::ARMISD::CALL_NOLINK
@ CALL_NOLINK
Definition: ARMISelLowering.h:70
llvm::ARMISD::VLD3LN_UPD
@ VLD3LN_UPD
Definition: ARMISelLowering.h:336
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: ARMISelLowering.cpp:21068
llvm::Function
Definition: Function.h:62
StringRef.h
llvm::ARMTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: ARMISelLowering.cpp:11728
llvm::ARMISD::WLS
@ WLS
Definition: ARMISelLowering.h:135
llvm::ARMTargetLowering::ExpandInlineAsm
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
Definition: ARMISelLowering.cpp:19905
llvm::InlineAsm::Constraint_Uq
@ Constraint_Uq
Definition: InlineAsm.h:262
llvm::ARMISD::VMOVIMM
@ VMOVIMM
Definition: ARMISelLowering.h:188
llvm::ARMISD::PRELOAD
@ PRELOAD
Definition: ARMISelLowering.h:130
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::ARMISD::DYN_ALLOC
@ DYN_ALLOC
Definition: ARMISelLowering.h:126
InlineAsm.h
llvm::ARMTargetLowering::lowerInterleavedLoad
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
Definition: ARMISelLowering.cpp:21215
llvm::ARMTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: ARMISelLowering.cpp:19959
llvm::ARMTargetLowering::PerformCMOVCombine
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
Definition: ARMISelLowering.cpp:17972
llvm::ARMTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: ARMISelLowering.cpp:3440
llvm::ARMISD::VIDUP
@ VIDUP
Definition: ARMISelLowering.h:224
llvm::ARM::RP
@ RP
Definition: ARMISelLowering.h:370
llvm::ARMISD::VLD1x3_UPD
@ VLD1x3_UPD
Definition: ARMISelLowering.h:343
llvm::ARMISD::VLD2DUP_UPD
@ VLD2DUP_UPD
Definition: ARMISelLowering.h:339
llvm::ARMTargetLowering::lowerInterleavedStore
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
Definition: ARMISelLowering.cpp:21368
llvm::ARM::rmMask
@ rmMask
Definition: ARMISelLowering.h:373
llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode
bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Definition: ARMISelLowering.cpp:19871
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::ARMTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: ARMISelLowering.cpp:19261
llvm::ARMISD::LE
@ LE
Definition: ARMISelLowering.h:138
llvm::ARMISD::VBICIMM
@ VBICIMM
Definition: ARMISelLowering.h:303
llvm::ARMISD::VSHRsIMM
@ VSHRsIMM
Definition: ARMISelLowering.h:157
llvm::MemOp
Definition: TargetLowering.h:111
llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override
Definition: ARMISelLowering.cpp:21106
llvm::ARMISD::LDRD
@ LDRD
Definition: ARMISelLowering.h:359
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::ARMTargetLowering::alignLoopsWithOptSize
bool alignLoopsWithOptSize() const override
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Definition: ARMISelLowering.cpp:21148
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:20948
llvm::ARMTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2083
llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: ARMISelLowering.cpp:13587
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:390
llvm::AttributeList
Definition: Attributes.h:403
llvm::ARMISD::VQSHRNsuIMM
@ VQSHRNsuIMM
Definition: ARMISelLowering.h:171
llvm::ARMTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Definition: ARMISelLowering.cpp:20609
llvm::InlineAsm::Constraint_Um
@ Constraint_Um
Definition: InlineAsm.h:260
llvm::ARMISD::CMPFPw0
@ CMPFPw0
Definition: ARMISelLowering.h:91
llvm::ARMISD::VDUP
@ VDUP
Definition: ARMISelLowering.h:199
llvm::ARMISD::VST1_UPD
@ VST1_UPD
Definition: ARMISelLowering.h:347
llvm::ARMISD::PIC_ADD
@ PIC_ADD
Definition: ARMISelLowering.h:80
llvm::ARMISD::FMSTAT
@ FMSTAT
Definition: ARMISelLowering.h:94
llvm::ARMISD::MEMCPY
@ MEMCPY
Definition: ARMISelLowering.h:310
llvm::ARMISD::BFI
@ BFI
Definition: ARMISelLowering.h:298
llvm::ARMISD::USAT
@ USAT
Definition: ARMISelLowering.h:100
llvm::ARMTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: ARMISelLowering.cpp:1916
llvm::ARMTargetLowering::hasStandaloneRem
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
Definition: ARMISelLowering.h:700
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::ARMISD::VST4LN_UPD
@ VST4LN_UPD
Definition: ARMISelLowering.h:353
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:61
llvm::ARMISD::VZIP
@ VZIP
Definition: ARMISelLowering.h:207
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::ARMISD::WIN__CHKSTK
@ WIN__CHKSTK
Definition: ARMISelLowering.h:132
llvm::ARMISD::SSAT
@ SSAT
Definition: ARMISelLowering.h:99
llvm::ARMISD::WIN__DBZCHK
@ WIN__DBZCHK
Definition: ARMISelLowering.h:133
llvm::ARMISD::VTBL1
@ VTBL1
Definition: ARMISelLowering.h:210
llvm::ARMTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: ARMISelLowering.cpp:20840
llvm::ARMTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: ARMISelLowering.cpp:10314
llvm::ARMISD::ASRL
@ ASRL
Definition: ARMISelLowering.h:82
llvm::ARMISD::VQRSHRNsIMM
@ VQRSHRNsIMM
Definition: ARMISelLowering.h:174
llvm::ARMTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: ARMISelLowering.cpp:20097
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
VectorType
Definition: ItaniumDemangle.h:1037
llvm::ARMISD::SERET_FLAG
@ SERET_FLAG
Definition: ARMISelLowering.h:77
llvm::ARMISD::SMLSLD
@ SMLSLD
Definition: ARMISelLowering.h:274
llvm::ARMTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: ARMISelLowering.cpp:19789
llvm::ARMISD::NodeType
NodeType
Definition: ARMISelLowering.h:55
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::ARMISD::VTST
@ VTST
Definition: ARMISelLowering.h:149
llvm::ARMTargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: ARMISelLowering.cpp:21661
llvm::ARMISD::VSHRuIMM
@ VSHRuIMM
Definition: ARMISelLowering.h:158
llvm::FixedVectorType
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:525
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::ARMISD::VMVNIMM
@ VMVNIMM
Definition: ARMISelLowering.h:189
llvm::ARMTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
Definition: ARMISelLowering.cpp:19580
llvm::ARMTargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: ARMISelLowering.cpp:21114
llvm::ARMISD::PREDICATE_CAST
@ PREDICATE_CAST
Definition: ARMISelLowering.h:140
llvm::ARMISD::SMMLAR
@ SMMLAR
Definition: ARMISelLowering.h:276
llvm::ARMTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: ARMISelLowering.cpp:20573
llvm::ARMISD::MVESEXT
@ MVESEXT
Definition: ARMISelLowering.h:143
llvm::ARMTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: ARMISelLowering.cpp:21072
llvm::ARMTargetLowering::isDesirableToTransformToIntegerOp
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
Definition: ARMISelLowering.cpp:18684
llvm::ARMISD::UMLAL
@ UMLAL
Definition: ARMISelLowering.h:265
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::ARMTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: ARMISelLowering.cpp:1646
MachineValueType.h
llvm::ARMISD::WLSSETUP
@ WLSSETUP
Definition: ARMISelLowering.h:136
llvm::ARMISD::BR2_JT
@ BR2_JT
Definition: ARMISelLowering.h:75
llvm::ARMTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind Kind) const override
Definition: ARMISelLowering.h:407
llvm::ARMTargetLowering::PerformIntrinsicCombine
SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const
PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
Definition: ARMISelLowering.cpp:17122
llvm::ARMISD::VST2LN_UPD
@ VST2LN_UPD
Definition: ARMISelLowering.h:351
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
llvm::ARMISD::QSUB8b
@ QSUB8b
Definition: ARMISelLowering.h:282
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::ARMISD::SMMLSR
@ SMMLSR
Definition: ARMISelLowering.h:277
TargetLowering.h
llvm::ARMISD::VQRSHRNsuIMM
@ VQRSHRNsuIMM
Definition: ARMISelLowering.h:176
llvm::ARMISD::VMULLs
@ VMULLs
Definition: ARMISelLowering.h:227
llvm::ARM::isBitFieldInvertedMask
bool isBitFieldInvertedMask(unsigned v)
Definition: ARMISelLowering.cpp:20578
llvm::ARMTargetLowering::shouldConvertSplatType
Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...
Definition: ARMISelLowering.cpp:18989
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
ARMBaseInfo.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ARMISD::VMLALVAs
@ VMLALVAs
Definition: ARMISelLowering.h:254
llvm::ARMISD::LOOP_DEC
@ LOOP_DEC
Definition: ARMISelLowering.h:137
llvm::ARMISD::VMOVSR
@ VMOVSR
Definition: ARMISelLowering.h:116
llvm::ARMTargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: ARMISelLowering.h:683
llvm::ARMISD::t2CALL_BTI
@ t2CALL_BTI
Definition: ARMISelLowering.h:72
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:256
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ARMISD::VQRSHRNuIMM
@ VQRSHRNuIMM
Definition: ARMISelLowering.h:175
llvm::ARMTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: ARMISelLowering.cpp:19669
llvm::ARMISD::VADDLVAs
@ VADDLVAs
Definition: ARMISelLowering.h:239
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::ARMTargetLowering::PerformMVEExtCombine
SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:18372
llvm::ARMTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: ARMISelLowering.cpp:21060
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:704
llvm::InlineAsm::Constraint_Uy
@ Constraint_Uy
Definition: InlineAsm.h:266
llvm::ARMISD::VQSHRNuIMM
@ VQSHRNuIMM
Definition: ARMISelLowering.h:170
llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
Definition: ARMISelLowering.cpp:18689
llvm::ARMISD::SRL_FLAG
@ SRL_FLAG
Definition: ARMISelLowering.h:104
llvm::ARMISD::VREV16
@ VREV16
Definition: ARMISelLowering.h:206
llvm::ARMTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: ARMISelLowering.cpp:1594
llvm::ARMISD::VADDLVps
@ VADDLVps
Definition: ARMISelLowering.h:241
llvm::InlineAsm::Constraint_Uv
@ Constraint_Uv
Definition: InlineAsm.h:265
llvm::ARMISD::SMLALDX
@ SMLALDX
Definition: ARMISelLowering.h:273
llvm::ARMISD::VCMP
@ VCMP
Definition: ARMISelLowering.h:147
llvm::ARMISD::VMLALVAu
@ VMLALVAu
Definition: ARMISelLowering.h:255
llvm::Instruction
Definition: Instruction.h:45
llvm::ARMISD::VMULLu
@ VMULLu
Definition: ARMISelLowering.h:228
llvm::ARMISD::VMOVDRR
@ VMOVDRR
Definition: ARMISelLowering.h:115
llvm::ARMISD::VLD1DUP
@ VLD1DUP
Definition: ARMISelLowering.h:325
llvm::ARMISD::VQSHLuIMM
@ VQSHLuIMM
Definition: ARMISelLowering.h:167
llvm::ARM::RoundingBitsPos
const unsigned RoundingBitsPos
Definition: ARMISelLowering.h:377
llvm::ARMISD::SUBC
@ SUBC
Definition: ARMISelLowering.h:110
llvm::ARMISD::VQMOVNu
@ VQMOVNu
Definition: ARMISelLowering.h:216
llvm::ARMISD::VMINVs
@ VMINVs
Definition: ARMISelLowering.h:259
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ARMTargetLowering::PerformCMOVToBFICombine
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
Definition: ARMISelLowering.cpp:17671
llvm::ARMISD::VST3_UPD
@ VST3_UPD
Definition: ARMISelLowering.h:349
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMISD::VLD1_UPD
@ VLD1_UPD
Definition: ARMISelLowering.h:331
llvm::ARMTargetLowering::isReadOnly
bool isReadOnly(const GlobalValue *GV) const
Definition: ARMISelLowering.cpp:3833
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMISD::SMLALD
@ SMLALD
Definition: ARMISelLowering.h:272
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARMTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: ARMISelLowering.cpp:20021
llvm::ARMISD::UQADD8b
@ UQADD8b
Definition: ARMISelLowering.h:285
llvm::VMVNModImm
@ VMVNModImm
Definition: ARMISelLowering.h:980
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMISD::VADDLVu
@ VADDLVu
Definition: ARMISelLowering.h:238
llvm::ARMISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: ARMISelLowering.h:120
llvm::ARMTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: ARMISelLowering.cpp:13552
llvm::ARMISD::QADD8b
@ QADD8b
Definition: ARMISelLowering.h:281
llvm::ARMISD::WrapperPIC
@ WrapperPIC
Definition: ARMISelLowering.h:61
llvm::ARMTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: ARMISelLowering.cpp:18476
llvm::ARMTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: ARMISelLowering.h:620
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::ARMISD::LSRL
@ LSRL
Definition: ARMISelLowering.h:83
llvm::ARMISD::CSINC
@ CSINC
Definition: ARMISelLowering.h:322
llvm::ARMISD::CALL_PRED
@ CALL_PRED
Definition: ARMISelLowering.h:69
llvm::ARM::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: ARMFastISel.cpp:3076
llvm::ARMISD::VRSHRuIMM
@ VRSHRuIMM
Definition: ARMISelLowering.h:162
llvm::ARMISD::WrapperJT
@ WrapperJT
Definition: ARMISelLowering.h:63
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::ARMISD::VMLALVApu
@ VMLALVApu
Definition: ARMISelLowering.h:257
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ARMISD::SUBS
@ SUBS
Definition: ARMISelLowering.h:97
llvm::ARMISD::VBSP
@ VBSP
Definition: ARMISelLowering.h:306
llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: ARMISelLowering.cpp:20957
llvm::ARMISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: ARMISelLowering.h:118
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::APFloat
Definition: APFloat.h:701
llvm::ARMISD::VMLAVu
@ VMLAVu
Definition: ARMISelLowering.h:247
llvm::ARMISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: ARMISelLowering.h:119
llvm::ARMISD::VADDLVAps
@ VADDLVAps
Definition: ARMISelLowering.h:243
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:309
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::ARMISD::VEXT
@ VEXT
Definition: ARMISelLowering.h:203
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: ARMISelLowering.h:692
llvm::ARMISD::SMULWT
@ SMULWT
Definition: ARMISelLowering.h:264
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARMISD::LSLL
@ LSLL
Definition: ARMISelLowering.h:84
llvm::ARMISD::VLD2DUP
@ VLD2DUP
Definition: ARMISelLowering.h:326
llvm::ARMISD::MEMCPYLOOP
@ MEMCPYLOOP
Definition: ARMISelLowering.h:314
llvm::ARMTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: ARMISelLowering.cpp:18866
llvm::ARMISD::VUZP
@ VUZP
Definition: ARMISelLowering.h:208
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::ARMISD::CMPFPEw0
@ CMPFPEw0
Definition: ARMISelLowering.h:92
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::ARMTargetLowering::shouldAlignPointerArgs
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
Definition: ARMISelLowering.cpp:1903
llvm::ARMISD::VQDMULH
@ VQDMULH
Definition: ARMISelLowering.h:230
llvm::ARMISD::VCMPZ
@ VCMPZ
Definition: ARMISelLowering.h:148
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::ARMISD::RET_FLAG
@ RET_FLAG
Definition: ARMISelLowering.h:76
llvm::ARMISD::BRCOND
@ BRCOND
Definition: ARMISelLowering.h:73
llvm::ARMISD::VCVTL
@ VCVTL
Definition: ARMISelLowering.h:221
llvm::ARMTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: ARMISelLowering.h:593
llvm::ARMISD::UQSUB16b
@ UQSUB16b
Definition: ARMISelLowering.h:288
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetLoweringBase::shouldFormOverflowOp
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: TargetLowering.h:2891
llvm::ARMISD::VREV64
@ VREV64
Definition: ARMISelLowering.h:204
llvm::ARMISD::VLD2LN_UPD
@ VLD2LN_UPD
Definition: ARMISelLowering.h:335
llvm::ARMISD::VST4_UPD
@ VST4_UPD
Definition: ARMISelLowering.h:350
llvm::ARMISD::VMOVRRD
@ VMOVRRD
Definition: ARMISelLowering.h:114
llvm::ARMISD::COPY_STRUCT_BYVAL
@ COPY_STRUCT_BYVAL
Definition: ARMISelLowering.h:66
llvm::ARMISD::THREAD_POINTER
@ THREAD_POINTER
Definition: ARMISelLowering.h:124
llvm::ARMTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
Definition: ARMISelLowering.cpp:8285
llvm::ARMISD::STRD
@ STRD
Definition: ARMISelLowering.h:360
llvm::ARMISD::VST1x4_UPD
@ VST1x4_UPD
Definition: ARMISelLowering.h:356
llvm::ARMTargetLowering::canCombineStoreAndExtract
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
Definition: ARMISelLowering.cpp:21031
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
IRBuilder.h
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::ARMISD::VADDLVApu
@ VADDLVApu
Definition: ARMISelLowering.h:244
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::ARMISD::VMINVu
@ VMINVu
Definition: ARMISelLowering.h:258
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::ARMISD::VMLALVps
@ VMLALVps
Definition: ARMISelLowering.h:252
llvm::ARMISD::VSHLs
@ VSHLs
Definition: ARMISelLowering.h:152
llvm::ARMTargetLowering::findRepresentativeClass
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: ARMISelLowering.cpp:1609
llvm::ARMTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: ARMISelLowering.cpp:20994
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1370
llvm::ARMISD::VECTOR_REG_CAST
@ VECTOR_REG_CAST
Definition: ARMISelLowering.h:141
llvm::ARMISD::VRSHRsIMM
@ VRSHRsIMM
Definition: ARMISelLowering.h:161
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ARMISD::VADDLVpu
@ VADDLVpu
Definition: ARMISelLowering.h:242
llvm::ARM::RM
@ RM
Definition: ARMISelLowering.h:371
llvm::ARMISD::VST3LN_UPD
@ VST3LN_UPD
Definition: ARMISelLowering.h:352
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::ARMISD::VMOVFPIMM
@ VMOVFPIMM
Definition: ARMISelLowering.h:192
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ARM::Rounding
Rounding
Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.
Definition: ARMISelLowering.h:368
llvm::ARMTargetLowering::PerformMVETruncCombine
SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: ARMISelLowering.cpp:18203
llvm::ARMISD::VLD4_UPD
@ VLD4_UPD
Definition: ARMISelLowering.h:334
llvm::ARMTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: ARMISelLowering.cpp:20913
llvm::ARMISD::VADDVs
@ VADDVs
Definition: ARMISelLowering.h:233
llvm::ARMISD::VTBL2
@ VTBL2
Definition: ARMISelLowering.h:211
llvm::ARMISD::QADD16b
@ QADD16b
Definition: ARMISelLowering.h:283
info
lazy value info
Definition: LazyValueInfo.cpp:59
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ARMISD::VREV32
@ VREV32
Definition: ARMISelLowering.h:205
llvm::ARMISD::VLD3_UPD
@ VLD3_UPD
Definition: ARMISelLowering.h:333
llvm::ARMISD::VSRIIMM
@ VSRIIMM
Definition: ARMISelLowering.h:180
llvm::ARMISD::VADDVu
@ VADDVu
Definition: ARMISelLowering.h:234
llvm::ARMTargetLowering::getSDagStackGuard
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: ARMISelLowering.cpp:21017
llvm::ARMISD::MVEZEXT
@ MVEZEXT
Definition: ARMISelLowering.h:144
llvm::ArrayRef< int >
RegInfo
Definition: AMDGPUAsmParser.cpp:2388
llvm::ARMISD::VGETLANEu
@ VGETLANEu
Definition: ARMISelLowering.h:184
llvm::ARMISD::VMLAVps
@ VMLAVps
Definition: ARMISelLowering.h:248
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::ARMISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: ARMISelLowering.h:57
llvm::ARMISD::VST1x2_UPD
@ VST1x2_UPD
Definition: ARMISelLowering.h:354
llvm::ARMISD::VADDVps
@ VADDVps
Definition: ARMISelLowering.h:235
llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: ARMISelLowering.cpp:20979
llvm::ARMISD::VLD1x4_UPD
@ VLD1x4_UPD
Definition: ARMISelLowering.h:344
llvm::ARMTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: ARMISelLowering.cpp:21064
llvm::ARMTargetLowering::isVectorLoadExtDesirable
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Definition: ARMISelLowering.cpp:19002
llvm::ARMISD::BUILD_VECTOR
@ BUILD_VECTOR
Definition: ARMISelLowering.h:295
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
llvm::ARMISD::VLD1DUP_UPD
@ VLD1DUP_UPD
Definition: ARMISelLowering.h:338
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMTargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: ARMISelLowering.cpp:18762
llvm::ARMISD::VMOVhr
@ VMOVhr
Definition: ARMISelLowering.h:196
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ARMISD::CMPFPE
@ CMPFPE
Definition: ARMISelLowering.h:90
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1253
Node
Definition: ItaniumDemangle.h:235
llvm::ARMISD::VRSHRNIMM
@ VRSHRNIMM
Definition: ARMISelLowering.h:163
llvm::ARMISD::MVETRUNC
@ MVETRUNC
Definition: ARMISelLowering.h:145
llvm::ARMISD::VST2_UPD
@ VST2_UPD
Definition: ARMISelLowering.h:348
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:180
llvm::ARMISD::SMLSLDX
@ SMLSLDX
Definition: ARMISelLowering.h:275
llvm::OtherModImm
@ OtherModImm
Definition: ARMISelLowering.h:982
llvm::ARMISD::VMLAVs
@ VMLAVs
Definition: ARMISelLowering.h:245
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:731
llvm::ARMTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: ARMISelLowering.cpp:18790
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
Definition: ARMISelLowering.cpp:21584
llvm::ARMISD::VSLIIMM
@ VSLIIMM
Definition: ARMISelLowering.h:179
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMISD::CSNEG
@ CSNEG
Definition: ARMISelLowering.h:321
Attributes.h
llvm::ARMTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: ARMISelLowering.cpp:19989
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:156
llvm::ARMISD::UQSUB8b
@ UQSUB8b
Definition: ARMISelLowering.h:286
llvm::ARMISD::VMLALVAps
@ VMLALVAps
Definition: ARMISelLowering.h:256
llvm::ARMISD::VLD1x2_UPD
@ VLD1x2_UPD
Definition: ARMISelLowering.h:342
llvm::ARMISD::VST1x3_UPD
@ VST1x3_UPD
Definition: ARMISelLowering.h:355
llvm::ARMISD::VSHLIMM
@ VSHLIMM
Definition: ARMISelLowering.h:156
llvm::InlineAsm::Constraint_Us
@ Constraint_Us
Definition: InlineAsm.h:263
llvm::ARMTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
Definition: ARMISelLowering.cpp:19327
llvm::ARMISD::SMULWB
@ SMULWB
Definition: ARMISelLowering.h:263
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1720
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::ARMISD::VGETLANEs
@ VGETLANEs
Definition: ARMISelLowering.h:185
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::ARMISD::SRA_FLAG
@ SRA_FLAG
Definition: ARMISelLowering.h:105
CallingConvLower.h
llvm::ARMTargetLowering::makeDMB
Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const
Definition: ARMISelLowering.cpp:20858
llvm::ARMISD::VMAXVu
@ VMAXVu
Definition: ARMISelLowering.h:260
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::ARMISD::VQMOVNs
@ VQMOVNs
Definition: ARMISelLowering.h:215
llvm::ARMISD::VLD4DUP_UPD
@ VLD4DUP_UPD
Definition: ARMISelLowering.h:341
llvm::ARMTargetLowering::getSubtarget
const ARMSubtarget * getSubtarget() const
Definition: ARMISelLowering.h:574
llvm::ARMISD::VADDVpu
@ VADDVpu
Definition: ARMISelLowering.h:236
llvm::ARMTargetLowering::PerformBRCONDCombine
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
Definition: ARMISelLowering.cpp:17932
llvm::ARM::RZ
@ RZ
Definition: ARMISelLowering.h:372
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4261
llvm::ARMISD::VMLALVu
@ VMLALVu
Definition: ARMISelLowering.h:251
ISDOpcodes.h
llvm::ARMISD::UMAAL
@ UMAAL
Definition: ARMISelLowering.h:267
Function.h
llvm::ARMISD::VDUPLANE
@ VDUPLANE
Definition: ARMISelLowering.h:200
llvm::ARMISD::tSECALL
@ tSECALL
Definition: ARMISelLowering.h:71
llvm::ARMISD::CMN
@ CMN
Definition: ARMISelLowering.h:87
llvm::ARMISD::VMLALVpu
@ VMLALVpu
Definition: ARMISelLowering.h:253
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::ARMISD::INTRET_FLAG
@ INTRET_FLAG
Definition: ARMISelLowering.h:78
llvm::ARMTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: ARMISelLowering.cpp:20888
llvm::ARMISD::ADDE
@ ADDE
Definition: ARMISelLowering.h:109
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ARMTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: ARMISelLowering.cpp:19032
llvm::ARMISD::CSINV
@ CSINV
Definition: ARMISelLowering.h:320
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::TargetLoweringBase::getSchedulingPreference
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
Definition: TargetLowering.h:869
llvm::ARMTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(const SDValue &AddNode, const SDValue &ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: ARMISelLowering.cpp:19357
llvm::ARMTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Definition: ARMISelLowering.cpp:21570
llvm::ARMISD::VQSHRNsIMM
@ VQSHRNsIMM
Definition: ARMISelLowering.h:169
llvm::ARMTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: ARMISelLowering.cpp:20590
CodeGen.h
llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
Definition: ARMISelLowering.cpp:20935
llvm::ARMISD::VQSHLsIMM
@ VQSHLsIMM
Definition: ARMISelLowering.h:166
llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Definition: ARMISelLowering.cpp:21196
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:2012
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::ARMTargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: ARMISelLowering.cpp:13607
SmallVector.h
llvm::ARMISD::VLD4DUP
@ VLD4DUP
Definition: ARMISelLowering.h:328
llvm::ARMISD::VCVTN
@ VCVTN
Definition: ARMISelLowering.h:219
llvm::TargetLoweringBase::ScalarCondVectorVal
@ ScalarCondVectorVal
Definition: TargetLowering.h:239
llvm::ARMTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Definition: ARMISelLowering.cpp:20850
llvm::ARMTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: ARMISelLowering.cpp:12137
llvm::ARMTargetLowering::getSSPStackGuardCheck
Function * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
Definition: ARMISelLowering.cpp:21024
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1265
llvm::ARMTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
Definition: ARMISelLowering.cpp:2088
N
#define N
llvm::ARMTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: ARMISelLowering.h:696
llvm::ARMISD::MEMBARRIER_MCR
@ MEMBARRIER_MCR
Definition: ARMISelLowering.h:128
llvm::ARMISD::VMLAVpu
@ VMLAVpu
Definition: ARMISelLowering.h:249
llvm::ARMTargetLowering::getNumInterleavedAccesses
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
Definition: ARMISelLowering.cpp:21155
llvm::ARMTargetLowering::isFNegFree
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition: ARMISelLowering.cpp:18828
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4353
llvm::ARMISD::CMPFP
@ CMPFP
Definition: ARMISelLowering.h:89
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::ARMISD::VLD3DUP
@ VLD3DUP
Definition: ARMISelLowering.h:327
llvm::ARMTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: ARMISelLowering.cpp:21600
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::ARMISD::TC_RETURN
@ TC_RETURN
Definition: ARMISelLowering.h:122
RegName
#define RegName(no)
llvm::ARMTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: ARMISelLowering.h:546
llvm::ARM_MB::MemBOpt
MemBOpt
Definition: ARMBaseInfo.h:58
llvm::ARMISD::VSHLu
@ VSHLu
Definition: ARMISelLowering.h:153
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: ARMISelLowering.cpp:10464
llvm::ARMISD::Wrapper
@ Wrapper
Definition: ARMISelLowering.h:59
llvm::ARMISD::SMLALBT
@ SMLALBT
Definition: ARMISelLowering.h:269
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
llvm::ARMTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Definition: ARMISelLowering.cpp:19343
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MVEVMVNModImm
@ MVEVMVNModImm
Definition: ARMISelLowering.h:981
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::ARMISD::SUBE
@ SUBE
Definition: ARMISelLowering.h:111
llvm::ARMISD::CMOV
@ CMOV
Definition: ARMISelLowering.h:96
llvm::Sched::Preference
Preference
Definition: TargetLowering.h:97
llvm::ARMISD::BR_JT
@ BR_JT
Definition: ARMISelLowering.h:74
llvm::ARMISD::UQADD16b
@ UQADD16b
Definition: ARMISelLowering.h:287
MachineFunction.h
model
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from where P can be anything The alignment inference code cannot handle loads from globals in static non mode because it doesn t look through the extra dyld stub load If you try vec_align ll without relocation model
Definition: README-SSE.txt:414
llvm::ARMISD::CALL
@ CALL
Definition: ARMISelLowering.h:68
llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Definition: ARMISelLowering.cpp:19206
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:61
llvm::InlineAsm::Constraint_Un
@ Constraint_Un
Definition: InlineAsm.h:261
llvm::ARMTargetLowering::ARMTargetLowering
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
Definition: ARMISelLowering.cpp:469
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:526
llvm::ARMISD::ADDC
@ ADDC
Definition: ARMISelLowering.h:108
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMISD::SMLALTB
@ SMLALTB
Definition: ARMISelLowering.h:270
llvm::ARMISD::VLD4LN_UPD
@ VLD4LN_UPD
Definition: ARMISelLowering.h:337
llvm::ARMTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Definition: ARMISelLowering.cpp:20999
llvm::ARMTargetLowering::getScalingFactorCost
InstructionCost getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
Definition: ARMISelLowering.cpp:19046
llvm::ARM::RN
@ RN
Definition: ARMISelLowering.h:369
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:237
llvm::VMOVModImmType
VMOVModImmType
Definition: ARMISelLowering.h:978
llvm::ARMISD::VORRIMM
@ VORRIMM
Definition: ARMISelLowering.h:301
llvm::ARMISD::VMAXVs
@ VMAXVs
Definition: ARMISelLowering.h:261
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ARMTargetLowering::isLegalInterleavedAccessType
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
Definition: ARMISelLowering.cpp:21160
llvm::ARMISD::VTRN
@ VTRN
Definition: ARMISelLowering.h:209
llvm::ARMTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: ARMISelLowering.cpp:21607
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::ARMISD::LSLS
@ LSLS
Definition: ARMISelLowering.h:112