LLVM  14.0.0git
AVRAsmParser.cpp
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1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AVR.h"
10 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCExpr.h"
15 
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/Support/Debug.h"
31 
32 #include <sstream>
33 
34 #define DEBUG_TYPE "avr-asm-parser"
35 
36 using namespace llvm;
37 
38 namespace {
39 /// Parses AVR assembly from a stream.
40 class AVRAsmParser : public MCTargetAsmParser {
41  const MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43  const MCRegisterInfo *MRI;
44  const std::string GENERATE_STUBS = "gs";
45 
46 #define GET_ASSEMBLER_HEADER
47 #include "AVRGenAsmMatcher.inc"
48 
49  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
52  bool MatchingInlineAsm) override;
53 
54  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
55  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
56  SMLoc &EndLoc) override;
57 
58  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
59  SMLoc NameLoc, OperandVector &Operands) override;
60 
61  bool ParseDirective(AsmToken DirectiveID) override;
62 
63  OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
64 
65  bool parseOperand(OperandVector &Operands);
66  int parseRegisterName(unsigned (*matchFn)(StringRef));
67  int parseRegisterName();
68  int parseRegister(bool RestoreOnFailure = false);
69  bool tryParseRegisterOperand(OperandVector &Operands);
70  bool tryParseExpression(OperandVector &Operands);
71  bool tryParseRelocExpression(OperandVector &Operands);
72  void eatComma();
73 
74  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
75  unsigned Kind) override;
76 
77  unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
78  MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
79  return MRI->getMatchingSuperReg(Reg, From, Class);
80  }
81 
82  bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
83  bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
84  uint64_t const &ErrorInfo);
85  bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
86 
87  bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
88 
89 public:
90  AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
91  const MCInstrInfo &MII, const MCTargetOptions &Options)
92  : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
94  MRI = getContext().getRegisterInfo();
95 
96  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
97  }
98 
99  MCAsmParser &getParser() const { return Parser; }
100  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 };
102 
103 /// An parsed AVR assembly operand.
104 class AVROperand : public MCParsedAsmOperand {
105  typedef MCParsedAsmOperand Base;
106  enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
107 
108 public:
109  AVROperand(StringRef Tok, SMLoc const &S)
110  : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
111  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
112  : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
113  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
114  : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
115  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
116  : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
117 
118  struct RegisterImmediate {
119  unsigned Reg;
120  MCExpr const *Imm;
121  };
122  union {
123  StringRef Tok;
124  RegisterImmediate RegImm;
125  };
126 
127  SMLoc Start, End;
128 
129 public:
130  void addRegOperands(MCInst &Inst, unsigned N) const {
131  assert(Kind == k_Register && "Unexpected operand kind");
132  assert(N == 1 && "Invalid number of operands!");
133 
135  }
136 
137  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
138  // Add as immediate when possible
139  if (!Expr)
141  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
142  Inst.addOperand(MCOperand::createImm(CE->getValue()));
143  else
144  Inst.addOperand(MCOperand::createExpr(Expr));
145  }
146 
147  void addImmOperands(MCInst &Inst, unsigned N) const {
148  assert(Kind == k_Immediate && "Unexpected operand kind");
149  assert(N == 1 && "Invalid number of operands!");
150 
151  const MCExpr *Expr = getImm();
152  addExpr(Inst, Expr);
153  }
154 
155  /// Adds the contained reg+imm operand to an instruction.
156  void addMemriOperands(MCInst &Inst, unsigned N) const {
157  assert(Kind == k_Memri && "Unexpected operand kind");
158  assert(N == 2 && "Invalid number of operands");
159 
161  addExpr(Inst, getImm());
162  }
163 
164  void addImmCom8Operands(MCInst &Inst, unsigned N) const {
165  assert(N == 1 && "Invalid number of operands!");
166  // The operand is actually a imm8, but we have its bitwise
167  // negation in the assembly source, so twiddle it here.
168  const auto *CE = cast<MCConstantExpr>(getImm());
169  Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
170  }
171 
172  bool isImmCom8() const {
173  if (!isImm())
174  return false;
175  const auto *CE = dyn_cast<MCConstantExpr>(getImm());
176  if (!CE)
177  return false;
178  int64_t Value = CE->getValue();
179  return isUInt<8>(Value);
180  }
181 
182  bool isReg() const override { return Kind == k_Register; }
183  bool isImm() const override { return Kind == k_Immediate; }
184  bool isToken() const override { return Kind == k_Token; }
185  bool isMem() const override { return Kind == k_Memri; }
186  bool isMemri() const { return Kind == k_Memri; }
187 
188  StringRef getToken() const {
189  assert(Kind == k_Token && "Invalid access!");
190  return Tok;
191  }
192 
193  unsigned getReg() const override {
194  assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
195 
196  return RegImm.Reg;
197  }
198 
199  const MCExpr *getImm() const {
200  assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
201  return RegImm.Imm;
202  }
203 
204  static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
205  return std::make_unique<AVROperand>(Str, S);
206  }
207 
208  static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
209  SMLoc E) {
210  return std::make_unique<AVROperand>(RegNum, S, E);
211  }
212 
213  static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
214  SMLoc E) {
215  return std::make_unique<AVROperand>(Val, S, E);
216  }
217 
218  static std::unique_ptr<AVROperand>
219  CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
220  return std::make_unique<AVROperand>(RegNum, Val, S, E);
221  }
222 
223  void makeToken(StringRef Token) {
224  Kind = k_Token;
225  Tok = Token;
226  }
227 
228  void makeReg(unsigned RegNo) {
229  Kind = k_Register;
230  RegImm = {RegNo, nullptr};
231  }
232 
233  void makeImm(MCExpr const *Ex) {
234  Kind = k_Immediate;
235  RegImm = {0, Ex};
236  }
237 
238  void makeMemri(unsigned RegNo, MCExpr const *Imm) {
239  Kind = k_Memri;
240  RegImm = {RegNo, Imm};
241  }
242 
243  SMLoc getStartLoc() const override { return Start; }
244  SMLoc getEndLoc() const override { return End; }
245 
246  void print(raw_ostream &O) const override {
247  switch (Kind) {
248  case k_Token:
249  O << "Token: \"" << getToken() << "\"";
250  break;
251  case k_Register:
252  O << "Register: " << getReg();
253  break;
254  case k_Immediate:
255  O << "Immediate: \"" << *getImm() << "\"";
256  break;
257  case k_Memri: {
258  // only manually print the size for non-negative values,
259  // as the sign is inserted automatically.
260  O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
261  break;
262  }
263  }
264  O << "\n";
265  }
266 };
267 
268 } // end anonymous namespace.
269 
270 // Auto-generated Match Functions
271 
272 /// Maps from the set of all register names to a register number.
273 /// \note Generated by TableGen.
274 static unsigned MatchRegisterName(StringRef Name);
275 
276 /// Maps from the set of all alternative registernames to a register number.
277 /// \note Generated by TableGen.
278 static unsigned MatchRegisterAltName(StringRef Name);
279 
280 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
281  OperandVector const &Operands,
282  uint64_t const &ErrorInfo) {
283  SMLoc ErrorLoc = Loc;
284  char const *Diag = 0;
285 
286  if (ErrorInfo != ~0U) {
287  if (ErrorInfo >= Operands.size()) {
288  Diag = "too few operands for instruction.";
289  } else {
290  AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
291 
292  // TODO: See if we can do a better error than just "invalid ...".
293  if (Op.getStartLoc() != SMLoc()) {
294  ErrorLoc = Op.getStartLoc();
295  }
296  }
297  }
298 
299  if (!Diag) {
300  Diag = "invalid operand for instruction";
301  }
302 
303  return Error(ErrorLoc, Diag);
304 }
305 
306 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
307  uint64_t const &ErrorInfo) {
308  return Error(Loc, "instruction requires a CPU feature not currently enabled");
309 }
310 
311 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
312  Inst.setLoc(Loc);
313  Out.emitInstruction(Inst, STI);
314 
315  return false;
316 }
317 
318 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
321  bool MatchingInlineAsm) {
322  MCInst Inst;
323  unsigned MatchResult =
324  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
325 
326  switch (MatchResult) {
327  case Match_Success:
328  return emit(Inst, Loc, Out);
329  case Match_MissingFeature:
330  return missingFeature(Loc, ErrorInfo);
331  case Match_InvalidOperand:
332  return invalidOperand(Loc, Operands, ErrorInfo);
333  case Match_MnemonicFail:
334  return Error(Loc, "invalid instruction");
335  default:
336  return true;
337  }
338 }
339 
340 /// Parses a register name using a given matching function.
341 /// Checks for lowercase or uppercase if necessary.
342 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
343  StringRef Name = Parser.getTok().getString();
344 
345  int RegNum = matchFn(Name);
346 
347  // GCC supports case insensitive register names. Some of the AVR registers
348  // are all lower case, some are all upper case but non are mixed. We prefer
349  // to use the original names in the register definitions. That is why we
350  // have to test both upper and lower case here.
351  if (RegNum == AVR::NoRegister) {
352  RegNum = matchFn(Name.lower());
353  }
354  if (RegNum == AVR::NoRegister) {
355  RegNum = matchFn(Name.upper());
356  }
357 
358  return RegNum;
359 }
360 
361 int AVRAsmParser::parseRegisterName() {
362  int RegNum = parseRegisterName(&MatchRegisterName);
363 
364  if (RegNum == AVR::NoRegister)
365  RegNum = parseRegisterName(&MatchRegisterAltName);
366 
367  return RegNum;
368 }
369 
370 int AVRAsmParser::parseRegister(bool RestoreOnFailure) {
371  int RegNum = AVR::NoRegister;
372 
373  if (Parser.getTok().is(AsmToken::Identifier)) {
374  // Check for register pair syntax
375  if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
376  AsmToken HighTok = Parser.getTok();
377  Parser.Lex();
378  AsmToken ColonTok = Parser.getTok();
379  Parser.Lex(); // Eat high (odd) register and colon
380 
381  if (Parser.getTok().is(AsmToken::Identifier)) {
382  // Convert lower (even) register to DREG
383  RegNum = toDREG(parseRegisterName());
384  }
385  if (RegNum == AVR::NoRegister && RestoreOnFailure) {
386  getLexer().UnLex(std::move(ColonTok));
387  getLexer().UnLex(std::move(HighTok));
388  }
389  } else {
390  RegNum = parseRegisterName();
391  }
392  }
393  return RegNum;
394 }
395 
396 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
397  int RegNo = parseRegister();
398 
399  if (RegNo == AVR::NoRegister)
400  return true;
401 
402  AsmToken const &T = Parser.getTok();
403  Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
404  Parser.Lex(); // Eat register token.
405 
406  return false;
407 }
408 
409 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
410  SMLoc S = Parser.getTok().getLoc();
411 
412  if (!tryParseRelocExpression(Operands))
413  return false;
414 
415  if ((Parser.getTok().getKind() == AsmToken::Plus ||
416  Parser.getTok().getKind() == AsmToken::Minus) &&
417  Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
418  // Don't handle this case - it should be split into two
419  // separate tokens.
420  return true;
421  }
422 
423  // Parse (potentially inner) expression
424  MCExpr const *Expression;
425  if (getParser().parseExpression(Expression))
426  return true;
427 
428  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
429  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
430  return false;
431 }
432 
433 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
434  bool isNegated = false;
436 
437  SMLoc S = Parser.getTok().getLoc();
438 
439  // Check for sign
440  AsmToken tokens[2];
441  size_t ReadCount = Parser.getLexer().peekTokens(tokens);
442 
443  if (ReadCount == 2) {
444  if ((tokens[0].getKind() == AsmToken::Identifier &&
445  tokens[1].getKind() == AsmToken::LParen) ||
446  (tokens[0].getKind() == AsmToken::LParen &&
447  tokens[1].getKind() == AsmToken::Minus)) {
448 
449  AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
450  if (CurTok == AsmToken::Minus || tokens[1].getKind() == AsmToken::Minus) {
451  isNegated = true;
452  } else {
453  assert(CurTok == AsmToken::Plus);
454  isNegated = false;
455  }
456 
457  // Eat the sign
458  if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
459  Parser.Lex();
460  }
461  }
462 
463  // Check if we have a target specific modifier (lo8, hi8, &c)
464  if (Parser.getTok().getKind() != AsmToken::Identifier ||
465  Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
466  // Not a reloc expr
467  return true;
468  }
469  StringRef ModifierName = Parser.getTok().getString();
470  ModifierKind = AVRMCExpr::getKindByName(ModifierName);
471 
472  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
473  Parser.Lex();
474  Parser.Lex(); // Eat modifier name and parenthesis
475  if (Parser.getTok().getString() == GENERATE_STUBS &&
476  Parser.getTok().getKind() == AsmToken::Identifier) {
477  std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
478  ModifierKind = AVRMCExpr::getKindByName(GSModName);
479  if (ModifierKind != AVRMCExpr::VK_AVR_None)
480  Parser.Lex(); // Eat gs modifier name
481  }
482  } else {
483  return Error(Parser.getTok().getLoc(), "unknown modifier");
484  }
485 
486  if (tokens[1].getKind() == AsmToken::Minus ||
487  tokens[1].getKind() == AsmToken::Plus) {
488  Parser.Lex();
489  assert(Parser.getTok().getKind() == AsmToken::LParen);
490  Parser.Lex(); // Eat the sign and parenthesis
491  }
492 
493  MCExpr const *InnerExpression;
494  if (getParser().parseExpression(InnerExpression))
495  return true;
496 
497  if (tokens[1].getKind() == AsmToken::Minus ||
498  tokens[1].getKind() == AsmToken::Plus) {
499  assert(Parser.getTok().getKind() == AsmToken::RParen);
500  Parser.Lex(); // Eat closing parenthesis
501  }
502 
503  // If we have a modifier wrap the inner expression
504  assert(Parser.getTok().getKind() == AsmToken::RParen);
505  Parser.Lex(); // Eat closing parenthesis
506 
507  MCExpr const *Expression =
508  AVRMCExpr::create(ModifierKind, InnerExpression, isNegated, getContext());
509 
510  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
511  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
512 
513  return false;
514 }
515 
516 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
517  LLVM_DEBUG(dbgs() << "parseOperand\n");
518 
519  switch (getLexer().getKind()) {
520  default:
521  return Error(Parser.getTok().getLoc(), "unexpected token in operand");
522 
524  // Try to parse a register, if it fails,
525  // fall through to the next case.
526  if (!tryParseRegisterOperand(Operands)) {
527  return false;
528  }
530  case AsmToken::LParen:
531  case AsmToken::Integer:
532  case AsmToken::Dot:
533  return tryParseExpression(Operands);
534  case AsmToken::Plus:
535  case AsmToken::Minus: {
536  // If the sign preceeds a number, parse the number,
537  // otherwise treat the sign a an independent token.
538  switch (getLexer().peekTok().getKind()) {
539  case AsmToken::Integer:
540  case AsmToken::BigNum:
542  case AsmToken::Real:
543  if (!tryParseExpression(Operands))
544  return false;
545  break;
546  default:
547  break;
548  }
549  // Treat the token as an independent token.
550  Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
551  Parser.getTok().getLoc()));
552  Parser.Lex(); // Eat the token.
553  return false;
554  }
555  }
556 
557  // Could not parse operand
558  return true;
559 }
560 
561 OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
562  LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
563 
564  SMLoc E, S;
565  MCExpr const *Expression;
566  int RegNo;
567 
568  // Parse register.
569  {
570  RegNo = parseRegister();
571 
572  if (RegNo == AVR::NoRegister)
573  return MatchOperand_ParseFail;
574 
575  S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
576  Parser.Lex(); // Eat register token.
577  }
578 
579  // Parse immediate;
580  {
581  if (getParser().parseExpression(Expression))
582  return MatchOperand_ParseFail;
583 
584  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
585  }
586 
587  Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
588 
589  return MatchOperand_Success;
590 }
591 
592 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
593  SMLoc &EndLoc) {
594  StartLoc = Parser.getTok().getLoc();
595  RegNo = parseRegister(/*RestoreOnFailure=*/false);
596  EndLoc = Parser.getTok().getLoc();
597 
598  return (RegNo == AVR::NoRegister);
599 }
600 
601 OperandMatchResultTy AVRAsmParser::tryParseRegister(unsigned &RegNo,
602  SMLoc &StartLoc,
603  SMLoc &EndLoc) {
604  StartLoc = Parser.getTok().getLoc();
605  RegNo = parseRegister(/*RestoreOnFailure=*/true);
606  EndLoc = Parser.getTok().getLoc();
607 
608  if (RegNo == AVR::NoRegister)
609  return MatchOperand_NoMatch;
610  return MatchOperand_Success;
611 }
612 
613 void AVRAsmParser::eatComma() {
614  if (getLexer().is(AsmToken::Comma)) {
615  Parser.Lex();
616  } else {
617  // GCC allows commas to be omitted.
618  }
619 }
620 
621 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
622  StringRef Mnemonic, SMLoc NameLoc,
624  Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
625 
626  bool first = true;
627  while (getLexer().isNot(AsmToken::EndOfStatement)) {
628  if (!first)
629  eatComma();
630 
631  first = false;
632 
633  auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
634 
635  if (MatchResult == MatchOperand_Success) {
636  continue;
637  }
638 
639  if (MatchResult == MatchOperand_ParseFail) {
640  SMLoc Loc = getLexer().getLoc();
641  Parser.eatToEndOfStatement();
642 
643  return Error(Loc, "failed to parse register and immediate pair");
644  }
645 
646  if (parseOperand(Operands)) {
647  SMLoc Loc = getLexer().getLoc();
648  Parser.eatToEndOfStatement();
649  return Error(Loc, "unexpected token in argument list");
650  }
651  }
652  Parser.Lex(); // Consume the EndOfStatement
653  return false;
654 }
655 
656 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
657  StringRef IDVal = DirectiveID.getIdentifier();
658  if (IDVal.lower() == ".long") {
659  parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
660  } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
661  parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
662  } else if (IDVal.lower() == ".byte") {
663  parseLiteralValues(1, DirectiveID.getLoc());
664  }
665  return true;
666 }
667 
668 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
669  MCAsmParser &Parser = getParser();
670  AVRMCELFStreamer &AVRStreamer =
671  static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
672  AsmToken Tokens[2];
673  size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
674  if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
675  Tokens[0].getKind() == AsmToken::Minus &&
676  Tokens[1].getKind() == AsmToken::Identifier) {
677  MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
678  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L,
680  return false;
681  }
682 
683  if (Parser.getTok().getKind() == AsmToken::Identifier &&
684  Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
685  StringRef ModifierName = Parser.getTok().getString();
686  AVRMCExpr::VariantKind ModifierKind =
687  AVRMCExpr::getKindByName(ModifierName);
688  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
689  Parser.Lex();
690  Parser.Lex(); // Eat the modifier and parenthesis
691  } else {
692  return Error(Parser.getTok().getLoc(), "unknown modifier");
693  }
694  MCSymbol *Symbol =
695  getContext().getOrCreateSymbol(Parser.getTok().getString());
696  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
697  return false;
698  }
699 
700  auto parseOne = [&]() -> bool {
701  const MCExpr *Value;
702  if (Parser.parseExpression(Value))
703  return true;
704  Parser.getStreamer().emitValue(Value, SizeInBytes, L);
705  return false;
706  };
707  return (parseMany(parseOne));
708 }
709 
712 }
713 
714 #define GET_REGISTER_MATCHER
715 #define GET_MATCHER_IMPLEMENTATION
716 #include "AVRGenAsmMatcher.inc"
717 
718 // Uses enums defined in AVRGenAsmMatcher.inc
719 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
720  unsigned ExpectedKind) {
721  AVROperand &Op = static_cast<AVROperand &>(AsmOp);
722  MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
723 
724  // If need be, GCC converts bare numbers to register names
725  // It's ugly, but GCC supports it.
726  if (Op.isImm()) {
727  if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
728  int64_t RegNum = Const->getValue();
729  std::ostringstream RegName;
730  RegName << "r" << RegNum;
731  RegNum = MatchRegisterName(RegName.str());
732  if (RegNum != AVR::NoRegister) {
733  Op.makeReg(RegNum);
734  if (validateOperandClass(Op, Expected) == Match_Success) {
735  return Match_Success;
736  }
737  }
738  // Let the other quirks try their magic.
739  }
740  }
741 
742  if (Op.isReg()) {
743  // If the instruction uses a register pair but we got a single, lower
744  // register we perform a "class cast".
745  if (isSubclass(Expected, MCK_DREGS)) {
746  unsigned correspondingDREG = toDREG(Op.getReg());
747 
748  if (correspondingDREG != AVR::NoRegister) {
749  Op.makeReg(correspondingDREG);
750  return validateOperandClass(Op, Expected);
751  }
752  }
753  }
754  return Match_InvalidOperand;
755 }
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
MathExtras.h
llvm::MCAsmParser::getStreamer
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::AVRMCExpr::getKindByName
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:209
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:39
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:147
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::MCAsmLexer::peekTok
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:113
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
AVRMCELFStreamer.h
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
MCParsedAsmOperand.h
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
MCInstBuilder.h
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:177
APInt.h
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:42
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCTargetAsmParser.h
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
AVRMCExpr.h
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
LLVMInitializeAVRAsmParser
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmParser()
Definition: AVRAsmParser.cpp:710
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1317
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:122
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::AVRMCExpr::VK_AVR_None
@ VK_AVR_None
Definition: AVRMCExpr.h:23
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MatchRegisterAltName
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
MCContext.h
llvm::AVRMCELFStreamer::emitValueForModiferKind
void emitValueForModiferKind(const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc=SMLoc(), AVRMCExpr::VariantKind ModifierKind=AVRMCExpr::VK_AVR_None)
Definition: AVRMCELFStreamer.cpp:23
MCSymbol.h
MCInst.h
llvm::getTheAVRTarget
Target & getTheAVRTarget()
Definition: AVRTargetInfo.cpp:12
llvm::SIZE_WORD
const int SIZE_WORD
Definition: AVRMCELFStreamer.h:23
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::Instruction
Definition: Instruction.h:45
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
AVRTargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AsmToken::getKind
TokenKind getKind() const
Definition: MCAsmMacro.h:81
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:2804
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:197
llvm::AVRMCExpr::create
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:38
MCAsmLexer.h
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:113
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCAsmParserExtension::Initialize
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Definition: MCAsmParserExtension.cpp:19
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1087
llvm::AsmToken::Colon
@ Colon
Definition: MCAsmMacro.h:43
llvm::MatchOperand_ParseFail
@ MatchOperand_ParseFail
Definition: MCTargetAsmParser.h:124
llvm::AsmToken::BigNum
@ BigNum
Definition: MCAsmMacro.h:33
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AVRMCELFStreamer
Definition: AVRMCELFStreamer.h:25
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::SIZE_LONG
const int SIZE_LONG
Definition: AVRMCELFStreamer.h:22
AVRMCTargetDesc.h
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:349
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::AsmToken::Comma
@ Comma
Definition: MCAsmMacro.h:49
llvm::Expression
Class representing an expression and its matching format.
Definition: FileCheckImpl.h:237
AVRRegisterInfo.h
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:123
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:38
llvm::AsmToken::Plus
@ Plus
Definition: MCAsmMacro.h:45
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AsmToken::RParen
@ RParen
Definition: MCAsmMacro.h:48
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::AsmToken::getString
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:121
llvm::MCAsmLexer::getKind
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:140
llvm::MCAsmParser::eatToEndOfStatement
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::AsmToken::Real
@ Real
Definition: MCAsmMacro.h:36
llvm::AsmToken::Identifier
@ Identifier
Definition: MCAsmMacro.h:28
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::AVRMCExpr::VariantKind
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:22
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:309
AVR.h
MCValue.h
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::AsmToken::TokenKind
TokenKind
Definition: MCAsmMacro.h:23
llvm::MCAsmLexer::peekTokens
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
llvm::MCAsmParser::getLexer
virtual MCAsmLexer & getLexer()=0
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
N
#define N
MCStreamer.h
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:123
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
RegName
#define RegName(no)
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572