LLVM  16.0.0git
AVRAsmParser.cpp
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1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AVR.h"
10 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCExpr.h"
15 
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/Support/Debug.h"
31 
32 #include <sstream>
33 
34 #define DEBUG_TYPE "avr-asm-parser"
35 
36 using namespace llvm;
37 
38 namespace {
39 /// Parses AVR assembly from a stream.
40 class AVRAsmParser : public MCTargetAsmParser {
41  const MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43  const MCRegisterInfo *MRI;
44  const std::string GENERATE_STUBS = "gs";
45 
46  enum AVRMatchResultTy {
47  Match_InvalidRegisterOnTiny = FIRST_TARGET_MATCH_RESULT_TY + 1,
48  };
49 
50 #define GET_ASSEMBLER_HEADER
51 #include "AVRGenAsmMatcher.inc"
52 
53  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
56  bool MatchingInlineAsm) override;
57 
58  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
59  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
60  SMLoc &EndLoc) override;
61 
62  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
63  SMLoc NameLoc, OperandVector &Operands) override;
64 
65  bool ParseDirective(AsmToken DirectiveID) override;
66 
67  OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
68 
69  bool parseOperand(OperandVector &Operands);
70  int parseRegisterName(unsigned (*matchFn)(StringRef));
71  int parseRegisterName();
72  int parseRegister(bool RestoreOnFailure = false);
73  bool tryParseRegisterOperand(OperandVector &Operands);
74  bool tryParseExpression(OperandVector &Operands);
75  bool tryParseRelocExpression(OperandVector &Operands);
76  void eatComma();
77 
78  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
79  unsigned Kind) override;
80 
81  unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
82  MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
83  return MRI->getMatchingSuperReg(Reg, From, Class);
84  }
85 
86  bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
87  bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
88  uint64_t const &ErrorInfo);
89  bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
90 
91  bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
92 
93 public:
94  AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
95  const MCInstrInfo &MII, const MCTargetOptions &Options)
96  : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
98  MRI = getContext().getRegisterInfo();
99 
100  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
101  }
102 
103  MCAsmParser &getParser() const { return Parser; }
104  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
105 };
106 
107 /// An parsed AVR assembly operand.
108 class AVROperand : public MCParsedAsmOperand {
109  typedef MCParsedAsmOperand Base;
110  enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
111 
112 public:
113  AVROperand(StringRef Tok, SMLoc const &S)
114  : Kind(k_Token), Tok(Tok), Start(S), End(S) {}
115  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
116  : Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
117  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
118  : Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
119  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
120  : Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
121 
122  struct RegisterImmediate {
123  unsigned Reg;
124  MCExpr const *Imm;
125  };
126  union {
127  StringRef Tok;
128  RegisterImmediate RegImm;
129  };
130 
131  SMLoc Start, End;
132 
133 public:
134  void addRegOperands(MCInst &Inst, unsigned N) const {
135  assert(Kind == k_Register && "Unexpected operand kind");
136  assert(N == 1 && "Invalid number of operands!");
137 
139  }
140 
141  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142  // Add as immediate when possible
143  if (!Expr)
145  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
146  Inst.addOperand(MCOperand::createImm(CE->getValue()));
147  else
148  Inst.addOperand(MCOperand::createExpr(Expr));
149  }
150 
151  void addImmOperands(MCInst &Inst, unsigned N) const {
152  assert(Kind == k_Immediate && "Unexpected operand kind");
153  assert(N == 1 && "Invalid number of operands!");
154 
155  const MCExpr *Expr = getImm();
156  addExpr(Inst, Expr);
157  }
158 
159  /// Adds the contained reg+imm operand to an instruction.
160  void addMemriOperands(MCInst &Inst, unsigned N) const {
161  assert(Kind == k_Memri && "Unexpected operand kind");
162  assert(N == 2 && "Invalid number of operands");
163 
165  addExpr(Inst, getImm());
166  }
167 
168  void addImmCom8Operands(MCInst &Inst, unsigned N) const {
169  assert(N == 1 && "Invalid number of operands!");
170  // The operand is actually a imm8, but we have its bitwise
171  // negation in the assembly source, so twiddle it here.
172  const auto *CE = cast<MCConstantExpr>(getImm());
173  Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
174  }
175 
176  bool isImmCom8() const {
177  if (!isImm())
178  return false;
179  const auto *CE = dyn_cast<MCConstantExpr>(getImm());
180  if (!CE)
181  return false;
182  int64_t Value = CE->getValue();
183  return isUInt<8>(Value);
184  }
185 
186  bool isReg() const override { return Kind == k_Register; }
187  bool isImm() const override { return Kind == k_Immediate; }
188  bool isToken() const override { return Kind == k_Token; }
189  bool isMem() const override { return Kind == k_Memri; }
190  bool isMemri() const { return Kind == k_Memri; }
191 
192  StringRef getToken() const {
193  assert(Kind == k_Token && "Invalid access!");
194  return Tok;
195  }
196 
197  unsigned getReg() const override {
198  assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
199 
200  return RegImm.Reg;
201  }
202 
203  const MCExpr *getImm() const {
204  assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
205  return RegImm.Imm;
206  }
207 
208  static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
209  return std::make_unique<AVROperand>(Str, S);
210  }
211 
212  static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
213  SMLoc E) {
214  return std::make_unique<AVROperand>(RegNum, S, E);
215  }
216 
217  static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
218  SMLoc E) {
219  return std::make_unique<AVROperand>(Val, S, E);
220  }
221 
222  static std::unique_ptr<AVROperand>
223  CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
224  return std::make_unique<AVROperand>(RegNum, Val, S, E);
225  }
226 
227  void makeToken(StringRef Token) {
228  Kind = k_Token;
229  Tok = Token;
230  }
231 
232  void makeReg(unsigned RegNo) {
233  Kind = k_Register;
234  RegImm = {RegNo, nullptr};
235  }
236 
237  void makeImm(MCExpr const *Ex) {
238  Kind = k_Immediate;
239  RegImm = {0, Ex};
240  }
241 
242  void makeMemri(unsigned RegNo, MCExpr const *Imm) {
243  Kind = k_Memri;
244  RegImm = {RegNo, Imm};
245  }
246 
247  SMLoc getStartLoc() const override { return Start; }
248  SMLoc getEndLoc() const override { return End; }
249 
250  void print(raw_ostream &O) const override {
251  switch (Kind) {
252  case k_Token:
253  O << "Token: \"" << getToken() << "\"";
254  break;
255  case k_Register:
256  O << "Register: " << getReg();
257  break;
258  case k_Immediate:
259  O << "Immediate: \"" << *getImm() << "\"";
260  break;
261  case k_Memri: {
262  // only manually print the size for non-negative values,
263  // as the sign is inserted automatically.
264  O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
265  break;
266  }
267  }
268  O << "\n";
269  }
270 };
271 
272 } // end anonymous namespace.
273 
274 // Auto-generated Match Functions
275 
276 /// Maps from the set of all register names to a register number.
277 /// \note Generated by TableGen.
278 static unsigned MatchRegisterName(StringRef Name);
279 
280 /// Maps from the set of all alternative registernames to a register number.
281 /// \note Generated by TableGen.
282 static unsigned MatchRegisterAltName(StringRef Name);
283 
284 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
285  OperandVector const &Operands,
286  uint64_t const &ErrorInfo) {
287  SMLoc ErrorLoc = Loc;
288  char const *Diag = nullptr;
289 
290  if (ErrorInfo != ~0U) {
291  if (ErrorInfo >= Operands.size()) {
292  Diag = "too few operands for instruction.";
293  } else {
294  AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
295 
296  // TODO: See if we can do a better error than just "invalid ...".
297  if (Op.getStartLoc() != SMLoc()) {
298  ErrorLoc = Op.getStartLoc();
299  }
300  }
301  }
302 
303  if (!Diag) {
304  Diag = "invalid operand for instruction";
305  }
306 
307  return Error(ErrorLoc, Diag);
308 }
309 
310 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
311  uint64_t const &ErrorInfo) {
312  return Error(Loc, "instruction requires a CPU feature not currently enabled");
313 }
314 
315 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
316  Inst.setLoc(Loc);
317  Out.emitInstruction(Inst, STI);
318 
319  return false;
320 }
321 
322 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
325  bool MatchingInlineAsm) {
326  MCInst Inst;
327  unsigned MatchResult =
328  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
329 
330  switch (MatchResult) {
331  case Match_Success:
332  return emit(Inst, Loc, Out);
333  case Match_MissingFeature:
334  return missingFeature(Loc, ErrorInfo);
335  case Match_InvalidOperand:
336  return invalidOperand(Loc, Operands, ErrorInfo);
337  case Match_MnemonicFail:
338  return Error(Loc, "invalid instruction");
339  case Match_InvalidRegisterOnTiny:
340  return Error(Loc, "invalid register on avrtiny");
341  default:
342  return true;
343  }
344 }
345 
346 /// Parses a register name using a given matching function.
347 /// Checks for lowercase or uppercase if necessary.
348 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
349  StringRef Name = Parser.getTok().getString();
350 
351  int RegNum = matchFn(Name);
352 
353  // GCC supports case insensitive register names. Some of the AVR registers
354  // are all lower case, some are all upper case but non are mixed. We prefer
355  // to use the original names in the register definitions. That is why we
356  // have to test both upper and lower case here.
357  if (RegNum == AVR::NoRegister) {
358  RegNum = matchFn(Name.lower());
359  }
360  if (RegNum == AVR::NoRegister) {
361  RegNum = matchFn(Name.upper());
362  }
363 
364  return RegNum;
365 }
366 
367 int AVRAsmParser::parseRegisterName() {
368  int RegNum = parseRegisterName(&MatchRegisterName);
369 
370  if (RegNum == AVR::NoRegister)
371  RegNum = parseRegisterName(&MatchRegisterAltName);
372 
373  return RegNum;
374 }
375 
376 int AVRAsmParser::parseRegister(bool RestoreOnFailure) {
377  int RegNum = AVR::NoRegister;
378 
379  if (Parser.getTok().is(AsmToken::Identifier)) {
380  // Check for register pair syntax
381  if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
382  AsmToken HighTok = Parser.getTok();
383  Parser.Lex();
384  AsmToken ColonTok = Parser.getTok();
385  Parser.Lex(); // Eat high (odd) register and colon
386 
387  if (Parser.getTok().is(AsmToken::Identifier)) {
388  // Convert lower (even) register to DREG
389  RegNum = toDREG(parseRegisterName());
390  }
391  if (RegNum == AVR::NoRegister && RestoreOnFailure) {
392  getLexer().UnLex(std::move(ColonTok));
393  getLexer().UnLex(std::move(HighTok));
394  }
395  } else {
396  RegNum = parseRegisterName();
397  }
398  }
399  return RegNum;
400 }
401 
402 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
403  int RegNo = parseRegister();
404 
405  if (RegNo == AVR::NoRegister)
406  return true;
407 
408  // Reject R0~R15 on avrtiny.
409  if (AVR::R0 <= RegNo && RegNo <= AVR::R15 &&
410  STI.hasFeature(AVR::FeatureTinyEncoding))
411  return Error(Parser.getTok().getLoc(), "invalid register on avrtiny");
412 
413  AsmToken const &T = Parser.getTok();
414  Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
415  Parser.Lex(); // Eat register token.
416 
417  return false;
418 }
419 
420 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
421  SMLoc S = Parser.getTok().getLoc();
422 
423  if (!tryParseRelocExpression(Operands))
424  return false;
425 
426  if ((Parser.getTok().getKind() == AsmToken::Plus ||
427  Parser.getTok().getKind() == AsmToken::Minus) &&
428  Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
429  // Don't handle this case - it should be split into two
430  // separate tokens.
431  return true;
432  }
433 
434  // Parse (potentially inner) expression
435  MCExpr const *Expression;
436  if (getParser().parseExpression(Expression))
437  return true;
438 
439  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
440  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
441  return false;
442 }
443 
444 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
445  bool isNegated = false;
447 
448  SMLoc S = Parser.getTok().getLoc();
449 
450  // Check for sign
451  AsmToken tokens[2];
452  size_t ReadCount = Parser.getLexer().peekTokens(tokens);
453 
454  if (ReadCount == 2) {
455  if ((tokens[0].getKind() == AsmToken::Identifier &&
456  tokens[1].getKind() == AsmToken::LParen) ||
457  (tokens[0].getKind() == AsmToken::LParen &&
458  tokens[1].getKind() == AsmToken::Minus)) {
459 
460  AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
461  if (CurTok == AsmToken::Minus || tokens[1].getKind() == AsmToken::Minus) {
462  isNegated = true;
463  } else {
464  assert(CurTok == AsmToken::Plus);
465  isNegated = false;
466  }
467 
468  // Eat the sign
469  if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
470  Parser.Lex();
471  }
472  }
473 
474  // Check if we have a target specific modifier (lo8, hi8, &c)
475  if (Parser.getTok().getKind() != AsmToken::Identifier ||
476  Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
477  // Not a reloc expr
478  return true;
479  }
480  StringRef ModifierName = Parser.getTok().getString();
481  ModifierKind = AVRMCExpr::getKindByName(ModifierName);
482 
483  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
484  Parser.Lex();
485  Parser.Lex(); // Eat modifier name and parenthesis
486  if (Parser.getTok().getString() == GENERATE_STUBS &&
487  Parser.getTok().getKind() == AsmToken::Identifier) {
488  std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
489  ModifierKind = AVRMCExpr::getKindByName(GSModName);
490  if (ModifierKind != AVRMCExpr::VK_AVR_None)
491  Parser.Lex(); // Eat gs modifier name
492  }
493  } else {
494  return Error(Parser.getTok().getLoc(), "unknown modifier");
495  }
496 
497  if (tokens[1].getKind() == AsmToken::Minus ||
498  tokens[1].getKind() == AsmToken::Plus) {
499  Parser.Lex();
500  assert(Parser.getTok().getKind() == AsmToken::LParen);
501  Parser.Lex(); // Eat the sign and parenthesis
502  }
503 
504  MCExpr const *InnerExpression;
505  if (getParser().parseExpression(InnerExpression))
506  return true;
507 
508  if (tokens[1].getKind() == AsmToken::Minus ||
509  tokens[1].getKind() == AsmToken::Plus) {
510  assert(Parser.getTok().getKind() == AsmToken::RParen);
511  Parser.Lex(); // Eat closing parenthesis
512  }
513 
514  // If we have a modifier wrap the inner expression
515  assert(Parser.getTok().getKind() == AsmToken::RParen);
516  Parser.Lex(); // Eat closing parenthesis
517 
518  MCExpr const *Expression =
519  AVRMCExpr::create(ModifierKind, InnerExpression, isNegated, getContext());
520 
521  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
522  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
523 
524  return false;
525 }
526 
527 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
528  LLVM_DEBUG(dbgs() << "parseOperand\n");
529 
530  switch (getLexer().getKind()) {
531  default:
532  return Error(Parser.getTok().getLoc(), "unexpected token in operand");
533 
535  // Try to parse a register, if it fails,
536  // fall through to the next case.
537  if (!tryParseRegisterOperand(Operands)) {
538  return false;
539  }
540  [[fallthrough]];
541  case AsmToken::LParen:
542  case AsmToken::Integer:
543  case AsmToken::Dot:
544  return tryParseExpression(Operands);
545  case AsmToken::Plus:
546  case AsmToken::Minus: {
547  // If the sign preceeds a number, parse the number,
548  // otherwise treat the sign a an independent token.
549  switch (getLexer().peekTok().getKind()) {
550  case AsmToken::Integer:
551  case AsmToken::BigNum:
553  case AsmToken::Real:
554  if (!tryParseExpression(Operands))
555  return false;
556  break;
557  default:
558  break;
559  }
560  // Treat the token as an independent token.
561  Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
562  Parser.getTok().getLoc()));
563  Parser.Lex(); // Eat the token.
564  return false;
565  }
566  }
567 
568  // Could not parse operand
569  return true;
570 }
571 
572 OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
573  LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
574 
575  SMLoc E, S;
576  MCExpr const *Expression;
577  int RegNo;
578 
579  // Parse register.
580  {
581  RegNo = parseRegister();
582 
583  if (RegNo == AVR::NoRegister)
584  return MatchOperand_ParseFail;
585 
586  S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
587  Parser.Lex(); // Eat register token.
588  }
589 
590  // Parse immediate;
591  {
592  if (getParser().parseExpression(Expression))
593  return MatchOperand_ParseFail;
594 
595  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
596  }
597 
598  Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
599 
600  return MatchOperand_Success;
601 }
602 
603 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
604  SMLoc &EndLoc) {
605  StartLoc = Parser.getTok().getLoc();
606  RegNo = parseRegister(/*RestoreOnFailure=*/false);
607  EndLoc = Parser.getTok().getLoc();
608 
609  return (RegNo == AVR::NoRegister);
610 }
611 
612 OperandMatchResultTy AVRAsmParser::tryParseRegister(unsigned &RegNo,
613  SMLoc &StartLoc,
614  SMLoc &EndLoc) {
615  StartLoc = Parser.getTok().getLoc();
616  RegNo = parseRegister(/*RestoreOnFailure=*/true);
617  EndLoc = Parser.getTok().getLoc();
618 
619  if (RegNo == AVR::NoRegister)
620  return MatchOperand_NoMatch;
621  return MatchOperand_Success;
622 }
623 
624 void AVRAsmParser::eatComma() {
625  if (getLexer().is(AsmToken::Comma)) {
626  Parser.Lex();
627  } else {
628  // GCC allows commas to be omitted.
629  }
630 }
631 
632 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
633  StringRef Mnemonic, SMLoc NameLoc,
635  Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
636 
637  bool first = true;
638  while (getLexer().isNot(AsmToken::EndOfStatement)) {
639  if (!first)
640  eatComma();
641 
642  first = false;
643 
644  auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
645 
646  if (MatchResult == MatchOperand_Success) {
647  continue;
648  }
649 
650  if (MatchResult == MatchOperand_ParseFail) {
651  SMLoc Loc = getLexer().getLoc();
652  Parser.eatToEndOfStatement();
653 
654  return Error(Loc, "failed to parse register and immediate pair");
655  }
656 
657  if (parseOperand(Operands)) {
658  SMLoc Loc = getLexer().getLoc();
659  Parser.eatToEndOfStatement();
660  return Error(Loc, "unexpected token in argument list");
661  }
662  }
663  Parser.Lex(); // Consume the EndOfStatement
664  return false;
665 }
666 
667 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
668  StringRef IDVal = DirectiveID.getIdentifier();
669  if (IDVal.lower() == ".long") {
670  parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
671  } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
672  parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
673  } else if (IDVal.lower() == ".byte") {
674  parseLiteralValues(1, DirectiveID.getLoc());
675  }
676  return true;
677 }
678 
679 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
680  MCAsmParser &Parser = getParser();
681  AVRMCELFStreamer &AVRStreamer =
682  static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
683  AsmToken Tokens[2];
684  size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
685  if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
686  Tokens[0].getKind() == AsmToken::Minus &&
687  Tokens[1].getKind() == AsmToken::Identifier) {
688  MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
689  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L,
691  return false;
692  }
693 
694  if (Parser.getTok().getKind() == AsmToken::Identifier &&
695  Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
696  StringRef ModifierName = Parser.getTok().getString();
697  AVRMCExpr::VariantKind ModifierKind =
698  AVRMCExpr::getKindByName(ModifierName);
699  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
700  Parser.Lex();
701  Parser.Lex(); // Eat the modifier and parenthesis
702  } else {
703  return Error(Parser.getTok().getLoc(), "unknown modifier");
704  }
705  MCSymbol *Symbol =
706  getContext().getOrCreateSymbol(Parser.getTok().getString());
707  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
708  return false;
709  }
710 
711  auto parseOne = [&]() -> bool {
712  const MCExpr *Value;
713  if (Parser.parseExpression(Value))
714  return true;
715  Parser.getStreamer().emitValue(Value, SizeInBytes, L);
716  return false;
717  };
718  return (parseMany(parseOne));
719 }
720 
723 }
724 
725 #define GET_REGISTER_MATCHER
726 #define GET_MATCHER_IMPLEMENTATION
727 #include "AVRGenAsmMatcher.inc"
728 
729 // Uses enums defined in AVRGenAsmMatcher.inc
730 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
731  unsigned ExpectedKind) {
732  AVROperand &Op = static_cast<AVROperand &>(AsmOp);
733  MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
734 
735  // If need be, GCC converts bare numbers to register names
736  // It's ugly, but GCC supports it.
737  if (Op.isImm()) {
738  if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
739  int64_t RegNum = Const->getValue();
740 
741  // Reject R0~R15 on avrtiny.
742  if (0 <= RegNum && RegNum <= 15 &&
743  STI.hasFeature(AVR::FeatureTinyEncoding))
744  return Match_InvalidRegisterOnTiny;
745 
746  std::ostringstream RegName;
747  RegName << "r" << RegNum;
748  RegNum = MatchRegisterName(RegName.str());
749  if (RegNum != AVR::NoRegister) {
750  Op.makeReg(RegNum);
751  if (validateOperandClass(Op, Expected) == Match_Success) {
752  return Match_Success;
753  }
754  }
755  // Let the other quirks try their magic.
756  }
757  }
758 
759  if (Op.isReg()) {
760  // If the instruction uses a register pair but we got a single, lower
761  // register we perform a "class cast".
762  if (isSubclass(Expected, MCK_DREGS)) {
763  unsigned correspondingDREG = toDREG(Op.getReg());
764 
765  if (correspondingDREG != AVR::NoRegister) {
766  Op.makeReg(correspondingDREG);
767  return validateOperandClass(Op, Expected);
768  }
769  }
770  }
771  return Match_InvalidOperand;
772 }
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
MathExtras.h
llvm::MCAsmParser::getStreamer
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::AVRMCExpr::getKindByName
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:209
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:37
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:189
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::MCAsmLexer::peekTok
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:111
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
AVRMCELFStreamer.h
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
MCParsedAsmOperand.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
MCInstBuilder.h
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:178
APInt.h
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCTargetAsmParser.h
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:1053
AVRMCExpr.h
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
LLVMInitializeAVRAsmParser
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmParser()
Definition: AVRAsmParser.cpp:721
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1360
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:127
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::AVRMCExpr::VK_AVR_None
@ VK_AVR_None
Definition: AVRMCExpr.h:23
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
MatchRegisterAltName
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
MCContext.h
llvm::AVRMCELFStreamer::emitValueForModiferKind
void emitValueForModiferKind(const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc=SMLoc(), AVRMCExpr::VariantKind ModifierKind=AVRMCExpr::VK_AVR_None)
Definition: AVRMCELFStreamer.cpp:23
MCSymbol.h
MCInst.h
llvm::getTheAVRTarget
Target & getTheAVRTarget()
Definition: AVRTargetInfo.cpp:12
llvm::SIZE_WORD
const int SIZE_WORD
Definition: AVRMCELFStreamer.h:23
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::Instruction
Definition: Instruction.h:42
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
AVRTargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::AsmToken::getKind
TokenKind getKind() const
Definition: MCAsmMacro.h:81
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:3219
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:240
llvm::AVRMCExpr::create
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:38
MCAsmLexer.h
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:118
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::MCAsmParserExtension::Initialize
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Definition: MCAsmParserExtension.cpp:21
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1096
llvm::AsmToken::Colon
@ Colon
Definition: MCAsmMacro.h:43
llvm::MatchOperand_ParseFail
@ MatchOperand_ParseFail
Definition: MCTargetAsmParser.h:129
llvm::AsmToken::BigNum
@ BigNum
Definition: MCAsmMacro.h:33
llvm::StringRef::lower
std::string lower() const
Definition: StringRef.cpp:112
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AVRMCELFStreamer
Definition: AVRMCELFStreamer.h:25
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:401
llvm::SIZE_LONG
const int SIZE_LONG
Definition: AVRMCELFStreamer.h:22
AVRMCTargetDesc.h
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:347
llvm::MCTargetOptions
Definition: MCTargetOptions.h:41
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::AsmToken::Comma
@ Comma
Definition: MCAsmMacro.h:49
llvm::Expression
Class representing an expression and its matching format.
Definition: FileCheckImpl.h:237
AVRRegisterInfo.h
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:128
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:38
llvm::AsmToken::Plus
@ Plus
Definition: MCAsmMacro.h:45
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AsmToken::RParen
@ RParen
Definition: MCAsmMacro.h:48
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AsmToken::getString
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:126
llvm::MCAsmLexer::getKind
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:138
llvm::MCAsmParser::eatToEndOfStatement
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::AsmToken::Real
@ Real
Definition: MCAsmMacro.h:36
llvm::AsmToken::Identifier
@ Identifier
Definition: MCAsmMacro.h:28
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::AVRMCExpr::VariantKind
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:22
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:314
AVR.h
MCValue.h
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AsmToken::TokenKind
TokenKind
Definition: MCAsmMacro.h:23
llvm::MCAsmLexer::peekTokens
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
llvm::RISCVMatInt::RegImm
@ RegImm
Definition: RISCVMatInt.h:22
llvm::MCAsmParser::getLexer
virtual MCAsmLexer & getLexer()=0
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
N
#define N
MCStreamer.h
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
RegName
#define RegName(no)
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:213
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58