LLVM 17.0.0git
AVRAsmParser.cpp
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1//===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AVR.h"
10#include "AVRRegisterInfo.h"
15
16#include "llvm/ADT/APInt.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCStreamer.h"
26#include "llvm/MC/MCSymbol.h"
27#include "llvm/MC/MCValue.h"
29#include "llvm/Support/Debug.h"
31
32#include <array>
33#include <sstream>
34
35#define DEBUG_TYPE "avr-asm-parser"
36
37using namespace llvm;
38
39namespace {
40/// Parses AVR assembly from a stream.
41class AVRAsmParser : public MCTargetAsmParser {
42 const MCSubtargetInfo &STI;
43 MCAsmParser &Parser;
44 const MCRegisterInfo *MRI;
45 const std::string GENERATE_STUBS = "gs";
46
47 enum AVRMatchResultTy {
48 Match_InvalidRegisterOnTiny = FIRST_TARGET_MATCH_RESULT_TY + 1,
49 };
50
51#define GET_ASSEMBLER_HEADER
52#include "AVRGenAsmMatcher.inc"
53
54 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
57 bool MatchingInlineAsm) override;
58
59 bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
60 SMLoc &EndLoc) override;
62 SMLoc &EndLoc) override;
63
65 SMLoc NameLoc, OperandVector &Operands) override;
66
67 bool ParseDirective(AsmToken DirectiveID) override;
68
70
71 bool parseOperand(OperandVector &Operands, bool maybeReg);
72 int parseRegisterName(unsigned (*matchFn)(StringRef));
73 int parseRegisterName();
74 int parseRegister(bool RestoreOnFailure = false);
75 bool tryParseRegisterOperand(OperandVector &Operands);
76 bool tryParseExpression(OperandVector &Operands);
77 bool tryParseRelocExpression(OperandVector &Operands);
78 void eatComma();
79
81 unsigned Kind) override;
82
83 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
84 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
85 return MRI->getMatchingSuperReg(Reg, From, Class);
86 }
87
88 bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
89 bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
90 uint64_t const &ErrorInfo);
91 bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
92
93 bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
94
95public:
96 AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
97 const MCInstrInfo &MII, const MCTargetOptions &Options)
98 : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
101
102 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
103 }
104
105 MCAsmParser &getParser() const { return Parser; }
106 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
107};
108
109/// An parsed AVR assembly operand.
110class AVROperand : public MCParsedAsmOperand {
111 typedef MCParsedAsmOperand Base;
112 enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
113
114public:
115 AVROperand(StringRef Tok, SMLoc const &S)
116 : Kind(k_Token), Tok(Tok), Start(S), End(S) {}
117 AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
118 : Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
119 AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
120 : Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
121 AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
122 : Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
123
124 struct RegisterImmediate {
125 unsigned Reg;
126 MCExpr const *Imm;
127 };
128 union {
129 StringRef Tok;
130 RegisterImmediate RegImm;
131 };
132
133 SMLoc Start, End;
134
135public:
136 void addRegOperands(MCInst &Inst, unsigned N) const {
137 assert(Kind == k_Register && "Unexpected operand kind");
138 assert(N == 1 && "Invalid number of operands!");
139
141 }
142
143 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
144 // Add as immediate when possible
145 if (!Expr)
147 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
148 Inst.addOperand(MCOperand::createImm(CE->getValue()));
149 else
151 }
152
153 void addImmOperands(MCInst &Inst, unsigned N) const {
154 assert(Kind == k_Immediate && "Unexpected operand kind");
155 assert(N == 1 && "Invalid number of operands!");
156
157 const MCExpr *Expr = getImm();
158 addExpr(Inst, Expr);
159 }
160
161 /// Adds the contained reg+imm operand to an instruction.
162 void addMemriOperands(MCInst &Inst, unsigned N) const {
163 assert(Kind == k_Memri && "Unexpected operand kind");
164 assert(N == 2 && "Invalid number of operands");
165
167 addExpr(Inst, getImm());
168 }
169
170 void addImmCom8Operands(MCInst &Inst, unsigned N) const {
171 assert(N == 1 && "Invalid number of operands!");
172 // The operand is actually a imm8, but we have its bitwise
173 // negation in the assembly source, so twiddle it here.
174 const auto *CE = cast<MCConstantExpr>(getImm());
175 Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
176 }
177
178 bool isImmCom8() const {
179 if (!isImm())
180 return false;
181 const auto *CE = dyn_cast<MCConstantExpr>(getImm());
182 if (!CE)
183 return false;
184 int64_t Value = CE->getValue();
185 return isUInt<8>(Value);
186 }
187
188 bool isReg() const override { return Kind == k_Register; }
189 bool isImm() const override { return Kind == k_Immediate; }
190 bool isToken() const override { return Kind == k_Token; }
191 bool isMem() const override { return Kind == k_Memri; }
192 bool isMemri() const { return Kind == k_Memri; }
193
194 StringRef getToken() const {
195 assert(Kind == k_Token && "Invalid access!");
196 return Tok;
197 }
198
199 unsigned getReg() const override {
200 assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
201
202 return RegImm.Reg;
203 }
204
205 const MCExpr *getImm() const {
206 assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
207 return RegImm.Imm;
208 }
209
210 static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
211 return std::make_unique<AVROperand>(Str, S);
212 }
213
214 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
215 SMLoc E) {
216 return std::make_unique<AVROperand>(RegNum, S, E);
217 }
218
219 static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
220 SMLoc E) {
221 return std::make_unique<AVROperand>(Val, S, E);
222 }
223
224 static std::unique_ptr<AVROperand>
225 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
226 return std::make_unique<AVROperand>(RegNum, Val, S, E);
227 }
228
229 void makeToken(StringRef Token) {
230 Kind = k_Token;
231 Tok = Token;
232 }
233
234 void makeReg(unsigned RegNo) {
235 Kind = k_Register;
236 RegImm = {RegNo, nullptr};
237 }
238
239 void makeImm(MCExpr const *Ex) {
240 Kind = k_Immediate;
241 RegImm = {0, Ex};
242 }
243
244 void makeMemri(unsigned RegNo, MCExpr const *Imm) {
245 Kind = k_Memri;
246 RegImm = {RegNo, Imm};
247 }
248
249 SMLoc getStartLoc() const override { return Start; }
250 SMLoc getEndLoc() const override { return End; }
251
252 void print(raw_ostream &O) const override {
253 switch (Kind) {
254 case k_Token:
255 O << "Token: \"" << getToken() << "\"";
256 break;
257 case k_Register:
258 O << "Register: " << getReg();
259 break;
260 case k_Immediate:
261 O << "Immediate: \"" << *getImm() << "\"";
262 break;
263 case k_Memri: {
264 // only manually print the size for non-negative values,
265 // as the sign is inserted automatically.
266 O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
267 break;
268 }
269 }
270 O << "\n";
271 }
272};
273
274} // end anonymous namespace.
275
276// Auto-generated Match Functions
277
278/// Maps from the set of all register names to a register number.
279/// \note Generated by TableGen.
281
282/// Maps from the set of all alternative registernames to a register number.
283/// \note Generated by TableGen.
285
286bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
287 OperandVector const &Operands,
288 uint64_t const &ErrorInfo) {
289 SMLoc ErrorLoc = Loc;
290 char const *Diag = nullptr;
291
292 if (ErrorInfo != ~0U) {
293 if (ErrorInfo >= Operands.size()) {
294 Diag = "too few operands for instruction.";
295 } else {
296 AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
297
298 // TODO: See if we can do a better error than just "invalid ...".
299 if (Op.getStartLoc() != SMLoc()) {
300 ErrorLoc = Op.getStartLoc();
301 }
302 }
303 }
304
305 if (!Diag) {
306 Diag = "invalid operand for instruction";
307 }
308
309 return Error(ErrorLoc, Diag);
310}
311
312bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
313 uint64_t const &ErrorInfo) {
314 return Error(Loc, "instruction requires a CPU feature not currently enabled");
315}
316
317bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
318 Inst.setLoc(Loc);
319 Out.emitInstruction(Inst, STI);
320
321 return false;
322}
323
324bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
327 bool MatchingInlineAsm) {
328 MCInst Inst;
329 unsigned MatchResult =
330 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
331
332 switch (MatchResult) {
333 case Match_Success:
334 return emit(Inst, Loc, Out);
335 case Match_MissingFeature:
336 return missingFeature(Loc, ErrorInfo);
337 case Match_InvalidOperand:
338 return invalidOperand(Loc, Operands, ErrorInfo);
339 case Match_MnemonicFail:
340 return Error(Loc, "invalid instruction");
341 case Match_InvalidRegisterOnTiny:
342 return Error(Loc, "invalid register on avrtiny");
343 default:
344 return true;
345 }
346}
347
348/// Parses a register name using a given matching function.
349/// Checks for lowercase or uppercase if necessary.
350int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
351 StringRef Name = Parser.getTok().getString();
352
353 int RegNum = matchFn(Name);
354
355 // GCC supports case insensitive register names. Some of the AVR registers
356 // are all lower case, some are all upper case but non are mixed. We prefer
357 // to use the original names in the register definitions. That is why we
358 // have to test both upper and lower case here.
359 if (RegNum == AVR::NoRegister) {
360 RegNum = matchFn(Name.lower());
361 }
362 if (RegNum == AVR::NoRegister) {
363 RegNum = matchFn(Name.upper());
364 }
365
366 return RegNum;
367}
368
369int AVRAsmParser::parseRegisterName() {
370 int RegNum = parseRegisterName(&MatchRegisterName);
371
372 if (RegNum == AVR::NoRegister)
373 RegNum = parseRegisterName(&MatchRegisterAltName);
374
375 return RegNum;
376}
377
378int AVRAsmParser::parseRegister(bool RestoreOnFailure) {
379 int RegNum = AVR::NoRegister;
380
381 if (Parser.getTok().is(AsmToken::Identifier)) {
382 // Check for register pair syntax
383 if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
384 AsmToken HighTok = Parser.getTok();
385 Parser.Lex();
386 AsmToken ColonTok = Parser.getTok();
387 Parser.Lex(); // Eat high (odd) register and colon
388
389 if (Parser.getTok().is(AsmToken::Identifier)) {
390 // Convert lower (even) register to DREG
391 RegNum = toDREG(parseRegisterName());
392 }
393 if (RegNum == AVR::NoRegister && RestoreOnFailure) {
394 getLexer().UnLex(std::move(ColonTok));
395 getLexer().UnLex(std::move(HighTok));
396 }
397 } else {
398 RegNum = parseRegisterName();
399 }
400 }
401 return RegNum;
402}
403
404bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
405 int RegNo = parseRegister();
406
407 if (RegNo == AVR::NoRegister)
408 return true;
409
410 // Reject R0~R15 on avrtiny.
411 if (AVR::R0 <= RegNo && RegNo <= AVR::R15 &&
412 STI.hasFeature(AVR::FeatureTinyEncoding))
413 return Error(Parser.getTok().getLoc(), "invalid register on avrtiny");
414
415 AsmToken const &T = Parser.getTok();
416 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
417 Parser.Lex(); // Eat register token.
418
419 return false;
420}
421
422bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
423 SMLoc S = Parser.getTok().getLoc();
424
425 if (!tryParseRelocExpression(Operands))
426 return false;
427
428 if ((Parser.getTok().getKind() == AsmToken::Plus ||
429 Parser.getTok().getKind() == AsmToken::Minus) &&
431 // Don't handle this case - it should be split into two
432 // separate tokens.
433 return true;
434 }
435
436 // Parse (potentially inner) expression
437 MCExpr const *Expression;
438 if (getParser().parseExpression(Expression))
439 return true;
440
442 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
443 return false;
444}
445
446bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
447 bool isNegated = false;
449
450 SMLoc S = Parser.getTok().getLoc();
451
452 // Reject the form in which sign comes first. This behaviour is
453 // in accordance with avr-gcc.
454 AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
455 if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
456 return true;
457
458 // Check for sign.
459 AsmToken tokens[2];
460 if (Parser.getLexer().peekTokens(tokens) == 2)
461 if (tokens[0].getKind() == AsmToken::LParen &&
462 tokens[1].getKind() == AsmToken::Minus)
463 isNegated = true;
464
465 // Check if we have a target specific modifier (lo8, hi8, &c)
466 if (CurTok != AsmToken::Identifier ||
467 Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
468 // Not a reloc expr
469 return true;
470 }
471 StringRef ModifierName = Parser.getTok().getString();
472 ModifierKind = AVRMCExpr::getKindByName(ModifierName);
473
474 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
475 Parser.Lex();
476 Parser.Lex(); // Eat modifier name and parenthesis
477 if (Parser.getTok().getString() == GENERATE_STUBS &&
478 Parser.getTok().getKind() == AsmToken::Identifier) {
479 std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
480 ModifierKind = AVRMCExpr::getKindByName(GSModName);
481 if (ModifierKind != AVRMCExpr::VK_AVR_None)
482 Parser.Lex(); // Eat gs modifier name
483 }
484 } else {
485 return Error(Parser.getTok().getLoc(), "unknown modifier");
486 }
487
488 if (tokens[1].getKind() == AsmToken::Minus ||
489 tokens[1].getKind() == AsmToken::Plus) {
490 Parser.Lex();
491 assert(Parser.getTok().getKind() == AsmToken::LParen);
492 Parser.Lex(); // Eat the sign and parenthesis
493 }
494
495 MCExpr const *InnerExpression;
496 if (getParser().parseExpression(InnerExpression))
497 return true;
498
499 if (tokens[1].getKind() == AsmToken::Minus ||
500 tokens[1].getKind() == AsmToken::Plus) {
501 assert(Parser.getTok().getKind() == AsmToken::RParen);
502 Parser.Lex(); // Eat closing parenthesis
503 }
504
505 // If we have a modifier wrap the inner expression
506 assert(Parser.getTok().getKind() == AsmToken::RParen);
507 Parser.Lex(); // Eat closing parenthesis
508
509 MCExpr const *Expression =
510 AVRMCExpr::create(ModifierKind, InnerExpression, isNegated, getContext());
511
513 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
514
515 return false;
516}
517
518bool AVRAsmParser::parseOperand(OperandVector &Operands, bool maybeReg) {
519 LLVM_DEBUG(dbgs() << "parseOperand\n");
520
521 switch (getLexer().getKind()) {
522 default:
523 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
524
526 // Try to parse a register, fall through to the next case if it fails.
527 if (maybeReg && !tryParseRegisterOperand(Operands)) {
528 return false;
529 }
530 [[fallthrough]];
531 case AsmToken::LParen:
533 case AsmToken::Dot:
534 return tryParseExpression(Operands);
535 case AsmToken::Plus:
536 case AsmToken::Minus: {
537 // If the sign preceeds a number, parse the number,
538 // otherwise treat the sign a an independent token.
539 switch (getLexer().peekTok().getKind()) {
541 case AsmToken::BigNum:
543 case AsmToken::Real:
544 if (!tryParseExpression(Operands))
545 return false;
546 break;
547 default:
548 break;
549 }
550 // Treat the token as an independent token.
551 Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
552 Parser.getTok().getLoc()));
553 Parser.Lex(); // Eat the token.
554 return false;
555 }
556 }
557
558 // Could not parse operand
559 return true;
560}
561
562OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
563 LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
564
565 SMLoc E, S;
566 MCExpr const *Expression;
567 int RegNo;
568
569 // Parse register.
570 {
571 RegNo = parseRegister();
572
573 if (RegNo == AVR::NoRegister)
575
576 S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
577 Parser.Lex(); // Eat register token.
578 }
579
580 // Parse immediate;
581 {
582 if (getParser().parseExpression(Expression))
584
585 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
586 }
587
588 Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
589
591}
592
593bool AVRAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
594 SMLoc &EndLoc) {
595 StartLoc = Parser.getTok().getLoc();
596 RegNo = parseRegister(/*RestoreOnFailure=*/false);
597 EndLoc = Parser.getTok().getLoc();
598
599 return (RegNo == AVR::NoRegister);
600}
601
602OperandMatchResultTy AVRAsmParser::tryParseRegister(MCRegister &RegNo,
603 SMLoc &StartLoc,
604 SMLoc &EndLoc) {
605 StartLoc = Parser.getTok().getLoc();
606 RegNo = parseRegister(/*RestoreOnFailure=*/true);
607 EndLoc = Parser.getTok().getLoc();
608
609 if (RegNo == AVR::NoRegister)
612}
613
614void AVRAsmParser::eatComma() {
615 if (getLexer().is(AsmToken::Comma)) {
616 Parser.Lex();
617 } else {
618 // GCC allows commas to be omitted.
619 }
620}
621
622bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
623 StringRef Mnemonic, SMLoc NameLoc,
625 Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
626
627 int OperandNum = -1;
628 while (getLexer().isNot(AsmToken::EndOfStatement)) {
629 OperandNum++;
630 if (OperandNum > 0)
631 eatComma();
632
633 auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
634
635 if (MatchResult == MatchOperand_Success) {
636 continue;
637 }
638
639 if (MatchResult == MatchOperand_ParseFail) {
640 SMLoc Loc = getLexer().getLoc();
641 Parser.eatToEndOfStatement();
642
643 return Error(Loc, "failed to parse register and immediate pair");
644 }
645
646 // These specific operands should be treated as addresses/symbols/labels,
647 // other than registers.
648 bool maybeReg = true;
649 if (OperandNum == 1) {
650 std::array<StringRef, 8> Insts = {"lds", "adiw", "sbiw", "ldi"};
651 for (auto Inst : Insts) {
652 if (Inst == Mnemonic) {
653 maybeReg = false;
654 break;
655 }
656 }
657 } else if (OperandNum == 0) {
658 std::array<StringRef, 8> Insts = {"sts", "call", "rcall", "rjmp", "jmp"};
659 for (auto Inst : Insts) {
660 if (Inst == Mnemonic) {
661 maybeReg = false;
662 break;
663 }
664 }
665 }
666
667 if (parseOperand(Operands, maybeReg)) {
668 SMLoc Loc = getLexer().getLoc();
669 Parser.eatToEndOfStatement();
670 return Error(Loc, "unexpected token in argument list");
671 }
672 }
673 Parser.Lex(); // Consume the EndOfStatement
674 return false;
675}
676
677bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
678 StringRef IDVal = DirectiveID.getIdentifier();
679 if (IDVal.lower() == ".long") {
680 parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
681 } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
682 parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
683 } else if (IDVal.lower() == ".byte") {
684 parseLiteralValues(1, DirectiveID.getLoc());
685 }
686 return true;
687}
688
689bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
690 MCAsmParser &Parser = getParser();
691 AVRMCELFStreamer &AVRStreamer =
692 static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
693 AsmToken Tokens[2];
694 size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
695 if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
696 Tokens[0].getKind() == AsmToken::Minus &&
697 Tokens[1].getKind() == AsmToken::Identifier) {
698 MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
699 AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L,
701 return false;
702 }
703
704 if (Parser.getTok().getKind() == AsmToken::Identifier &&
705 Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
706 StringRef ModifierName = Parser.getTok().getString();
707 AVRMCExpr::VariantKind ModifierKind =
708 AVRMCExpr::getKindByName(ModifierName);
709 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
710 Parser.Lex();
711 Parser.Lex(); // Eat the modifier and parenthesis
712 } else {
713 return Error(Parser.getTok().getLoc(), "unknown modifier");
714 }
716 getContext().getOrCreateSymbol(Parser.getTok().getString());
717 AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
718 return false;
719 }
720
721 auto parseOne = [&]() -> bool {
722 const MCExpr *Value;
723 if (Parser.parseExpression(Value))
724 return true;
725 Parser.getStreamer().emitValue(Value, SizeInBytes, L);
726 return false;
727 };
728 return (parseMany(parseOne));
729}
730
733}
734
735#define GET_REGISTER_MATCHER
736#define GET_MATCHER_IMPLEMENTATION
737#include "AVRGenAsmMatcher.inc"
738
739// Uses enums defined in AVRGenAsmMatcher.inc
740unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
741 unsigned ExpectedKind) {
742 AVROperand &Op = static_cast<AVROperand &>(AsmOp);
743 MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
744
745 // If need be, GCC converts bare numbers to register names
746 // It's ugly, but GCC supports it.
747 if (Op.isImm()) {
748 if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
749 int64_t RegNum = Const->getValue();
750
751 // Reject R0~R15 on avrtiny.
752 if (0 <= RegNum && RegNum <= 15 &&
753 STI.hasFeature(AVR::FeatureTinyEncoding))
754 return Match_InvalidRegisterOnTiny;
755
756 std::ostringstream RegName;
757 RegName << "r" << RegNum;
758 RegNum = MatchRegisterName(RegName.str());
759 if (RegNum != AVR::NoRegister) {
760 Op.makeReg(RegNum);
761 if (validateOperandClass(Op, Expected) == Match_Success) {
762 return Match_Success;
763 }
764 }
765 // Let the other quirks try their magic.
766 }
767 }
768
769 if (Op.isReg()) {
770 // If the instruction uses a register pair but we got a single, lower
771 // register we perform a "class cast".
772 if (isSubclass(Expected, MCK_DREGS)) {
773 unsigned correspondingDREG = toDREG(Op.getReg());
774
775 if (correspondingDREG != AVR::NoRegister) {
776 Op.makeReg(correspondingDREG);
777 return validateOperandClass(Op, Expected);
778 }
779 }
780 }
781 return Match_InvalidOperand;
782}
unsigned const MachineRegisterInfo * MRI
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
This file implements a class to represent arbitrary precision integral constant values and operations...
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmParser()
BlockVerifier::State From
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
dxil metadata emit
#define LLVM_DEBUG(X)
Definition: Debug.h:101
std::string Name
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
#define RegName(no)
static LVOptions Options
Definition: LVOptions.cpp:25
mir Rename Register Operands
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void emitValueForModiferKind(const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc=SMLoc(), AVRMCExpr::VariantKind ModifierKind=AVRMCExpr::VK_AVR_None)
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:38
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:209
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:22
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
TokenKind getKind() const
Definition: MCAsmMacro.h:81
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
Base class for user error types.
Definition: Error.h:348
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
Tagged union holding either a T or a Error.
Definition: Error.h:470
Class representing an expression and its matching format.
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:37
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:111
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:138
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:123
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
virtual MCAsmLexer & getLexer()=0
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void setLoc(SMLoc loc)
Definition: MCInst.h:203
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
virtual unsigned getReg() const =0
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
virtual bool isReg() const =0
isReg - Is this a register operand?
virtual bool isMem() const =0
isMem - Is this a memory operand?
virtual void print(raw_ostream &OS) const =0
print - Print a debug representation of the operand to the given stream.
virtual bool isToken() const =0
isToken - Is this a token operand?
virtual bool isImm() const =0
isImm - Is this an immediate operand?
virtual SMLoc getEndLoc() const =0
getEndLoc - Get the location of the last token of this operand.
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual bool ParseDirective(AsmToken DirectiveID)=0
ParseDirective - Parse a target specific assembler directive.
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
void setAvailableFeatures(const FeatureBitset &Value)
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
virtual OperandMatchResultTy tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
const MCSubtargetInfo * STI
Current STI.
Represents a location in source code.
Definition: SMLoc.h:23
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
const char * getPointer() const
Definition: SMLoc.h:34
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
std::string lower() const
Definition: StringRef.cpp:111
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ CE
Windows NT (Windows on ARM)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ MatchOperand_NoMatch
@ MatchOperand_ParseFail
@ MatchOperand_Success
Target & getTheAVRTarget()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
const int SIZE_WORD
const int SIZE_LONG
#define N
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...