LLVM  14.0.0git
AVRAsmParser.cpp
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1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AVR.h"
10 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCExpr.h"
15 
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Support/Debug.h"
31 
32 #include <sstream>
33 
34 #define DEBUG_TYPE "avr-asm-parser"
35 
36 using namespace llvm;
37 
38 namespace {
39 /// Parses AVR assembly from a stream.
40 class AVRAsmParser : public MCTargetAsmParser {
41  const MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43  const MCRegisterInfo *MRI;
44  const std::string GENERATE_STUBS = "gs";
45 
46 #define GET_ASSEMBLER_HEADER
47 #include "AVRGenAsmMatcher.inc"
48 
49  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
51  uint64_t &ErrorInfo,
52  bool MatchingInlineAsm) override;
53 
54  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
55  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
56  SMLoc &EndLoc) override;
57 
58  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
59  SMLoc NameLoc, OperandVector &Operands) override;
60 
61  bool ParseDirective(AsmToken DirectiveID) override;
62 
63  OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
64 
65  bool parseOperand(OperandVector &Operands);
66  int parseRegisterName(unsigned (*matchFn)(StringRef));
67  int parseRegisterName();
68  int parseRegister(bool RestoreOnFailure = false);
69  bool tryParseRegisterOperand(OperandVector &Operands);
70  bool tryParseExpression(OperandVector &Operands);
71  bool tryParseRelocExpression(OperandVector &Operands);
72  void eatComma();
73 
74  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
75  unsigned Kind) override;
76 
77  unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
78  MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
79  return MRI->getMatchingSuperReg(Reg, From, Class);
80  }
81 
82  bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
83  bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
84  uint64_t const &ErrorInfo);
85  bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
86 
87  bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
88 
89 public:
90  AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
91  const MCInstrInfo &MII, const MCTargetOptions &Options)
92  : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
94  MRI = getContext().getRegisterInfo();
95 
96  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
97  }
98 
99  MCAsmParser &getParser() const { return Parser; }
100  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 };
102 
103 /// An parsed AVR assembly operand.
104 class AVROperand : public MCParsedAsmOperand {
105  typedef MCParsedAsmOperand Base;
106  enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
107 
108 public:
109  AVROperand(StringRef Tok, SMLoc const &S)
110  : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
111  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
112  : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
113  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
114  : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
115  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
116  : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
117 
118  struct RegisterImmediate {
119  unsigned Reg;
120  MCExpr const *Imm;
121  };
122  union {
123  StringRef Tok;
124  RegisterImmediate RegImm;
125  };
126 
127  SMLoc Start, End;
128 
129 public:
130  void addRegOperands(MCInst &Inst, unsigned N) const {
131  assert(Kind == k_Register && "Unexpected operand kind");
132  assert(N == 1 && "Invalid number of operands!");
133 
135  }
136 
137  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
138  // Add as immediate when possible
139  if (!Expr)
141  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
142  Inst.addOperand(MCOperand::createImm(CE->getValue()));
143  else
144  Inst.addOperand(MCOperand::createExpr(Expr));
145  }
146 
147  void addImmOperands(MCInst &Inst, unsigned N) const {
148  assert(Kind == k_Immediate && "Unexpected operand kind");
149  assert(N == 1 && "Invalid number of operands!");
150 
151  const MCExpr *Expr = getImm();
152  addExpr(Inst, Expr);
153  }
154 
155  /// Adds the contained reg+imm operand to an instruction.
156  void addMemriOperands(MCInst &Inst, unsigned N) const {
157  assert(Kind == k_Memri && "Unexpected operand kind");
158  assert(N == 2 && "Invalid number of operands");
159 
161  addExpr(Inst, getImm());
162  }
163 
164  void addImmCom8Operands(MCInst &Inst, unsigned N) const {
165  assert(N == 1 && "Invalid number of operands!");
166  // The operand is actually a imm8, but we have its bitwise
167  // negation in the assembly source, so twiddle it here.
168  const auto *CE = cast<MCConstantExpr>(getImm());
169  Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
170  }
171 
172  bool isImmCom8() const {
173  if (!isImm()) return false;
174  const auto *CE = dyn_cast<MCConstantExpr>(getImm());
175  if (!CE) return false;
176  int64_t Value = CE->getValue();
177  return isUInt<8>(Value);
178  }
179 
180  bool isReg() const override { return Kind == k_Register; }
181  bool isImm() const override { return Kind == k_Immediate; }
182  bool isToken() const override { return Kind == k_Token; }
183  bool isMem() const override { return Kind == k_Memri; }
184  bool isMemri() const { return Kind == k_Memri; }
185 
186  StringRef getToken() const {
187  assert(Kind == k_Token && "Invalid access!");
188  return Tok;
189  }
190 
191  unsigned getReg() const override {
192  assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
193 
194  return RegImm.Reg;
195  }
196 
197  const MCExpr *getImm() const {
198  assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
199  return RegImm.Imm;
200  }
201 
202  static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
203  return std::make_unique<AVROperand>(Str, S);
204  }
205 
206  static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
207  SMLoc E) {
208  return std::make_unique<AVROperand>(RegNum, S, E);
209  }
210 
211  static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
212  SMLoc E) {
213  return std::make_unique<AVROperand>(Val, S, E);
214  }
215 
216  static std::unique_ptr<AVROperand>
217  CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
218  return std::make_unique<AVROperand>(RegNum, Val, S, E);
219  }
220 
221  void makeToken(StringRef Token) {
222  Kind = k_Token;
223  Tok = Token;
224  }
225 
226  void makeReg(unsigned RegNo) {
227  Kind = k_Register;
228  RegImm = {RegNo, nullptr};
229  }
230 
231  void makeImm(MCExpr const *Ex) {
232  Kind = k_Immediate;
233  RegImm = {0, Ex};
234  }
235 
236  void makeMemri(unsigned RegNo, MCExpr const *Imm) {
237  Kind = k_Memri;
238  RegImm = {RegNo, Imm};
239  }
240 
241  SMLoc getStartLoc() const override { return Start; }
242  SMLoc getEndLoc() const override { return End; }
243 
244  void print(raw_ostream &O) const override {
245  switch (Kind) {
246  case k_Token:
247  O << "Token: \"" << getToken() << "\"";
248  break;
249  case k_Register:
250  O << "Register: " << getReg();
251  break;
252  case k_Immediate:
253  O << "Immediate: \"" << *getImm() << "\"";
254  break;
255  case k_Memri: {
256  // only manually print the size for non-negative values,
257  // as the sign is inserted automatically.
258  O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
259  break;
260  }
261  }
262  O << "\n";
263  }
264 };
265 
266 } // end anonymous namespace.
267 
268 // Auto-generated Match Functions
269 
270 /// Maps from the set of all register names to a register number.
271 /// \note Generated by TableGen.
272 static unsigned MatchRegisterName(StringRef Name);
273 
274 /// Maps from the set of all alternative registernames to a register number.
275 /// \note Generated by TableGen.
276 static unsigned MatchRegisterAltName(StringRef Name);
277 
278 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
279  OperandVector const &Operands,
280  uint64_t const &ErrorInfo) {
281  SMLoc ErrorLoc = Loc;
282  char const *Diag = 0;
283 
284  if (ErrorInfo != ~0U) {
285  if (ErrorInfo >= Operands.size()) {
286  Diag = "too few operands for instruction.";
287  } else {
288  AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
289 
290  // TODO: See if we can do a better error than just "invalid ...".
291  if (Op.getStartLoc() != SMLoc()) {
292  ErrorLoc = Op.getStartLoc();
293  }
294  }
295  }
296 
297  if (!Diag) {
298  Diag = "invalid operand for instruction";
299  }
300 
301  return Error(ErrorLoc, Diag);
302 }
303 
304 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
305  uint64_t const &ErrorInfo) {
306  return Error(Loc, "instruction requires a CPU feature not currently enabled");
307 }
308 
309 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
310  Inst.setLoc(Loc);
311  Out.emitInstruction(Inst, STI);
312 
313  return false;
314 }
315 
316 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
318  MCStreamer &Out, uint64_t &ErrorInfo,
319  bool MatchingInlineAsm) {
320  MCInst Inst;
321  unsigned MatchResult =
322  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
323 
324  switch (MatchResult) {
325  case Match_Success: return emit(Inst, Loc, Out);
326  case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
327  case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
328  case Match_MnemonicFail: return Error(Loc, "invalid instruction");
329  default: return true;
330  }
331 }
332 
333 /// Parses a register name using a given matching function.
334 /// Checks for lowercase or uppercase if necessary.
335 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
336  StringRef Name = Parser.getTok().getString();
337 
338  int RegNum = matchFn(Name);
339 
340  // GCC supports case insensitive register names. Some of the AVR registers
341  // are all lower case, some are all upper case but non are mixed. We prefer
342  // to use the original names in the register definitions. That is why we
343  // have to test both upper and lower case here.
344  if (RegNum == AVR::NoRegister) {
345  RegNum = matchFn(Name.lower());
346  }
347  if (RegNum == AVR::NoRegister) {
348  RegNum = matchFn(Name.upper());
349  }
350 
351  return RegNum;
352 }
353 
354 int AVRAsmParser::parseRegisterName() {
355  int RegNum = parseRegisterName(&MatchRegisterName);
356 
357  if (RegNum == AVR::NoRegister)
358  RegNum = parseRegisterName(&MatchRegisterAltName);
359 
360  return RegNum;
361 }
362 
363 int AVRAsmParser::parseRegister(bool RestoreOnFailure) {
364  int RegNum = AVR::NoRegister;
365 
366  if (Parser.getTok().is(AsmToken::Identifier)) {
367  // Check for register pair syntax
368  if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
369  AsmToken HighTok = Parser.getTok();
370  Parser.Lex();
371  AsmToken ColonTok = Parser.getTok();
372  Parser.Lex(); // Eat high (odd) register and colon
373 
374  if (Parser.getTok().is(AsmToken::Identifier)) {
375  // Convert lower (even) register to DREG
376  RegNum = toDREG(parseRegisterName());
377  }
378  if (RegNum == AVR::NoRegister && RestoreOnFailure) {
379  getLexer().UnLex(std::move(ColonTok));
380  getLexer().UnLex(std::move(HighTok));
381  }
382  } else {
383  RegNum = parseRegisterName();
384  }
385  }
386  return RegNum;
387 }
388 
389 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
390  int RegNo = parseRegister();
391 
392  if (RegNo == AVR::NoRegister)
393  return true;
394 
395  AsmToken const &T = Parser.getTok();
396  Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
397  Parser.Lex(); // Eat register token.
398 
399  return false;
400 }
401 
402 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
403  SMLoc S = Parser.getTok().getLoc();
404 
405  if (!tryParseRelocExpression(Operands))
406  return false;
407 
408  if ((Parser.getTok().getKind() == AsmToken::Plus ||
409  Parser.getTok().getKind() == AsmToken::Minus) &&
410  Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
411  // Don't handle this case - it should be split into two
412  // separate tokens.
413  return true;
414  }
415 
416  // Parse (potentially inner) expression
417  MCExpr const *Expression;
418  if (getParser().parseExpression(Expression))
419  return true;
420 
421  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
422  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
423  return false;
424 }
425 
426 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
427  bool isNegated = false;
429 
430  SMLoc S = Parser.getTok().getLoc();
431 
432  // Check for sign
433  AsmToken tokens[2];
434  size_t ReadCount = Parser.getLexer().peekTokens(tokens);
435 
436  if (ReadCount == 2) {
437  if ((tokens[0].getKind() == AsmToken::Identifier &&
438  tokens[1].getKind() == AsmToken::LParen) ||
439  (tokens[0].getKind() == AsmToken::LParen &&
440  tokens[1].getKind() == AsmToken::Minus)) {
441 
442  AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
443  if (CurTok == AsmToken::Minus ||
444  tokens[1].getKind() == AsmToken::Minus) {
445  isNegated = true;
446  } else {
447  assert(CurTok == AsmToken::Plus);
448  isNegated = false;
449  }
450 
451  // Eat the sign
452  if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
453  Parser.Lex();
454  }
455  }
456 
457  // Check if we have a target specific modifier (lo8, hi8, &c)
458  if (Parser.getTok().getKind() != AsmToken::Identifier ||
459  Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
460  // Not a reloc expr
461  return true;
462  }
463  StringRef ModifierName = Parser.getTok().getString();
464  ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
465 
466  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
467  Parser.Lex();
468  Parser.Lex(); // Eat modifier name and parenthesis
469  if (Parser.getTok().getString() == GENERATE_STUBS &&
470  Parser.getTok().getKind() == AsmToken::Identifier) {
471  std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
472  ModifierKind = AVRMCExpr::getKindByName(GSModName.c_str());
473  if (ModifierKind != AVRMCExpr::VK_AVR_None)
474  Parser.Lex(); // Eat gs modifier name
475  }
476  } else {
477  return Error(Parser.getTok().getLoc(), "unknown modifier");
478  }
479 
480  if (tokens[1].getKind() == AsmToken::Minus ||
481  tokens[1].getKind() == AsmToken::Plus) {
482  Parser.Lex();
483  assert(Parser.getTok().getKind() == AsmToken::LParen);
484  Parser.Lex(); // Eat the sign and parenthesis
485  }
486 
487  MCExpr const *InnerExpression;
488  if (getParser().parseExpression(InnerExpression))
489  return true;
490 
491  if (tokens[1].getKind() == AsmToken::Minus ||
492  tokens[1].getKind() == AsmToken::Plus) {
493  assert(Parser.getTok().getKind() == AsmToken::RParen);
494  Parser.Lex(); // Eat closing parenthesis
495  }
496 
497  // If we have a modifier wrap the inner expression
498  assert(Parser.getTok().getKind() == AsmToken::RParen);
499  Parser.Lex(); // Eat closing parenthesis
500 
501  MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
502  isNegated, getContext());
503 
504  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
505  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
506 
507  return false;
508 }
509 
510 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
511  LLVM_DEBUG(dbgs() << "parseOperand\n");
512 
513  switch (getLexer().getKind()) {
514  default:
515  return Error(Parser.getTok().getLoc(), "unexpected token in operand");
516 
518  // Try to parse a register, if it fails,
519  // fall through to the next case.
520  if (!tryParseRegisterOperand(Operands)) {
521  return false;
522  }
524  case AsmToken::LParen:
525  case AsmToken::Integer:
526  case AsmToken::Dot:
527  return tryParseExpression(Operands);
528  case AsmToken::Plus:
529  case AsmToken::Minus: {
530  // If the sign preceeds a number, parse the number,
531  // otherwise treat the sign a an independent token.
532  switch (getLexer().peekTok().getKind()) {
533  case AsmToken::Integer:
534  case AsmToken::BigNum:
536  case AsmToken::Real:
537  if (!tryParseExpression(Operands))
538  return false;
539  break;
540  default:
541  break;
542  }
543  // Treat the token as an independent token.
544  Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
545  Parser.getTok().getLoc()));
546  Parser.Lex(); // Eat the token.
547  return false;
548  }
549  }
550 
551  // Could not parse operand
552  return true;
553 }
554 
556 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
557  LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
558 
559  SMLoc E, S;
560  MCExpr const *Expression;
561  int RegNo;
562 
563  // Parse register.
564  {
565  RegNo = parseRegister();
566 
567  if (RegNo == AVR::NoRegister)
568  return MatchOperand_ParseFail;
569 
570  S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
571  Parser.Lex(); // Eat register token.
572  }
573 
574  // Parse immediate;
575  {
576  if (getParser().parseExpression(Expression))
577  return MatchOperand_ParseFail;
578 
579  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
580  }
581 
582  Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
583 
584  return MatchOperand_Success;
585 }
586 
587 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
588  SMLoc &EndLoc) {
589  StartLoc = Parser.getTok().getLoc();
590  RegNo = parseRegister(/*RestoreOnFailure=*/false);
591  EndLoc = Parser.getTok().getLoc();
592 
593  return (RegNo == AVR::NoRegister);
594 }
595 
596 OperandMatchResultTy AVRAsmParser::tryParseRegister(unsigned &RegNo,
597  SMLoc &StartLoc,
598  SMLoc &EndLoc) {
599  StartLoc = Parser.getTok().getLoc();
600  RegNo = parseRegister(/*RestoreOnFailure=*/true);
601  EndLoc = Parser.getTok().getLoc();
602 
603  if (RegNo == AVR::NoRegister)
604  return MatchOperand_NoMatch;
605  return MatchOperand_Success;
606 }
607 
608 void AVRAsmParser::eatComma() {
609  if (getLexer().is(AsmToken::Comma)) {
610  Parser.Lex();
611  } else {
612  // GCC allows commas to be omitted.
613  }
614 }
615 
616 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
617  StringRef Mnemonic, SMLoc NameLoc,
619  Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
620 
621  bool first = true;
622  while (getLexer().isNot(AsmToken::EndOfStatement)) {
623  if (!first) eatComma();
624 
625  first = false;
626 
627  auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
628 
629  if (MatchResult == MatchOperand_Success) {
630  continue;
631  }
632 
633  if (MatchResult == MatchOperand_ParseFail) {
634  SMLoc Loc = getLexer().getLoc();
635  Parser.eatToEndOfStatement();
636 
637  return Error(Loc, "failed to parse register and immediate pair");
638  }
639 
640  if (parseOperand(Operands)) {
641  SMLoc Loc = getLexer().getLoc();
642  Parser.eatToEndOfStatement();
643  return Error(Loc, "unexpected token in argument list");
644  }
645  }
646  Parser.Lex(); // Consume the EndOfStatement
647  return false;
648 }
649 
650 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
651  StringRef IDVal = DirectiveID.getIdentifier();
652  if (IDVal.lower() == ".long") {
653  parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
654  } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
655  parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
656  } else if (IDVal.lower() == ".byte") {
657  parseLiteralValues(1, DirectiveID.getLoc());
658  }
659  return true;
660 }
661 
662 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
663  MCAsmParser &Parser = getParser();
664  AVRMCELFStreamer &AVRStreamer =
665  static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
666  AsmToken Tokens[2];
667  size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
668  if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
669  Tokens[0].getKind() == AsmToken::Minus &&
670  Tokens[1].getKind() == AsmToken::Identifier) {
671  MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
672  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L,
674  return false;
675  }
676 
677  if (Parser.getTok().getKind() == AsmToken::Identifier &&
678  Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
679  StringRef ModifierName = Parser.getTok().getString();
680  AVRMCExpr::VariantKind ModifierKind =
681  AVRMCExpr::getKindByName(ModifierName.str().c_str());
682  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
683  Parser.Lex();
684  Parser.Lex(); // Eat the modifier and parenthesis
685  } else {
686  return Error(Parser.getTok().getLoc(), "unknown modifier");
687  }
688  MCSymbol *Symbol =
689  getContext().getOrCreateSymbol(Parser.getTok().getString());
690  AVRStreamer.emitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
691  return false;
692  }
693 
694  auto parseOne = [&]() -> bool {
695  const MCExpr *Value;
696  if (Parser.parseExpression(Value))
697  return true;
698  Parser.getStreamer().emitValue(Value, SizeInBytes, L);
699  return false;
700  };
701  return (parseMany(parseOne));
702 }
703 
706 }
707 
708 #define GET_REGISTER_MATCHER
709 #define GET_MATCHER_IMPLEMENTATION
710 #include "AVRGenAsmMatcher.inc"
711 
712 // Uses enums defined in AVRGenAsmMatcher.inc
713 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
714  unsigned ExpectedKind) {
715  AVROperand &Op = static_cast<AVROperand &>(AsmOp);
716  MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
717 
718  // If need be, GCC converts bare numbers to register names
719  // It's ugly, but GCC supports it.
720  if (Op.isImm()) {
721  if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
722  int64_t RegNum = Const->getValue();
723  std::ostringstream RegName;
724  RegName << "r" << RegNum;
725  RegNum = MatchRegisterName(RegName.str().c_str());
726  if (RegNum != AVR::NoRegister) {
727  Op.makeReg(RegNum);
728  if (validateOperandClass(Op, Expected) == Match_Success) {
729  return Match_Success;
730  }
731  }
732  // Let the other quirks try their magic.
733  }
734  }
735 
736  if (Op.isReg()) {
737  // If the instruction uses a register pair but we got a single, lower
738  // register we perform a "class cast".
739  if (isSubclass(Expected, MCK_DREGS)) {
740  unsigned correspondingDREG = toDREG(Op.getReg());
741 
742  if (correspondingDREG != AVR::NoRegister) {
743  Op.makeReg(correspondingDREG);
744  return validateOperandClass(Op, Expected);
745  }
746  }
747  }
748  return Match_InvalidOperand;
749 }
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
MathExtras.h
llvm::MCAsmParser::getStreamer
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::AVRMCExpr::getKindByName
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:209
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:39
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:147
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::MCAsmLexer::peekTok
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:113
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
AVRMCELFStreamer.h
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
MCParsedAsmOperand.h
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
MCInstBuilder.h
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:175
APInt.h
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:42
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCTargetAsmParser.h
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
AVRMCExpr.h
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
LLVMInitializeAVRAsmParser
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmParser()
Definition: AVRAsmParser.cpp:704
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1317
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:122
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::AVRMCExpr::VK_AVR_None
@ VK_AVR_None
Definition: AVRMCExpr.h:23
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MatchRegisterAltName
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
MCContext.h
llvm::AVRMCELFStreamer::emitValueForModiferKind
void emitValueForModiferKind(const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc=SMLoc(), AVRMCExpr::VariantKind ModifierKind=AVRMCExpr::VK_AVR_None)
Definition: AVRMCELFStreamer.cpp:23
MCSymbol.h
MCInst.h
llvm::getTheAVRTarget
Target & getTheAVRTarget()
Definition: AVRTargetInfo.cpp:12
llvm::SIZE_WORD
const int SIZE_WORD
Definition: AVRMCELFStreamer.h:23
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::Instruction
Definition: Instruction.h:45
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
AVRTargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AsmToken::getKind
TokenKind getKind() const
Definition: MCAsmMacro.h:81
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:2748
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:179
llvm::AVRMCExpr::create
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:39
MCAsmLexer.h
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:113
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCAsmParserExtension::Initialize
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Definition: MCAsmParserExtension.cpp:19
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1085
llvm::AsmToken::Colon
@ Colon
Definition: MCAsmMacro.h:43
llvm::MatchOperand_ParseFail
@ MatchOperand_ParseFail
Definition: MCTargetAsmParser.h:124
llvm::AsmToken::BigNum
@ BigNum
Definition: MCAsmMacro.h:33
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AVRMCELFStreamer
Definition: AVRMCELFStreamer.h:25
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::SIZE_LONG
const int SIZE_LONG
Definition: AVRMCELFStreamer.h:22
AVRMCTargetDesc.h
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:349
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::AsmToken::Comma
@ Comma
Definition: MCAsmMacro.h:49
llvm::Expression
Class representing an expression and its matching format.
Definition: FileCheckImpl.h:237
AVRRegisterInfo.h
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:123
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:38
llvm::AsmToken::Plus
@ Plus
Definition: MCAsmMacro.h:45
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AsmToken::RParen
@ RParen
Definition: MCAsmMacro.h:48
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::AsmToken::getString
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:121
llvm::MCAsmLexer::getKind
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:140
llvm::MCAsmParser::eatToEndOfStatement
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::AsmToken::Real
@ Real
Definition: MCAsmMacro.h:36
llvm::AsmToken::Identifier
@ Identifier
Definition: MCAsmMacro.h:28
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::AVRMCExpr::VariantKind
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:22
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:309
AVR.h
MCValue.h
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::AsmToken::TokenKind
TokenKind
Definition: MCAsmMacro.h:23
llvm::MCAsmLexer::peekTokens
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
llvm::MCAsmParser::getLexer
virtual MCAsmLexer & getLexer()=0
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
N
#define N
MCStreamer.h
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:123
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
RegName
#define RegName(no)
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580