LLVM  13.0.0git
Macros | Functions | Variables
AMDGPULegalizerInfo.cpp File Reference
#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
Include dependency graph for AMDGPULegalizerInfo.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "amdgpu-legalinfo"
 

Functions

static LLT getPow2VectorType (LLT Ty)
 
static LLT getPow2ScalarType (LLT Ty)
 
static LegalityPredicate isSmallOddVector (unsigned TypeIdx)
 \returs true if this is an odd sized vector which should widen by adding an additional element. More...
 
static LegalityPredicate sizeIsMultipleOf32 (unsigned TypeIdx)
 
static LegalityPredicate isWideVec16 (unsigned TypeIdx)
 
static LegalizeMutation oneMoreElement (unsigned TypeIdx)
 
static LegalizeMutation fewerEltsToSize64Vector (unsigned TypeIdx)
 
static LegalizeMutation moreEltsToNext32Bit (unsigned TypeIdx)
 
static LLT getBitcastRegisterType (const LLT Ty)
 
static LegalizeMutation bitcastToRegisterType (unsigned TypeIdx)
 
static LegalizeMutation bitcastToVectorElement32 (unsigned TypeIdx)
 
static LegalityPredicate vectorSmallerThan (unsigned TypeIdx, unsigned Size)
 
static LegalityPredicate vectorWiderThan (unsigned TypeIdx, unsigned Size)
 
static LegalityPredicate numElementsNotEven (unsigned TypeIdx)
 
static bool isRegisterSize (unsigned Size)
 
static bool isRegisterVectorElementType (LLT EltTy)
 
static bool isRegisterVectorType (LLT Ty)
 
static bool isRegisterType (LLT Ty)
 
static LegalityPredicate isRegisterType (unsigned TypeIdx)
 
static LegalityPredicate elementTypeIsLegal (unsigned TypeIdx)
 
static LegalityPredicate isWideScalarTruncStore (unsigned TypeIdx)
 
static unsigned maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad)
 
static bool isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
 
static bool loadStoreBitcastWorkaround (const LLT Ty)
 
static bool isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
 
static bool shouldBitcastLoadStoreType (const GCNSubtarget &ST, const LLT Ty, const unsigned MemSizeInBits)
 Return true if a load or store of the type should be lowered with a bitcast to a different type. More...
 
static bool shouldWidenLoad (const GCNSubtarget &ST, unsigned SizeInBits, unsigned AlignInBits, unsigned AddrSpace, unsigned Opcode)
 Return true if we should legalize a load by widening an odd sized memory access up to the alignment. More...
 
static bool shouldWidenLoad (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
 
static MachineInstrBuilder extractF64Exponent (Register Hi, MachineIRBuilder &B)
 
static LLT widenToNextPowerOf2 (LLT Ty)
 
static Register stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)
 
static bool isNot (const MachineRegisterInfo &MRI, const MachineInstr &MI)
 
static MachineInstrverifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br, MachineBasicBlock *&UncondBrTarget, bool &Negated)
 
static std::pair< Register, RegisteremitReciprocalU64 (MachineIRBuilder &B, Register Val)
 
static void toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, AMDGPU::SIModeRegisterDefaults Mode)
 
static unsigned getDSFPAtomicOpcode (Intrinsic::ID IID)
 
static unsigned getBufferAtomicPseudo (Intrinsic::ID IntrID)
 
static void packImage16bitOpsToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
 Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements. More...
 
static void convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
 Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg. More...
 

Variables

static cl::opt< bool > EnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)
 
static constexpr unsigned MaxRegisterSize = 1024
 

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo:
This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-legalinfo"

Definition at line 30 of file AMDGPULegalizerInfo.cpp.

Function Documentation

◆ bitcastToRegisterType()

static LegalizeMutation bitcastToRegisterType ( unsigned  TypeIdx)
static

Definition at line 144 of file AMDGPULegalizerInfo.cpp.

References getBitcastRegisterType().

◆ bitcastToVectorElement32()

static LegalizeMutation bitcastToVectorElement32 ( unsigned  TypeIdx)
static

◆ convertImageAddrToPacked()

static void convertImageAddrToPacked ( MachineIRBuilder B,
MachineInstr MI,
int  DimIdx,
int  NumVAddrs 
)
static

Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Definition at line 4063 of file AMDGPULegalizerInfo.cpp.

References llvm::SmallVectorImpl< T >::append(), assert(), B, llvm::SrcOp::getReg(), I, llvm::isPowerOf2_32(), MI, llvm::NextPowerOf2(), llvm::LLT::scalar(), llvm::RegState::Undef, and llvm::LLT::vector().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ elementTypeIsLegal()

static LegalityPredicate elementTypeIsLegal ( unsigned  TypeIdx)
static

◆ emitReciprocalU64()

static std::pair<Register, Register> emitReciprocalU64 ( MachineIRBuilder B,
Register  Val 
)
static

◆ extractF64Exponent()

static MachineInstrBuilder extractF64Exponent ( Register  Hi,
MachineIRBuilder B 
)
static

◆ fewerEltsToSize64Vector()

static LegalizeMutation fewerEltsToSize64Vector ( unsigned  TypeIdx)
static

◆ getBitcastRegisterType()

static LLT getBitcastRegisterType ( const LLT  Ty)
static

◆ getBufferAtomicPseudo()

static unsigned getBufferAtomicPseudo ( Intrinsic::ID  IntrID)
static

◆ getDSFPAtomicOpcode()

static unsigned getDSFPAtomicOpcode ( Intrinsic::ID  IID)
static

◆ getPow2ScalarType()

static LLT getPow2ScalarType ( LLT  Ty)
static

◆ getPow2VectorType()

static LLT getPow2VectorType ( LLT  Ty)
static

◆ isLoadStoreLegal()

static bool isLoadStoreLegal ( const GCNSubtarget ST,
const LegalityQuery Query,
unsigned  Opcode 
)
static

◆ isLoadStoreSizeLegal()

static bool isLoadStoreSizeLegal ( const GCNSubtarget ST,
const LegalityQuery Query,
unsigned  Opcode 
)
static

◆ isNot()

static bool isNot ( const MachineRegisterInfo MRI,
const MachineInstr MI 
)
static

◆ isRegisterSize()

static bool isRegisterSize ( unsigned  Size)
static

Definition at line 181 of file AMDGPULegalizerInfo.cpp.

References MaxRegisterSize, and llvm::Check::Size.

Referenced by isRegisterType(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [1/2]

static bool isRegisterType ( LLT  Ty)
static

◆ isRegisterType() [2/2]

static LegalityPredicate isRegisterType ( unsigned  TypeIdx)
static

Definition at line 209 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

◆ isRegisterVectorElementType()

static bool isRegisterVectorElementType ( LLT  EltTy)
static

Definition at line 185 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

Referenced by shouldBitcastLoadStoreType().

◆ isRegisterVectorType()

static bool isRegisterVectorType ( LLT  Ty)
static

◆ isSmallOddVector()

static LegalityPredicate isSmallOddVector ( unsigned  TypeIdx)
static

\returs true if this is an odd sized vector which should widen by adding an additional element.

This is mostly to handle <3 x s16> -> <4 x s16>. This excludes s1 vectors, which should always be scalarized.

Definition at line 65 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ isWideScalarTruncStore()

static LegalityPredicate isWideScalarTruncStore ( unsigned  TypeIdx)
static

Definition at line 225 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

◆ isWideVec16()

static LegalityPredicate isWideVec16 ( unsigned  TypeIdx)
static

◆ loadStoreBitcastWorkaround()

static bool loadStoreBitcastWorkaround ( const LLT  Ty)
static

◆ maxSizeForAddrSpace()

static unsigned maxSizeForAddrSpace ( const GCNSubtarget ST,
unsigned  AS,
bool  IsLoad 
)
static

◆ moreEltsToNext32Bit()

static LegalizeMutation moreEltsToNext32Bit ( unsigned  TypeIdx)
static

◆ numElementsNotEven()

static LegalityPredicate numElementsNotEven ( unsigned  TypeIdx)
static

Definition at line 174 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), and llvm::LLT::isVector().

◆ oneMoreElement()

static LegalizeMutation oneMoreElement ( unsigned  TypeIdx)
static

◆ packImage16bitOpsToDwords()

static void packImage16bitOpsToDwords ( MachineIRBuilder B,
MachineInstr MI,
SmallVectorImpl< Register > &  PackedAddrs,
unsigned  ArgOffset,
const AMDGPU::ImageDimIntrinsicInfo Intr,
bool  IsA16,
bool  IsG16 
)
static

Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.

Definition at line 4013 of file AMDGPULegalizerInfo.cpp.

References B, llvm::SrcOp::getReg(), I, Intr, MI, llvm::LLT::scalar(), and llvm::LLT::vector().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ shouldBitcastLoadStoreType()

static bool shouldBitcastLoadStoreType ( const GCNSubtarget ST,
const LLT  Ty,
const unsigned  MemSizeInBits 
)
static

Return true if a load or store of the type should be lowered with a bitcast to a different type.

Definition at line 355 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and llvm::Check::Size.

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ shouldWidenLoad() [1/2]

static bool shouldWidenLoad ( const GCNSubtarget ST,
const LegalityQuery Query,
unsigned  Opcode 
)
static

◆ shouldWidenLoad() [2/2]

static bool shouldWidenLoad ( const GCNSubtarget ST,
unsigned  SizeInBits,
unsigned  AlignInBits,
unsigned  AddrSpace,
unsigned  Opcode 
)
static

Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

Note this case when the memory access itself changes, not the size of the result register.

Definition at line 370 of file AMDGPULegalizerInfo.cpp.

References Align, llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, llvm::NextPowerOf2(), and llvm::ARM_MB::ST.

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().

◆ sizeIsMultipleOf32()

static LegalityPredicate sizeIsMultipleOf32 ( unsigned  TypeIdx)
static

Definition at line 79 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

◆ stripAnySourceMods()

static Register stripAnySourceMods ( Register  OrigSrc,
MachineRegisterInfo MRI 
)
static

Definition at line 2582 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

◆ toggleSPDenormMode()

static void toggleSPDenormMode ( bool  Enable,
MachineIRBuilder B,
const GCNSubtarget ST,
AMDGPU::SIModeRegisterDefaults  Mode 
)
static

◆ vectorSmallerThan()

static LegalityPredicate vectorSmallerThan ( unsigned  TypeIdx,
unsigned  Size 
)
static

◆ vectorWiderThan()

static LegalityPredicate vectorWiderThan ( unsigned  TypeIdx,
unsigned  Size 
)
static

◆ verifyCFIntrinsic()

static MachineInstr* verifyCFIntrinsic ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineInstr *&  Br,
MachineBasicBlock *&  UncondBrTarget,
bool &  Negated 
)
static

◆ widenToNextPowerOf2()

static LLT widenToNextPowerOf2 ( LLT  Ty)
static

Variable Documentation

◆ EnableNewLegality

cl::opt<bool> EnableNewLegality("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)
static

◆ MaxRegisterSize

constexpr unsigned MaxRegisterSize = 1024
staticconstexpr