This file implements the targeting of the Machinelegalizer class for AMDGPU. More...

#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"

Include dependency graph for AMDGPULegalizerInfo.cpp:

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Macros
#define	DEBUG_TYPE "amdgpu-legalinfo"

Functions
static LLT	getPow2VectorType (LLT Ty)

static LLT	getPow2ScalarType (LLT Ty)

static LegalityPredicate	isSmallOddVector (unsigned TypeIdx)

static LegalityPredicate	sizeIsMultipleOf32 (unsigned TypeIdx)

static LegalityPredicate	isWideVec16 (unsigned TypeIdx)

static LegalizeMutation	oneMoreElement (unsigned TypeIdx)

static LegalizeMutation	fewerEltsToSize64Vector (unsigned TypeIdx)

static LegalizeMutation	moreEltsToNext32Bit (unsigned TypeIdx)

static LLT	getBitcastRegisterType (const LLT Ty)

static LegalizeMutation	bitcastToRegisterType (unsigned TypeIdx)

static LegalizeMutation	bitcastToVectorElement32 (unsigned TypeIdx)

static LegalityPredicate	vectorSmallerThan (unsigned TypeIdx, unsigned Size)

static LegalityPredicate	vectorWiderThan (unsigned TypeIdx, unsigned Size)

static LegalityPredicate	numElementsNotEven (unsigned TypeIdx)

static bool	isRegisterSize (unsigned Size)

static bool	isRegisterVectorElementType (LLT EltTy)

static bool	isRegisterVectorType (LLT Ty)

static bool	isRegisterType (LLT Ty)

static LegalityPredicate	isRegisterType (unsigned TypeIdx)

static LegalityPredicate	elementTypeIsLegal (unsigned TypeIdx)

static LegalityPredicate	isWideScalarExtLoadTruncStore (unsigned TypeIdx)

static unsigned	maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad)

static bool	isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query)

static bool	loadStoreBitcastWorkaround (const LLT Ty)

static bool	isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query)

static bool	shouldBitcastLoadStoreType (const GCNSubtarget &ST, const LLT Ty, const LLT MemTy)
	Return true if a load or store of the type should be lowered with a bitcast to a different type.

static bool	shouldWidenLoad (const GCNSubtarget &ST, LLT MemoryTy, uint64_t AlignInBits, unsigned AddrSpace, unsigned Opcode)
	Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

static bool	shouldWidenLoad (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)

static bool	isKnownNonNull (Register Val, MachineRegisterInfo &MRI, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
	Return true if the value is a known valid address, such that a null check is not necessary.

static MachineInstrBuilder	extractF64Exponent (Register Hi, MachineIRBuilder &B)

static LLT	widenToNextPowerOf2 (LLT Ty)

static Register	stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)

static bool	isNot (const MachineRegisterInfo &MRI, const MachineInstr &MI)

static MachineInstr *	verifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr &Br, MachineBasicBlock &UncondBrTarget, bool &Negated)

static bool	replaceWithConstant (MachineIRBuilder &B, MachineInstr &MI, int64_t C)

static std::pair< Register, Register >	emitReciprocalU64 (MachineIRBuilder &B, Register Val)

static void	toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, AMDGPU::SIModeRegisterDefaults Mode)

static unsigned	getDSFPAtomicOpcode (Intrinsic::ID IID)

static void	buildBufferLoad (unsigned Opc, Register LoadDstReg, Register RSrc, Register VIndex, Register VOffset, Register SOffset, unsigned ImmOffset, unsigned Format, unsigned AuxiliaryData, MachineMemOperand *MMO, bool IsTyped, bool HasVIndex, MachineIRBuilder &B)

static unsigned	getBufferAtomicPseudo (Intrinsic::ID IntrID)

static void	packImage16bitOpsToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
	Turn a set of s16 typed registers in `AddrRegs` into a dword sized vector with s16 typed elements.

static void	convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
	Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Variables
static cl::opt< bool >	EnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)

static constexpr unsigned	MaxRegisterSize = 1024

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo:: This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-legalinfo"

Definition at line 31 of file AMDGPULegalizerInfo.cpp.

Function Documentation

◆ bitcastToRegisterType()

static LegalizeMutation bitcastToRegisterType ( unsigned TypeIdx )

static

Definition at line 146 of file AMDGPULegalizerInfo.cpp.

References getBitcastRegisterType().

◆ bitcastToVectorElement32()

static LegalizeMutation bitcastToVectorElement32 ( unsigned TypeIdx )

static

Definition at line 153 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

◆ buildBufferLoad()

static void buildBufferLoad	(	unsigned	Opc,
		Register	LoadDstReg,
		Register	RSrc,
		Register	VIndex,
		Register	VOffset,
		Register	SOffset,
		unsigned	ImmOffset,
		unsigned	Format,
		unsigned	AuxiliaryData,
		MachineMemOperand *	MMO,
		bool	IsTyped,
		bool	HasVIndex,
		MachineIRBuilder &	B
	)

static

Definition at line 4471 of file AMDGPULegalizerInfo.cpp.

References B, and llvm::Format.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad().

◆ convertImageAddrToPacked()

static void convertImageAddrToPacked	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		int	DimIdx,
		int	NumVAddrs
	)

static

Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Definition at line 4830 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::LLT::scalar(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ elementTypeIsLegal()

static LegalityPredicate elementTypeIsLegal ( unsigned TypeIdx )

static

Definition at line 218 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ emitReciprocalU64()

static std::pair< Register, Register > emitReciprocalU64	(	MachineIRBuilder &	B,
		Register	Val
	)

static

Definition at line 3477 of file AMDGPULegalizerInfo.cpp.

References B, llvm::BitsToFloat(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl().

◆ extractF64Exponent()

static MachineInstrBuilder extractF64Exponent	(	Register	Hi,
		MachineIRBuilder &	B
	)

static

Definition at line 2113 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Hi, and llvm::LLT::scalar().

◆ fewerEltsToSize64Vector()

static LegalizeMutation fewerEltsToSize64Vector ( unsigned TypeIdx )

static

Definition at line 104 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ getBitcastRegisterType()

static LLT getBitcastRegisterType ( const LLT Ty )

static

Definition at line 134 of file AMDGPULegalizerInfo.cpp.

References llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), and Size.

Referenced by bitcastToRegisterType(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getBufferAtomicPseudo()

static unsigned getBufferAtomicPseudo ( Intrinsic::ID IntrID )

static

Definition at line 4641 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic().

◆ getDSFPAtomicOpcode()

static unsigned getDSFPAtomicOpcode ( Intrinsic::ID IID )

static

Definition at line 4112 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic().

◆ getPow2ScalarType()

static LLT getPow2ScalarType ( LLT Ty )

static

Definition at line 57 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::Log2_32_Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getPow2VectorType()

static LLT getPow2VectorType ( LLT Ty )

static

Definition at line 50 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), and llvm::Log2_32_Ceil().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ isKnownNonNull()

static bool isKnownNonNull	(	Register	Val,
		MachineRegisterInfo &	MRI,
		const AMDGPUTargetMachine &	TM,
		unsigned	AddrSpace
	)

static

Return true if the value is a known valid address, such that a null check is not necessary.

Definition at line 1909 of file AMDGPULegalizerInfo.cpp.

References llvm::ConstantInt::getSExtValue(), MRI, and TM.

Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ isLoadStoreLegal()

static bool isLoadStoreLegal	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query
	)

static

Definition at line 354 of file AMDGPULegalizerInfo.cpp.

References isLoadStoreSizeLegal(), isRegisterType(), loadStoreBitcastWorkaround(), and llvm::LegalityQuery::Types.

◆ isLoadStoreSizeLegal()

static bool isLoadStoreSizeLegal	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query
	)

static

Definition at line 266 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), assert(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), maxSizeForAddrSpace(), llvm::LegalityQuery::MMODescrs, llvm::LegalityQuery::Opcode, RegSize, Size, and llvm::LegalityQuery::Types.

Referenced by isLoadStoreLegal().

◆ isNot()

static bool isNot	(	const MachineRegisterInfo &	MRI,
		const MachineInstr &	MI
	)

static

Definition at line 3198 of file AMDGPULegalizerInfo.cpp.

References llvm::getIConstantVRegSExtVal(), MI, and MRI.

Referenced by llvm::MCAsmParserExtension::ParseDirectiveCGProfile(), and verifyCFIntrinsic().

◆ isRegisterSize()

static bool isRegisterSize ( unsigned Size )

static

Definition at line 184 of file AMDGPULegalizerInfo.cpp.

References MaxRegisterSize, and Size.

Referenced by isRegisterType(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [1/2]

static bool isRegisterType ( LLT Ty )

static

Definition at line 200 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterVectorType(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), isLoadStoreLegal(), isRegisterType(), llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [2/2]

static LegalityPredicate isRegisterType ( unsigned TypeIdx )

static

Definition at line 212 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

◆ isRegisterVectorElementType()

static bool isRegisterVectorElementType ( LLT EltTy )

static

Definition at line 188 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

Referenced by shouldBitcastLoadStoreType().

◆ isRegisterVectorType()

static bool isRegisterVectorType ( LLT Ty )

static

Definition at line 193 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), and llvm::LLT::getSizeInBits().

Referenced by isRegisterType().

◆ isSmallOddVector()

static LegalityPredicate isSmallOddVector ( unsigned TypeIdx )

static

Returns: true if this is an odd sized vector which should widen by adding an additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This excludes s1 vectors, which should always be scalarized.

Definition at line 66 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ isWideScalarExtLoadTruncStore()

static LegalityPredicate isWideScalarExtLoadTruncStore ( unsigned TypeIdx )

static

Definition at line 230 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().

◆ isWideVec16()

static LegalityPredicate isWideVec16 ( unsigned TypeIdx )

static

Definition at line 87 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), llvm::LLT::getScalarType(), and llvm::LLT::getSizeInBits().

◆ loadStoreBitcastWorkaround()

static bool loadStoreBitcastWorkaround ( const LLT Ty )

static

Definition at line 336 of file AMDGPULegalizerInfo.cpp.

References EnableNewLegality, llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isPointer(), llvm::LLT::isVector(), and Size.

Referenced by isLoadStoreLegal(), and shouldBitcastLoadStoreType().

◆ maxSizeForAddrSpace()

static unsigned maxSizeForAddrSpace	(	const GCNSubtarget &	ST,
		unsigned	AS,
		bool	IsLoad
	)

static

Definition at line 241 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLoadStoreSizeLegal(), and shouldWidenLoad().

◆ moreEltsToNext32Bit()

static LegalizeMutation moreEltsToNext32Bit ( unsigned TypeIdx )

static

Definition at line 118 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), and Size.

◆ numElementsNotEven()

static LegalityPredicate numElementsNotEven ( unsigned TypeIdx )

static

Definition at line 177 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), and llvm::LLT::isVector().

◆ oneMoreElement()

static LegalizeMutation oneMoreElement ( unsigned TypeIdx )

static

Definition at line 95 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), and llvm::LLT::getNumElements().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ packImage16bitOpsToDwords()

static void packImage16bitOpsToDwords	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		SmallVectorImpl< Register > &	PackedAddrs,
		unsigned	ArgOffset,
		const AMDGPU::ImageDimIntrinsicInfo *	Intr,
		bool	IsA16,
		bool	IsG16
	)

static

Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.

Definition at line 4769 of file AMDGPULegalizerInfo.cpp.

References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, Intr, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ replaceWithConstant()

static bool replaceWithConstant	(	MachineIRBuilder &	B,
		MachineInstr &	MI,
		int64_t	C
	)

static

Definition at line 3319 of file AMDGPULegalizerInfo.cpp.

References B, llvm::CallingConv::C, and MI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic().

◆ shouldBitcastLoadStoreType()

static bool shouldBitcastLoadStoreType	(	const GCNSubtarget &	ST,
		const LLT	Ty,
		const LLT	MemTy
	)

static

Return true if a load or store of the type should be lowered with a bitcast to a different type.

Definition at line 362 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ shouldWidenLoad() [1/2]

static bool shouldWidenLoad	(	const GCNSubtarget &	ST,
		const LegalityQuery &	Query,
		unsigned	Opcode
	)

static

Definition at line 415 of file AMDGPULegalizerInfo.cpp.

References llvm::LegalityQuery::MMODescrs, shouldWidenLoad(), and llvm::LegalityQuery::Types.

◆ shouldWidenLoad() [2/2]

static bool shouldWidenLoad	(	const GCNSubtarget &	ST,
		LLT	MemoryTy,
		uint64_t	AlignInBits,
		unsigned	AddrSpace,
		unsigned	Opcode
	)

static

Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

Note this case when the memory access itself changes, not the size of the result register.

Definition at line 381 of file AMDGPULegalizerInfo.cpp.

References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::CallingConv::Fast, llvm::LLT::getSizeInBits(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, and llvm::NextPowerOf2().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().

◆ sizeIsMultipleOf32()

static LegalityPredicate sizeIsMultipleOf32 ( unsigned TypeIdx )

static

Definition at line 80 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

◆ stripAnySourceMods()

static Register stripAnySourceMods	(	Register	OrigSrc,
		MachineRegisterInfo &	MRI
	)

static

Definition at line 2792 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

◆ toggleSPDenormMode()

static void toggleSPDenormMode	(	bool	Enable,
		MachineIRBuilder &	B,
		const GCNSubtarget &	ST,
		AMDGPU::SIModeRegisterDefaults	Mode
	)

static

Definition at line 3850 of file AMDGPULegalizerInfo.cpp.

References B, llvm::Enable, FP_DENORM_FLUSH_NONE, llvm::AMDGPU::Hwreg::ID_MODE, llvm::AMDGPU::Hwreg::OFFSET_SHIFT_, and llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32().

◆ vectorSmallerThan()

static LegalityPredicate vectorSmallerThan	(	unsigned	TypeIdx,
		unsigned	Size
	)

static

Definition at line 163 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

◆ vectorWiderThan()

static LegalityPredicate vectorWiderThan	(	unsigned	TypeIdx,
		unsigned	Size
	)

static

Definition at line 170 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ verifyCFIntrinsic()

static MachineInstr * verifyCFIntrinsic	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineInstr *&	Br,
		MachineBasicBlock *&	UncondBrTarget,
		bool &	Negated
	)

static

Definition at line 3207 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::eraseInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), isNot(), MI, MRI, and UseMI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().

◆ widenToNextPowerOf2()

static LLT widenToNextPowerOf2 ( LLT Ty )

static

Definition at line 2591 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), llvm::PowerOf2Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().

Variable Documentation

◆ EnableNewLegality

cl::opt< bool > EnableNewLegality("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)	(	"amdgpu-global-isel-new-legality"	,
		cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns")	,
		cl::init(false)	,
		cl::ReallyHidden
	)

static

Referenced by loadStoreBitcastWorkaround().

◆ MaxRegisterSize

constexpr unsigned MaxRegisterSize = 1024

staticconstexpr

Definition at line 47 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterSize().

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ bitcastToRegisterType()

◆ bitcastToVectorElement32()

◆ buildBufferLoad()

◆ convertImageAddrToPacked()

◆ elementTypeIsLegal()

◆ emitReciprocalU64()

◆ extractF64Exponent()

◆ fewerEltsToSize64Vector()

◆ getBitcastRegisterType()

◆ getBufferAtomicPseudo()

◆ getDSFPAtomicOpcode()

◆ getPow2ScalarType()

◆ getPow2VectorType()

◆ isKnownNonNull()

◆ isLoadStoreLegal()

◆ isLoadStoreSizeLegal()

◆ isNot()

◆ isRegisterSize()

◆ isRegisterType() [1/2]

◆ isRegisterType() [2/2]

◆ isRegisterVectorElementType()

◆ isRegisterVectorType()

◆ isSmallOddVector()

◆ isWideScalarExtLoadTruncStore()

◆ isWideVec16()

◆ loadStoreBitcastWorkaround()

◆ maxSizeForAddrSpace()

◆ moreEltsToNext32Bit()

◆ numElementsNotEven()

◆ oneMoreElement()

◆ packImage16bitOpsToDwords()

◆ replaceWithConstant()

◆ shouldBitcastLoadStoreType()

◆ shouldWidenLoad() [1/2]

◆ shouldWidenLoad() [2/2]

◆ sizeIsMultipleOf32()

◆ stripAnySourceMods()

◆ toggleSPDenormMode()

◆ vectorSmallerThan()

◆ vectorWiderThan()

◆ verifyCFIntrinsic()

◆ widenToNextPowerOf2()

Variable Documentation

◆ EnableNewLegality

◆ MaxRegisterSize