LLVM 24.0.0git
Macros | Functions | Variables
AMDGPULegalizerInfo.cpp File Reference

This file implements the targeting of the Machinelegalizer class for AMDGPU. More...

#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMemoryUtils.h"
#include "AMDGPUTargetMachine.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/PseudoSourceValueManager.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/Support/AMDGPUAddrSpace.h"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "amdgpu-legalinfo"

Functions

static LLT getPow2VectorType (LLT Ty)
static LLT getPow2ScalarType (LLT Ty)
static LegalityPredicate isSmallOddVector (unsigned TypeIdx)
static LegalityPredicate sizeIsMultipleOf32 (unsigned TypeIdx)
static LegalityPredicate isWideVec16 (unsigned TypeIdx)
static LegalizeMutation oneMoreElement (unsigned TypeIdx)
static LegalizeMutation fewerEltsToSize64Vector (unsigned TypeIdx)
static LegalizeMutation moreEltsToNext32Bit (unsigned TypeIdx)
static LegalizeMutation getScalarTypeFromMemDesc (unsigned TypeIdx)
static LegalizeMutation moreElementsToNextExistingRegClass (unsigned TypeIdx)
static LLT getBufferRsrcScalarType (const LLT Ty)
static LLT getBufferRsrcRegisterType (const LLT Ty)
static LLT getBitcastRegisterType (const LLT Ty)
static LegalizeMutation bitcastToRegisterType (unsigned TypeIdx)
static LegalizeMutation bitcastToVectorElement32 (unsigned TypeIdx)
static LegalityPredicate vectorSmallerThan (unsigned TypeIdx, unsigned Size)
static LegalityPredicate vectorWiderThan (unsigned TypeIdx, unsigned Size)
static LegalityPredicate numElementsNotEven (unsigned TypeIdx)
static bool isRegisterSize (const GCNSubtarget &ST, unsigned Size)
static bool isRegisterVectorElementType (LLT EltTy)
static bool isRegisterVectorType (LLT Ty)
static bool isRegisterType (const GCNSubtarget &ST, LLT Ty)
static LegalityPredicate isRegisterType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate isIllegalRegisterType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate elementTypeIsLegal (unsigned TypeIdx)
static bool isRegisterClassType (const GCNSubtarget &ST, LLT Ty)
static LegalityPredicate isRegisterClassType (const GCNSubtarget &ST, unsigned TypeIdx)
static LegalityPredicate isWideScalarExtLoadTruncStore (unsigned TypeIdx)
static LegalityPredicate isTruncStoreToSizePowerOf2 (unsigned TypeIdx)
static unsigned maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad, bool IsAtomic)
static bool isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query)
static bool hasBufferRsrcWorkaround (const LLT Ty)
static bool loadStoreBitcastWorkaround (const GCNSubtarget &ST, const LLT Ty)
static bool isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query)
static bool shouldBitcastLoadStoreType (const GCNSubtarget &ST, const LLT Ty, const LLT MemTy)
 Return true if a load or store of the type should be lowered with a bitcast to a different type.
static bool shouldWidenLoad (const GCNSubtarget &ST, LLT MemoryTy, uint64_t AlignInBits, unsigned AddrSpace, unsigned Opcode)
 Return true if we should legalize a load by widening an odd sized memory access up to the alignment.
static bool shouldWidenLoad (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
static LLT castBufferRsrcFromV4I32 (MachineInstr &MI, MachineIRBuilder &B, MachineRegisterInfo &MRI, unsigned Idx)
 Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx and then to transform it to a p8 via bitcasts and inttoptr.
static Register castBufferRsrcToV4I32 (Register Pointer, MachineIRBuilder &B)
 Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.
static void castBufferRsrcArgToV4I32 (MachineInstr &MI, MachineIRBuilder &B, unsigned Idx)
static bool isKnownNonNull (Register Val, MachineRegisterInfo &MRI, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
 Return true if the value is a known valid address, such that a null check is not necessary.
static MachineInstrBuilder extractF64Exponent (Register Hi, MachineIRBuilder &B)
static LLT widenToNextPowerOf2 (LLT Ty)
static bool valueIsKnownNeverF32Denorm (const MachineRegisterInfo &MRI, Register Src)
 Return true if it's known that Src can never be an f32 denormal value.
static bool allowApproxFunc (const MachineFunction &MF, unsigned Flags)
static bool needsDenormHandlingF32 (const MachineFunction &MF, Register Src, unsigned Flags)
static Register getMad (MachineIRBuilder &B, LLT Ty, Register X, Register Y, Register Z, unsigned Flags)
static MachineInstrBuilder buildExp (MachineIRBuilder &B, const DstOp &Dst, const SrcOp &Src, unsigned Flags)
static Register stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)
static bool isNot (const MachineRegisterInfo &MRI, const MachineInstr &MI)
static MachineInstr * verifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br, MachineBasicBlock *&UncondBrTarget, bool &Negated)
static bool replaceWithConstant (MachineIRBuilder &B, MachineInstr &MI, int64_t C)
static std::pair< Register, Register > emitReciprocalU64 (MachineIRBuilder &B, Register Val)
static void toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, SIModeRegisterDefaults Mode)
static void buildBufferLoad (unsigned Opc, Register LoadDstReg, Register RSrc, Register VIndex, Register VOffset, Register SOffset, unsigned ImmOffset, unsigned Format, unsigned AuxiliaryData, MachineMemOperand *MMO, bool IsTyped, bool HasVIndex, MachineIRBuilder &B)
static void buildTFEBufferLoad (unsigned Opc, ArrayRef< Register > ValueDsts, Register StatusDst, Register RSrc, Register VIndex, Register VOffset, Register SOffset, unsigned ImmOffset, unsigned Format, unsigned AuxiliaryData, MachineMemOperand *MMO, bool IsTyped, bool HasVIndex, MachineIRBuilder &B)
static unsigned getBufferAtomicPseudo (Intrinsic::ID IntrID)
static void packImage16bitOpsToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
 Turn a set of f16 typed registers in AddrRegs into a dword sized vector with f16 typed elements.
static void convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
 Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Variables

static constexpr unsigned MaxRegisterSize = 1024
constexpr LLT F16 = LLT::float16()
constexpr LLT BF16 = LLT::bfloat16()
constexpr LLT F32 = LLT::float32()
constexpr LLT F64 = LLT::float64()
constexpr LLT V2F16 = LLT::fixed_vector(2, F16)
constexpr LLT V2BF16 = LLT::fixed_vector(2, BF16)
constexpr LLT V2F32 = LLT::fixed_vector(2, F32)
constexpr LLT V2F64 = LLT::fixed_vector(2, F64)
constexpr LLT S1 = LLT::scalar(1)
constexpr LLT S8 = LLT::scalar(8)
constexpr LLT S16 = LLT::scalar(16)
constexpr LLT S32 = LLT::scalar(32)
constexpr LLT S64 = LLT::scalar(64)
constexpr LLT S96 = LLT::scalar(96)
constexpr LLT S128 = LLT::scalar(128)
constexpr LLT S160 = LLT::scalar(160)
constexpr LLT S192 = LLT::scalar(192)
constexpr LLT S224 = LLT::scalar(224)
constexpr LLT S256 = LLT::scalar(256)
constexpr LLT S512 = LLT::scalar(512)
constexpr LLT S1024 = LLT::scalar(1024)
constexpr LLT MaxScalar = LLT::scalar(MaxRegisterSize)
constexpr LLT V2S8 = LLT::fixed_vector(2, 8)
constexpr LLT V2S16 = LLT::fixed_vector(2, 16)
constexpr LLT V4S16 = LLT::fixed_vector(4, 16)
constexpr LLT V6S16 = LLT::fixed_vector(6, 16)
constexpr LLT V8S16 = LLT::fixed_vector(8, 16)
constexpr LLT V10S16 = LLT::fixed_vector(10, 16)
constexpr LLT V12S16 = LLT::fixed_vector(12, 16)
constexpr LLT V16S16 = LLT::fixed_vector(16, 16)
constexpr LLT V2S32 = LLT::fixed_vector(2, 32)
constexpr LLT V3S32 = LLT::fixed_vector(3, 32)
constexpr LLT V4S32 = LLT::fixed_vector(4, 32)
constexpr LLT V5S32 = LLT::fixed_vector(5, 32)
constexpr LLT V6S32 = LLT::fixed_vector(6, 32)
constexpr LLT V7S32 = LLT::fixed_vector(7, 32)
constexpr LLT V8S32 = LLT::fixed_vector(8, 32)
constexpr LLT V9S32 = LLT::fixed_vector(9, 32)
constexpr LLT V10S32 = LLT::fixed_vector(10, 32)
constexpr LLT V11S32 = LLT::fixed_vector(11, 32)
constexpr LLT V12S32 = LLT::fixed_vector(12, 32)
constexpr LLT V16S32 = LLT::fixed_vector(16, 32)
constexpr LLT V32S32 = LLT::fixed_vector(32, 32)
constexpr LLT V2S64 = LLT::fixed_vector(2, 64)
constexpr LLT V3S64 = LLT::fixed_vector(3, 64)
constexpr LLT V4S64 = LLT::fixed_vector(4, 64)
constexpr LLT V5S64 = LLT::fixed_vector(5, 64)
constexpr LLT V6S64 = LLT::fixed_vector(6, 64)
constexpr LLT V7S64 = LLT::fixed_vector(7, 64)
constexpr LLT V8S64 = LLT::fixed_vector(8, 64)
constexpr LLT V16S64 = LLT::fixed_vector(16, 64)
constexpr LLT V2S128 = LLT::fixed_vector(2, 128)
constexpr LLT V4S128 = LLT::fixed_vector(4, 128)
constexpr std::initializer_list< LLT > AllScalarTypes
constexpr std::initializer_list< LLT > AllS16Vectors
constexpr std::initializer_list< LLT > AllS32Vectors
constexpr std::initializer_list< LLT > AllS64Vectors
constexpr std::initializer_list< LLT > AllVectors
static constexpr unsigned SPDenormModeBitField
static constexpr unsigned FPEnvModeBitField
static constexpr unsigned FPEnvTrapBitField

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo
This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-legalinfo"

Definition at line 40 of file AMDGPULegalizerInfo.cpp.

Function Documentation

◆ allowApproxFunc()

bool allowApproxFunc ( const MachineFunction & MF,
unsigned Flags )
static

Definition at line 3705 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineInstr::FmAfn.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFPow(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

◆ bitcastToRegisterType()

LegalizeMutation bitcastToRegisterType ( unsigned TypeIdx)
static

Definition at line 191 of file AMDGPULegalizerInfo.cpp.

References getBitcastRegisterType().

◆ bitcastToVectorElement32()

LegalizeMutation bitcastToVectorElement32 ( unsigned TypeIdx)
static

Definition at line 198 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::ElementCount::getFixed(), llvm::LLT::integer(), llvm::LLT::scalarOrVector(), and llvm::Size.

◆ buildBufferLoad()

void buildBufferLoad ( unsigned Opc,
Register LoadDstReg,
Register RSrc,
Register VIndex,
Register VOffset,
Register SOffset,
unsigned ImmOffset,
unsigned Format,
unsigned AuxiliaryData,
MachineMemOperand * MMO,
bool IsTyped,
bool HasVIndex,
MachineIRBuilder & B )
static

Definition at line 6853 of file AMDGPULegalizerInfo.cpp.

References B(), and Opc.

Referenced by buildTFEBufferLoad(), and llvm::AMDGPULegalizerInfo::legalizeBufferLoad().

◆ buildExp()

MachineInstrBuilder buildExp ( MachineIRBuilder & B,
const DstOp & Dst,
const SrcOp & Src,
unsigned Flags )
static

Definition at line 4000 of file AMDGPULegalizerInfo.cpp.

References B(), and F32.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp10Unsafe(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafeImpl(), and llvm::AMDGPULegalizerInfo::legalizeFPow().

◆ buildTFEBufferLoad()

void buildTFEBufferLoad ( unsigned Opc,
ArrayRef< Register > ValueDsts,
Register StatusDst,
Register RSrc,
Register VIndex,
Register VOffset,
Register SOffset,
unsigned ImmOffset,
unsigned Format,
unsigned AuxiliaryData,
MachineMemOperand * MMO,
bool IsTyped,
bool HasVIndex,
MachineIRBuilder & B )
static

Definition at line 6874 of file AMDGPULegalizerInfo.cpp.

References B(), buildBufferLoad(), llvm::LLT::fixed_vector(), llvm::LLT::integer(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ArrayRef< T >::size().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad().

◆ castBufferRsrcArgToV4I32()

void castBufferRsrcArgToV4I32 ( MachineInstr & MI,
MachineIRBuilder & B,
unsigned Idx )
static

Definition at line 678 of file AMDGPULegalizerInfo.cpp.

References B(), castBufferRsrcToV4I32(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), MI, and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeSBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeSBufferPrefetch(), and llvm::AMDGPULegalizerInfo::legalizeStore().

◆ castBufferRsrcFromV4I32()

LLT castBufferRsrcFromV4I32 ( MachineInstr & MI,
MachineIRBuilder & B,
MachineRegisterInfo & MRI,
unsigned Idx )
static

Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx and then to transform it to a p8 via bitcasts and inttoptr.

In addition, handle vectors of p8. Returns the new type.

Definition at line 618 of file AMDGPULegalizerInfo.cpp.

References B(), getBufferRsrcRegisterType(), getBufferRsrcScalarType(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), I, llvm::LLT::integer(), MI, MRI, NumParts, Scalar, and llvm::MachineOperand::setReg().

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ castBufferRsrcToV4I32()

Register castBufferRsrcToV4I32 ( Register Pointer,
MachineIRBuilder & B )
static

Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.

This is a hack, which is needed in order to account for the fact that we can't define a register class for s128 without breaking SelectionDAG.

Definition at line 659 of file AMDGPULegalizerInfo.cpp.

References B(), getBufferRsrcRegisterType(), getBufferRsrcScalarType(), I, llvm::LLT::integer(), MRI, NumParts, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and Scalar.

Referenced by castBufferRsrcArgToV4I32(), and llvm::AMDGPULegalizerInfo::fixStoreSourceType().

◆ convertImageAddrToPacked()

void convertImageAddrToPacked ( MachineIRBuilder & B,
MachineInstr & MI,
int DimIdx,
int NumVAddrs )
static

Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.

Definition at line 7334 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, llvm::LLT::integer(), MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ elementTypeIsLegal()

LegalityPredicate elementTypeIsLegal ( unsigned TypeIdx)
static

Definition at line 279 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ emitReciprocalU64()

std::pair< Register, Register > emitReciprocalU64 ( MachineIRBuilder & B,
Register Val )
static

Definition at line 5360 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::bit_cast(), F32, and llvm::LLT::integer().

Referenced by llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl().

◆ extractF64Exponent()

MachineInstrBuilder extractF64Exponent ( Register Hi,
MachineIRBuilder & B )
static

Definition at line 2839 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::Hi, and llvm::LLT::integer().

◆ fewerEltsToSize64Vector()

LegalizeMutation fewerEltsToSize64Vector ( unsigned TypeIdx)
static

Definition at line 105 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LLT::scalarOrVector(), and llvm::Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ getBitcastRegisterType()

LLT getBitcastRegisterType ( const LLT Ty)
static

Definition at line 179 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), llvm::LLT::integer(), and llvm::Size.

Referenced by bitcastToRegisterType(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getBufferAtomicPseudo()

unsigned getBufferAtomicPseudo ( Intrinsic::ID IntrID)
static

Definition at line 7108 of file AMDGPULegalizerInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic().

◆ getBufferRsrcRegisterType()

LLT getBufferRsrcRegisterType ( const LLT Ty)
static

Definition at line 172 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), and llvm::LLT::integer().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

◆ getBufferRsrcScalarType()

LLT getBufferRsrcScalarType ( const LLT Ty)
static

Definition at line 165 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::scalar(), and llvm::LLT::vector().

Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().

◆ getMad()

Register getMad ( MachineIRBuilder & B,
LLT Ty,
Register X,
Register Y,
Register Z,
unsigned Flags )
static

Definition at line 3785 of file AMDGPULegalizerInfo.cpp.

References B(), llvm::FMul, X, and Y.

◆ getPow2ScalarType()

LLT getPow2ScalarType ( LLT Ty)
static

Definition at line 58 of file AMDGPULegalizerInfo.cpp.

References llvm::Log2_32_Ceil(), and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getPow2VectorType()

LLT getPow2VectorType ( LLT Ty)
static

Definition at line 51 of file AMDGPULegalizerInfo.cpp.

References llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), and llvm::Log2_32_Ceil().

Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ getScalarTypeFromMemDesc()

LegalizeMutation getScalarTypeFromMemDesc ( unsigned TypeIdx)
static

Definition at line 136 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::integer().

◆ hasBufferRsrcWorkaround()

bool hasBufferRsrcWorkaround ( const LLT Ty)
static

Definition at line 511 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, and hasBufferRsrcWorkaround().

Referenced by castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), hasBufferRsrcWorkaround(), isLoadStoreLegal(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeSBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeStore(), and loadStoreBitcastWorkaround().

◆ isIllegalRegisterType()

LegalityPredicate isIllegalRegisterType ( const GCNSubtarget & ST,
unsigned TypeIdx )
static

Definition at line 270 of file AMDGPULegalizerInfo.cpp.

References llvm::SIRegisterInfo::getSGPRClassForBitWidth(), and isRegisterType().

◆ isKnownNonNull()

bool isKnownNonNull ( Register Val,
MachineRegisterInfo & MRI,
const AMDGPUTargetMachine & TM,
unsigned AddrSpace )
static

Return true if the value is a known valid address, such that a null check is not necessary.

Definition at line 2573 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPU::getNullPointerValue(), llvm::ConstantInt::getSExtValue(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ isLoadStoreLegal()

bool isLoadStoreLegal ( const GCNSubtarget & ST,
const LegalityQuery & Query )
static

Definition at line 544 of file AMDGPULegalizerInfo.cpp.

References hasBufferRsrcWorkaround(), isLoadStoreSizeLegal(), isRegisterType(), loadStoreBitcastWorkaround(), and llvm::LegalityQuery::Types.

◆ isLoadStoreSizeLegal()

bool isLoadStoreSizeLegal ( const GCNSubtarget & ST,
const LegalityQuery & Query )
static

Definition at line 435 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, maxSizeForAddrSpace(), llvm::LegalityQuery::MMODescrs, llvm::NotAtomic, llvm::LegalityQuery::Opcode, RegSize, llvm::Size, TLI, llvm::LegalityQuery::Types, and uint64_t.

Referenced by isLoadStoreLegal().

◆ isNot()

bool isNot ( const MachineRegisterInfo & MRI,
const MachineInstr & MI )
static

Definition at line 4903 of file AMDGPULegalizerInfo.cpp.

References llvm::getIConstantVRegSExtVal(), MI, and MRI.

Referenced by llvm::MCAsmParser::parseAtSpecifier(), llvm::MCAsmParserExtension::parseDirectiveCGProfile(), and verifyCFIntrinsic().

◆ isRegisterClassType() [1/2]

bool isRegisterClassType ( const GCNSubtarget & ST,
LLT Ty )
static

Definition at line 368 of file AMDGPULegalizerInfo.cpp.

References AllS16Vectors, AllS32Vectors, AllS64Vectors, AllScalarTypes, llvm::is_contained(), S16, and llvm::LLT::scalar().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

◆ isRegisterClassType() [2/2]

LegalityPredicate isRegisterClassType ( const GCNSubtarget & ST,
unsigned TypeIdx )
static

Definition at line 378 of file AMDGPULegalizerInfo.cpp.

References isRegisterClassType().

◆ isRegisterSize()

bool isRegisterSize ( const GCNSubtarget & ST,
unsigned Size )
static

Definition at line 230 of file AMDGPULegalizerInfo.cpp.

References MaxRegisterSize, and llvm::Size.

Referenced by isRegisterType(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [1/2]

bool isRegisterType ( const GCNSubtarget & ST,
LLT Ty )
static

Definition at line 248 of file AMDGPULegalizerInfo.cpp.

References isRegisterSize(), and isRegisterVectorType().

Referenced by isIllegalRegisterType(), isLoadStoreLegal(), isRegisterType(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), and shouldBitcastLoadStoreType().

◆ isRegisterType() [2/2]

LegalityPredicate isRegisterType ( const GCNSubtarget & ST,
unsigned TypeIdx )
static

Definition at line 260 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

◆ isRegisterVectorElementType()

bool isRegisterVectorElementType ( LLT EltTy)
static

Definition at line 235 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

Referenced by shouldBitcastLoadStoreType().

◆ isRegisterVectorType()

bool isRegisterVectorType ( LLT Ty)
static

Definition at line 240 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterType().

◆ isSmallOddVector()

LegalityPredicate isSmallOddVector ( unsigned TypeIdx)
static
Returns
true if this is an odd sized vector which should widen by adding an additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This excludes s1 vectors, which should always be scalarized.

Definition at line 67 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getElementType(), and llvm::LLT::getSizeInBits().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ isTruncStoreToSizePowerOf2()

LegalityPredicate isTruncStoreToSizePowerOf2 ( unsigned TypeIdx)
static

Definition at line 397 of file AMDGPULegalizerInfo.cpp.

References llvm::isPowerOf2_64(), and isWideScalarExtLoadTruncStore().

◆ isWideScalarExtLoadTruncStore()

LegalityPredicate isWideScalarExtLoadTruncStore ( unsigned TypeIdx)
static

Definition at line 387 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::isVector().

Referenced by isTruncStoreToSizePowerOf2().

◆ isWideVec16()

LegalityPredicate isWideVec16 ( unsigned TypeIdx)
static

Definition at line 88 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getScalarType(), and llvm::LLT::getSizeInBits().

◆ loadStoreBitcastWorkaround()

bool loadStoreBitcastWorkaround ( const GCNSubtarget & ST,
const LLT Ty )
static

Definition at line 525 of file AMDGPULegalizerInfo.cpp.

References hasBufferRsrcWorkaround(), and llvm::Size.

Referenced by isLoadStoreLegal(), and shouldBitcastLoadStoreType().

◆ maxSizeForAddrSpace()

unsigned maxSizeForAddrSpace ( const GCNSubtarget & ST,
unsigned AS,
bool IsLoad,
bool IsAtomic )
static

Definition at line 408 of file AMDGPULegalizerInfo.cpp.

References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLoadStoreSizeLegal(), and shouldWidenLoad().

◆ moreElementsToNextExistingRegClass()

LegalizeMutation moreElementsToNextExistingRegClass ( unsigned TypeIdx)
static

Definition at line 144 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getNumElements(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), and MaxRegisterSize.

◆ moreEltsToNext32Bit()

LegalizeMutation moreEltsToNext32Bit ( unsigned TypeIdx)
static

Definition at line 119 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), and llvm::Size.

◆ needsDenormHandlingF32()

bool needsDenormHandlingF32 ( const MachineFunction & MF,
Register Src,
unsigned Flags )
static

Definition at line 3709 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineFunction::getDenormalMode(), llvm::MachineFunction::getRegInfo(), llvm::APFloatBase::IEEEsingle(), llvm::DenormalMode::Input, llvm::DenormalMode::PreserveSign, and valueIsKnownNeverF32Denorm().

Referenced by llvm::AMDGPULegalizerInfo::getScaledLogInput(), llvm::AMDGPULegalizerInfo::legalizeFExp10Unsafe(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().

◆ numElementsNotEven()

LegalityPredicate numElementsNotEven ( unsigned TypeIdx)
static

Definition at line 223 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getNumElements(), and llvm::LLT::isVector().

◆ oneMoreElement()

LegalizeMutation oneMoreElement ( unsigned TypeIdx)
static

Definition at line 96 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::fixed_vector(), and llvm::LLT::getElementType().

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ packImage16bitOpsToDwords()

void packImage16bitOpsToDwords ( MachineIRBuilder & B,
MachineInstr & MI,
SmallVectorImpl< Register > & PackedAddrs,
unsigned ArgOffset,
const AMDGPU::ImageDimIntrinsicInfo * Intr,
bool IsA16,
bool IsG16 )
static

Turn a set of f16 typed registers in AddrRegs into a dword sized vector with f16 typed elements.

Definition at line 7272 of file AMDGPULegalizerInfo.cpp.

References assert(), B(), llvm::AMDGPU::ImageDimIntrinsicInfo::BiasIndex, llvm::AMDGPU::ImageDimIntrinsicInfo::CoordStart, F16, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), llvm::AMDGPU::ImageDimIntrinsicInfo::GradientStart, I, MI, llvm::AMDGPU::ImageDimIntrinsicInfo::NumBiasArgs, llvm::AMDGPU::ImageDimIntrinsicInfo::NumGradients, llvm::SmallVectorTemplateBase< T, bool >::push_back(), V2F16, llvm::AMDGPU::ImageDimIntrinsicInfo::VAddrEnd, and llvm::AMDGPU::ImageDimIntrinsicInfo::VAddrStart.

Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().

◆ replaceWithConstant()

bool replaceWithConstant ( MachineIRBuilder & B,
MachineInstr & MI,
int64_t C )
static

Definition at line 5198 of file AMDGPULegalizerInfo.cpp.

References B(), C(), and MI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic().

◆ shouldBitcastLoadStoreType()

bool shouldBitcastLoadStoreType ( const GCNSubtarget & ST,
const LLT Ty,
const LLT MemTy )
static

Return true if a load or store of the type should be lowered with a bitcast to a different type.

Definition at line 552 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and llvm::Size.

Referenced by llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().

◆ shouldWidenLoad() [1/2]

bool shouldWidenLoad ( const GCNSubtarget & ST,
const LegalityQuery & Query,
unsigned Opcode )
static

Definition at line 605 of file AMDGPULegalizerInfo.cpp.

References llvm::LegalityQuery::MMODescrs, llvm::NotAtomic, shouldWidenLoad(), and llvm::LegalityQuery::Types.

◆ shouldWidenLoad() [2/2]

bool shouldWidenLoad ( const GCNSubtarget & ST,
LLT MemoryTy,
uint64_t AlignInBits,
unsigned AddrSpace,
unsigned Opcode )
static

Return true if we should legalize a load by widening an odd sized memory access up to the alignment.

Note this case when the memory access itself changes, not the size of the result register.

Definition at line 571 of file AMDGPULegalizerInfo.cpp.

References llvm::Fast, llvm::LLT::getSizeInBits(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, llvm::NextPowerOf2(), TLI, and uint64_t.

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().

◆ sizeIsMultipleOf32()

LegalityPredicate sizeIsMultipleOf32 ( unsigned TypeIdx)
static

Definition at line 81 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits().

◆ stripAnySourceMods()

Register stripAnySourceMods ( Register OrigSrc,
MachineRegisterInfo & MRI )
static

Definition at line 4426 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef(), and MRI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

◆ toggleSPDenormMode()

void toggleSPDenormMode ( bool Enable,
MachineIRBuilder & B,
const GCNSubtarget & ST,
SIModeRegisterDefaults Mode )
static

Definition at line 5788 of file AMDGPULegalizerInfo.cpp.

References B(), Enable, FP_DENORM_FLUSH_NONE, Mode, and SPDenormModeBitField.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32().

◆ valueIsKnownNeverF32Denorm()

bool valueIsKnownNeverF32Denorm ( const MachineRegisterInfo & MRI,
Register Src )
static

Return true if it's known that Src can never be an f32 denormal value.

Definition at line 3670 of file AMDGPULegalizerInfo.cpp.

References llvm::cast(), DefMI, F16, getIntrinsicID(), and MRI.

◆ vectorSmallerThan()

LegalityPredicate vectorSmallerThan ( unsigned TypeIdx,
unsigned Size )
static

Definition at line 209 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::Size.

◆ vectorWiderThan()

LegalityPredicate vectorWiderThan ( unsigned TypeIdx,
unsigned Size )
static

Definition at line 216 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::Size.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ verifyCFIntrinsic()

MachineInstr * verifyCFIntrinsic ( MachineInstr & MI,
MachineRegisterInfo & MRI,
MachineInstr *& Br,
MachineBasicBlock *& UncondBrTarget,
bool & Negated )
static

Definition at line 4912 of file AMDGPULegalizerInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::eraseInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), isNot(), MI, MRI, llvm::Next, and UseMI.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().

◆ widenToNextPowerOf2()

LLT widenToNextPowerOf2 ( LLT Ty)
static

Definition at line 3504 of file AMDGPULegalizerInfo.cpp.

References llvm::LLT::changeElementCount(), llvm::LLT::changeElementSize(), llvm::ElementCount::getFixed(), and llvm::PowerOf2Ceil().

Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().

Variable Documentation

◆ AllS16Vectors

std::initializer_list<LLT> AllS16Vectors
constexpr
Initial value:
{
V2S16, V4S16, V6S16, V8S16, V10S16, V12S16, V16S16, V2S128, V4S128}
V4S128
constexpr LLT V4S128
Definition AMDGPULegalizerInfo.cpp:346
V2S16
constexpr LLT V2S16
Definition AMDGPULegalizerInfo.cpp:314
V8S16
constexpr LLT V8S16
Definition AMDGPULegalizerInfo.cpp:317
V4S16
constexpr LLT V4S16
Definition AMDGPULegalizerInfo.cpp:315
V2S128
constexpr LLT V2S128
Definition AMDGPULegalizerInfo.cpp:345
V10S16
constexpr LLT V10S16
Definition AMDGPULegalizerInfo.cpp:318
V6S16
constexpr LLT V6S16
Definition AMDGPULegalizerInfo.cpp:316
V12S16
constexpr LLT V12S16
Definition AMDGPULegalizerInfo.cpp:319
V16S16
constexpr LLT V16S16
Definition AMDGPULegalizerInfo.cpp:320

Definition at line 351 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterClassType().

◆ AllS32Vectors

std::initializer_list<LLT> AllS32Vectors
constexpr
Initial value:
= {
V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
V9S32, V10S32, V11S32, V12S32, V16S32, V32S32}
V9S32
constexpr LLT V9S32
Definition AMDGPULegalizerInfo.cpp:329
V11S32
constexpr LLT V11S32
Definition AMDGPULegalizerInfo.cpp:331
V8S32
constexpr LLT V8S32
Definition AMDGPULegalizerInfo.cpp:328
V6S32
constexpr LLT V6S32
Definition AMDGPULegalizerInfo.cpp:326
V4S32
constexpr LLT V4S32
Definition AMDGPULegalizerInfo.cpp:324
V3S32
constexpr LLT V3S32
Definition AMDGPULegalizerInfo.cpp:323
V10S32
constexpr LLT V10S32
Definition AMDGPULegalizerInfo.cpp:330
V16S32
constexpr LLT V16S32
Definition AMDGPULegalizerInfo.cpp:333
V7S32
constexpr LLT V7S32
Definition AMDGPULegalizerInfo.cpp:327
V32S32
constexpr LLT V32S32
Definition AMDGPULegalizerInfo.cpp:334
V5S32
constexpr LLT V5S32
Definition AMDGPULegalizerInfo.cpp:325
V2S32
constexpr LLT V2S32
Definition AMDGPULegalizerInfo.cpp:322
V12S32
constexpr LLT V12S32
Definition AMDGPULegalizerInfo.cpp:332

Definition at line 354 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

◆ AllS64Vectors

std::initializer_list<LLT> AllS64Vectors
constexpr
Initial value:
= {
V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64, V16S64}
V7S64
constexpr LLT V7S64
Definition AMDGPULegalizerInfo.cpp:341
V6S64
constexpr LLT V6S64
Definition AMDGPULegalizerInfo.cpp:340
V2S64
constexpr LLT V2S64
Definition AMDGPULegalizerInfo.cpp:336
V4S64
constexpr LLT V4S64
Definition AMDGPULegalizerInfo.cpp:338
V16S64
constexpr LLT V16S64
Definition AMDGPULegalizerInfo.cpp:343
V5S64
constexpr LLT V5S64
Definition AMDGPULegalizerInfo.cpp:339
V3S64
constexpr LLT V3S64
Definition AMDGPULegalizerInfo.cpp:337
V8S64
constexpr LLT V8S64
Definition AMDGPULegalizerInfo.cpp:342

Definition at line 358 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().

◆ AllScalarTypes

std::initializer_list<LLT> AllScalarTypes
constexpr
Initial value:
= {
S32, S64, S96, S128, S160, S192, S224, S256, S512, S1024}
S1024
constexpr LLT S1024
Definition AMDGPULegalizerInfo.cpp:310
S224
constexpr LLT S224
Definition AMDGPULegalizerInfo.cpp:307
S512
constexpr LLT S512
Definition AMDGPULegalizerInfo.cpp:309
S32
constexpr LLT S32
Definition AMDGPULegalizerInfo.cpp:301
S192
constexpr LLT S192
Definition AMDGPULegalizerInfo.cpp:306
S160
constexpr LLT S160
Definition AMDGPULegalizerInfo.cpp:305
S256
constexpr LLT S256
Definition AMDGPULegalizerInfo.cpp:308
S96
constexpr LLT S96
Definition AMDGPULegalizerInfo.cpp:303
S64
constexpr LLT S64
Definition AMDGPULegalizerInfo.cpp:302
S128
constexpr LLT S128
Definition AMDGPULegalizerInfo.cpp:304

Definition at line 348 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterClassType().

◆ AllVectors

std::initializer_list<LLT> AllVectors
constexpr
Initial value:
{
V2S16, V4S16, V6S16, V8S16, V10S16, V12S16, V16S16, V2S128,
V4S128, V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
V9S32, V10S32, V11S32, V12S32, V16S32, V32S32, V2S64, V3S64,
V4S64, V5S64, V6S64, V7S64, V8S64, V16S64}

Definition at line 361 of file AMDGPULegalizerInfo.cpp.

◆ BF16

LLT BF16 = LLT::bfloat16()
constexpr

Definition at line 290 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ F16

LLT F16 = LLT::float16()
constexpr

Definition at line 289 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFFREXP(), llvm::AMDGPULegalizerInfo::legalizeFlog2(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPULegalizerInfo::legalizeFlogUnsafe(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPULegalizerInfo::legalizeFSQRT(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), packImage16bitOpsToDwords(), and valueIsKnownNeverF32Denorm().

◆ F32

LLT F32 = LLT::float32()
constexpr

Definition at line 291 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), buildExp(), emitReciprocalU64(), llvm::yaml::ScalarEnumerationTraits< WasmYAML::ValueType >::enumeration(), llvm::TargetLowering::expandFP_ROUND(), llvm::AMDGPULegalizerInfo::getScaledLogInput(), getTcgen05LdRedID(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFExp10Unsafe(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), llvm::AMDGPULegalizerInfo::legalizeFlog2(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPULegalizerInfo::legalizeFlogUnsafe(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPULegalizerInfo::legalizeFPow(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFSQRT(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF16(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF32(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), and llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl().

◆ F64

LLT F64 = LLT::float64()
constexpr

Definition at line 292 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), combineBitcast(), llvm::yaml::ScalarEnumerationTraits< WasmYAML::ValueType >::enumeration(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFEXPF64(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFSQRT(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), and PerformExtractEltToVMOVRRD().

◆ FPEnvModeBitField

unsigned FPEnvModeBitField
staticconstexpr
Initial value:
=
AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 0, 23)
llvm::AMDGPU::EncodingFields< HwregId, HwregOffset, HwregSize >::encode
static constexpr uint64_t encode(Fields... Values)
Definition AMDGPUBaseInfo.h:338

Definition at line 8307 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().

◆ FPEnvTrapBitField

unsigned FPEnvTrapBitField
staticconstexpr
Initial value:
=
AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_TRAPSTS, 0, 5)

Definition at line 8310 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().

◆ MaxRegisterSize

unsigned MaxRegisterSize = 1024
staticconstexpr

Definition at line 48 of file AMDGPULegalizerInfo.cpp.

Referenced by isRegisterSize(), and moreElementsToNextExistingRegClass().

◆ MaxScalar

LLT MaxScalar = LLT::scalar(MaxRegisterSize)
constexpr

Definition at line 311 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ S1

LLT S1 = LLT::scalar(1)
constexpr

Definition at line 298 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::BinaryOperator::BinaryOperator(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::BinaryOperator::Create(), llvm::CmpInst::Create(), llvm::SelectInst::Create(), llvm::sandboxir::CmpInst::create(), CreateAdd(), CreateMul(), CreateNeg(), llvm::CmpInst::CreateWithCopiedFlags(), llvm::sandboxir::CmpInst::createWithCopiedFlags(), llvm::BinaryOperator::DECLARE_TRANSPARENT_OPERAND_ACCESSORS(), llvm::PMDataManager::dumpPassInfo(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), foldShuffleOfUnaryOps(), getAnySgprS1(), getNearestMatchingScope(), getPRMTSelector(), llvm::SelectionDAG::getStrcmp(), llvm::SelectionDAG::getStrstr(), gsiRecordCmp(), llvm::ScalarEvolution::haveSameSign(), INITIALIZE_PASS(), llvm::isEqual(), llvm::Mips::isGpOff(), isMemOPCandidate(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFEXPF64(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFPow(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), matchBinaryPermuteShuffle(), matchUniformityAndLLT(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performVectorExtCombine(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), runImpl(), llvm::set_difference(), llvm::set_intersect(), llvm::set_intersection(), llvm::set_intersection_impl(), llvm::set_intersects(), llvm::detail::set_intersects_impl(), llvm::set_is_subset(), llvm::set_subtract(), llvm::set_subtract(), llvm::set_union(), simplifyLoopInst(), llvm::GISelCSEInfo::verify(), and visitORCommutative().

◆ S1024

LLT S1024 = LLT::scalar(1024)
constexpr

Definition at line 310 of file AMDGPULegalizerInfo.cpp.

◆ S128

LLT S128 = LLT::scalar(128)
constexpr

Definition at line 304 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and matchUniformityAndLLT().

◆ S16

LLT S16 = LLT::scalar(16)
constexpr

Definition at line 300 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), isRegisterClassType(), LLTToId(), matchUniformityAndLLT(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ S160

LLT S160 = LLT::scalar(160)
constexpr

Definition at line 305 of file AMDGPULegalizerInfo.cpp.

◆ S192

LLT S192 = LLT::scalar(192)
constexpr

Definition at line 306 of file AMDGPULegalizerInfo.cpp.

◆ S224

LLT S224 = LLT::scalar(224)
constexpr

Definition at line 307 of file AMDGPULegalizerInfo.cpp.

◆ S256

LLT S256 = LLT::scalar(256)
constexpr

Definition at line 308 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ S32

LLT S32 = LLT::scalar(32)
constexpr

Definition at line 301 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPURegisterBankInfo::handleD16VData(), LLTToId(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), llvm::LegalizerHelper::lowerU64ToF64BitFloatOps(), matchUniformityAndLLT(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), reinsertVectorIndexAdd(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), and unpackV2S16ToS32().

◆ S512

LLT S512 = LLT::scalar(512)
constexpr

Definition at line 309 of file AMDGPULegalizerInfo.cpp.

◆ S64

LLT S64 = LLT::scalar(64)
constexpr

Definition at line 302 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), LLTToId(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerU64ToF32WithSITOFP(), llvm::LegalizerHelper::lowerU64ToF64BitFloatOps(), matchUniformityAndLLT(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ S8

LLT S8 = LLT::scalar(8)
constexpr

Definition at line 299 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ S96

LLT S96 = LLT::scalar(96)
constexpr

Definition at line 303 of file AMDGPULegalizerInfo.cpp.

◆ SPDenormModeBitField

unsigned SPDenormModeBitField
staticconstexpr
Initial value:
=
AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 4, 2)

Definition at line 5783 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32(), and toggleSPDenormMode().

◆ V10S16

LLT V10S16 = LLT::fixed_vector(10, 16)
constexpr

Definition at line 318 of file AMDGPULegalizerInfo.cpp.

◆ V10S32

LLT V10S32 = LLT::fixed_vector(10, 32)
constexpr

Definition at line 330 of file AMDGPULegalizerInfo.cpp.

◆ V11S32

LLT V11S32 = LLT::fixed_vector(11, 32)
constexpr

Definition at line 331 of file AMDGPULegalizerInfo.cpp.

◆ V12S16

LLT V12S16 = LLT::fixed_vector(12, 16)
constexpr

Definition at line 319 of file AMDGPULegalizerInfo.cpp.

◆ V12S32

LLT V12S32 = LLT::fixed_vector(12, 32)
constexpr

Definition at line 332 of file AMDGPULegalizerInfo.cpp.

◆ V16S16

LLT V16S16 = LLT::fixed_vector(16, 16)
constexpr

Definition at line 320 of file AMDGPULegalizerInfo.cpp.

◆ V16S32

LLT V16S32 = LLT::fixed_vector(16, 32)
constexpr

Definition at line 333 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ V16S64

LLT V16S64 = LLT::fixed_vector(16, 64)
constexpr

Definition at line 343 of file AMDGPULegalizerInfo.cpp.

◆ V2BF16

LLT V2BF16 = LLT::fixed_vector(2, BF16)
constexpr

Definition at line 294 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ V2F16

LLT V2F16 = LLT::fixed_vector(2, F16)
constexpr

Definition at line 293 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), and packImage16bitOpsToDwords().

◆ V2F32

LLT V2F32 = LLT::fixed_vector(2, F32)
constexpr

Definition at line 295 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and convertToIRType().

◆ V2F64

LLT V2F64 = LLT::fixed_vector(2, F64)
constexpr

Definition at line 296 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and convertToIRType().

◆ V2S128

LLT V2S128 = LLT::fixed_vector(2, 128)
constexpr

Definition at line 345 of file AMDGPULegalizerInfo.cpp.

◆ V2S16

LLT V2S16 = LLT::fixed_vector(2, 16)
constexpr

Definition at line 314 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), LLTToId(), and matchUniformityAndLLT().

◆ V2S32

LLT V2S32 = LLT::fixed_vector(2, 32)
constexpr

Definition at line 322 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), LLTToId(), and matchUniformityAndLLT().

◆ V2S64

LLT V2S64 = LLT::fixed_vector(2, 64)
constexpr

Definition at line 336 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ V2S8

LLT V2S8 = LLT::fixed_vector(2, 8)
constexpr

Definition at line 313 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ V32S32

LLT V32S32 = LLT::fixed_vector(32, 32)
constexpr

Definition at line 334 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ V3S32

LLT V3S32 = LLT::fixed_vector(3, 32)
constexpr

Definition at line 323 of file AMDGPULegalizerInfo.cpp.

Referenced by LLTToId(), and matchUniformityAndLLT().

◆ V3S64

LLT V3S64 = LLT::fixed_vector(3, 64)
constexpr

Definition at line 337 of file AMDGPULegalizerInfo.cpp.

◆ V4S128

LLT V4S128 = LLT::fixed_vector(4, 128)
constexpr

Definition at line 346 of file AMDGPULegalizerInfo.cpp.

◆ V4S16

LLT V4S16 = LLT::fixed_vector(4, 16)
constexpr

Definition at line 315 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().

◆ V4S32

LLT V4S32 = LLT::fixed_vector(4, 32)
constexpr

Definition at line 324 of file AMDGPULegalizerInfo.cpp.

Referenced by LLTToId(), matchUniformityAndLLT(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ V4S64

LLT V4S64 = LLT::fixed_vector(4, 64)
constexpr

Definition at line 338 of file AMDGPULegalizerInfo.cpp.

◆ V5S32

LLT V5S32 = LLT::fixed_vector(5, 32)
constexpr

Definition at line 325 of file AMDGPULegalizerInfo.cpp.

◆ V5S64

LLT V5S64 = LLT::fixed_vector(5, 64)
constexpr

Definition at line 339 of file AMDGPULegalizerInfo.cpp.

◆ V6S16

LLT V6S16 = LLT::fixed_vector(6, 16)
constexpr

Definition at line 316 of file AMDGPULegalizerInfo.cpp.

◆ V6S32

LLT V6S32 = LLT::fixed_vector(6, 32)
constexpr

Definition at line 326 of file AMDGPULegalizerInfo.cpp.

◆ V6S64

LLT V6S64 = LLT::fixed_vector(6, 64)
constexpr

Definition at line 340 of file AMDGPULegalizerInfo.cpp.

◆ V7S32

LLT V7S32 = LLT::fixed_vector(7, 32)
constexpr

Definition at line 327 of file AMDGPULegalizerInfo.cpp.

◆ V7S64

LLT V7S64 = LLT::fixed_vector(7, 64)
constexpr

Definition at line 341 of file AMDGPULegalizerInfo.cpp.

◆ V8S16

LLT V8S16 = LLT::fixed_vector(8, 16)
constexpr

Definition at line 317 of file AMDGPULegalizerInfo.cpp.

Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().

◆ V8S32

LLT V8S32 = LLT::fixed_vector(8, 32)
constexpr

Definition at line 328 of file AMDGPULegalizerInfo.cpp.

◆ V8S64

LLT V8S64 = LLT::fixed_vector(8, 64)
constexpr

Definition at line 342 of file AMDGPULegalizerInfo.cpp.

◆ V9S32

LLT V9S32 = LLT::fixed_vector(9, 32)
constexpr

Definition at line 329 of file AMDGPULegalizerInfo.cpp.

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