LLVM  15.0.0git
CSEMIRBuilder.cpp
Go to the documentation of this file.
1 //===-- llvm/CodeGen/GlobalISel/CSEMIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the CSEMIRBuilder class which CSEs as it builds
10 /// instructions.
11 //===----------------------------------------------------------------------===//
12 //
13 
20 
21 using namespace llvm;
22 
23 bool CSEMIRBuilder::dominates(MachineBasicBlock::const_iterator A,
25  auto MBBEnd = getMBB().end();
26  if (B == MBBEnd)
27  return true;
28  assert(A->getParent() == B->getParent() &&
29  "Iterators should be in same block");
30  const MachineBasicBlock *BBA = A->getParent();
32  for (; &*I != A && &*I != B; ++I)
33  ;
34  return &*I == A;
35 }
36 
38 CSEMIRBuilder::getDominatingInstrForID(FoldingSetNodeID &ID,
39  void *&NodeInsertPos) {
40  GISelCSEInfo *CSEInfo = getCSEInfo();
41  assert(CSEInfo && "Can't get here without setting CSEInfo");
42  MachineBasicBlock *CurMBB = &getMBB();
43  MachineInstr *MI =
44  CSEInfo->getMachineInstrIfExists(ID, CurMBB, NodeInsertPos);
45  if (MI) {
46  CSEInfo->countOpcodeHit(MI->getOpcode());
47  auto CurrPos = getInsertPt();
48  auto MII = MachineBasicBlock::iterator(MI);
49  if (MII == CurrPos) {
50  // Move the insert point ahead of the instruction so any future uses of
51  // this builder will have the def ready.
52  setInsertPt(*CurMBB, std::next(MII));
53  } else if (!dominates(MI, CurrPos)) {
54  CurMBB->splice(CurrPos, CurMBB, MI);
55  }
56  return MachineInstrBuilder(getMF(), MI);
57  }
58  return MachineInstrBuilder();
59 }
60 
61 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const {
62  const GISelCSEInfo *CSEInfo = getCSEInfo();
63  if (!CSEInfo || !CSEInfo->shouldCSE(Opc))
64  return false;
65  return true;
66 }
67 
68 void CSEMIRBuilder::profileDstOp(const DstOp &Op,
69  GISelInstProfileBuilder &B) const {
70  switch (Op.getDstOpKind()) {
72  B.addNodeIDRegType(Op.getRegClass());
73  break;
75  // Regs can have LLT&(RB|RC). If those exist, profile them as well.
76  B.addNodeIDReg(Op.getReg());
77  break;
78  }
79  default:
80  B.addNodeIDRegType(Op.getLLTTy(*getMRI()));
81  break;
82  }
83 }
84 
85 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op,
86  GISelInstProfileBuilder &B) const {
87  switch (Op.getSrcOpKind()) {
89  B.addNodeIDImmediate(static_cast<int64_t>(Op.getImm()));
90  break;
92  B.addNodeIDImmediate(static_cast<int64_t>(Op.getPredicate()));
93  break;
94  default:
95  B.addNodeIDRegType(Op.getReg());
96  break;
97  }
98 }
99 
100 void CSEMIRBuilder::profileMBBOpcode(GISelInstProfileBuilder &B,
101  unsigned Opc) const {
102  // First add the MBB (Local CSE).
103  B.addNodeIDMBB(&getMBB());
104  // Then add the opcode.
105  B.addNodeIDOpcode(Opc);
106 }
107 
108 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
109  ArrayRef<SrcOp> SrcOps,
110  Optional<unsigned> Flags,
111  GISelInstProfileBuilder &B) const {
112 
113  profileMBBOpcode(B, Opc);
114  // Then add the DstOps.
115  profileDstOps(DstOps, B);
116  // Then add the SrcOps.
117  profileSrcOps(SrcOps, B);
118  // Add Flags if passed in.
119  if (Flags)
120  B.addNodeIDFlag(*Flags);
121 }
122 
123 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB,
124  void *NodeInsertPos) {
125  assert(canPerformCSEForOpc(MIB->getOpcode()) &&
126  "Attempting to CSE illegal op");
127  MachineInstr *MIBInstr = MIB;
128  getCSEInfo()->insertInstr(MIBInstr, NodeInsertPos);
129  return MIB;
130 }
131 
132 bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) {
133  if (DstOps.size() == 1)
134  return true; // always possible to emit copy to just 1 vreg.
135 
136  return llvm::all_of(DstOps, [](const DstOp &Op) {
137  DstOp::DstType DT = Op.getDstOpKind();
138  return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC;
139  });
140 }
141 
143 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
144  MachineInstrBuilder &MIB) {
145  assert(checkCopyToDefsPossible(DstOps) &&
146  "Impossible return a single MIB with copies to multiple defs");
147  if (DstOps.size() == 1) {
148  const DstOp &Op = DstOps[0];
149  if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg)
150  return buildCopy(Op.getReg(), MIB.getReg(0));
151  }
152 
153  // If we didn't generate a copy then we're re-using an existing node directly
154  // instead of emitting any code. Merge the debug location we wanted to emit
155  // into the instruction we're CSE'ing with. Debug locations arent part of the
156  // profile so we don't need to recompute it.
157  if (getDebugLoc()) {
158  GISelChangeObserver *Observer = getState().Observer;
159  if (Observer)
160  Observer->changingInstr(*MIB);
161  MIB->setDebugLoc(
163  if (Observer)
164  Observer->changedInstr(*MIB);
165  }
166 
167  return MIB;
168 }
169 
171  ArrayRef<DstOp> DstOps,
172  ArrayRef<SrcOp> SrcOps,
174  switch (Opc) {
175  default:
176  break;
177  case TargetOpcode::G_ADD:
178  case TargetOpcode::G_PTR_ADD:
179  case TargetOpcode::G_AND:
180  case TargetOpcode::G_ASHR:
181  case TargetOpcode::G_LSHR:
182  case TargetOpcode::G_MUL:
183  case TargetOpcode::G_OR:
184  case TargetOpcode::G_SHL:
185  case TargetOpcode::G_SUB:
186  case TargetOpcode::G_XOR:
187  case TargetOpcode::G_UDIV:
188  case TargetOpcode::G_SDIV:
189  case TargetOpcode::G_UREM:
190  case TargetOpcode::G_SREM:
191  case TargetOpcode::G_SMIN:
192  case TargetOpcode::G_SMAX:
193  case TargetOpcode::G_UMIN:
194  case TargetOpcode::G_UMAX: {
195  // Try to constant fold these.
196  assert(SrcOps.size() == 2 && "Invalid sources");
197  assert(DstOps.size() == 1 && "Invalid dsts");
198  LLT SrcTy = SrcOps[0].getLLTTy(*getMRI());
199 
200  if (Opc == TargetOpcode::G_PTR_ADD &&
201  getDataLayout().isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
202  break;
203 
204  if (SrcTy.isVector()) {
205  // Try to constant fold vector constants.
207  Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI());
208  if (!VecCst.empty())
209  return buildBuildVectorConstant(DstOps[0], VecCst);
210  break;
211  }
212 
213  if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(),
214  SrcOps[1].getReg(), *getMRI()))
215  return buildConstant(DstOps[0], *Cst);
216  break;
217  }
218  case TargetOpcode::G_FADD:
219  case TargetOpcode::G_FSUB:
220  case TargetOpcode::G_FMUL:
221  case TargetOpcode::G_FDIV:
222  case TargetOpcode::G_FREM:
223  case TargetOpcode::G_FMINNUM:
224  case TargetOpcode::G_FMAXNUM:
225  case TargetOpcode::G_FMINNUM_IEEE:
226  case TargetOpcode::G_FMAXNUM_IEEE:
227  case TargetOpcode::G_FMINIMUM:
228  case TargetOpcode::G_FMAXIMUM:
229  case TargetOpcode::G_FCOPYSIGN: {
230  // Try to constant fold these.
231  assert(SrcOps.size() == 2 && "Invalid sources");
232  assert(DstOps.size() == 1 && "Invalid dsts");
234  Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()))
235  return buildFConstant(DstOps[0], *Cst);
236  break;
237  }
238  case TargetOpcode::G_SEXT_INREG: {
239  assert(DstOps.size() == 1 && "Invalid dst ops");
240  assert(SrcOps.size() == 2 && "Invalid src ops");
241  const DstOp &Dst = DstOps[0];
242  const SrcOp &Src0 = SrcOps[0];
243  const SrcOp &Src1 = SrcOps[1];
244  if (auto MaybeCst =
245  ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
246  return buildConstant(Dst, *MaybeCst);
247  break;
248  }
249  case TargetOpcode::G_SITOFP:
250  case TargetOpcode::G_UITOFP: {
251  // Try to constant fold these.
252  assert(SrcOps.size() == 1 && "Invalid sources");
253  assert(DstOps.size() == 1 && "Invalid dsts");
255  Opc, DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getReg(), *getMRI()))
256  return buildFConstant(DstOps[0], *Cst);
257  break;
258  }
259  case TargetOpcode::G_CTLZ: {
260  assert(SrcOps.size() == 1 && "Expected one source");
261  assert(DstOps.size() == 1 && "Expected one dest");
262  auto MaybeCsts = ConstantFoldCTLZ(SrcOps[0].getReg(), *getMRI());
263  if (!MaybeCsts)
264  break;
265  if (MaybeCsts->size() == 1)
266  return buildConstant(DstOps[0], (*MaybeCsts)[0]);
267  // This was a vector constant. Build a G_BUILD_VECTOR for them.
268  SmallVector<Register> ConstantRegs;
269  LLT VecTy = DstOps[0].getLLTTy(*getMRI());
270  for (unsigned Cst : *MaybeCsts)
271  ConstantRegs.emplace_back(
272  buildConstant(VecTy.getScalarType(), Cst).getReg(0));
273  return buildBuildVector(DstOps[0], ConstantRegs);
274  }
275  }
276  bool CanCopy = checkCopyToDefsPossible(DstOps);
277  if (!canPerformCSEForOpc(Opc))
278  return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
279  // If we can CSE this instruction, but involves generating copies to multiple
280  // regs, give up. This frequently happens to UNMERGEs.
281  if (!CanCopy) {
282  auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
283  // CSEInfo would have tracked this instruction. Remove it from the temporary
284  // insts.
285  getCSEInfo()->handleRemoveInst(&*MIB);
286  return MIB;
287  }
289  GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
290  void *InsertPos = nullptr;
291  profileEverything(Opc, DstOps, SrcOps, Flag, ProfBuilder);
292  MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
293  if (MIB) {
294  // Handle generating copies here.
295  return generateCopiesIfRequired(DstOps, MIB);
296  }
297  // This instruction does not exist in the CSEInfo. Build it and CSE it.
298  MachineInstrBuilder NewMIB =
299  MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
300  return memoizeMI(NewMIB, InsertPos);
301 }
302 
304  const ConstantInt &Val) {
305  constexpr unsigned Opc = TargetOpcode::G_CONSTANT;
306  if (!canPerformCSEForOpc(Opc))
307  return MachineIRBuilder::buildConstant(Res, Val);
308 
309  // For vectors, CSE the element only for now.
310  LLT Ty = Res.getLLTTy(*getMRI());
311  if (Ty.isVector())
312  return buildSplatVector(Res, buildConstant(Ty.getElementType(), Val));
313 
315  GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
316  void *InsertPos = nullptr;
317  profileMBBOpcode(ProfBuilder, Opc);
318  profileDstOp(Res, ProfBuilder);
320  MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
321  if (MIB) {
322  // Handle generating copies here.
323  return generateCopiesIfRequired({Res}, MIB);
324  }
325 
327  return memoizeMI(NewMIB, InsertPos);
328 }
329 
331  const ConstantFP &Val) {
332  constexpr unsigned Opc = TargetOpcode::G_FCONSTANT;
333  if (!canPerformCSEForOpc(Opc))
334  return MachineIRBuilder::buildFConstant(Res, Val);
335 
336  // For vectors, CSE the element only for now.
337  LLT Ty = Res.getLLTTy(*getMRI());
338  if (Ty.isVector())
339  return buildSplatVector(Res, buildFConstant(Ty.getElementType(), Val));
340 
342  GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
343  void *InsertPos = nullptr;
344  profileMBBOpcode(ProfBuilder, Opc);
345  profileDstOp(Res, ProfBuilder);
347  MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
348  if (MIB) {
349  // Handle generating copies here.
350  return generateCopiesIfRequired({Res}, MIB);
351  }
353  return memoizeMI(NewMIB, InsertPos);
354 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::DstOp::DstType::Ty_LLT
@ Ty_LLT
llvm::GISelCSEInfo::handleRemoveInst
void handleRemoveInst(MachineInstr *MI)
Remove this inst from the CSE map.
Definition: CSEInfo.cpp:207
llvm::DILocation::getMergedLocation
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
Definition: DebugInfoMetadata.cpp:101
DebugInfoMetadata.h
llvm::MachineIRBuilder::getCSEInfo
GISelCSEInfo * getCSEInfo()
Definition: MachineIRBuilder.h:304
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:678
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:287
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::GISelInstProfileBuilder::addNodeIDMachineOperand
const GISelInstProfileBuilder & addNodeIDMachineOperand(const MachineOperand &MO) const
Definition: CSEInfo.cpp:399
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:167
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:557
llvm::GISelCSEInfo::shouldCSE
bool shouldCSE(unsigned Opc) const
Definition: CSEInfo.cpp:222
llvm::Optional< unsigned >
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:658
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::getDebugLoc
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:365
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:283
CSEInfo.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1605
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::DstOp::DstType::Ty_RC
@ Ty_RC
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
Utils.h
CSEMIRBuilder.h
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:279
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:746
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:763
llvm::GISelChangeObserver::changingInstr
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
llvm::CSEMIRBuilder::buildFConstant
MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val) override
Build and insert Res = G_FCONSTANT Val.
Definition: CSEMIRBuilder.cpp:330
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::CSEMIRBuilder::buildConstant
MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val) override
Build and insert Res = G_CONSTANT Val.
Definition: CSEMIRBuilder.cpp:303
llvm::SrcOp::getImm
int64_t getImm() const
Definition: MachineIRBuilder.h:200
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::GISelChangeObserver::changedInstr
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:312
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:313
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:308
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:294
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:60
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:178
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:278
llvm::GISelCSEInfo::countOpcodeHit
void countOpcodeHit(unsigned Opc)
Definition: CSEInfo.cpp:168
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:317
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:788
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::DstOp::DstType
DstType
Definition: MachineIRBuilder.h:73
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:777
llvm::SrcOp::SrcType::Ty_Imm
@ Ty_Imm
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::GISelInstProfileBuilder
Definition: CSEInfo.h:167
llvm::MachineIRBuilder::buildBuildVectorConstant
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:668
llvm::MachineInstr::setDebugLoc
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
Definition: MachineInstr.h:1724
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:94
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::DstOp::DstType::Ty_Reg
@ Ty_Reg
llvm::DstOp
Definition: MachineIRBuilder.h:65
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::ConstantFoldVectorBinop
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:612
llvm::MachineIRBuilder::getState
MachineIRBuilderState & getState()
Getter for the State.
Definition: MachineIRBuilder.h:291
GISelChangeObserver.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::CSEMIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, Optional< unsigned > Flag=None) override
Definition: CSEMIRBuilder.cpp:170
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:794
llvm::SrcOp
Definition: MachineIRBuilder.h:126
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:927
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:493
llvm::LLT
Definition: LowLevelTypeImpl.h:39