LLVM  16.0.0git
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
21 
22 using namespace llvm;
23 
25  State.MF = &MF;
26  State.MBB = nullptr;
27  State.MRI = &MF.getRegInfo();
28  State.TII = MF.getSubtarget().getInstrInfo();
29  State.DL = DebugLoc();
30  State.PCSections = nullptr;
32  State.Observer = nullptr;
33 }
34 
35 //------------------------------------------------------------------------------
36 // Build instruction variants.
37 //------------------------------------------------------------------------------
38 
40  return BuildMI(getMF(), {getDL(), getPCSections()}, getTII().get(Opcode));
41 }
42 
44  getMBB().insert(getInsertPt(), MIB);
45  recordInsertion(MIB);
46  return MIB;
47 }
48 
51  const MDNode *Expr) {
52  assert(isa<DILocalVariable>(Variable) && "not a variable");
53  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
54  assert(
55  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
56  "Expected inlined-at fields to agree");
57  return insertInstr(BuildMI(getMF(), getDL(),
58  getTII().get(TargetOpcode::DBG_VALUE),
59  /*IsIndirect*/ false, Reg, Variable, Expr));
60 }
61 
64  const MDNode *Expr) {
65  assert(isa<DILocalVariable>(Variable) && "not a variable");
66  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
67  assert(
68  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
69  "Expected inlined-at fields to agree");
70  return insertInstr(BuildMI(getMF(), getDL(),
71  getTII().get(TargetOpcode::DBG_VALUE),
72  /*IsIndirect*/ true, Reg, Variable, Expr));
73 }
74 
76  const MDNode *Variable,
77  const MDNode *Expr) {
78  assert(isa<DILocalVariable>(Variable) && "not a variable");
79  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
80  assert(
81  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
82  "Expected inlined-at fields to agree");
83  return buildInstr(TargetOpcode::DBG_VALUE)
84  .addFrameIndex(FI)
85  .addImm(0)
86  .addMetadata(Variable)
87  .addMetadata(Expr);
88 }
89 
91  const MDNode *Variable,
92  const MDNode *Expr) {
93  assert(isa<DILocalVariable>(Variable) && "not a variable");
94  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
95  assert(
96  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
97  "Expected inlined-at fields to agree");
98  auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
99 
100  auto *NumericConstant = [&] () -> const Constant* {
101  if (const auto *CE = dyn_cast<ConstantExpr>(&C))
102  if (CE->getOpcode() == Instruction::IntToPtr)
103  return CE->getOperand(0);
104  return &C;
105  }();
106 
107  if (auto *CI = dyn_cast<ConstantInt>(NumericConstant)) {
108  if (CI->getBitWidth() > 64)
109  MIB.addCImm(CI);
110  else
111  MIB.addImm(CI->getZExtValue());
112  } else if (auto *CFP = dyn_cast<ConstantFP>(NumericConstant)) {
113  MIB.addFPImm(CFP);
114  } else if (isa<ConstantPointerNull>(NumericConstant)) {
115  MIB.addImm(0);
116  } else {
117  // Insert $noreg if we didn't find a usable constant and had to drop it.
118  MIB.addReg(Register());
119  }
120 
121  MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
122  return insertInstr(MIB);
123 }
124 
126  assert(isa<DILabel>(Label) && "not a label");
127  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
128  "Expected inlined-at fields to agree");
129  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
130 
131  return MIB.addMetadata(Label);
132 }
133 
135  const SrcOp &Size,
136  Align Alignment) {
137  assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
138  auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
139  Res.addDefToMIB(*getMRI(), MIB);
140  Size.addSrcToMIB(MIB);
141  MIB.addImm(Alignment.value());
142  return MIB;
143 }
144 
146  int Idx) {
147  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
148  auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
149  Res.addDefToMIB(*getMRI(), MIB);
150  MIB.addFrameIndex(Idx);
151  return MIB;
152 }
153 
155  const GlobalValue *GV) {
156  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
158  GV->getType()->getAddressSpace() &&
159  "address space mismatch");
160 
161  auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
162  Res.addDefToMIB(*getMRI(), MIB);
163  MIB.addGlobalAddress(GV);
164  return MIB;
165 }
166 
168  unsigned JTI) {
169  return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
170  .addJumpTableIndex(JTI);
171 }
172 
173 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
174  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
175  assert((Res == Op0) && "type mismatch");
176 }
177 
178 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
179  const LLT Op1) {
180  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
181  assert((Res == Op0 && Res == Op1) && "type mismatch");
182 }
183 
184 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
185  const LLT Op1) {
186  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
187  assert((Res == Op0) && "type mismatch");
188 }
189 
191  const SrcOp &Op0,
192  const SrcOp &Op1) {
193  assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
194  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
195  assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
196 
197  return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
198 }
199 
202  const LLT ValueTy, uint64_t Value) {
203  assert(Res == 0 && "Res is a result argument");
204  assert(ValueTy.isScalar() && "invalid offset type");
205 
206  if (Value == 0) {
207  Res = Op0;
208  return None;
209  }
210 
212  auto Cst = buildConstant(ValueTy, Value);
213  return buildPtrAdd(Res, Op0, Cst.getReg(0));
214 }
215 
217  const SrcOp &Op0,
218  uint32_t NumBits) {
219  LLT PtrTy = Res.getLLTTy(*getMRI());
220  LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
221  Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
222  buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
223  return buildPtrMask(Res, Op0, MaskReg);
224 }
225 
228  const SrcOp &Op0) {
229  LLT ResTy = Res.getLLTTy(*getMRI());
230  LLT Op0Ty = Op0.getLLTTy(*getMRI());
231 
232  assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
233  assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
234  "Different vector element types");
235  assert((ResTy.getNumElements() > Op0Ty.getNumElements()) &&
236  "Op0 has more elements");
237 
238  auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
240  for (auto Op : Unmerge.getInstr()->defs())
241  Regs.push_back(Op.getReg());
243  unsigned NumberOfPadElts = ResTy.getNumElements() - Regs.size();
244  for (unsigned i = 0; i < NumberOfPadElts; ++i)
245  Regs.push_back(Undef);
246  return buildMerge(Res, Regs);
247 }
248 
251  const SrcOp &Op0) {
252  LLT ResTy = Res.getLLTTy(*getMRI());
253  LLT Op0Ty = Op0.getLLTTy(*getMRI());
254 
255  assert((ResTy.isVector() && Op0Ty.isVector()) && "Non vector type");
256  assert((ResTy.getElementType() == Op0Ty.getElementType()) &&
257  "Different vector element types");
258  assert((ResTy.getNumElements() < Op0Ty.getNumElements()) &&
259  "Op0 has fewer elements");
260 
262  auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
263  for (unsigned i = 0; i < ResTy.getNumElements(); ++i)
264  Regs.push_back(Unmerge.getReg(i));
265  return buildMerge(Res, Regs);
266 }
267 
269  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
270 }
271 
273  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
274  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
275 }
276 
278  unsigned JTI,
279  Register IndexReg) {
280  assert(getMRI()->getType(TablePtr).isPointer() &&
281  "Table reg must be a pointer");
282  return buildInstr(TargetOpcode::G_BRJT)
283  .addUse(TablePtr)
284  .addJumpTableIndex(JTI)
285  .addUse(IndexReg);
286 }
287 
289  const SrcOp &Op) {
290  return buildInstr(TargetOpcode::COPY, Res, Op);
291 }
292 
294  const ConstantInt &Val) {
295  LLT Ty = Res.getLLTTy(*getMRI());
296  LLT EltTy = Ty.getScalarType();
297  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
298  "creating constant with the wrong size");
299 
300  if (Ty.isVector()) {
301  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
302  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
303  .addCImm(&Val);
304  return buildSplatVector(Res, Const);
305  }
306 
307  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
308  Const->setDebugLoc(DebugLoc());
309  Res.addDefToMIB(*getMRI(), Const);
310  Const.addCImm(&Val);
311  return Const;
312 }
313 
315  int64_t Val) {
316  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
318  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
319  return buildConstant(Res, *CI);
320 }
321 
323  const ConstantFP &Val) {
324  LLT Ty = Res.getLLTTy(*getMRI());
325  LLT EltTy = Ty.getScalarType();
326 
328  == EltTy.getSizeInBits() &&
329  "creating fconstant with the wrong size");
330 
331  assert(!Ty.isPointer() && "invalid operand type");
332 
333  if (Ty.isVector()) {
334  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
335  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
336  .addFPImm(&Val);
337 
338  return buildSplatVector(Res, Const);
339  }
340 
341  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
342  Const->setDebugLoc(DebugLoc());
343  Res.addDefToMIB(*getMRI(), Const);
344  Const.addFPImm(&Val);
345  return Const;
346 }
347 
349  const APInt &Val) {
350  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
351  return buildConstant(Res, *CI);
352 }
353 
355  double Val) {
356  LLT DstTy = Res.getLLTTy(*getMRI());
357  auto &Ctx = getMF().getFunction().getContext();
358  auto *CFP =
360  return buildFConstant(Res, *CFP);
361 }
362 
364  const APFloat &Val) {
365  auto &Ctx = getMF().getFunction().getContext();
366  auto *CFP = ConstantFP::get(Ctx, Val);
367  return buildFConstant(Res, *CFP);
368 }
369 
371  MachineBasicBlock &Dest) {
372  assert(Tst.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
373 
374  auto MIB = buildInstr(TargetOpcode::G_BRCOND);
375  Tst.addSrcToMIB(MIB);
376  MIB.addMBB(&Dest);
377  return MIB;
378 }
379 
382  MachinePointerInfo PtrInfo, Align Alignment,
383  MachineMemOperand::Flags MMOFlags,
384  const AAMDNodes &AAInfo) {
385  MMOFlags |= MachineMemOperand::MOLoad;
386  assert((MMOFlags & MachineMemOperand::MOStore) == 0);
387 
388  LLT Ty = Dst.getLLTTy(*getMRI());
389  MachineMemOperand *MMO =
390  getMF().getMachineMemOperand(PtrInfo, MMOFlags, Ty, Alignment, AAInfo);
391  return buildLoad(Dst, Addr, *MMO);
392 }
393 
395  const DstOp &Res,
396  const SrcOp &Addr,
397  MachineMemOperand &MMO) {
398  assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
399  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
400 
401  auto MIB = buildInstr(Opcode);
402  Res.addDefToMIB(*getMRI(), MIB);
403  Addr.addSrcToMIB(MIB);
404  MIB.addMemOperand(&MMO);
405  return MIB;
406 }
407 
409  const DstOp &Dst, const SrcOp &BasePtr,
410  MachineMemOperand &BaseMMO, int64_t Offset) {
411  LLT LoadTy = Dst.getLLTTy(*getMRI());
412  MachineMemOperand *OffsetMMO =
413  getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy);
414 
415  if (Offset == 0) // This may be a size or type changing load.
416  return buildLoad(Dst, BasePtr, *OffsetMMO);
417 
418  LLT PtrTy = BasePtr.getLLTTy(*getMRI());
419  LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
420  auto ConstOffset = buildConstant(OffsetTy, Offset);
421  auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
422  return buildLoad(Dst, Ptr, *OffsetMMO);
423 }
424 
426  const SrcOp &Addr,
427  MachineMemOperand &MMO) {
428  assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
429  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
430 
431  auto MIB = buildInstr(TargetOpcode::G_STORE);
432  Val.addSrcToMIB(MIB);
433  Addr.addSrcToMIB(MIB);
434  MIB.addMemOperand(&MMO);
435  return MIB;
436 }
437 
440  MachinePointerInfo PtrInfo, Align Alignment,
441  MachineMemOperand::Flags MMOFlags,
442  const AAMDNodes &AAInfo) {
443  MMOFlags |= MachineMemOperand::MOStore;
444  assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
445 
446  LLT Ty = Val.getLLTTy(*getMRI());
447  MachineMemOperand *MMO =
448  getMF().getMachineMemOperand(PtrInfo, MMOFlags, Ty, Alignment, AAInfo);
449  return buildStore(Val, Addr, *MMO);
450 }
451 
453  const SrcOp &Op) {
454  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
455 }
456 
458  const SrcOp &Op) {
459  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
460 }
461 
463  const SrcOp &Op) {
464  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
465 }
466 
467 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
468  const auto *TLI = getMF().getSubtarget().getTargetLowering();
469  switch (TLI->getBooleanContents(IsVec, IsFP)) {
471  return TargetOpcode::G_SEXT;
473  return TargetOpcode::G_ZEXT;
474  default:
475  return TargetOpcode::G_ANYEXT;
476  }
477 }
478 
480  const SrcOp &Op,
481  bool IsFP) {
482  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
483  return buildInstr(ExtOp, Res, Op);
484 }
485 
487  const SrcOp &Op,
488  bool IsVector,
489  bool IsFP) {
490  const auto *TLI = getMF().getSubtarget().getTargetLowering();
491  switch (TLI->getBooleanContents(IsVector, IsFP)) {
493  return buildSExtInReg(Res, Op, 1);
495  return buildZExtInReg(Res, Op, 1);
497  return buildCopy(Res, Op);
498  }
499 
500  llvm_unreachable("unexpected BooleanContent");
501 }
502 
504  const DstOp &Res,
505  const SrcOp &Op) {
506  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
507  TargetOpcode::G_SEXT == ExtOpc) &&
508  "Expecting Extending Opc");
509  assert(Res.getLLTTy(*getMRI()).isScalar() ||
510  Res.getLLTTy(*getMRI()).isVector());
511  assert(Res.getLLTTy(*getMRI()).isScalar() ==
512  Op.getLLTTy(*getMRI()).isScalar());
513 
514  unsigned Opcode = TargetOpcode::COPY;
515  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
516  Op.getLLTTy(*getMRI()).getSizeInBits())
517  Opcode = ExtOpc;
518  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
519  Op.getLLTTy(*getMRI()).getSizeInBits())
520  Opcode = TargetOpcode::G_TRUNC;
521  else
522  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
523 
524  return buildInstr(Opcode, Res, Op);
525 }
526 
528  const SrcOp &Op) {
529  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
530 }
531 
533  const SrcOp &Op) {
534  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
535 }
536 
538  const SrcOp &Op) {
539  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
540 }
541 
543  const SrcOp &Op,
544  int64_t ImmOp) {
545  LLT ResTy = Res.getLLTTy(*getMRI());
546  auto Mask = buildConstant(
547  ResTy, APInt::getLowBitsSet(ResTy.getScalarSizeInBits(), ImmOp));
548  return buildAnd(Res, Op, Mask);
549 }
550 
552  const SrcOp &Src) {
553  LLT SrcTy = Src.getLLTTy(*getMRI());
554  LLT DstTy = Dst.getLLTTy(*getMRI());
555  if (SrcTy == DstTy)
556  return buildCopy(Dst, Src);
557 
558  unsigned Opcode;
559  if (SrcTy.isPointer() && DstTy.isScalar())
560  Opcode = TargetOpcode::G_PTRTOINT;
561  else if (DstTy.isPointer() && SrcTy.isScalar())
562  Opcode = TargetOpcode::G_INTTOPTR;
563  else {
564  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
565  Opcode = TargetOpcode::G_BITCAST;
566  }
567 
568  return buildInstr(Opcode, Dst, Src);
569 }
570 
572  const SrcOp &Src,
573  uint64_t Index) {
574  LLT SrcTy = Src.getLLTTy(*getMRI());
575  LLT DstTy = Dst.getLLTTy(*getMRI());
576 
577 #ifndef NDEBUG
578  assert(SrcTy.isValid() && "invalid operand type");
579  assert(DstTy.isValid() && "invalid operand type");
580  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
581  "extracting off end of register");
582 #endif
583 
584  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
585  assert(Index == 0 && "insertion past the end of a register");
586  return buildCast(Dst, Src);
587  }
588 
589  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
590  Dst.addDefToMIB(*getMRI(), Extract);
591  Src.addSrcToMIB(Extract);
592  Extract.addImm(Index);
593  return Extract;
594 }
595 
597  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
598 }
599 
601  ArrayRef<Register> Ops) {
602  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
603  // we need some temporary storage for the DstOp objects. Here we use a
604  // sufficiently large SmallVector to not go through the heap.
605  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
606  assert(TmpVec.size() > 1);
607  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
608 }
609 
612  std::initializer_list<SrcOp> Ops) {
613  assert(Ops.size() > 1);
614  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
615 }
616 
618  const SrcOp &Op) {
619  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
620  // we need some temporary storage for the DstOp objects. Here we use a
621  // sufficiently large SmallVector to not go through the heap.
622  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
623  assert(TmpVec.size() > 1);
624  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
625 }
626 
628  const SrcOp &Op) {
629  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
630  SmallVector<DstOp, 8> TmpVec(NumReg, Res);
631  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
632 }
633 
635  const SrcOp &Op) {
636  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
637  // we need some temporary storage for the DstOp objects. Here we use a
638  // sufficiently large SmallVector to not go through the heap.
639  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
640  assert(TmpVec.size() > 1);
641  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
642 }
643 
645  ArrayRef<Register> Ops) {
646  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
647  // we need some temporary storage for the DstOp objects. Here we use a
648  // sufficiently large SmallVector to not go through the heap.
649  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
650  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
651 }
652 
655  ArrayRef<APInt> Ops) {
656  SmallVector<SrcOp> TmpVec;
657  TmpVec.reserve(Ops.size());
658  LLT EltTy = Res.getLLTTy(*getMRI()).getElementType();
659  for (const auto &Op : Ops)
660  TmpVec.push_back(buildConstant(EltTy, Op));
661  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
662 }
663 
665  const SrcOp &Src) {
666  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
667  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
668 }
669 
672  ArrayRef<Register> Ops) {
673  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
674  // we need some temporary storage for the DstOp objects. Here we use a
675  // sufficiently large SmallVector to not go through the heap.
676  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
677  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
678 }
679 
681  const SrcOp &Src) {
682  LLT DstTy = Res.getLLTTy(*getMRI());
683  assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
684  "Expected Src to match Dst elt ty");
685  auto UndefVec = buildUndef(DstTy);
686  auto Zero = buildConstant(LLT::scalar(64), 0);
687  auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
688  SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
689  return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
690 }
691 
693  const SrcOp &Src1,
694  const SrcOp &Src2,
696  LLT DstTy = Res.getLLTTy(*getMRI());
697  LLT Src1Ty = Src1.getLLTTy(*getMRI());
698  LLT Src2Ty = Src2.getLLTTy(*getMRI());
699  assert((size_t)(Src1Ty.getNumElements() + Src2Ty.getNumElements()) >=
700  Mask.size());
701  assert(DstTy.getElementType() == Src1Ty.getElementType() &&
702  DstTy.getElementType() == Src2Ty.getElementType());
703  (void)DstTy;
704  (void)Src1Ty;
705  (void)Src2Ty;
707  return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
708  .addShuffleMask(MaskAlloc);
709 }
710 
713  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
714  // we need some temporary storage for the DstOp objects. Here we use a
715  // sufficiently large SmallVector to not go through the heap.
716  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
717  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
718 }
719 
721  const SrcOp &Src,
722  const SrcOp &Op,
723  unsigned Index) {
724  assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
725  Res.getLLTTy(*getMRI()).getSizeInBits() &&
726  "insertion past the end of a register");
727 
728  if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
729  Op.getLLTTy(*getMRI()).getSizeInBits()) {
730  return buildCast(Res, Op);
731  }
732 
733  return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
734 }
735 
737  ArrayRef<Register> ResultRegs,
738  bool HasSideEffects) {
739  auto MIB =
740  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
741  : TargetOpcode::G_INTRINSIC);
742  for (unsigned ResultReg : ResultRegs)
743  MIB.addDef(ResultReg);
744  MIB.addIntrinsicID(ID);
745  return MIB;
746 }
747 
750  bool HasSideEffects) {
751  auto MIB =
752  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
753  : TargetOpcode::G_INTRINSIC);
754  for (DstOp Result : Results)
755  Result.addDefToMIB(*getMRI(), MIB);
756  MIB.addIntrinsicID(ID);
757  return MIB;
758 }
759 
761  const SrcOp &Op) {
762  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
763 }
764 
766  const SrcOp &Op,
767  Optional<unsigned> Flags) {
768  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
769 }
770 
772  const DstOp &Res,
773  const SrcOp &Op0,
774  const SrcOp &Op1) {
775  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
776 }
777 
779  const DstOp &Res,
780  const SrcOp &Op0,
781  const SrcOp &Op1,
782  Optional<unsigned> Flags) {
783 
784  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
785 }
786 
788  const SrcOp &Tst,
789  const SrcOp &Op0,
790  const SrcOp &Op1,
791  Optional<unsigned> Flags) {
792 
793  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
794 }
795 
798  const SrcOp &Elt, const SrcOp &Idx) {
799  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
800 }
801 
804  const SrcOp &Idx) {
805  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
806 }
807 
809  Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
810  Register NewVal, MachineMemOperand &MMO) {
811 #ifndef NDEBUG
812  LLT OldValResTy = getMRI()->getType(OldValRes);
813  LLT SuccessResTy = getMRI()->getType(SuccessRes);
814  LLT AddrTy = getMRI()->getType(Addr);
815  LLT CmpValTy = getMRI()->getType(CmpVal);
816  LLT NewValTy = getMRI()->getType(NewVal);
817  assert(OldValResTy.isScalar() && "invalid operand type");
818  assert(SuccessResTy.isScalar() && "invalid operand type");
819  assert(AddrTy.isPointer() && "invalid operand type");
820  assert(CmpValTy.isValid() && "invalid operand type");
821  assert(NewValTy.isValid() && "invalid operand type");
822  assert(OldValResTy == CmpValTy && "type mismatch");
823  assert(OldValResTy == NewValTy && "type mismatch");
824 #endif
825 
826  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
827  .addDef(OldValRes)
828  .addDef(SuccessRes)
829  .addUse(Addr)
830  .addUse(CmpVal)
831  .addUse(NewVal)
832  .addMemOperand(&MMO);
833 }
834 
837  Register CmpVal, Register NewVal,
838  MachineMemOperand &MMO) {
839 #ifndef NDEBUG
840  LLT OldValResTy = getMRI()->getType(OldValRes);
841  LLT AddrTy = getMRI()->getType(Addr);
842  LLT CmpValTy = getMRI()->getType(CmpVal);
843  LLT NewValTy = getMRI()->getType(NewVal);
844  assert(OldValResTy.isScalar() && "invalid operand type");
845  assert(AddrTy.isPointer() && "invalid operand type");
846  assert(CmpValTy.isValid() && "invalid operand type");
847  assert(NewValTy.isValid() && "invalid operand type");
848  assert(OldValResTy == CmpValTy && "type mismatch");
849  assert(OldValResTy == NewValTy && "type mismatch");
850 #endif
851 
852  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
853  .addDef(OldValRes)
854  .addUse(Addr)
855  .addUse(CmpVal)
856  .addUse(NewVal)
857  .addMemOperand(&MMO);
858 }
859 
861  unsigned Opcode, const DstOp &OldValRes,
862  const SrcOp &Addr, const SrcOp &Val,
863  MachineMemOperand &MMO) {
864 
865 #ifndef NDEBUG
866  LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
867  LLT AddrTy = Addr.getLLTTy(*getMRI());
868  LLT ValTy = Val.getLLTTy(*getMRI());
869  assert(OldValResTy.isScalar() && "invalid operand type");
870  assert(AddrTy.isPointer() && "invalid operand type");
871  assert(ValTy.isValid() && "invalid operand type");
872  assert(OldValResTy == ValTy && "type mismatch");
873  assert(MMO.isAtomic() && "not atomic mem operand");
874 #endif
875 
876  auto MIB = buildInstr(Opcode);
877  OldValRes.addDefToMIB(*getMRI(), MIB);
878  Addr.addSrcToMIB(MIB);
879  Val.addSrcToMIB(MIB);
880  MIB.addMemOperand(&MMO);
881  return MIB;
882 }
883 
886  Register Val, MachineMemOperand &MMO) {
887  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
888  MMO);
889 }
892  Register Val, MachineMemOperand &MMO) {
893  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
894  MMO);
895 }
898  Register Val, MachineMemOperand &MMO) {
899  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
900  MMO);
901 }
904  Register Val, MachineMemOperand &MMO) {
905  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
906  MMO);
907 }
910  Register Val, MachineMemOperand &MMO) {
911  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
912  MMO);
913 }
915  Register Addr,
916  Register Val,
917  MachineMemOperand &MMO) {
918  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
919  MMO);
920 }
923  Register Val, MachineMemOperand &MMO) {
924  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
925  MMO);
926 }
929  Register Val, MachineMemOperand &MMO) {
930  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
931  MMO);
932 }
935  Register Val, MachineMemOperand &MMO) {
936  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
937  MMO);
938 }
941  Register Val, MachineMemOperand &MMO) {
942  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
943  MMO);
944 }
947  Register Val, MachineMemOperand &MMO) {
948  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
949  MMO);
950 }
951 
954  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
955  MachineMemOperand &MMO) {
956  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
957  MMO);
958 }
959 
961 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
962  MachineMemOperand &MMO) {
963  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
964  MMO);
965 }
966 
969  const SrcOp &Val, MachineMemOperand &MMO) {
970  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMAX, OldValRes, Addr, Val,
971  MMO);
972 }
973 
976  const SrcOp &Val, MachineMemOperand &MMO) {
977  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMIN, OldValRes, Addr, Val,
978  MMO);
979 }
980 
982 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
983  return buildInstr(TargetOpcode::G_FENCE)
984  .addImm(Ordering)
985  .addImm(Scope);
986 }
987 
990 #ifndef NDEBUG
991  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
992 #endif
993 
994  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
995 }
996 
997 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
998  bool IsExtend) {
999 #ifndef NDEBUG
1000  if (DstTy.isVector()) {
1001  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
1002  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
1003  "different number of elements in a trunc/ext");
1004  } else
1005  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
1006 
1007  if (IsExtend)
1008  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
1009  "invalid narrowing extend");
1010  else
1011  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
1012  "invalid widening trunc");
1013 #endif
1014 }
1015 
1016 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
1017  const LLT Op0Ty, const LLT Op1Ty) {
1018 #ifndef NDEBUG
1019  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
1020  "invalid operand type");
1021  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
1022  if (ResTy.isScalar() || ResTy.isPointer())
1023  assert(TstTy.isScalar() && "type mismatch");
1024  else
1025  assert((TstTy.isScalar() ||
1026  (TstTy.isVector() &&
1027  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
1028  "type mismatch");
1029 #endif
1030 }
1031 
1033  ArrayRef<DstOp> DstOps,
1034  ArrayRef<SrcOp> SrcOps,
1035  Optional<unsigned> Flags) {
1036  switch (Opc) {
1037  default:
1038  break;
1039  case TargetOpcode::G_SELECT: {
1040  assert(DstOps.size() == 1 && "Invalid select");
1041  assert(SrcOps.size() == 3 && "Invalid select");
1043  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
1044  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
1045  break;
1046  }
1047  case TargetOpcode::G_FNEG:
1048  case TargetOpcode::G_ABS:
1049  // All these are unary ops.
1050  assert(DstOps.size() == 1 && "Invalid Dst");
1051  assert(SrcOps.size() == 1 && "Invalid Srcs");
1052  validateUnaryOp(DstOps[0].getLLTTy(*getMRI()),
1053  SrcOps[0].getLLTTy(*getMRI()));
1054  break;
1055  case TargetOpcode::G_ADD:
1056  case TargetOpcode::G_AND:
1057  case TargetOpcode::G_MUL:
1058  case TargetOpcode::G_OR:
1059  case TargetOpcode::G_SUB:
1060  case TargetOpcode::G_XOR:
1061  case TargetOpcode::G_UDIV:
1062  case TargetOpcode::G_SDIV:
1063  case TargetOpcode::G_UREM:
1064  case TargetOpcode::G_SREM:
1065  case TargetOpcode::G_SMIN:
1066  case TargetOpcode::G_SMAX:
1067  case TargetOpcode::G_UMIN:
1068  case TargetOpcode::G_UMAX:
1069  case TargetOpcode::G_UADDSAT:
1070  case TargetOpcode::G_SADDSAT:
1071  case TargetOpcode::G_USUBSAT:
1072  case TargetOpcode::G_SSUBSAT: {
1073  // All these are binary ops.
1074  assert(DstOps.size() == 1 && "Invalid Dst");
1075  assert(SrcOps.size() == 2 && "Invalid Srcs");
1076  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
1077  SrcOps[0].getLLTTy(*getMRI()),
1078  SrcOps[1].getLLTTy(*getMRI()));
1079  break;
1080  }
1081  case TargetOpcode::G_SHL:
1082  case TargetOpcode::G_ASHR:
1083  case TargetOpcode::G_LSHR:
1084  case TargetOpcode::G_USHLSAT:
1085  case TargetOpcode::G_SSHLSAT: {
1086  assert(DstOps.size() == 1 && "Invalid Dst");
1087  assert(SrcOps.size() == 2 && "Invalid Srcs");
1088  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
1089  SrcOps[0].getLLTTy(*getMRI()),
1090  SrcOps[1].getLLTTy(*getMRI()));
1091  break;
1092  }
1093  case TargetOpcode::G_SEXT:
1094  case TargetOpcode::G_ZEXT:
1095  case TargetOpcode::G_ANYEXT:
1096  assert(DstOps.size() == 1 && "Invalid Dst");
1097  assert(SrcOps.size() == 1 && "Invalid Srcs");
1098  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1099  SrcOps[0].getLLTTy(*getMRI()), true);
1100  break;
1101  case TargetOpcode::G_TRUNC:
1102  case TargetOpcode::G_FPTRUNC: {
1103  assert(DstOps.size() == 1 && "Invalid Dst");
1104  assert(SrcOps.size() == 1 && "Invalid Srcs");
1105  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1106  SrcOps[0].getLLTTy(*getMRI()), false);
1107  break;
1108  }
1109  case TargetOpcode::G_BITCAST: {
1110  assert(DstOps.size() == 1 && "Invalid Dst");
1111  assert(SrcOps.size() == 1 && "Invalid Srcs");
1112  assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1113  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1114  break;
1115  }
1116  case TargetOpcode::COPY:
1117  assert(DstOps.size() == 1 && "Invalid Dst");
1118  // If the caller wants to add a subreg source it has to be done separately
1119  // so we may not have any SrcOps at this point yet.
1120  break;
1121  case TargetOpcode::G_FCMP:
1122  case TargetOpcode::G_ICMP: {
1123  assert(DstOps.size() == 1 && "Invalid Dst Operands");
1124  assert(SrcOps.size() == 3 && "Invalid Src Operands");
1125  // For F/ICMP, the first src operand is the predicate, followed by
1126  // the two comparands.
1127  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1128  "Expecting predicate");
1129  assert([&]() -> bool {
1130  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1131  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1132  : CmpInst::isFPPredicate(Pred);
1133  }() && "Invalid predicate");
1134  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1135  "Type mismatch");
1136  assert([&]() -> bool {
1137  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1138  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1139  if (Op0Ty.isScalar() || Op0Ty.isPointer())
1140  return DstTy.isScalar();
1141  else
1142  return DstTy.isVector() &&
1143  DstTy.getNumElements() == Op0Ty.getNumElements();
1144  }() && "Type Mismatch");
1145  break;
1146  }
1147  case TargetOpcode::G_UNMERGE_VALUES: {
1148  assert(!DstOps.empty() && "Invalid trivial sequence");
1149  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1150  assert(llvm::all_of(DstOps,
1151  [&, this](const DstOp &Op) {
1152  return Op.getLLTTy(*getMRI()) ==
1153  DstOps[0].getLLTTy(*getMRI());
1154  }) &&
1155  "type mismatch in output list");
1156  assert((TypeSize::ScalarTy)DstOps.size() *
1157  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1158  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1159  "input operands do not cover output register");
1160  break;
1161  }
1162  case TargetOpcode::G_MERGE_VALUES: {
1163  assert(!SrcOps.empty() && "invalid trivial sequence");
1164  assert(DstOps.size() == 1 && "Invalid Dst");
1165  assert(llvm::all_of(SrcOps,
1166  [&, this](const SrcOp &Op) {
1167  return Op.getLLTTy(*getMRI()) ==
1168  SrcOps[0].getLLTTy(*getMRI());
1169  }) &&
1170  "type mismatch in input list");
1171  assert((TypeSize::ScalarTy)SrcOps.size() *
1172  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1173  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1174  "input operands do not cover output register");
1175  if (SrcOps.size() == 1)
1176  return buildCast(DstOps[0], SrcOps[0]);
1177  if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1178  if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1179  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1180  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1181  }
1182  break;
1183  }
1184  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1185  assert(DstOps.size() == 1 && "Invalid Dst size");
1186  assert(SrcOps.size() == 2 && "Invalid Src size");
1187  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1188  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1189  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1190  "Invalid operand type");
1191  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1192  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1193  DstOps[0].getLLTTy(*getMRI()) &&
1194  "Type mismatch");
1195  break;
1196  }
1197  case TargetOpcode::G_INSERT_VECTOR_ELT: {
1198  assert(DstOps.size() == 1 && "Invalid dst size");
1199  assert(SrcOps.size() == 3 && "Invalid src size");
1200  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1201  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1202  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1203  SrcOps[1].getLLTTy(*getMRI()) &&
1204  "Type mismatch");
1205  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1206  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1207  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1208  "Type mismatch");
1209  break;
1210  }
1211  case TargetOpcode::G_BUILD_VECTOR: {
1212  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1213  "Must have at least 2 operands");
1214  assert(DstOps.size() == 1 && "Invalid DstOps");
1215  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1216  "Res type must be a vector");
1217  assert(llvm::all_of(SrcOps,
1218  [&, this](const SrcOp &Op) {
1219  return Op.getLLTTy(*getMRI()) ==
1220  SrcOps[0].getLLTTy(*getMRI());
1221  }) &&
1222  "type mismatch in input list");
1223  assert((TypeSize::ScalarTy)SrcOps.size() *
1224  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1225  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1226  "input scalars do not exactly cover the output vector register");
1227  break;
1228  }
1229  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1230  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1231  "Must have at least 2 operands");
1232  assert(DstOps.size() == 1 && "Invalid DstOps");
1233  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1234  "Res type must be a vector");
1235  assert(llvm::all_of(SrcOps,
1236  [&, this](const SrcOp &Op) {
1237  return Op.getLLTTy(*getMRI()) ==
1238  SrcOps[0].getLLTTy(*getMRI());
1239  }) &&
1240  "type mismatch in input list");
1241  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1242  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1243  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1244  break;
1245  }
1246  case TargetOpcode::G_CONCAT_VECTORS: {
1247  assert(DstOps.size() == 1 && "Invalid DstOps");
1248  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1249  "Must have at least 2 operands");
1250  assert(llvm::all_of(SrcOps,
1251  [&, this](const SrcOp &Op) {
1252  return (Op.getLLTTy(*getMRI()).isVector() &&
1253  Op.getLLTTy(*getMRI()) ==
1254  SrcOps[0].getLLTTy(*getMRI()));
1255  }) &&
1256  "type mismatch in input list");
1257  assert((TypeSize::ScalarTy)SrcOps.size() *
1258  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1259  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1260  "input vectors do not exactly cover the output vector register");
1261  break;
1262  }
1263  case TargetOpcode::G_UADDE: {
1264  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1265  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1266  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1267  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1268  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1269  "Invalid operand");
1270  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1271  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1272  "type mismatch");
1273  break;
1274  }
1275  }
1276 
1277  auto MIB = buildInstr(Opc);
1278  for (const DstOp &Op : DstOps)
1279  Op.addDefToMIB(*getMRI(), MIB);
1280  for (const SrcOp &Op : SrcOps)
1281  Op.addSrcToMIB(MIB);
1282  if (Flags)
1283  MIB->setFlags(*Flags);
1284  return MIB;
1285 }
i
i
Definition: README.txt:29
llvm::MachineIRBuilder::buildAtomicRMWFMin
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:975
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:24
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:797
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:154
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:860
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:771
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:59
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:136
DebugInfoMetadata.h
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:481
getFunction
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:236
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:664
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:289
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:542
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:914
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::PointerType::getAddressSpace
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:682
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:532
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:167
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:891
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:836
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:125
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:286
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:765
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:298
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::UnivariateLinearPolyBase< TypeSize >::ScalarTy
typename LinearPolyBaseTypeTraits< TypeSize >::ScalarTy ScalarTy
Definition: TypeSize.h:167
llvm::Optional
Definition: APInt.h:33
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:644
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:828
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:39
MachineIRBuilder.h
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:503
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:58
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:495
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:961
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:982
llvm::LegalityPredicates::isPointer
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
Definition: LegalityPredicates.cpp:79
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1223
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:134
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:1016
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:293
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:178
MachineRegisterInfo.h
llvm::AVR::getAddressSpace
AddressSpace getAddressSpace(T *V)
Definition: AVR.h:64
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:226
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1590
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:808
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:617
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:934
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:462
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:803
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:904
llvm::CmpInst::isFPPredicate
bool isFPPredicate() const
Definition: InstrTypes.h:826
getScalarSizeInBits
static unsigned getScalarSizeInBits(Type *Ty)
Definition: SystemZTargetTransformInfo.cpp:403
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:82
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:479
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:235
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:537
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:778
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:232
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:75
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:712
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:903
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:271
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:879
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1600
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:63
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:370
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:394
llvm::MachineIRBuilder::getPCSections
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
Definition: MachineIRBuilder.h:374
llvm::None
const NoneType None
Definition: None.h:24
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:928
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:272
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:173
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:268
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:216
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::APFloat
Definition: APFloat.h:701
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:322
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:277
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:527
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:310
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:190
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:909
llvm::MachineIRBuilder::buildAtomicRMWFMax
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:968
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:787
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:90
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:296
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:953
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
getType
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
Definition: M68kELFObjectWriter.cpp:48
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:827
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:62
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:383
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:150
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFunction::allocateShuffleMask
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
Definition: MachineFunction.cpp:555
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:288
uint32_t
TargetSubtargetInfo.h
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:720
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:48
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:571
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MachineIRBuilder::buildSExtInReg
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Definition: MachineIRBuilder.h:655
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:452
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:201
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:167
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LegalityPredicates::isScalar
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
Definition: LegalityPredicates.cpp:67
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:145
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:760
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:52
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1326
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:596
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:50
llvm::ConstantFP::get
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:926
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:946
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:692
llvm::MachineIRBuilder::buildBuildVectorConstant
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:654
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:922
llvm::MachineIRBuilder::buildPadVectorWithUndefElements
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
Definition: MachineIRBuilder.cpp:227
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:296
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:231
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:265
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:46
llvm::MachineIRBuilderState::PCSections
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
Definition: MachineIRBuilder.h:54
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::MachineIRBuilder::buildDeleteTrailingVectorElements
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
Definition: MachineIRBuilder.cpp:250
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:989
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:997
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:96
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:940
llvm::LegalityPredicates::isVector
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Definition: LegalityPredicates.cpp:73
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:187
llvm::MachineIRBuilder::buildBoolExtInReg
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
Definition: MachineIRBuilder.cpp:486
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:184
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:97
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:736
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:457
llvm::DstOp
Definition: MachineIRBuilder.h:67
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:600
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:167
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:408
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:897
llvm::GlobalValue::getType
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:284
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
Definition: APInt.h:289
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:311
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:671
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:467
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:425
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:885
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
MachineFunction.h
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:650
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:50
llvm::SrcOp
Definition: MachineIRBuilder.h:128
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:551
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:680
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:230
llvm::LLT
Definition: LowLevelTypeImpl.h:39