Go to the documentation of this file.
52 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
53 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
55 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
56 "Expected inlined-at fields to agree");
59 false,
Reg, Variable, Expr));
65 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
66 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
68 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
69 "Expected inlined-at fields to agree");
72 true,
Reg, Variable, Expr));
78 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
79 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
81 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
82 "Expected inlined-at fields to agree");
93 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
94 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
96 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
97 "Expected inlined-at fields to agree");
99 if (
auto *CI = dyn_cast<ConstantInt>(&
C)) {
100 if (CI->getBitWidth() > 64)
103 MIB.addImm(CI->getZExtValue());
104 }
else if (
auto *CFP = dyn_cast<ConstantFP>(&
C)) {
111 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
116 assert(isa<DILabel>(Label) &&
"not a label");
117 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.
DL) &&
118 "Expected inlined-at fields to agree");
119 auto MIB =
buildInstr(TargetOpcode::DBG_LABEL);
121 return MIB.addMetadata(Label);
128 auto MIB =
buildInstr(TargetOpcode::G_DYN_STACKALLOC);
130 Size.addSrcToMIB(MIB);
131 MIB.addImm(Alignment.value());
138 auto MIB =
buildInstr(TargetOpcode::G_FRAME_INDEX);
140 MIB.addFrameIndex(Idx);
149 "address space mismatch");
151 auto MIB =
buildInstr(TargetOpcode::G_GLOBAL_VALUE);
153 MIB.addGlobalAddress(GV);
159 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
160 .addJumpTableIndex(JTI);
165 assert((Res == Op0) &&
"type mismatch");
171 assert((Res == Op0 && Res == Op1) &&
"type mismatch");
177 assert((Res == Op0) &&
"type mismatch");
187 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
193 assert(Res == 0 &&
"Res is a result argument");
212 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
224 "Different vector element types");
226 "Op0 has more elements");
230 for (
auto Op : Unmerge.getInstr()->defs())
231 Regs.push_back(
Op.getReg());
234 for (
unsigned i = 0;
i < NumberOfPadElts; ++
i)
235 Regs.push_back(
Undef);
247 "Different vector element types");
249 "Op0 has fewer elements");
254 Regs.push_back(Unmerge.getReg(
i));
271 "Table reg must be a pointer");
288 "creating constant with the wrong size");
291 auto Const =
buildInstr(TargetOpcode::G_CONSTANT)
297 auto Const =
buildInstr(TargetOpcode::G_CONSTANT);
319 "creating fconstant with the wrong size");
324 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT)
331 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT);
334 Const.addFPImm(&Val);
364 auto MIB =
buildInstr(TargetOpcode::G_BRCOND);
393 Addr.addSrcToMIB(MIB);
394 MIB.addMemOperand(&MMO);
406 return buildLoad(Dst, BasePtr, *OffsetMMO);
411 auto Ptr =
buildPtrAdd(PtrTy, BasePtr, ConstOffset);
423 Addr.addSrcToMIB(MIB);
424 MIB.addMemOperand(&MMO);
459 switch (TLI->getBooleanContents(IsVec, IsFP)) {
461 return TargetOpcode::G_SEXT;
463 return TargetOpcode::G_ZEXT;
465 return TargetOpcode::G_ANYEXT;
479 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
480 TargetOpcode::G_SEXT == ExtOpc) &&
481 "Expecting Extending Opc");
487 unsigned Opcode = TargetOpcode::COPY;
489 Op.getLLTTy(*
getMRI()).getSizeInBits())
492 Op.getLLTTy(*
getMRI()).getSizeInBits())
493 Opcode = TargetOpcode::G_TRUNC;
533 Opcode = TargetOpcode::G_PTRTOINT;
535 Opcode = TargetOpcode::G_INTTOPTR;
538 Opcode = TargetOpcode::G_BITCAST;
554 "extracting off end of register");
558 assert(
Index == 0 &&
"insertion past the end of a register");
562 auto Extract =
buildInstr(TargetOpcode::G_EXTRACT);
563 Dst.addDefToMIB(*
getMRI(), Extract);
564 Src.addSrcToMIB(Extract);
565 Extract.addImm(
Index);
570 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
579 assert(TmpVec.size() > 1);
580 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
585 std::initializer_list<SrcOp> Ops) {
587 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
596 assert(TmpVec.size() > 1);
597 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
604 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
613 assert(TmpVec.size() > 1);
614 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
623 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
634 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
640 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
650 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
657 "Expected Src to match Dst elt ty");
680 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
681 .addShuffleMask(MaskAlloc);
690 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
699 "insertion past the end of a register");
702 Op.getLLTTy(*
getMRI()).getSizeInBits()) {
711 bool HasSideEffects) {
713 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
714 : TargetOpcode::G_INTRINSIC);
715 for (
unsigned ResultReg : ResultRegs)
716 MIB.addDef(ResultReg);
717 MIB.addIntrinsicID(
ID);
723 bool HasSideEffects) {
725 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
726 : TargetOpcode::G_INTRINSIC);
728 Result.addDefToMIB(*
getMRI(), MIB);
729 MIB.addIntrinsicID(
ID);
741 return buildInstr(TargetOpcode::G_FPTRUNC, Res,
Op, Flags);
748 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
757 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
766 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
772 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
778 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
795 assert(OldValResTy == CmpValTy &&
"type mismatch");
796 assert(OldValResTy == NewValTy &&
"type mismatch");
799 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
821 assert(OldValResTy == CmpValTy &&
"type mismatch");
822 assert(OldValResTy == NewValTy &&
"type mismatch");
825 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
834 unsigned Opcode,
const DstOp &OldValRes,
845 assert(OldValResTy == ValTy &&
"type mismatch");
851 Addr.addSrcToMIB(MIB);
853 MIB.addMemOperand(&MMO);
960 assert(SrcTy.
isVector() &&
"mismatched cast between vector and non-vector");
962 "different number of elements in a trunc/ext");
968 "invalid narrowing extend");
971 "invalid widening trunc");
976 const LLT Op0Ty,
const LLT Op1Ty) {
979 "invalid operand type");
980 assert((ResTy == Op0Ty && ResTy == Op1Ty) &&
"type mismatch");
998 case TargetOpcode::G_SELECT: {
999 assert(DstOps.
size() == 1 &&
"Invalid select");
1000 assert(SrcOps.
size() == 3 &&
"Invalid select");
1002 DstOps[0].getLLTTy(*
getMRI()), SrcOps[0].getLLTTy(*
getMRI()),
1003 SrcOps[1].getLLTTy(*
getMRI()), SrcOps[2].getLLTTy(*
getMRI()));
1006 case TargetOpcode::G_FNEG:
1007 case TargetOpcode::G_ABS:
1010 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1012 SrcOps[0].getLLTTy(*
getMRI()));
1014 case TargetOpcode::G_ADD:
1015 case TargetOpcode::G_AND:
1016 case TargetOpcode::G_MUL:
1017 case TargetOpcode::G_OR:
1018 case TargetOpcode::G_SUB:
1019 case TargetOpcode::G_XOR:
1020 case TargetOpcode::G_UDIV:
1021 case TargetOpcode::G_SDIV:
1022 case TargetOpcode::G_UREM:
1023 case TargetOpcode::G_SREM:
1024 case TargetOpcode::G_SMIN:
1025 case TargetOpcode::G_SMAX:
1026 case TargetOpcode::G_UMIN:
1027 case TargetOpcode::G_UMAX:
1028 case TargetOpcode::G_UADDSAT:
1029 case TargetOpcode::G_SADDSAT:
1030 case TargetOpcode::G_USUBSAT:
1031 case TargetOpcode::G_SSUBSAT: {
1034 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1036 SrcOps[0].getLLTTy(*
getMRI()),
1037 SrcOps[1].getLLTTy(*
getMRI()));
1040 case TargetOpcode::G_SHL:
1041 case TargetOpcode::G_ASHR:
1042 case TargetOpcode::G_LSHR:
1043 case TargetOpcode::G_USHLSAT:
1044 case TargetOpcode::G_SSHLSAT: {
1046 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1048 SrcOps[0].getLLTTy(*
getMRI()),
1049 SrcOps[1].getLLTTy(*
getMRI()));
1052 case TargetOpcode::G_SEXT:
1053 case TargetOpcode::G_ZEXT:
1054 case TargetOpcode::G_ANYEXT:
1056 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1058 SrcOps[0].getLLTTy(*
getMRI()),
true);
1060 case TargetOpcode::G_TRUNC:
1061 case TargetOpcode::G_FPTRUNC: {
1063 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1065 SrcOps[0].getLLTTy(*
getMRI()),
false);
1068 case TargetOpcode::G_BITCAST: {
1070 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1071 assert(DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1072 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
"invalid bitcast");
1075 case TargetOpcode::COPY:
1080 case TargetOpcode::G_FCMP:
1081 case TargetOpcode::G_ICMP: {
1082 assert(DstOps.
size() == 1 &&
"Invalid Dst Operands");
1083 assert(SrcOps.
size() == 3 &&
"Invalid Src Operands");
1087 "Expecting predicate");
1092 }() &&
"Invalid predicate");
1096 LLT Op0Ty = SrcOps[1].getLLTTy(*
getMRI());
1097 LLT DstTy = DstOps[0].getLLTTy(*
getMRI());
1103 }() &&
"Type Mismatch");
1106 case TargetOpcode::G_UNMERGE_VALUES: {
1107 assert(!DstOps.
empty() &&
"Invalid trivial sequence");
1108 assert(SrcOps.
size() == 1 &&
"Invalid src for Unmerge");
1112 DstOps[0].getLLTTy(*
getMRI());
1114 "type mismatch in output list");
1116 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1117 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1118 "input operands do not cover output register");
1121 case TargetOpcode::G_MERGE_VALUES: {
1122 assert(!SrcOps.
empty() &&
"invalid trivial sequence");
1127 SrcOps[0].getLLTTy(*
getMRI());
1129 "type mismatch in input list");
1131 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1132 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1133 "input operands do not cover output register");
1134 if (SrcOps.
size() == 1)
1138 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1139 return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1143 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1144 assert(DstOps.
size() == 1 &&
"Invalid Dst size");
1145 assert(SrcOps.
size() == 2 &&
"Invalid Src size");
1149 "Invalid operand type");
1151 assert(SrcOps[0].getLLTTy(*
getMRI()).getElementType() ==
1152 DstOps[0].getLLTTy(*
getMRI()) &&
1156 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1157 assert(DstOps.
size() == 1 &&
"Invalid dst size");
1158 assert(SrcOps.
size() == 3 &&
"Invalid src size");
1160 SrcOps[0].getLLTTy(*
getMRI()).
isVector() &&
"Invalid operand type");
1161 assert(DstOps[0].getLLTTy(*
getMRI()).getElementType() ==
1162 SrcOps[1].getLLTTy(*
getMRI()) &&
1165 assert(DstOps[0].getLLTTy(*
getMRI()).getNumElements() ==
1166 SrcOps[0].getLLTTy(*
getMRI()).getNumElements() &&
1170 case TargetOpcode::G_BUILD_VECTOR: {
1172 "Must have at least 2 operands");
1173 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1175 "Res type must be a vector");
1179 SrcOps[0].getLLTTy(*
getMRI());
1181 "type mismatch in input list");
1183 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1184 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1185 "input scalars do not exactly cover the output vector register");
1188 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1190 "Must have at least 2 operands");
1191 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1193 "Res type must be a vector");
1197 SrcOps[0].getLLTTy(*
getMRI());
1199 "type mismatch in input list");
1200 if (SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1201 DstOps[0].getLLTTy(*
getMRI()).getElementType().getSizeInBits())
1202 return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1205 case TargetOpcode::G_CONCAT_VECTORS: {
1206 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1208 "Must have at least 2 operands");
1213 SrcOps[0].getLLTTy(*
getMRI()));
1215 "type mismatch in input list");
1217 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1218 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1219 "input vectors do not exactly cover the output vector register");
1222 case TargetOpcode::G_UADDE: {
1223 assert(DstOps.
size() == 2 &&
"Invalid no of dst operands");
1224 assert(SrcOps.
size() == 3 &&
"Invalid no of src operands");
1227 (DstOps[0].getLLTTy(*
getMRI()) == SrcOps[1].getLLTTy(*
getMRI())) &&
1237 for (
const DstOp &
Op : DstOps)
1239 for (
const SrcOp &
Op : SrcOps)
1240 Op.addSrcToMIB(MIB);
1242 MIB->setFlags(*Flags);
void setMF(MachineFunction &MF)
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
unsigned getScalarSizeInBits() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
MachineBasicBlock::iterator II
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
static Function * getFunction(Constant *C)
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
LLT getScalarType() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
A description of a memory reference used in the backend.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
const APFloat & getValueAPF() const
typename LinearPolyBaseTypeTraits< TypeSize >::ScalarTy ScalarTy
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Function Alias Analysis Results
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
const fltSemantics & getSemantics() const
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
bool empty() const
empty - Check if the array is empty.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
AddressSpace getAddressSpace(T *V)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
This is the shared class of boolean and integer constants.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
bool isFPPredicate() const
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
(vector float) vec_cmpeq(*A, *B) C
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
void recordInsertion(MachineInstr *InsertedInstr) const
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
@ ZeroOrNegativeOneBooleanContent
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineFunction & getMF()
Getter for the function we currently build.
ConstantFP - Floating Point Values [float, double].
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Register getReg(unsigned Idx) const
Get the register for the operand index.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addFrameIndex(int Idx) const
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
This is an important base class in LLVM.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
This class contains a discriminated union of information about pointers in memory operands,...
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Flags
Flags values. These may be or'd together.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Class for arbitrary precision integers.
bool isIntPredicate() const
GISelChangeObserver * Observer
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
The address of a basic block.
void addSrcToMIB(MachineInstrBuilder &MIB) const
MachineInstrBundleIterator< MachineInstr > iterator
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
@ MOLoad
The memory access reads data.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Wrapper class representing virtual and physical registers.
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Function & getFunction()
Return the LLVM function that this machine code represents.
Should compile to something r4 addze r3 instead we get
DebugLoc DL
Debug location to be set to any instruction we create.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
@ ZeroOrOneBooleanContent
const TargetInstrInfo & getTII()
MachineFunction * MF
MachineFunction under construction.
@ MOStore
The memory access writes data.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
virtual const TargetLowering * getTargetLowering() const
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
size_t size() const
size - Get the array size.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
PointerType * getType() const
Global values are always pointers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
void reserve(size_type N)
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
LLVM Value Representation.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
@ Undef
Value of the register doesn't matter.