LLVM  13.0.0git
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
36 //------------------------------------------------------------------------------
37 // Build instruction variants.
38 //------------------------------------------------------------------------------
39 
41  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
42  return MIB;
43 }
44 
46  getMBB().insert(getInsertPt(), MIB);
47  recordInsertion(MIB);
48  return MIB;
49 }
50 
53  const MDNode *Expr) {
54  assert(isa<DILocalVariable>(Variable) && "not a variable");
55  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
56  assert(
57  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
58  "Expected inlined-at fields to agree");
59  return insertInstr(BuildMI(getMF(), getDL(),
60  getTII().get(TargetOpcode::DBG_VALUE),
61  /*IsIndirect*/ false, Reg, Variable, Expr));
62 }
63 
66  const MDNode *Expr) {
67  assert(isa<DILocalVariable>(Variable) && "not a variable");
68  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
69  assert(
70  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
71  "Expected inlined-at fields to agree");
72  return insertInstr(BuildMI(getMF(), getDL(),
73  getTII().get(TargetOpcode::DBG_VALUE),
74  /*IsIndirect*/ true, Reg, Variable, Expr));
75 }
76 
78  const MDNode *Variable,
79  const MDNode *Expr) {
80  assert(isa<DILocalVariable>(Variable) && "not a variable");
81  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
82  assert(
83  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
84  "Expected inlined-at fields to agree");
85  return buildInstr(TargetOpcode::DBG_VALUE)
86  .addFrameIndex(FI)
87  .addImm(0)
88  .addMetadata(Variable)
89  .addMetadata(Expr);
90 }
91 
93  const MDNode *Variable,
94  const MDNode *Expr) {
95  assert(isa<DILocalVariable>(Variable) && "not a variable");
96  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
97  assert(
98  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
99  "Expected inlined-at fields to agree");
100  auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
101  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
102  if (CI->getBitWidth() > 64)
103  MIB.addCImm(CI);
104  else
105  MIB.addImm(CI->getZExtValue());
106  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
107  MIB.addFPImm(CFP);
108  } else {
109  // Insert $noreg if we didn't find a usable constant and had to drop it.
110  MIB.addReg(Register());
111  }
112 
113  MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
114  return insertInstr(MIB);
115 }
116 
118  assert(isa<DILabel>(Label) && "not a label");
119  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
120  "Expected inlined-at fields to agree");
121  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
122 
123  return MIB.addMetadata(Label);
124 }
125 
127  const SrcOp &Size,
128  Align Alignment) {
129  assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
130  auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
131  Res.addDefToMIB(*getMRI(), MIB);
132  Size.addSrcToMIB(MIB);
133  MIB.addImm(Alignment.value());
134  return MIB;
135 }
136 
138  int Idx) {
139  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
140  auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
141  Res.addDefToMIB(*getMRI(), MIB);
142  MIB.addFrameIndex(Idx);
143  return MIB;
144 }
145 
147  const GlobalValue *GV) {
148  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
149  assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
150  GV->getType()->getAddressSpace() &&
151  "address space mismatch");
152 
153  auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
154  Res.addDefToMIB(*getMRI(), MIB);
155  MIB.addGlobalAddress(GV);
156  return MIB;
157 }
158 
160  unsigned JTI) {
161  return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
162  .addJumpTableIndex(JTI);
163 }
164 
165 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
166  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
167  assert((Res == Op0) && "type mismatch");
168 }
169 
170 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
171  const LLT Op1) {
172  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
173  assert((Res == Op0 && Res == Op1) && "type mismatch");
174 }
175 
176 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
177  const LLT Op1) {
178  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
179  assert((Res == Op0) && "type mismatch");
180 }
181 
183  const SrcOp &Op0,
184  const SrcOp &Op1) {
185  assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
186  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
187  assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
188 
189  return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
190 }
191 
194  const LLT ValueTy, uint64_t Value) {
195  assert(Res == 0 && "Res is a result argument");
196  assert(ValueTy.isScalar() && "invalid offset type");
197 
198  if (Value == 0) {
199  Res = Op0;
200  return None;
201  }
202 
204  auto Cst = buildConstant(ValueTy, Value);
205  return buildPtrAdd(Res, Op0, Cst.getReg(0));
206 }
207 
209  const SrcOp &Op0,
210  uint32_t NumBits) {
211  LLT PtrTy = Res.getLLTTy(*getMRI());
212  LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
213  Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
214  buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
215  return buildPtrMask(Res, Op0, MaskReg);
216 }
217 
219  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
220 }
221 
223  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
224  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
225 }
226 
228  unsigned JTI,
229  Register IndexReg) {
230  assert(getMRI()->getType(TablePtr).isPointer() &&
231  "Table reg must be a pointer");
232  return buildInstr(TargetOpcode::G_BRJT)
233  .addUse(TablePtr)
234  .addJumpTableIndex(JTI)
235  .addUse(IndexReg);
236 }
237 
239  const SrcOp &Op) {
240  return buildInstr(TargetOpcode::COPY, Res, Op);
241 }
242 
244  const SrcOp &Op,
245  unsigned Size) {
246  return buildInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op).addImm(Size);
247 }
248 
250  const SrcOp &Op,
251  unsigned Size) {
252  return buildInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op).addImm(Size);
253 }
254 
256  const ConstantInt &Val) {
257  LLT Ty = Res.getLLTTy(*getMRI());
258  LLT EltTy = Ty.getScalarType();
259  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
260  "creating constant with the wrong size");
261 
262  if (Ty.isVector()) {
263  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
264  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
265  .addCImm(&Val);
266  return buildSplatVector(Res, Const);
267  }
268 
269  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
270  Const->setDebugLoc(DebugLoc());
271  Res.addDefToMIB(*getMRI(), Const);
272  Const.addCImm(&Val);
273  return Const;
274 }
275 
277  int64_t Val) {
278  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
280  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
281  return buildConstant(Res, *CI);
282 }
283 
285  const ConstantFP &Val) {
286  LLT Ty = Res.getLLTTy(*getMRI());
287  LLT EltTy = Ty.getScalarType();
288 
290  == EltTy.getSizeInBits() &&
291  "creating fconstant with the wrong size");
292 
293  assert(!Ty.isPointer() && "invalid operand type");
294 
295  if (Ty.isVector()) {
296  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
297  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
298  .addFPImm(&Val);
299 
300  return buildSplatVector(Res, Const);
301  }
302 
303  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
304  Const->setDebugLoc(DebugLoc());
305  Res.addDefToMIB(*getMRI(), Const);
306  Const.addFPImm(&Val);
307  return Const;
308 }
309 
311  const APInt &Val) {
312  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
313  return buildConstant(Res, *CI);
314 }
315 
317  double Val) {
318  LLT DstTy = Res.getLLTTy(*getMRI());
319  auto &Ctx = getMF().getFunction().getContext();
320  auto *CFP =
322  return buildFConstant(Res, *CFP);
323 }
324 
326  const APFloat &Val) {
327  auto &Ctx = getMF().getFunction().getContext();
328  auto *CFP = ConstantFP::get(Ctx, Val);
329  return buildFConstant(Res, *CFP);
330 }
331 
333  MachineBasicBlock &Dest) {
334  assert(Tst.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
335 
336  auto MIB = buildInstr(TargetOpcode::G_BRCOND);
337  Tst.addSrcToMIB(MIB);
338  MIB.addMBB(&Dest);
339  return MIB;
340 }
341 
344  MachinePointerInfo PtrInfo, Align Alignment,
345  MachineMemOperand::Flags MMOFlags,
346  const AAMDNodes &AAInfo) {
347  MMOFlags |= MachineMemOperand::MOLoad;
348  assert((MMOFlags & MachineMemOperand::MOStore) == 0);
349 
352  MachineMemOperand *MMO =
353  getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
354  return buildLoad(Dst, Addr, *MMO);
355 }
356 
358  const DstOp &Res,
359  const SrcOp &Addr,
360  MachineMemOperand &MMO) {
361  assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
362  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
363 
364  auto MIB = buildInstr(Opcode);
365  Res.addDefToMIB(*getMRI(), MIB);
366  Addr.addSrcToMIB(MIB);
367  MIB.addMemOperand(&MMO);
368  return MIB;
369 }
370 
372  const DstOp &Dst, const SrcOp &BasePtr,
373  MachineMemOperand &BaseMMO, int64_t Offset) {
374  LLT LoadTy = Dst.getLLTTy(*getMRI());
375  MachineMemOperand *OffsetMMO =
376  getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy.getSizeInBytes());
377 
378  if (Offset == 0) // This may be a size or type changing load.
379  return buildLoad(Dst, BasePtr, *OffsetMMO);
380 
381  LLT PtrTy = BasePtr.getLLTTy(*getMRI());
382  LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
383  auto ConstOffset = buildConstant(OffsetTy, Offset);
384  auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
385  return buildLoad(Dst, Ptr, *OffsetMMO);
386 }
387 
389  const SrcOp &Addr,
390  MachineMemOperand &MMO) {
391  assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
392  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
393 
394  auto MIB = buildInstr(TargetOpcode::G_STORE);
395  Val.addSrcToMIB(MIB);
396  Addr.addSrcToMIB(MIB);
397  MIB.addMemOperand(&MMO);
398  return MIB;
399 }
400 
403  MachinePointerInfo PtrInfo, Align Alignment,
404  MachineMemOperand::Flags MMOFlags,
405  const AAMDNodes &AAInfo) {
406  MMOFlags |= MachineMemOperand::MOStore;
407  assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
408 
411  MachineMemOperand *MMO =
412  getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
413  return buildStore(Val, Addr, *MMO);
414 }
415 
417  const SrcOp &Op) {
418  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
419 }
420 
422  const SrcOp &Op) {
423  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
424 }
425 
427  const SrcOp &Op) {
428  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
429 }
430 
431 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
432  const auto *TLI = getMF().getSubtarget().getTargetLowering();
433  switch (TLI->getBooleanContents(IsVec, IsFP)) {
435  return TargetOpcode::G_SEXT;
437  return TargetOpcode::G_ZEXT;
438  default:
439  return TargetOpcode::G_ANYEXT;
440  }
441 }
442 
444  const SrcOp &Op,
445  bool IsFP) {
446  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
447  return buildInstr(ExtOp, Res, Op);
448 }
449 
451  const DstOp &Res,
452  const SrcOp &Op) {
453  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
454  TargetOpcode::G_SEXT == ExtOpc) &&
455  "Expecting Extending Opc");
456  assert(Res.getLLTTy(*getMRI()).isScalar() ||
457  Res.getLLTTy(*getMRI()).isVector());
458  assert(Res.getLLTTy(*getMRI()).isScalar() ==
459  Op.getLLTTy(*getMRI()).isScalar());
460 
461  unsigned Opcode = TargetOpcode::COPY;
462  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
463  Op.getLLTTy(*getMRI()).getSizeInBits())
464  Opcode = ExtOpc;
465  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
466  Op.getLLTTy(*getMRI()).getSizeInBits())
467  Opcode = TargetOpcode::G_TRUNC;
468  else
469  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
470 
471  return buildInstr(Opcode, Res, Op);
472 }
473 
475  const SrcOp &Op) {
476  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
477 }
478 
480  const SrcOp &Op) {
481  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
482 }
483 
485  const SrcOp &Op) {
486  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
487 }
488 
490  const SrcOp &Op,
491  int64_t ImmOp) {
492  LLT ResTy = Res.getLLTTy(*getMRI());
493  auto Mask = buildConstant(
494  ResTy, APInt::getLowBitsSet(ResTy.getScalarSizeInBits(), ImmOp));
495  return buildAnd(Res, Op, Mask);
496 }
497 
499  const SrcOp &Src) {
500  LLT SrcTy = Src.getLLTTy(*getMRI());
501  LLT DstTy = Dst.getLLTTy(*getMRI());
502  if (SrcTy == DstTy)
503  return buildCopy(Dst, Src);
504 
505  unsigned Opcode;
506  if (SrcTy.isPointer() && DstTy.isScalar())
507  Opcode = TargetOpcode::G_PTRTOINT;
508  else if (DstTy.isPointer() && SrcTy.isScalar())
509  Opcode = TargetOpcode::G_INTTOPTR;
510  else {
511  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
512  Opcode = TargetOpcode::G_BITCAST;
513  }
514 
515  return buildInstr(Opcode, Dst, Src);
516 }
517 
519  const SrcOp &Src,
520  uint64_t Index) {
521  LLT SrcTy = Src.getLLTTy(*getMRI());
522  LLT DstTy = Dst.getLLTTy(*getMRI());
523 
524 #ifndef NDEBUG
525  assert(SrcTy.isValid() && "invalid operand type");
526  assert(DstTy.isValid() && "invalid operand type");
527  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
528  "extracting off end of register");
529 #endif
530 
531  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
532  assert(Index == 0 && "insertion past the end of a register");
533  return buildCast(Dst, Src);
534  }
535 
536  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
537  Dst.addDefToMIB(*getMRI(), Extract);
538  Src.addSrcToMIB(Extract);
539  Extract.addImm(Index);
540  return Extract;
541 }
542 
544  ArrayRef<uint64_t> Indices) {
545 #ifndef NDEBUG
546  assert(Ops.size() == Indices.size() && "incompatible args");
547  assert(!Ops.empty() && "invalid trivial sequence");
548  assert(llvm::is_sorted(Indices) &&
549  "sequence offsets must be in ascending order");
550 
551  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
552  for (auto Op : Ops)
553  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
554 #endif
555 
556  LLT ResTy = getMRI()->getType(Res);
557  LLT OpTy = getMRI()->getType(Ops[0]);
558  unsigned OpSize = OpTy.getSizeInBits();
559  bool MaybeMerge = true;
560  for (unsigned i = 0; i < Ops.size(); ++i) {
561  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
562  MaybeMerge = false;
563  break;
564  }
565  }
566 
567  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
568  buildMerge(Res, Ops);
569  return;
570  }
571 
572  Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
573  buildUndef(ResIn);
574 
575  for (unsigned i = 0; i < Ops.size(); ++i) {
576  Register ResOut = i + 1 == Ops.size()
577  ? Res
579  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
580  ResIn = ResOut;
581  }
582 }
583 
585  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
586 }
587 
589  ArrayRef<Register> Ops) {
590  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
591  // we need some temporary storage for the DstOp objects. Here we use a
592  // sufficiently large SmallVector to not go through the heap.
593  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
594  assert(TmpVec.size() > 1);
595  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
596 }
597 
600  std::initializer_list<SrcOp> Ops) {
601  assert(Ops.size() > 1);
602  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
603 }
604 
606  const SrcOp &Op) {
607  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
608  // we need some temporary storage for the DstOp objects. Here we use a
609  // sufficiently large SmallVector to not go through the heap.
610  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
611  assert(TmpVec.size() > 1);
612  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
613 }
614 
616  const SrcOp &Op) {
617  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
619  for (unsigned I = 0; I != NumReg; ++I)
620  TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
621  return buildUnmerge(TmpVec, Op);
622 }
623 
625  const SrcOp &Op) {
626  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
627  // we need some temporary storage for the DstOp objects. Here we use a
628  // sufficiently large SmallVector to not go through the heap.
629  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
630  assert(TmpVec.size() > 1);
631  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
632 }
633 
635  ArrayRef<Register> Ops) {
636  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
637  // we need some temporary storage for the DstOp objects. Here we use a
638  // sufficiently large SmallVector to not go through the heap.
639  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
640  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
641 }
642 
644  const SrcOp &Src) {
645  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
646  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
647 }
648 
651  ArrayRef<Register> Ops) {
652  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
653  // we need some temporary storage for the DstOp objects. Here we use a
654  // sufficiently large SmallVector to not go through the heap.
655  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
656  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
657 }
658 
660  const SrcOp &Src) {
661  LLT DstTy = Res.getLLTTy(*getMRI());
662  assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
663  "Expected Src to match Dst elt ty");
664  auto UndefVec = buildUndef(DstTy);
665  auto Zero = buildConstant(LLT::scalar(64), 0);
666  auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
667  SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
668  return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
669 }
670 
672  const SrcOp &Src1,
673  const SrcOp &Src2,
675  LLT DstTy = Res.getLLTTy(*getMRI());
676  LLT Src1Ty = Src1.getLLTTy(*getMRI());
677  LLT Src2Ty = Src2.getLLTTy(*getMRI());
678  assert(Src1Ty.getNumElements() + Src2Ty.getNumElements() >= Mask.size());
679  assert(DstTy.getElementType() == Src1Ty.getElementType() &&
680  DstTy.getElementType() == Src2Ty.getElementType());
681  (void)Src1Ty;
682  (void)Src2Ty;
684  return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {DstTy}, {Src1, Src2})
685  .addShuffleMask(MaskAlloc);
686 }
687 
690  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
691  // we need some temporary storage for the DstOp objects. Here we use a
692  // sufficiently large SmallVector to not go through the heap.
693  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
694  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
695 }
696 
698  const SrcOp &Src,
699  const SrcOp &Op,
700  unsigned Index) {
701  assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
702  Res.getLLTTy(*getMRI()).getSizeInBits() &&
703  "insertion past the end of a register");
704 
705  if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
706  Op.getLLTTy(*getMRI()).getSizeInBits()) {
707  return buildCast(Res, Op);
708  }
709 
710  return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
711 }
712 
714  ArrayRef<Register> ResultRegs,
715  bool HasSideEffects) {
716  auto MIB =
717  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
718  : TargetOpcode::G_INTRINSIC);
719  for (unsigned ResultReg : ResultRegs)
720  MIB.addDef(ResultReg);
721  MIB.addIntrinsicID(ID);
722  return MIB;
723 }
724 
727  bool HasSideEffects) {
728  auto MIB =
729  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
730  : TargetOpcode::G_INTRINSIC);
731  for (DstOp Result : Results)
732  Result.addDefToMIB(*getMRI(), MIB);
733  MIB.addIntrinsicID(ID);
734  return MIB;
735 }
736 
738  const SrcOp &Op) {
739  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
740 }
741 
743  const SrcOp &Op,
744  Optional<unsigned> Flags) {
745  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
746 }
747 
749  const DstOp &Res,
750  const SrcOp &Op0,
751  const SrcOp &Op1) {
752  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
753 }
754 
756  const DstOp &Res,
757  const SrcOp &Op0,
758  const SrcOp &Op1,
759  Optional<unsigned> Flags) {
760 
761  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
762 }
763 
765  const SrcOp &Tst,
766  const SrcOp &Op0,
767  const SrcOp &Op1,
768  Optional<unsigned> Flags) {
769 
770  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
771 }
772 
775  const SrcOp &Elt, const SrcOp &Idx) {
776  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
777 }
778 
781  const SrcOp &Idx) {
782  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
783 }
784 
786  Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
787  Register NewVal, MachineMemOperand &MMO) {
788 #ifndef NDEBUG
789  LLT OldValResTy = getMRI()->getType(OldValRes);
790  LLT SuccessResTy = getMRI()->getType(SuccessRes);
791  LLT AddrTy = getMRI()->getType(Addr);
792  LLT CmpValTy = getMRI()->getType(CmpVal);
793  LLT NewValTy = getMRI()->getType(NewVal);
794  assert(OldValResTy.isScalar() && "invalid operand type");
795  assert(SuccessResTy.isScalar() && "invalid operand type");
796  assert(AddrTy.isPointer() && "invalid operand type");
797  assert(CmpValTy.isValid() && "invalid operand type");
798  assert(NewValTy.isValid() && "invalid operand type");
799  assert(OldValResTy == CmpValTy && "type mismatch");
800  assert(OldValResTy == NewValTy && "type mismatch");
801 #endif
802 
803  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
804  .addDef(OldValRes)
805  .addDef(SuccessRes)
806  .addUse(Addr)
807  .addUse(CmpVal)
808  .addUse(NewVal)
809  .addMemOperand(&MMO);
810 }
811 
814  Register CmpVal, Register NewVal,
815  MachineMemOperand &MMO) {
816 #ifndef NDEBUG
817  LLT OldValResTy = getMRI()->getType(OldValRes);
818  LLT AddrTy = getMRI()->getType(Addr);
819  LLT CmpValTy = getMRI()->getType(CmpVal);
820  LLT NewValTy = getMRI()->getType(NewVal);
821  assert(OldValResTy.isScalar() && "invalid operand type");
822  assert(AddrTy.isPointer() && "invalid operand type");
823  assert(CmpValTy.isValid() && "invalid operand type");
824  assert(NewValTy.isValid() && "invalid operand type");
825  assert(OldValResTy == CmpValTy && "type mismatch");
826  assert(OldValResTy == NewValTy && "type mismatch");
827 #endif
828 
829  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
830  .addDef(OldValRes)
831  .addUse(Addr)
832  .addUse(CmpVal)
833  .addUse(NewVal)
834  .addMemOperand(&MMO);
835 }
836 
838  unsigned Opcode, const DstOp &OldValRes,
839  const SrcOp &Addr, const SrcOp &Val,
840  MachineMemOperand &MMO) {
841 
842 #ifndef NDEBUG
843  LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
844  LLT AddrTy = Addr.getLLTTy(*getMRI());
845  LLT ValTy = Val.getLLTTy(*getMRI());
846  assert(OldValResTy.isScalar() && "invalid operand type");
847  assert(AddrTy.isPointer() && "invalid operand type");
848  assert(ValTy.isValid() && "invalid operand type");
849  assert(OldValResTy == ValTy && "type mismatch");
850  assert(MMO.isAtomic() && "not atomic mem operand");
851 #endif
852 
853  auto MIB = buildInstr(Opcode);
854  OldValRes.addDefToMIB(*getMRI(), MIB);
855  Addr.addSrcToMIB(MIB);
856  Val.addSrcToMIB(MIB);
857  MIB.addMemOperand(&MMO);
858  return MIB;
859 }
860 
863  Register Val, MachineMemOperand &MMO) {
864  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
865  MMO);
866 }
869  Register Val, MachineMemOperand &MMO) {
870  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
871  MMO);
872 }
875  Register Val, MachineMemOperand &MMO) {
876  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
877  MMO);
878 }
881  Register Val, MachineMemOperand &MMO) {
882  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
883  MMO);
884 }
887  Register Val, MachineMemOperand &MMO) {
888  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
889  MMO);
890 }
892  Register Addr,
893  Register Val,
894  MachineMemOperand &MMO) {
895  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
896  MMO);
897 }
900  Register Val, MachineMemOperand &MMO) {
901  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
902  MMO);
903 }
906  Register Val, MachineMemOperand &MMO) {
907  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
908  MMO);
909 }
912  Register Val, MachineMemOperand &MMO) {
913  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
914  MMO);
915 }
918  Register Val, MachineMemOperand &MMO) {
919  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
920  MMO);
921 }
924  Register Val, MachineMemOperand &MMO) {
925  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
926  MMO);
927 }
928 
931  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
932  MachineMemOperand &MMO) {
933  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
934  MMO);
935 }
936 
938 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
939  MachineMemOperand &MMO) {
940  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
941  MMO);
942 }
943 
945 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
946  return buildInstr(TargetOpcode::G_FENCE)
947  .addImm(Ordering)
948  .addImm(Scope);
949 }
950 
953 #ifndef NDEBUG
954  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
955 #endif
956 
957  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
958 }
959 
960 void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
961  bool IsExtend) {
962 #ifndef NDEBUG
963  if (DstTy.isVector()) {
964  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
965  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
966  "different number of elements in a trunc/ext");
967  } else
968  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
969 
970  if (IsExtend)
971  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
972  "invalid narrowing extend");
973  else
974  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
975  "invalid widening trunc");
976 #endif
977 }
978 
979 void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
980  const LLT Op0Ty, const LLT Op1Ty) {
981 #ifndef NDEBUG
982  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
983  "invalid operand type");
984  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
985  if (ResTy.isScalar() || ResTy.isPointer())
986  assert(TstTy.isScalar() && "type mismatch");
987  else
988  assert((TstTy.isScalar() ||
989  (TstTy.isVector() &&
990  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
991  "type mismatch");
992 #endif
993 }
994 
996  ArrayRef<DstOp> DstOps,
997  ArrayRef<SrcOp> SrcOps,
998  Optional<unsigned> Flags) {
999  switch (Opc) {
1000  default:
1001  break;
1002  case TargetOpcode::G_SELECT: {
1003  assert(DstOps.size() == 1 && "Invalid select");
1004  assert(SrcOps.size() == 3 && "Invalid select");
1006  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
1007  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
1008  break;
1009  }
1010  case TargetOpcode::G_FNEG:
1011  case TargetOpcode::G_ABS:
1012  // All these are unary ops.
1013  assert(DstOps.size() == 1 && "Invalid Dst");
1014  assert(SrcOps.size() == 1 && "Invalid Srcs");
1015  validateUnaryOp(DstOps[0].getLLTTy(*getMRI()),
1016  SrcOps[0].getLLTTy(*getMRI()));
1017  break;
1018  case TargetOpcode::G_ADD:
1019  case TargetOpcode::G_AND:
1020  case TargetOpcode::G_MUL:
1021  case TargetOpcode::G_OR:
1022  case TargetOpcode::G_SUB:
1023  case TargetOpcode::G_XOR:
1024  case TargetOpcode::G_UDIV:
1025  case TargetOpcode::G_SDIV:
1026  case TargetOpcode::G_UREM:
1027  case TargetOpcode::G_SREM:
1028  case TargetOpcode::G_SMIN:
1029  case TargetOpcode::G_SMAX:
1030  case TargetOpcode::G_UMIN:
1031  case TargetOpcode::G_UMAX:
1032  case TargetOpcode::G_UADDSAT:
1033  case TargetOpcode::G_SADDSAT:
1034  case TargetOpcode::G_USUBSAT:
1035  case TargetOpcode::G_SSUBSAT: {
1036  // All these are binary ops.
1037  assert(DstOps.size() == 1 && "Invalid Dst");
1038  assert(SrcOps.size() == 2 && "Invalid Srcs");
1039  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
1040  SrcOps[0].getLLTTy(*getMRI()),
1041  SrcOps[1].getLLTTy(*getMRI()));
1042  break;
1043  }
1044  case TargetOpcode::G_SHL:
1045  case TargetOpcode::G_ASHR:
1046  case TargetOpcode::G_LSHR:
1047  case TargetOpcode::G_USHLSAT:
1048  case TargetOpcode::G_SSHLSAT: {
1049  assert(DstOps.size() == 1 && "Invalid Dst");
1050  assert(SrcOps.size() == 2 && "Invalid Srcs");
1051  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
1052  SrcOps[0].getLLTTy(*getMRI()),
1053  SrcOps[1].getLLTTy(*getMRI()));
1054  break;
1055  }
1056  case TargetOpcode::G_SEXT:
1057  case TargetOpcode::G_ZEXT:
1058  case TargetOpcode::G_ANYEXT:
1059  assert(DstOps.size() == 1 && "Invalid Dst");
1060  assert(SrcOps.size() == 1 && "Invalid Srcs");
1061  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1062  SrcOps[0].getLLTTy(*getMRI()), true);
1063  break;
1064  case TargetOpcode::G_TRUNC:
1065  case TargetOpcode::G_FPTRUNC: {
1066  assert(DstOps.size() == 1 && "Invalid Dst");
1067  assert(SrcOps.size() == 1 && "Invalid Srcs");
1068  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1069  SrcOps[0].getLLTTy(*getMRI()), false);
1070  break;
1071  }
1072  case TargetOpcode::G_BITCAST: {
1073  assert(DstOps.size() == 1 && "Invalid Dst");
1074  assert(SrcOps.size() == 1 && "Invalid Srcs");
1075  assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1076  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
1077  break;
1078  }
1079  case TargetOpcode::COPY:
1080  assert(DstOps.size() == 1 && "Invalid Dst");
1081  // If the caller wants to add a subreg source it has to be done separately
1082  // so we may not have any SrcOps at this point yet.
1083  break;
1084  case TargetOpcode::G_FCMP:
1085  case TargetOpcode::G_ICMP: {
1086  assert(DstOps.size() == 1 && "Invalid Dst Operands");
1087  assert(SrcOps.size() == 3 && "Invalid Src Operands");
1088  // For F/ICMP, the first src operand is the predicate, followed by
1089  // the two comparands.
1090  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1091  "Expecting predicate");
1092  assert([&]() -> bool {
1093  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1094  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1095  : CmpInst::isFPPredicate(Pred);
1096  }() && "Invalid predicate");
1097  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1098  "Type mismatch");
1099  assert([&]() -> bool {
1100  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1101  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1102  if (Op0Ty.isScalar() || Op0Ty.isPointer())
1103  return DstTy.isScalar();
1104  else
1105  return DstTy.isVector() &&
1106  DstTy.getNumElements() == Op0Ty.getNumElements();
1107  }() && "Type Mismatch");
1108  break;
1109  }
1110  case TargetOpcode::G_UNMERGE_VALUES: {
1111  assert(!DstOps.empty() && "Invalid trivial sequence");
1112  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1113  assert(llvm::all_of(DstOps,
1114  [&, this](const DstOp &Op) {
1115  return Op.getLLTTy(*getMRI()) ==
1116  DstOps[0].getLLTTy(*getMRI());
1117  }) &&
1118  "type mismatch in output list");
1119  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1120  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1121  "input operands do not cover output register");
1122  break;
1123  }
1124  case TargetOpcode::G_MERGE_VALUES: {
1125  assert(!SrcOps.empty() && "invalid trivial sequence");
1126  assert(DstOps.size() == 1 && "Invalid Dst");
1127  assert(llvm::all_of(SrcOps,
1128  [&, this](const SrcOp &Op) {
1129  return Op.getLLTTy(*getMRI()) ==
1130  SrcOps[0].getLLTTy(*getMRI());
1131  }) &&
1132  "type mismatch in input list");
1133  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1134  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1135  "input operands do not cover output register");
1136  if (SrcOps.size() == 1)
1137  return buildCast(DstOps[0], SrcOps[0]);
1138  if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
1139  if (SrcOps[0].getLLTTy(*getMRI()).isVector())
1140  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1141  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1142  }
1143  break;
1144  }
1145  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1146  assert(DstOps.size() == 1 && "Invalid Dst size");
1147  assert(SrcOps.size() == 2 && "Invalid Src size");
1148  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1149  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1150  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1151  "Invalid operand type");
1152  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1153  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1154  DstOps[0].getLLTTy(*getMRI()) &&
1155  "Type mismatch");
1156  break;
1157  }
1158  case TargetOpcode::G_INSERT_VECTOR_ELT: {
1159  assert(DstOps.size() == 1 && "Invalid dst size");
1160  assert(SrcOps.size() == 3 && "Invalid src size");
1161  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1162  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1163  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1164  SrcOps[1].getLLTTy(*getMRI()) &&
1165  "Type mismatch");
1166  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1167  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1168  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1169  "Type mismatch");
1170  break;
1171  }
1172  case TargetOpcode::G_BUILD_VECTOR: {
1173  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1174  "Must have at least 2 operands");
1175  assert(DstOps.size() == 1 && "Invalid DstOps");
1176  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1177  "Res type must be a vector");
1178  assert(llvm::all_of(SrcOps,
1179  [&, this](const SrcOp &Op) {
1180  return Op.getLLTTy(*getMRI()) ==
1181  SrcOps[0].getLLTTy(*getMRI());
1182  }) &&
1183  "type mismatch in input list");
1184  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1185  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1186  "input scalars do not exactly cover the output vector register");
1187  break;
1188  }
1189  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1190  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1191  "Must have at least 2 operands");
1192  assert(DstOps.size() == 1 && "Invalid DstOps");
1193  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1194  "Res type must be a vector");
1195  assert(llvm::all_of(SrcOps,
1196  [&, this](const SrcOp &Op) {
1197  return Op.getLLTTy(*getMRI()) ==
1198  SrcOps[0].getLLTTy(*getMRI());
1199  }) &&
1200  "type mismatch in input list");
1201  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1202  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1203  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1204  break;
1205  }
1206  case TargetOpcode::G_CONCAT_VECTORS: {
1207  assert(DstOps.size() == 1 && "Invalid DstOps");
1208  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1209  "Must have at least 2 operands");
1210  assert(llvm::all_of(SrcOps,
1211  [&, this](const SrcOp &Op) {
1212  return (Op.getLLTTy(*getMRI()).isVector() &&
1213  Op.getLLTTy(*getMRI()) ==
1214  SrcOps[0].getLLTTy(*getMRI()));
1215  }) &&
1216  "type mismatch in input list");
1217  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1218  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1219  "input vectors do not exactly cover the output vector register");
1220  break;
1221  }
1222  case TargetOpcode::G_UADDE: {
1223  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1224  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1225  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1226  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1227  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1228  "Invalid operand");
1229  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1230  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1231  "type mismatch");
1232  break;
1233  }
1234  }
1235 
1236  auto MIB = buildInstr(Opc);
1237  for (const DstOp &Op : DstOps)
1238  Op.addDefToMIB(*getMRI(), MIB);
1239  for (const SrcOp &Op : SrcOps)
1240  Op.addSrcToMIB(MIB);
1241  if (Flags)
1242  MIB->setFlags(*Flags);
1243  return MIB;
1244 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:26
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:774
getSizeInBytes
static Optional< uint64_t > getSizeInBytes(Optional< uint64_t > SizeInBits)
Definition: AutoInitRemark.cpp:40
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
Definition: AllocatorList.h:23
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:837
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:748
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:163
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:50
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:134
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:424
getFunction
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:253
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:643
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:288
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:489
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:891
llvm::PointerType::getAddressSpace
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:677
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:479
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:121
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:316
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:868
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:813
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:117
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:285
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:742
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:295
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:634
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
MachineIRBuilder.h
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:450
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:49
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:487
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:938
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:945
llvm::LegalityPredicates::isPointer
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
Definition: LegalityPredicates.cpp:79
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1213
llvm::MemoryLocation::getSizeOrUnknown
static uint64_t getSizeOrUnknown(const TypeSize &T)
Definition: MemoryLocation.h:281
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:126
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:979
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:170
MachineRegisterInfo.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:219
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1274
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1482
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:568
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:785
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:605
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:911
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:426
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:780
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:840
llvm::CmpInst::isFPPredicate
bool isFPPredicate() const
Definition: InstrTypes.h:816
getScalarSizeInBits
static unsigned getScalarSizeInBits(Type *Ty)
Definition: SystemZTargetTransformInfo.cpp:366
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:73
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:443
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:234
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:484
llvm::LLT::getSizeInBytes
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:117
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:755
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:233
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:77
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:689
llvm::TypeSize::Fixed
static TypeSize Fixed(ScalarTy MinVal)
Definition: TypeSize.h:423
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:880
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:899
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1513
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:65
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:332
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:357
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:905
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:222
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:165
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:218
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:208
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:558
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::APFloat
Definition: APFloat.h:701
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:284
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:227
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:474
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.cpp:243
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.cpp:249
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:309
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
MemoryLocation.h
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
DebugInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:96
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:100
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:886
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:764
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:94
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:92
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:930
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:92
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:817
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:53
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:847
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:141
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFunction::allocateShuffleMask
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
Definition: MachineFunction.cpp:510
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
uint32_t
llvm::MachineIRBuilder::buildSequence
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
Definition: MachineIRBuilder.cpp:543
TargetSubtargetInfo.h
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:697
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:41
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:518
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:416
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:193
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:159
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LegalityPredicates::isScalar
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
Definition: LegalityPredicates.cpp:67
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:737
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:45
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1337
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:584
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:52
llvm::ConstantFP::get
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:946
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:923
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:671
llvm::is_sorted
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition: STLExtras.h:1553
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:899
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:267
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:264
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:39
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:952
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:960
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:87
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:917
llvm::LegalityPredicates::isVector
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Definition: LegalityPredicates.cpp:73
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:92
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:176
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:96
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:713
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:421
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:588
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:158
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:371
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:874
llvm::GlobalValue::getType
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:271
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:667
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:269
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:650
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:431
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:862
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:188
MachineFunction.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:43
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:498
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:659
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40