52 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
53 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
55 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
56 "Expected inlined-at fields to agree");
59 false, Reg, Variable, Expr));
65 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
66 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
68 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
69 "Expected inlined-at fields to agree");
72 true, Reg, Variable, Expr));
78 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
79 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
81 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
82 "Expected inlined-at fields to agree");
93 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
94 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
96 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
97 "Expected inlined-at fields to agree");
100 auto *NumericConstant = [&] () ->
const Constant* {
101 if (
const auto *CE = dyn_cast<ConstantExpr>(&
C))
102 if (CE->getOpcode() == Instruction::IntToPtr)
103 return CE->getOperand(0);
107 if (
auto *CI = dyn_cast<ConstantInt>(NumericConstant)) {
108 if (CI->getBitWidth() > 64)
111 MIB.addImm(CI->getZExtValue());
112 }
else if (
auto *CFP = dyn_cast<ConstantFP>(NumericConstant)) {
114 }
else if (isa<ConstantPointerNull>(NumericConstant)) {
121 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
126 assert(isa<DILabel>(Label) &&
"not a label");
127 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.
DL) &&
128 "Expected inlined-at fields to agree");
129 auto MIB =
buildInstr(TargetOpcode::DBG_LABEL);
131 return MIB.addMetadata(Label);
138 auto MIB =
buildInstr(TargetOpcode::G_DYN_STACKALLOC);
140 Size.addSrcToMIB(MIB);
141 MIB.addImm(Alignment.
value());
148 auto MIB =
buildInstr(TargetOpcode::G_FRAME_INDEX);
150 MIB.addFrameIndex(
Idx);
159 "address space mismatch");
161 auto MIB =
buildInstr(TargetOpcode::G_GLOBAL_VALUE);
163 MIB.addGlobalAddress(GV);
169 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
170 .addJumpTableIndex(JTI);
175 assert((Res == Op0) &&
"type mismatch");
181 assert((Res == Op0 && Res == Op1) &&
"type mismatch");
187 assert((Res == Op0) &&
"type mismatch");
197 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
200std::optional<MachineInstrBuilder>
203 assert(Res == 0 &&
"Res is a result argument");
222 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
234 "Different vector element types");
236 "Op0 has more elements");
240 for (
auto Op : Unmerge.getInstr()->defs())
244 for (
unsigned i = 0; i < NumberOfPadElts; ++i)
257 "Different vector element types");
259 "Op0 has fewer elements");
281 "Table reg must be a pointer");
290 return buildInstr(TargetOpcode::COPY, Res, Op);
298 "creating constant with the wrong size");
301 auto Const =
buildInstr(TargetOpcode::G_CONSTANT)
307 auto Const =
buildInstr(TargetOpcode::G_CONSTANT);
329 "creating fconstant with the wrong size");
334 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT)
341 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT);
344 Const.addFPImm(&Val);
374 auto MIB =
buildInstr(TargetOpcode::G_BRCOND);
403 Addr.addSrcToMIB(MIB);
404 MIB.addMemOperand(&MMO);
416 return buildLoad(Dst, BasePtr, *OffsetMMO);
433 Addr.addSrcToMIB(MIB);
434 MIB.addMemOperand(&MMO);
454 return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
459 return buildInstr(TargetOpcode::G_SEXT, Res, Op);
464 return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
469 switch (TLI->getBooleanContents(IsVec, IsFP)) {
471 return TargetOpcode::G_SEXT;
473 return TargetOpcode::G_ZEXT;
475 return TargetOpcode::G_ANYEXT;
491 switch (TLI->getBooleanContents(IsVector, IsFP)) {
506 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
507 TargetOpcode::G_SEXT == ExtOpc) &&
508 "Expecting Extending Opc");
512 Op.getLLTTy(*
getMRI()).isScalar());
514 unsigned Opcode = TargetOpcode::COPY;
516 Op.getLLTTy(*
getMRI()).getSizeInBits())
519 Op.getLLTTy(*
getMRI()).getSizeInBits())
520 Opcode = TargetOpcode::G_TRUNC;
560 Opcode = TargetOpcode::G_PTRTOINT;
562 Opcode = TargetOpcode::G_INTTOPTR;
565 Opcode = TargetOpcode::G_BITCAST;
581 "extracting off end of register");
585 assert(
Index == 0 &&
"insertion past the end of a register");
589 auto Extract =
buildInstr(TargetOpcode::G_EXTRACT);
590 Dst.addDefToMIB(*
getMRI(), Extract);
591 Src.addSrcToMIB(Extract);
592 Extract.addImm(
Index);
597 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
607 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
618 return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
623 std::initializer_list<SrcOp> Ops) {
625 return buildInstr(getOpcodeForMerge(Res, Ops), Res, Ops);
628unsigned MachineIRBuilder::getOpcodeForMerge(
const DstOp &
DstOp,
631 if (SrcOps[0].getLLTTy(*
getMRI()).isVector())
632 return TargetOpcode::G_CONCAT_VECTORS;
633 return TargetOpcode::G_BUILD_VECTOR;
636 return TargetOpcode::G_MERGE_VALUES;
646 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
653 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
663 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
672 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
681 for (
const auto &Op : Ops)
683 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
689 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
699 if (TmpVec[0].getLLTTy(*
getMRI()).getSizeInBits() ==
701 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
702 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
709 "Expected Src to match Dst elt ty");
732 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
733 .addShuffleMask(MaskAlloc);
742 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
751 "insertion past the end of a register");
754 Op.getLLTTy(*
getMRI()).getSizeInBits()) {
763 bool HasSideEffects) {
765 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
766 : TargetOpcode::G_INTRINSIC);
767 for (
unsigned ResultReg : ResultRegs)
768 MIB.addDef(ResultReg);
769 MIB.addIntrinsicID(
ID);
775 bool HasSideEffects) {
777 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
778 : TargetOpcode::G_INTRINSIC);
780 Result.addDefToMIB(*
getMRI(), MIB);
781 MIB.addIntrinsicID(
ID);
787 return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
792 std::optional<unsigned> Flags) {
793 return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
800 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
807 std::optional<unsigned> Flags) {
809 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
815 std::optional<unsigned> Flags) {
817 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
823 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt,
Idx});
829 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val,
Idx});
846 assert(OldValResTy == CmpValTy &&
"type mismatch");
847 assert(OldValResTy == NewValTy &&
"type mismatch");
850 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
872 assert(OldValResTy == CmpValTy &&
"type mismatch");
873 assert(OldValResTy == NewValTy &&
"type mismatch");
876 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
885 unsigned Opcode,
const DstOp &OldValRes,
896 assert(OldValResTy == ValTy &&
"type mismatch");
902 Addr.addSrcToMIB(MIB);
904 MIB.addMemOperand(&MMO);
1025 assert(SrcTy.
isVector() &&
"mismatched cast between vector and non-vector");
1027 "different number of elements in a trunc/ext");
1033 "invalid narrowing extend");
1036 "invalid widening trunc");
1041 const LLT Op0Ty,
const LLT Op1Ty) {
1044 "invalid operand type");
1045 assert((ResTy == Op0Ty && ResTy == Op1Ty) &&
"type mismatch");
1059 std::optional<unsigned> Flags) {
1063 case TargetOpcode::G_SELECT: {
1064 assert(DstOps.
size() == 1 &&
"Invalid select");
1065 assert(SrcOps.
size() == 3 &&
"Invalid select");
1067 DstOps[0].getLLTTy(*
getMRI()), SrcOps[0].getLLTTy(*
getMRI()),
1068 SrcOps[1].getLLTTy(*
getMRI()), SrcOps[2].getLLTTy(*
getMRI()));
1071 case TargetOpcode::G_FNEG:
1072 case TargetOpcode::G_ABS:
1075 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1077 SrcOps[0].getLLTTy(*
getMRI()));
1079 case TargetOpcode::G_ADD:
1080 case TargetOpcode::G_AND:
1081 case TargetOpcode::G_MUL:
1082 case TargetOpcode::G_OR:
1083 case TargetOpcode::G_SUB:
1084 case TargetOpcode::G_XOR:
1085 case TargetOpcode::G_UDIV:
1086 case TargetOpcode::G_SDIV:
1087 case TargetOpcode::G_UREM:
1088 case TargetOpcode::G_SREM:
1089 case TargetOpcode::G_SMIN:
1090 case TargetOpcode::G_SMAX:
1091 case TargetOpcode::G_UMIN:
1092 case TargetOpcode::G_UMAX:
1093 case TargetOpcode::G_UADDSAT:
1094 case TargetOpcode::G_SADDSAT:
1095 case TargetOpcode::G_USUBSAT:
1096 case TargetOpcode::G_SSUBSAT: {
1099 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1101 SrcOps[0].getLLTTy(*
getMRI()),
1102 SrcOps[1].getLLTTy(*
getMRI()));
1105 case TargetOpcode::G_SHL:
1106 case TargetOpcode::G_ASHR:
1107 case TargetOpcode::G_LSHR:
1108 case TargetOpcode::G_USHLSAT:
1109 case TargetOpcode::G_SSHLSAT: {
1111 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1113 SrcOps[0].getLLTTy(*
getMRI()),
1114 SrcOps[1].getLLTTy(*
getMRI()));
1117 case TargetOpcode::G_SEXT:
1118 case TargetOpcode::G_ZEXT:
1119 case TargetOpcode::G_ANYEXT:
1121 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1123 SrcOps[0].getLLTTy(*
getMRI()),
true);
1125 case TargetOpcode::G_TRUNC:
1126 case TargetOpcode::G_FPTRUNC: {
1128 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1130 SrcOps[0].getLLTTy(*
getMRI()),
false);
1133 case TargetOpcode::G_BITCAST: {
1135 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1136 assert(DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1137 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
"invalid bitcast");
1140 case TargetOpcode::COPY:
1145 case TargetOpcode::G_FCMP:
1146 case TargetOpcode::G_ICMP: {
1147 assert(DstOps.
size() == 1 &&
"Invalid Dst Operands");
1148 assert(SrcOps.
size() == 3 &&
"Invalid Src Operands");
1152 "Expecting predicate");
1157 }() &&
"Invalid predicate");
1161 LLT Op0Ty = SrcOps[1].getLLTTy(*
getMRI());
1162 LLT DstTy = DstOps[0].getLLTTy(*
getMRI());
1168 }() &&
"Type Mismatch");
1171 case TargetOpcode::G_UNMERGE_VALUES: {
1172 assert(!DstOps.
empty() &&
"Invalid trivial sequence");
1173 assert(SrcOps.
size() == 1 &&
"Invalid src for Unmerge");
1175 [&,
this](
const DstOp &Op) {
1176 return Op.getLLTTy(*
getMRI()) ==
1177 DstOps[0].getLLTTy(*
getMRI());
1179 "type mismatch in output list");
1181 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1182 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1183 "input operands do not cover output register");
1186 case TargetOpcode::G_MERGE_VALUES: {
1187 assert(SrcOps.
size() >= 2 &&
"invalid trivial sequence");
1190 [&,
this](
const SrcOp &Op) {
1191 return Op.getLLTTy(*
getMRI()) ==
1192 SrcOps[0].getLLTTy(*
getMRI());
1194 "type mismatch in input list");
1196 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1197 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1198 "input operands do not cover output register");
1200 "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");
1203 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1204 assert(DstOps.
size() == 1 &&
"Invalid Dst size");
1205 assert(SrcOps.
size() == 2 &&
"Invalid Src size");
1206 assert(SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1208 DstOps[0].getLLTTy(*
getMRI()).isPointer()) &&
1209 "Invalid operand type");
1210 assert(SrcOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand type");
1211 assert(SrcOps[0].getLLTTy(*
getMRI()).getElementType() ==
1212 DstOps[0].getLLTTy(*
getMRI()) &&
1216 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1217 assert(DstOps.
size() == 1 &&
"Invalid dst size");
1218 assert(SrcOps.
size() == 3 &&
"Invalid src size");
1220 SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1221 assert(DstOps[0].getLLTTy(*
getMRI()).getElementType() ==
1222 SrcOps[1].getLLTTy(*
getMRI()) &&
1224 assert(SrcOps[2].getLLTTy(*
getMRI()).isScalar() &&
"Invalid index");
1225 assert(DstOps[0].getLLTTy(*
getMRI()).getNumElements() ==
1226 SrcOps[0].getLLTTy(*
getMRI()).getNumElements() &&
1230 case TargetOpcode::G_BUILD_VECTOR: {
1232 "Must have at least 2 operands");
1233 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1235 "Res type must be a vector");
1237 [&,
this](
const SrcOp &Op) {
1238 return Op.getLLTTy(*
getMRI()) ==
1239 SrcOps[0].getLLTTy(*
getMRI());
1241 "type mismatch in input list");
1243 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1244 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1245 "input scalars do not exactly cover the output vector register");
1248 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1250 "Must have at least 2 operands");
1251 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1253 "Res type must be a vector");
1255 [&,
this](
const SrcOp &Op) {
1256 return Op.getLLTTy(*
getMRI()) ==
1257 SrcOps[0].getLLTTy(*
getMRI());
1259 "type mismatch in input list");
1262 case TargetOpcode::G_CONCAT_VECTORS: {
1263 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1265 "Must have at least 2 operands");
1267 [&,
this](
const SrcOp &Op) {
1268 return (Op.getLLTTy(*
getMRI()).isVector() &&
1269 Op.getLLTTy(*
getMRI()) ==
1270 SrcOps[0].getLLTTy(*
getMRI()));
1272 "type mismatch in input list");
1274 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1275 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1276 "input vectors do not exactly cover the output vector register");
1279 case TargetOpcode::G_UADDE: {
1280 assert(DstOps.
size() == 2 &&
"Invalid no of dst operands");
1281 assert(SrcOps.
size() == 3 &&
"Invalid no of src operands");
1282 assert(DstOps[0].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1284 (DstOps[0].getLLTTy(*
getMRI()) == SrcOps[1].getLLTTy(*
getMRI())) &&
1286 assert(DstOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1294 for (
const DstOp &Op : DstOps)
1295 Op.addDefToMIB(*
getMRI(), MIB);
1296 for (
const SrcOp &Op : SrcOps)
1297 Op.addSrcToMIB(MIB);
1299 MIB->setFlags(*Flags);
Function Alias Analysis Results
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static Function * getFunction(Constant *C)
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
This file declares the MachineIRBuilder class.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
const fltSemantics & getSemantics() const
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
The address of a basic block.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isFPPredicate() const
bool isIntPredicate() const
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
This is the shared class of boolean and integer constants.
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
This is an important base class in LLVM.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
PointerType * getType() const
Global values are always pointers.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr LLT getScalarType() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBundleIterator< MachineInstr > iterator
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
A description of a memory reference used in the backend.
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Flags
Flags values. These may be or'd together.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Wrapper class representing virtual and physical registers.
void reserve(size_type N)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
void addSrcToMIB(MachineInstrBuilder &MIB) const
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...