LLVM  16.0.0git
CSKYISelDAGToDAG.cpp
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1 //===-- CSKYISelDAGToDAG.cpp - A dag to dag inst selector for CSKY---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the CSKY target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "CSKY.h"
14 #include "CSKYSubtarget.h"
15 #include "CSKYTargetMachine.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "csky-isel"
24 
25 namespace {
26 class CSKYDAGToDAGISel : public SelectionDAGISel {
27  const CSKYSubtarget *Subtarget;
28 
29 public:
30  explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM) : SelectionDAGISel(TM) {}
31 
32  StringRef getPassName() const override {
33  return "CSKY DAG->DAG Pattern Instruction Selection";
34  }
35 
36  bool runOnMachineFunction(MachineFunction &MF) override {
37  // Reset the subtarget each time through.
38  Subtarget = &MF.getSubtarget<CSKYSubtarget>();
40  return true;
41  }
42 
43  void Select(SDNode *N) override;
44  bool selectAddCarry(SDNode *N);
45  bool selectSubCarry(SDNode *N);
46  bool selectBITCAST_TO_LOHI(SDNode *N);
47  bool selectInlineAsm(SDNode *N);
48 
50 
51  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
52  std::vector<SDValue> &OutOps) override;
53 
54 #include "CSKYGenDAGISel.inc"
55 };
56 } // namespace
57 
59  // If we have a custom node, we have already selected
60  if (N->isMachineOpcode()) {
61  LLVM_DEBUG(dbgs() << "== "; N->dump(CurDAG); dbgs() << "\n");
62  N->setNodeId(-1);
63  return;
64  }
65 
66  SDLoc Dl(N);
67  unsigned Opcode = N->getOpcode();
68  bool IsSelected = false;
69 
70  switch (Opcode) {
71  default:
72  break;
73  case ISD::ADDCARRY:
74  IsSelected = selectAddCarry(N);
75  break;
76  case ISD::SUBCARRY:
77  IsSelected = selectSubCarry(N);
78  break;
80  Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);
81  ReplaceNode(N, CurDAG->getRegister(GP, N->getValueType(0)).getNode());
82 
83  IsSelected = true;
84  break;
85  }
86  case ISD::FrameIndex: {
87  SDValue Imm = CurDAG->getTargetConstant(0, Dl, MVT::i32);
88  int FI = cast<FrameIndexSDNode>(N)->getIndex();
89  SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
90  ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32
91  : CSKY::ADDI16XZ,
92  Dl, MVT::i32, TFI, Imm));
93 
94  IsSelected = true;
95  break;
96  }
98  IsSelected = selectBITCAST_TO_LOHI(N);
99  break;
100  case ISD::INLINEASM:
101  case ISD::INLINEASM_BR:
102  IsSelected = selectInlineAsm(N);
103  break;
104  }
105 
106  if (IsSelected)
107  return;
108 
109  // Select the default instruction.
110  SelectCode(N);
111 }
112 
113 bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
114  std::vector<SDValue> AsmNodeOperands;
115  unsigned Flag, Kind;
116  bool Changed = false;
117  unsigned NumOps = N->getNumOperands();
118 
119  // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
120  // However, some instructions (e.g. mula.s32) require GPR pair.
121  // Since there is no constraint to explicitly specify a
122  // reg pair, we use GPRPair reg class for "%r" for 64-bit data.
123 
124  SDLoc dl(N);
125  SDValue Glue =
126  N->getGluedNode() ? N->getOperand(NumOps - 1) : SDValue(nullptr, 0);
127 
128  SmallVector<bool, 8> OpChanged;
129  // Glue node will be appended late.
130  for (unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e;
131  ++i) {
132  SDValue op = N->getOperand(i);
133  AsmNodeOperands.push_back(op);
134 
136  continue;
137 
138  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
139  Flag = C->getZExtValue();
141  } else
142  continue;
143 
144  // Immediate operands to inline asm in the SelectionDAG are modeled with
145  // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
146  // the second is a constant with the value of the immediate. If we get here
147  // and we have a Kind_Imm, skip the next operand, and continue.
148  if (Kind == InlineAsm::Kind_Imm) {
149  SDValue op = N->getOperand(++i);
150  AsmNodeOperands.push_back(op);
151  continue;
152  }
153 
154  unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
155  if (NumRegs)
156  OpChanged.push_back(false);
157 
158  unsigned DefIdx = 0;
159  bool IsTiedToChangedOp = false;
160  // If it's a use that is tied with a previous def, it has no
161  // reg class constraint.
162  if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
163  IsTiedToChangedOp = OpChanged[DefIdx];
164 
165  // Memory operands to inline asm in the SelectionDAG are modeled with two
166  // operands: a constant of value InlineAsm::Kind_Mem followed by the input
167  // operand. If we get here and we have a Kind_Mem, skip the next operand (so
168  // it doesn't get misinterpreted), and continue. We do this here because
169  // it's important to update the OpChanged array correctly before moving on.
170  if (Kind == InlineAsm::Kind_Mem) {
171  SDValue op = N->getOperand(++i);
172  AsmNodeOperands.push_back(op);
173  continue;
174  }
175 
178  continue;
179 
180  unsigned RC;
181  bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
182  if ((!IsTiedToChangedOp && (!HasRC || RC != CSKY::GPRRegClassID)) ||
183  NumRegs != 2)
184  continue;
185 
186  assert((i + 2 < NumOps) && "Invalid number of operands in inline asm");
187  SDValue V0 = N->getOperand(i + 1);
188  SDValue V1 = N->getOperand(i + 2);
189  unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
190  unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
191  SDValue PairedReg;
192  MachineRegisterInfo &MRI = MF->getRegInfo();
193 
194  if (Kind == InlineAsm::Kind_RegDef ||
196  // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
197  // the original GPRs.
198 
199  Register GPVR = MRI.createVirtualRegister(&CSKY::GPRPairRegClass);
200  PairedReg = CurDAG->getRegister(GPVR, MVT::i64);
201  SDValue Chain = SDValue(N, 0);
202 
203  SDNode *GU = N->getGluedUser();
204  SDValue RegCopy =
205  CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::i64, Chain.getValue(1));
206 
207  // Extract values from a GPRPair reg and copy to the original GPR reg.
208  SDValue Sub0 =
209  CurDAG->getTargetExtractSubreg(CSKY::sub32_0, dl, MVT::i32, RegCopy);
210  SDValue Sub1 =
211  CurDAG->getTargetExtractSubreg(CSKY::sub32_32, dl, MVT::i32, RegCopy);
212  SDValue T0 =
213  CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1));
214  SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
215 
216  // Update the original glue user.
217  std::vector<SDValue> Ops(GU->op_begin(), GU->op_end() - 1);
218  Ops.push_back(T1.getValue(1));
219  CurDAG->UpdateNodeOperands(GU, Ops);
220  } else {
221  // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
222  // GPRPair and then pass the GPRPair to the inline asm.
223  SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
224 
225  // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
226  SDValue T0 =
227  CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1));
228  SDValue T1 =
229  CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1));
230  SDValue Pair = SDValue(createGPRPairNode(MVT::i64, T0, T1), 0);
231 
232  // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
233  // i32 VRs of inline asm with it.
234  Register GPVR = MRI.createVirtualRegister(&CSKY::GPRPairRegClass);
235  PairedReg = CurDAG->getRegister(GPVR, MVT::i64);
236  Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
237 
238  AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
239  Glue = Chain.getValue(1);
240  }
241 
242  Changed = true;
243 
244  if (PairedReg.getNode()) {
245  OpChanged[OpChanged.size() - 1] = true;
246  Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
247  if (IsTiedToChangedOp)
249  else
250  Flag = InlineAsm::getFlagWordForRegClass(Flag, CSKY::GPRPairRegClassID);
251  // Replace the current flag.
252  AsmNodeOperands[AsmNodeOperands.size() - 1] =
253  CurDAG->getTargetConstant(Flag, dl, MVT::i32);
254  // Add the new register node and skip the original two GPRs.
255  AsmNodeOperands.push_back(PairedReg);
256  // Skip the next two GPRs.
257  i += 2;
258  }
259  }
260 
261  if (Glue.getNode())
262  AsmNodeOperands.push_back(Glue);
263  if (!Changed)
264  return false;
265 
266  SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
267  CurDAG->getVTList(MVT::Other, MVT::Glue),
268  AsmNodeOperands);
269  New->setNodeId(-1);
270  ReplaceNode(N, New.getNode());
271  return true;
272 }
273 
274 bool CSKYDAGToDAGISel::selectBITCAST_TO_LOHI(SDNode *N) {
275  SDLoc Dl(N);
276  auto VT = N->getValueType(0);
277  auto V = N->getOperand(0);
278 
279  if (!Subtarget->hasFPUv2DoubleFloat())
280  return false;
281 
282  SDValue V1 = SDValue(CurDAG->getMachineNode(CSKY::FMFVRL_D, Dl, VT, V), 0);
283  SDValue V2 = SDValue(CurDAG->getMachineNode(CSKY::FMFVRH_D, Dl, VT, V), 0);
284 
285  ReplaceUses(SDValue(N, 0), V1);
286  ReplaceUses(SDValue(N, 1), V2);
287  CurDAG->RemoveDeadNode(N);
288 
289  return true;
290 }
291 
292 bool CSKYDAGToDAGISel::selectAddCarry(SDNode *N) {
293  MachineSDNode *NewNode = nullptr;
294  auto Type0 = N->getValueType(0);
295  auto Type1 = N->getValueType(1);
296  auto Op0 = N->getOperand(0);
297  auto Op1 = N->getOperand(1);
298  auto Op2 = N->getOperand(2);
299 
300  SDLoc Dl(N);
301 
302  if (isNullConstant(Op2)) {
303  auto *CA = CurDAG->getMachineNode(
304  Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1);
305  NewNode = CurDAG->getMachineNode(
306  Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1},
307  {Op0, Op1, SDValue(CA, 0)});
308  } else if (isOneConstant(Op2)) {
309  auto *CA = CurDAG->getMachineNode(
310  Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1);
311  NewNode = CurDAG->getMachineNode(
312  Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1},
313  {Op0, Op1, SDValue(CA, 0)});
314  } else {
315  NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32
316  : CSKY::ADDC16,
317  Dl, {Type0, Type1}, {Op0, Op1, Op2});
318  }
319  ReplaceNode(N, NewNode);
320  return true;
321 }
322 
323 static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget,
324  SelectionDAG *DAG, SDLoc Dl, SDValue OldCarry) {
325  auto NewCarryReg =
326  DAG->getMachineNode(Subtarget->has2E3() ? CSKY::MVCV32 : CSKY::MVCV16, Dl,
327  MVT::i32, OldCarry);
328  auto NewCarry =
329  DAG->getMachineNode(Subtarget->hasE2() ? CSKY::BTSTI32 : CSKY::BTSTI16,
330  Dl, OldCarry.getValueType(), SDValue(NewCarryReg, 0),
331  DAG->getTargetConstant(0, Dl, MVT::i32));
332  return SDValue(NewCarry, 0);
333 }
334 
335 bool CSKYDAGToDAGISel::selectSubCarry(SDNode *N) {
336  MachineSDNode *NewNode = nullptr;
337  auto Type0 = N->getValueType(0);
338  auto Type1 = N->getValueType(1);
339  auto Op0 = N->getOperand(0);
340  auto Op1 = N->getOperand(1);
341  auto Op2 = N->getOperand(2);
342 
343  SDLoc Dl(N);
344 
345  if (isNullConstant(Op2)) {
346  auto *CA = CurDAG->getMachineNode(
347  Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1);
348  NewNode = CurDAG->getMachineNode(
349  Subtarget->has2E3() ? CSKY::SUBC32 : CSKY::SUBC16, Dl, {Type0, Type1},
350  {Op0, Op1, SDValue(CA, 0)});
351  } else if (isOneConstant(Op2)) {
352  auto *CA = CurDAG->getMachineNode(
353  Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1);
354  NewNode = CurDAG->getMachineNode(
355  Subtarget->has2E3() ? CSKY::SUBC32 : CSKY::SUBC16, Dl, {Type0, Type1},
356  {Op0, Op1, SDValue(CA, 0)});
357  } else {
358  auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2);
359  NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::SUBC32
360  : CSKY::SUBC16,
361  Dl, {Type0, Type1}, {Op0, Op1, CarryIn});
362  }
363  auto CarryOut = InvertCarryFlag(Subtarget, CurDAG, Dl, SDValue(NewNode, 1));
364 
365  ReplaceUses(SDValue(N, 0), SDValue(NewNode, 0));
366  ReplaceUses(SDValue(N, 1), CarryOut);
367  CurDAG->RemoveDeadNode(N);
368 
369  return true;
370 }
371 
373  SDLoc dl(V0.getNode());
374  SDValue RegClass =
375  CurDAG->getTargetConstant(CSKY::GPRPairRegClassID, dl, MVT::i32);
376  SDValue SubReg0 = CurDAG->getTargetConstant(CSKY::sub32_0, dl, MVT::i32);
377  SDValue SubReg1 = CurDAG->getTargetConstant(CSKY::sub32_32, dl, MVT::i32);
378  const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1};
379  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
380 }
381 
382 bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
383  const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
384  switch (ConstraintID) {
386  // We just support simple memory operands that have a single address
387  // operand and need no special handling.
388  OutOps.push_back(Op);
389  return false;
390  default:
391  break;
392  }
393 
394  return true;
395 }
396 
398  return new CSKYDAGToDAGISel(TM);
399 }
i
i
Definition: README.txt:29
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:242
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1581
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InvertCarryFlag
static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget, SelectionDAG *DAG, SDLoc Dl, SDValue OldCarry)
Definition: CSKYISelDAGToDAG.cpp:323
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1103
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::isOneConstant
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Definition: SelectionDAG.cpp:10728
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2889
CSKYTargetMachine.h
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:272
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:361
CSKY.h
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:239
SelectionDAG.h
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:240
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::createCSKYISelDag
FunctionPass * createCSKYISelDag(CSKYTargetMachine &TM)
Definition: CSKYISelDAGToDAG.cpp:397
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SDNode::op_end
op_iterator op_end() const
Definition: SelectionDAGNodes.h:926
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1138
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
CSKYSubtarget.h
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ISD::GLOBAL_OFFSET_TABLE
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:87
llvm::InlineAsm::Op_InputChain
@ Op_InputChain
Definition: InlineAsm.h:216
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::CSKYSubtarget
Definition: CSKYSubtarget.h:30
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:344
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:54
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:220
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:238
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
CSKYMCTargetDesc.h
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9742
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::InlineAsm::getFlagWordForRegClass
static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC)
getFlagWordForRegClass - Augment an existing flag word returned by getFlagWord with the required regi...
Definition: InlineAsm.h:319
SelectionDAGISel.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::InlineAsm::getFlagWord
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
Definition: InlineAsm.h:288
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
llvm::CSKYTargetMachine
Definition: CSKYTargetMachine.h:22
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InlineAsm::getFlagWordForMatchingOp
static unsigned getFlagWordForMatchingOp(unsigned InputFlag, unsigned MatchedOperandNo)
getFlagWordForMatchingOp - Augment an existing flag word returned by getFlagWord with information ind...
Definition: InlineAsm.h:307
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::NVPTX::PTXLdStInstCode::V2
@ V2
Definition: NVPTX.h:123
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:370
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10713
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
MachineFrameInfo.h
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::InlineAsm::Constraint_m
@ Constraint_m
Definition: InlineAsm.h:255
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SDNode::op_begin
op_iterator op_begin() const
Definition: SelectionDAGNodes.h:925
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:41
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:355
N
#define N
llvm::CSKYSubtarget::hasE2
bool hasE2() const
Definition: CSKYSubtarget.h:187
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:666
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::CSKYISD::BITCAST_TO_LOHI
@ BITCAST_TO_LOHI
Definition: CSKYISelLowering.h:36
llvm::CSKYSubtarget::has2E3
bool has2E3() const
Definition: CSKYSubtarget.h:188
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:373
createGPRPairNode
static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V)
Definition: AArch64ISelLowering.cpp:20633
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:243