31#define DEBUG_TYPE "mccodeemitter"
41 mutable unsigned Offset;
57 unsigned getMemOpValue(
const MCInst &
MI,
unsigned Op,
61 unsigned getPCRelImmOpValue(
const MCInst &
MI,
unsigned Op,
65 unsigned getCGImmOpValue(
const MCInst &
MI,
unsigned Op,
69 unsigned getCCOpValue(
const MCInst &
MI,
unsigned Op,
75 : Ctx(ctx), MCII(MCII) {}
93 uint64_t BinaryOpCode = getBinaryCodeForInstr(
MI, Fixups, STI);
94 size_t WordCount =
Size / 2;
102unsigned MSP430MCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
121unsigned MSP430MCCodeEmitter::getMemOpValue(
const MCInst &
MI,
unsigned Op,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI)
const {
124 const MCOperand &MO1 =
MI.getOperand(
Op);
125 assert(MO1.isReg() &&
"Register operand expected");
128 const MCOperand &MO2 =
MI.getOperand(
Op + 1);
131 return ((
unsigned)MO2.getImm() << 4) |
Reg;
134 assert(MO2.isExpr() &&
"Expr operand expected");
153unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(
const MCInst &
MI,
unsigned Op,
154 SmallVectorImpl<MCFixup> &Fixups,
155 const MCSubtargetInfo &STI)
const {
156 const MCOperand &MO =
MI.getOperand(
Op);
160 assert(MO.isExpr() &&
"Expr operand expected");
166unsigned MSP430MCCodeEmitter::getCGImmOpValue(
const MCInst &
MI,
unsigned Op,
167 SmallVectorImpl<MCFixup> &Fixups,
168 const MCSubtargetInfo &STI)
const {
169 const MCOperand &MO =
MI.getOperand(
Op);
170 assert(MO.isImm() &&
"Expr operand expected");
172 int64_t
Imm = MO.getImm();
181 case -1:
return 0x33;
185unsigned MSP430MCCodeEmitter::getCCOpValue(
const MCInst &
MI,
unsigned Op,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI)
const {
188 const MCOperand &MO =
MI.getOperand(
Op);
189 assert(MO.isImm() &&
"Immediate operand expected");
190 switch (MO.getImm()) {
208#include "MSP430GenMCCodeEmitter.inc"
This file declares a class to represent arbitrary precision floating point values and provide a varie...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
Encode the given Inst to bytes and append to CB.
MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createMSP430MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Creates a machine code emitter for MSP430.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
DWARFExpression::Operation Op
Description of the encoding of one expression Op.