LLVM  14.0.0git
SystemZShortenInst.cpp
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1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass tries to replace instructions with shorter forms. For example,
10 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
11 // other 32 bits of the GR64 destination are not live.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "SystemZTargetMachine.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "systemz-shorten-inst"
24 
25 namespace {
26 class SystemZShortenInst : public MachineFunctionPass {
27 public:
28  static char ID;
29  SystemZShortenInst(const SystemZTargetMachine &tm);
30 
31  StringRef getPassName() const override {
32  return "SystemZ Instruction Shortening";
33  }
34 
35  bool processBlock(MachineBasicBlock &MBB);
36  bool runOnMachineFunction(MachineFunction &F) override;
37  MachineFunctionProperties getRequiredProperties() const override {
40  }
41 
42 private:
43  bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44  bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45  bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46  bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47  bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48  bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
49  bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
50 
51  const SystemZInstrInfo *TII;
52  const TargetRegisterInfo *TRI;
53  LivePhysRegs LiveRegs;
54 };
55 
56 char SystemZShortenInst::ID = 0;
57 } // end anonymous namespace
58 
60  return new SystemZShortenInst(TM);
61 }
62 
63 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
64  : MachineFunctionPass(ID), TII(nullptr) {}
65 
66 // Tie operands if MI has become a two-address instruction.
68  if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
69  !MI.getOperand(0).isTied())
70  MI.tieOperands(0, 1);
71 }
72 
73 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
74 // are the halfword immediate loads for the same word. Try to use one of them
75 // instead of IIxF.
76 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
77  unsigned LLIxH) {
78  Register Reg = MI.getOperand(0).getReg();
79  // The new opcode will clear the other half of the GR64 reg, so
80  // cancel if that is live.
81  unsigned thisSubRegIdx =
82  (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83  : SystemZ::subreg_l32);
84  unsigned otherSubRegIdx =
85  (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86  : SystemZ::subreg_l32);
87  unsigned GR64BitReg =
88  TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
89  Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
90  if (LiveRegs.contains(OtherReg))
91  return false;
92 
93  uint64_t Imm = MI.getOperand(1).getImm();
94  if (SystemZ::isImmLL(Imm)) {
95  MI.setDesc(TII->get(LLIxL));
96  MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
97  return true;
98  }
99  if (SystemZ::isImmLH(Imm)) {
100  MI.setDesc(TII->get(LLIxH));
101  MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
102  MI.getOperand(1).setImm(Imm >> 16);
103  return true;
104  }
105  return false;
106 }
107 
108 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
110  if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
111  MI.setDesc(TII->get(Opcode));
112  return true;
113  }
114  return false;
115 }
116 
117 // Change MI's opcode to Opcode if register operands 0 and 1 have a
118 // 4-bit encoding.
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
120  if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121  SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
122  MI.setDesc(TII->get(Opcode));
123  return true;
124  }
125  return false;
126 }
127 
128 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
129 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
130 // with op 1, if MI becomes 2-address.
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
132  if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133  MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134  SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
135  MI.setDesc(TII->get(Opcode));
137  return true;
138  }
139  return false;
140 }
141 
142 // Calls shortenOn001 if CCLive is false. CC def operand is added in
143 // case of success.
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
145  if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
146  MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
148  return true;
149  }
150  return false;
151 }
152 
153 // MI is a vector-style conversion instruction with the operand order:
154 // destination, source, exact-suppress, rounding-mode. If both registers
155 // have a 4-bit encoding then change it to Opcode, which has operand order:
156 // destination, rouding-mode, source, exact-suppress.
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
158  if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159  SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
160  MachineOperand Dest(MI.getOperand(0));
161  MachineOperand Src(MI.getOperand(1));
162  MachineOperand Suppress(MI.getOperand(2));
163  MachineOperand Mode(MI.getOperand(3));
164  MI.RemoveOperand(3);
165  MI.RemoveOperand(2);
166  MI.RemoveOperand(1);
167  MI.RemoveOperand(0);
168  MI.setDesc(TII->get(Opcode));
169  MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
170  .add(Dest)
171  .add(Mode)
172  .add(Src)
173  .add(Suppress);
174  return true;
175  }
176  return false;
177 }
178 
179 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {
180  MachineOperand &DstMO = MI.getOperand(0);
181  MachineOperand &LHSMO = MI.getOperand(1);
182  MachineOperand &RHSMO = MI.getOperand(2);
183  MachineOperand &AccMO = MI.getOperand(3);
184  if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 &&
185  SystemZMC::getFirstReg(LHSMO.getReg()) < 16 &&
186  SystemZMC::getFirstReg(RHSMO.getReg()) < 16 &&
187  SystemZMC::getFirstReg(AccMO.getReg()) < 16 &&
188  DstMO.getReg() == AccMO.getReg()) {
189  MachineOperand Lhs(LHSMO);
190  MachineOperand Rhs(RHSMO);
191  MachineOperand Src(AccMO);
192  MI.RemoveOperand(3);
193  MI.RemoveOperand(2);
194  MI.RemoveOperand(1);
195  MI.setDesc(TII->get(Opcode));
196  MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
197  .add(Src)
198  .add(Lhs)
199  .add(Rhs);
200  return true;
201  }
202  return false;
203 }
204 
205 // Process all instructions in MBB. Return true if something changed.
206 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
207  bool Changed = false;
208 
209  // Set up the set of live registers at the end of MBB (live out)
210  LiveRegs.clear();
211  LiveRegs.addLiveOuts(MBB);
212 
213  // Iterate backwards through the block looking for instructions to change.
214  for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
215  MachineInstr &MI = *MBBI;
216  switch (MI.getOpcode()) {
217  case SystemZ::IILF:
218  Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
219  break;
220 
221  case SystemZ::IIHF:
222  Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
223  break;
224 
225  case SystemZ::WFADB:
226  Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
227  break;
228 
229  case SystemZ::WFASB:
230  Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
231  break;
232 
233  case SystemZ::WFDDB:
234  Changed |= shortenOn001(MI, SystemZ::DDBR);
235  break;
236 
237  case SystemZ::WFDSB:
238  Changed |= shortenOn001(MI, SystemZ::DEBR);
239  break;
240 
241  case SystemZ::WFIDB:
242  Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
243  break;
244 
245  case SystemZ::WFISB:
246  Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
247  break;
248 
249  case SystemZ::WLDEB:
250  Changed |= shortenOn01(MI, SystemZ::LDEBR);
251  break;
252 
253  case SystemZ::WLEDB:
254  Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
255  break;
256 
257  case SystemZ::WFMDB:
258  Changed |= shortenOn001(MI, SystemZ::MDBR);
259  break;
260 
261  case SystemZ::WFMSB:
262  Changed |= shortenOn001(MI, SystemZ::MEEBR);
263  break;
264 
265  case SystemZ::WFMADB:
266  Changed |= shortenFusedFPOp(MI, SystemZ::MADBR);
267  break;
268 
269  case SystemZ::WFMASB:
270  Changed |= shortenFusedFPOp(MI, SystemZ::MAEBR);
271  break;
272 
273  case SystemZ::WFMSDB:
274  Changed |= shortenFusedFPOp(MI, SystemZ::MSDBR);
275  break;
276 
277  case SystemZ::WFMSSB:
278  Changed |= shortenFusedFPOp(MI, SystemZ::MSEBR);
279  break;
280 
281  case SystemZ::WFLCDB:
282  Changed |= shortenOn01(MI, SystemZ::LCDFR);
283  break;
284 
285  case SystemZ::WFLCSB:
286  Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
287  break;
288 
289  case SystemZ::WFLNDB:
290  Changed |= shortenOn01(MI, SystemZ::LNDFR);
291  break;
292 
293  case SystemZ::WFLNSB:
294  Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
295  break;
296 
297  case SystemZ::WFLPDB:
298  Changed |= shortenOn01(MI, SystemZ::LPDFR);
299  break;
300 
301  case SystemZ::WFLPSB:
302  Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
303  break;
304 
305  case SystemZ::WFSQDB:
306  Changed |= shortenOn01(MI, SystemZ::SQDBR);
307  break;
308 
309  case SystemZ::WFSQSB:
310  Changed |= shortenOn01(MI, SystemZ::SQEBR);
311  break;
312 
313  case SystemZ::WFSDB:
314  Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
315  break;
316 
317  case SystemZ::WFSSB:
318  Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
319  break;
320 
321  case SystemZ::WFCDB:
322  Changed |= shortenOn01(MI, SystemZ::CDBR);
323  break;
324 
325  case SystemZ::WFCSB:
326  Changed |= shortenOn01(MI, SystemZ::CEBR);
327  break;
328 
329  case SystemZ::WFKDB:
330  Changed |= shortenOn01(MI, SystemZ::KDBR);
331  break;
332 
333  case SystemZ::WFKSB:
334  Changed |= shortenOn01(MI, SystemZ::KEBR);
335  break;
336 
337  case SystemZ::VL32:
338  // For z13 we prefer LDE over LE to avoid partial register dependencies.
339  Changed |= shortenOn0(MI, SystemZ::LDE32);
340  break;
341 
342  case SystemZ::VST32:
343  Changed |= shortenOn0(MI, SystemZ::STE);
344  break;
345 
346  case SystemZ::VL64:
347  Changed |= shortenOn0(MI, SystemZ::LD);
348  break;
349 
350  case SystemZ::VST64:
351  Changed |= shortenOn0(MI, SystemZ::STD);
352  break;
353 
354  default: {
355  int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
356  if (TwoOperandOpcode == -1)
357  break;
358 
359  if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
360  (!MI.isCommutable() ||
361  MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
362  !TII->commuteInstruction(MI, false, 1, 2)))
363  break;
364 
365  MI.setDesc(TII->get(TwoOperandOpcode));
366  MI.tieOperands(0, 1);
367  if (TwoOperandOpcode == SystemZ::SLL ||
368  TwoOperandOpcode == SystemZ::SLA ||
369  TwoOperandOpcode == SystemZ::SRL ||
370  TwoOperandOpcode == SystemZ::SRA) {
371  // These shifts only use the low 6 bits of the shift count.
372  MachineOperand &ImmMO = MI.getOperand(3);
373  ImmMO.setImm(ImmMO.getImm() & 0xfff);
374  }
375  Changed = true;
376  break;
377  }
378  }
379 
380  LiveRegs.stepBackward(MI);
381  }
382 
383  return Changed;
384 }
385 
386 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
387  if (skipFunction(F.getFunction()))
388  return false;
389 
390  const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
391  TII = ST.getInstrInfo();
392  TRI = ST.getRegisterInfo();
393  LiveRegs.init(*TRI);
394 
395  bool Changed = false;
396  for (auto &MBB : F)
397  Changed |= processBlock(MBB);
398 
399  return Changed;
400 }
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