LLVM  13.0.0git
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
17 #include "WebAssembly.h"
19 #include "WebAssemblySubtarget.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "wasm-instr-info"
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30 
31 // defines WebAssembly::getNamedOperandIdx
32 #define GET_INSTRINFO_NAMED_OPS
33 #include "WebAssemblyGenInstrInfo.inc"
34 
36  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
37  WebAssembly::ADJCALLSTACKUP,
38  WebAssembly::CATCHRET),
39  RI(STI.getTargetTriple()) {}
40 
42  const MachineInstr &MI, AAResults *AA) const {
43  switch (MI.getOpcode()) {
44  case WebAssembly::CONST_I32:
45  case WebAssembly::CONST_I64:
46  case WebAssembly::CONST_F32:
47  case WebAssembly::CONST_F64:
48  // isReallyTriviallyReMaterializableGeneric misses these because of the
49  // ARGUMENTS implicit def, so we manualy override it here.
50  return true;
51  default:
52  return false;
53  }
54 }
55 
58  const DebugLoc &DL, MCRegister DestReg,
59  MCRegister SrcReg, bool KillSrc) const {
60  // This method is called by post-RA expansion, which expects only pregs to
61  // exist. However we need to handle both here.
62  auto &MRI = MBB.getParent()->getRegInfo();
63  const TargetRegisterClass *RC =
65  ? MRI.getRegClass(DestReg)
67 
68  unsigned CopyOpcode;
69  if (RC == &WebAssembly::I32RegClass)
70  CopyOpcode = WebAssembly::COPY_I32;
71  else if (RC == &WebAssembly::I64RegClass)
72  CopyOpcode = WebAssembly::COPY_I64;
73  else if (RC == &WebAssembly::F32RegClass)
74  CopyOpcode = WebAssembly::COPY_F32;
75  else if (RC == &WebAssembly::F64RegClass)
76  CopyOpcode = WebAssembly::COPY_F64;
77  else if (RC == &WebAssembly::V128RegClass)
78  CopyOpcode = WebAssembly::COPY_V128;
79  else if (RC == &WebAssembly::FUNCREFRegClass)
80  CopyOpcode = WebAssembly::COPY_FUNCREF;
81  else if (RC == &WebAssembly::EXTERNREFRegClass)
82  CopyOpcode = WebAssembly::COPY_EXTERNREF;
83  else
84  llvm_unreachable("Unexpected register class");
85 
86  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
87  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
88 }
89 
91  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
92  // If the operands are stackified, we can't reorder them.
94  *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
95  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
96  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
97  return nullptr;
98 
99  // Otherwise use the default implementation.
100  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
101 }
102 
103 // Branch analysis.
105  MachineBasicBlock *&TBB,
106  MachineBasicBlock *&FBB,
108  bool /*AllowModify*/) const {
109  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
110  // WebAssembly has control flow that doesn't have explicit branches or direct
111  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
112  // is created after CFGStackify.
113  if (MFI.isCFGStackified())
114  return true;
115 
116  bool HaveCond = false;
117  for (MachineInstr &MI : MBB.terminators()) {
118  switch (MI.getOpcode()) {
119  default:
120  // Unhandled instruction; bail out.
121  return true;
122  case WebAssembly::BR_IF:
123  if (HaveCond)
124  return true;
125  Cond.push_back(MachineOperand::CreateImm(true));
126  Cond.push_back(MI.getOperand(1));
127  TBB = MI.getOperand(0).getMBB();
128  HaveCond = true;
129  break;
130  case WebAssembly::BR_UNLESS:
131  if (HaveCond)
132  return true;
133  Cond.push_back(MachineOperand::CreateImm(false));
134  Cond.push_back(MI.getOperand(1));
135  TBB = MI.getOperand(0).getMBB();
136  HaveCond = true;
137  break;
138  case WebAssembly::BR:
139  if (!HaveCond)
140  TBB = MI.getOperand(0).getMBB();
141  else
142  FBB = MI.getOperand(0).getMBB();
143  break;
144  }
145  if (MI.isBarrier())
146  break;
147  }
148 
149  return false;
150 }
151 
153  int *BytesRemoved) const {
154  assert(!BytesRemoved && "code size not handled");
155 
157  unsigned Count = 0;
158 
159  while (I != MBB.instr_begin()) {
160  --I;
161  if (I->isDebugInstr())
162  continue;
163  if (!I->isTerminator())
164  break;
165  // Remove the branch.
166  I->eraseFromParent();
167  I = MBB.instr_end();
168  ++Count;
169  }
170 
171  return Count;
172 }
173 
176  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
177  assert(!BytesAdded && "code size not handled");
178 
179  if (Cond.empty()) {
180  if (!TBB)
181  return 0;
182 
184  return 1;
185  }
186 
187  assert(Cond.size() == 2 && "Expected a flag and a successor block");
188 
189  if (Cond[0].getImm())
190  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
191  else
192  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
193  if (!FBB)
194  return 1;
195 
197  return 2;
198 }
199 
202  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
203  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
204  return false;
205 }
206 
209  static const std::pair<int, const char *> TargetIndices[] = {
210  {WebAssembly::TI_LOCAL, "wasm-local"},
211  {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
212  {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
213  {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
214  {WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
215  return makeArrayRef(TargetIndices);
216 }
llvm::WebAssemblyInstrInfo::WebAssemblyInstrInfo
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
Definition: WebAssemblyInstrInfo.cpp:35
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::WebAssemblyInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: WebAssemblyInstrInfo.cpp:174
llvm
Definition: AllocatorList.h:23
WebAssembly.h
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::WebAssemblyInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: WebAssemblyInstrInfo.cpp:90
llvm::WebAssemblyInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: WebAssemblyInstrInfo.cpp:56
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:288
MachineRegisterInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:167
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:147
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:770
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:984
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
WebAssemblyInstrInfo.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:49
llvm::WebAssemblyInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: WebAssemblyInstrInfo.cpp:41
llvm::WebAssembly::TI_OPERAND_STACK
@ TI_OPERAND_STACK
Definition: WebAssembly.h:91
llvm::WebAssembly::TI_GLOBAL_RELOC
@ TI_GLOBAL_RELOC
Definition: WebAssembly.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
WebAssemblyMCTargetDesc.h
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
WebAssemblyGenInstrInfo
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::WebAssemblyInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: WebAssemblyInstrInfo.cpp:200
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::WebAssemblyFunctionInfo::isVRegStackified
bool isVRegStackified(unsigned VReg) const
Definition: WebAssemblyMachineFunctionInfo.h:136
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::WebAssemblyFunctionInfo
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Definition: WebAssemblyMachineFunctionInfo.h:33
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
WebAssemblyMachineFunctionInfo.h
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::WebAssemblyInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: WebAssemblyInstrInfo.cpp:104
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::WebAssemblyInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: WebAssemblyInstrInfo.cpp:208
llvm::WebAssembly::TI_GLOBAL_FIXED
@ TI_GLOBAL_FIXED
Definition: WebAssembly.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::WebAssembly::TI_LOCAL
@ TI_LOCAL
Definition: WebAssembly.h:87
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:922
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::WebAssembly::TI_LOCAL_INDIRECT
@ TI_LOCAL_INDIRECT
Definition: WebAssembly.h:97
WebAssemblySubtarget.h
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::WebAssemblyInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: WebAssemblyInstrInfo.cpp:152
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22