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26 #define DEBUG_TYPE "wasm-instr-info"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
32 #define GET_INSTRINFO_NAMED_OPS
33 #include "WebAssemblyGenInstrInfo.inc"
37 WebAssembly::ADJCALLSTACKUP,
39 RI(STI.getTargetTriple()) {}
43 switch (
MI.getOpcode()) {
44 case WebAssembly::CONST_I32:
45 case WebAssembly::CONST_I64:
46 case WebAssembly::CONST_F32:
47 case WebAssembly::CONST_F64:
69 if (RC == &WebAssembly::I32RegClass)
70 CopyOpcode = WebAssembly::COPY_I32;
71 else if (RC == &WebAssembly::I64RegClass)
72 CopyOpcode = WebAssembly::COPY_I64;
73 else if (RC == &WebAssembly::F32RegClass)
74 CopyOpcode = WebAssembly::COPY_F32;
75 else if (RC == &WebAssembly::F64RegClass)
76 CopyOpcode = WebAssembly::COPY_F64;
77 else if (RC == &WebAssembly::V128RegClass)
78 CopyOpcode = WebAssembly::COPY_V128;
79 else if (RC == &WebAssembly::FUNCREFRegClass)
80 CopyOpcode = WebAssembly::COPY_FUNCREF;
81 else if (RC == &WebAssembly::EXTERNREFRegClass)
82 CopyOpcode = WebAssembly::COPY_EXTERNREF;
91 MachineInstr &
MI,
bool NewMI,
unsigned OpIdx1,
unsigned OpIdx2)
const {
113 if (MFI.isCFGStackified())
116 bool HaveCond =
false;
118 switch (
MI.getOpcode()) {
122 case WebAssembly::BR_IF:
126 Cond.push_back(
MI.getOperand(1));
127 TBB =
MI.getOperand(0).getMBB();
130 case WebAssembly::BR_UNLESS:
134 Cond.push_back(
MI.getOperand(1));
135 TBB =
MI.getOperand(0).getMBB();
140 TBB =
MI.getOperand(0).getMBB();
142 FBB =
MI.getOperand(0).getMBB();
153 int *BytesRemoved)
const {
154 assert(!BytesRemoved &&
"code size not handled");
161 if (
I->isDebugInstr())
163 if (!
I->isTerminator())
166 I->eraseFromParent();
177 assert(!BytesAdded &&
"code size not handled");
187 assert(
Cond.size() == 2 &&
"Expected a flag and a successor block");
189 if (
Cond[0].getImm())
202 assert(
Cond.size() == 2 &&
"Expected a flag and a condition expression");
209 static const std::pair<int, const char *> TargetIndices[] = {
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
const TargetRegisterInfo * getTargetRegisterInfo() const
iterator_range< iterator > terminators()
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static MachineOperand CreateImm(int64_t Val)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
@ Kill
The last use of a register.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Representation of each machine instruction.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isVRegStackified(unsigned VReg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
instr_iterator instr_begin()
instr_iterator instr_end()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
unsigned const MachineRegisterInfo * MRI
Should compile to something r4 addze r3 instead we get
@ BR
Control flow instructions. These all have token chains.
Iterator for intrusive lists based on ilist_node.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Wrapper class representing physical registers. Should be passed by value.