LLVM  16.0.0git
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
18 #include "WebAssembly.h"
20 #include "WebAssemblySubtarget.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "wasm-instr-info"
28 
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "WebAssemblyGenInstrInfo.inc"
31 
32 // defines WebAssembly::getNamedOperandIdx
33 #define GET_INSTRINFO_NAMED_OPS
34 #include "WebAssemblyGenInstrInfo.inc"
35 
37  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
38  WebAssembly::ADJCALLSTACKUP,
39  WebAssembly::CATCHRET),
40  RI(STI.getTargetTriple()) {}
41 
43  const MachineInstr &MI) const {
44  switch (MI.getOpcode()) {
45  case WebAssembly::CONST_I32:
46  case WebAssembly::CONST_I64:
47  case WebAssembly::CONST_F32:
48  case WebAssembly::CONST_F64:
49  // isReallyTriviallyReMaterializableGeneric misses these because of the
50  // ARGUMENTS implicit def, so we manualy override it here.
51  return true;
52  default:
53  return false;
54  }
55 }
56 
59  const DebugLoc &DL, MCRegister DestReg,
60  MCRegister SrcReg, bool KillSrc) const {
61  // This method is called by post-RA expansion, which expects only pregs to
62  // exist. However we need to handle both here.
63  auto &MRI = MBB.getParent()->getRegInfo();
64  const TargetRegisterClass *RC =
66  ? MRI.getRegClass(DestReg)
68 
69  unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC);
70 
71  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
72  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
73 }
74 
76  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
77  // If the operands are stackified, we can't reorder them.
79  *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
80  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
81  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
82  return nullptr;
83 
84  // Otherwise use the default implementation.
85  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
86 }
87 
88 // Branch analysis.
91  MachineBasicBlock *&FBB,
93  bool /*AllowModify*/) const {
94  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
95  // WebAssembly has control flow that doesn't have explicit branches or direct
96  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
97  // is created after CFGStackify.
98  if (MFI.isCFGStackified())
99  return true;
100 
101  bool HaveCond = false;
102  for (MachineInstr &MI : MBB.terminators()) {
103  switch (MI.getOpcode()) {
104  default:
105  // Unhandled instruction; bail out.
106  return true;
107  case WebAssembly::BR_IF:
108  if (HaveCond)
109  return true;
110  Cond.push_back(MachineOperand::CreateImm(true));
111  Cond.push_back(MI.getOperand(1));
112  TBB = MI.getOperand(0).getMBB();
113  HaveCond = true;
114  break;
115  case WebAssembly::BR_UNLESS:
116  if (HaveCond)
117  return true;
118  Cond.push_back(MachineOperand::CreateImm(false));
119  Cond.push_back(MI.getOperand(1));
120  TBB = MI.getOperand(0).getMBB();
121  HaveCond = true;
122  break;
123  case WebAssembly::BR:
124  if (!HaveCond)
125  TBB = MI.getOperand(0).getMBB();
126  else
127  FBB = MI.getOperand(0).getMBB();
128  break;
129  }
130  if (MI.isBarrier())
131  break;
132  }
133 
134  return false;
135 }
136 
138  int *BytesRemoved) const {
139  assert(!BytesRemoved && "code size not handled");
140 
142  unsigned Count = 0;
143 
144  while (I != MBB.instr_begin()) {
145  --I;
146  if (I->isDebugInstr())
147  continue;
148  if (!I->isTerminator())
149  break;
150  // Remove the branch.
151  I->eraseFromParent();
152  I = MBB.instr_end();
153  ++Count;
154  }
155 
156  return Count;
157 }
158 
161  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
162  assert(!BytesAdded && "code size not handled");
163 
164  if (Cond.empty()) {
165  if (!TBB)
166  return 0;
167 
169  return 1;
170  }
171 
172  assert(Cond.size() == 2 && "Expected a flag and a successor block");
173 
174  if (Cond[0].getImm())
175  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
176  else
177  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
178  if (!FBB)
179  return 1;
180 
182  return 2;
183 }
184 
187  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
188  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
189  return false;
190 }
191 
194  static const std::pair<int, const char *> TargetIndices[] = {
195  {WebAssembly::TI_LOCAL, "wasm-local"},
196  {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
197  {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
198  {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
199  {WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
200  return makeArrayRef(TargetIndices);
201 }
202 
203 const MachineOperand &
206 }
llvm::WebAssemblyInstrInfo::WebAssemblyInstrInfo
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
Definition: WebAssemblyInstrInfo.cpp:36
llvm::WebAssembly::getCalleeOp
const MachineOperand & getCalleeOp(const MachineInstr &MI)
Returns the operand number of a callee, assuming the argument is a call instruction.
Definition: WebAssemblyUtilities.cpp:108
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::WebAssemblyInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: WebAssemblyInstrInfo.cpp:159
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
WebAssembly.h
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::WebAssemblyInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: WebAssemblyInstrInfo.cpp:75
llvm::WebAssemblyInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: WebAssemblyInstrInfo.cpp:57
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:325
MachineRegisterInfo.h
llvm::WebAssemblyInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
Definition: WebAssemblyInstrInfo.cpp:42
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:166
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1044
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
WebAssemblyInstrInfo.h
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::WebAssembly::getCopyOpcodeForRegClass
unsigned getCopyOpcodeForRegClass(const TargetRegisterClass *RC)
Returns the appropriate copy opcode for the given register class.
Definition: WebAssemblyUtilities.cpp:183
llvm::WebAssembly::TI_OPERAND_STACK
@ TI_OPERAND_STACK
Definition: WebAssembly.h:93
llvm::WebAssembly::TI_GLOBAL_RELOC
@ TI_GLOBAL_RELOC
Definition: WebAssembly.h:96
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
WebAssemblyUtilities.h
WebAssemblyMCTargetDesc.h
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
WebAssemblyGenInstrInfo
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::WebAssemblyInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: WebAssemblyInstrInfo.cpp:185
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::WebAssemblyFunctionInfo::isVRegStackified
bool isVRegStackified(unsigned VReg) const
Definition: WebAssemblyMachineFunctionInfo.h:134
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::WebAssemblyFunctionInfo
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Definition: WebAssemblyMachineFunctionInfo.h:33
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::WebAssemblyInstrInfo::getCalleeOperand
const MachineOperand & getCalleeOperand(const MachineInstr &MI) const override
Definition: WebAssemblyInstrInfo.cpp:204
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:289
WebAssemblyMachineFunctionInfo.h
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:291
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::WebAssemblyInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: WebAssemblyInstrInfo.cpp:89
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::WebAssemblyInstrInfo::getSerializableTargetIndices
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
Definition: WebAssemblyInstrInfo.cpp:193
llvm::WebAssembly::TI_GLOBAL_FIXED
@ TI_GLOBAL_FIXED
Definition: WebAssembly.h:91
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::WebAssembly::TI_LOCAL
@ TI_LOCAL
Definition: WebAssembly.h:89
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::WebAssembly::TI_LOCAL_INDIRECT
@ TI_LOCAL_INDIRECT
Definition: WebAssembly.h:99
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
WebAssemblySubtarget.h
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
MachineInstrBuilder.h
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::WebAssemblyInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: WebAssemblyInstrInfo.cpp:137
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24