Go to the documentation of this file.
40 cl::desc(
"Disable hazard detection during preRA scheduling"));
74 unsigned Quantity)
const {
75 for (
unsigned i = 0;
i < Quantity; ++
i)
102 bool AtInsnStart =
true;
105 for (; *Str; ++Str) {
115 if (AtInsnStart && !isSpace(
static_cast<unsigned char>(*Str))) {
116 unsigned AddLength = MaxInstLength;
117 if (strncmp(Str,
".space", 6) == 0) {
120 SpaceSize = strtol(Str + 6, &EStr, 10);
121 SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;
122 while (*EStr !=
'\n' && isSpace(
static_cast<unsigned char>(*EStr)))
124 if (*EStr ==
'\0' || *EStr ==
'\n' ||
126 AddLength = SpaceSize;
154 if (
MI->shouldUpdateCallSiteInfo())
166 bool NewMI,
unsigned Idx1,
167 unsigned Idx2)
const {
170 if (HasDef && !
MI.getOperand(0).isReg())
174 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
175 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
177 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
178 "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
179 assert(
MI.getOperand(Idx1).isReg() &&
MI.getOperand(Idx2).isReg() &&
180 "This only knows how to commute register operands so far");
185 unsigned SubReg0 = HasDef ?
MI.getOperand(0).getSubReg() : 0;
186 unsigned SubReg1 =
MI.getOperand(Idx1).getSubReg();
187 unsigned SubReg2 =
MI.getOperand(Idx2).getSubReg();
188 bool Reg1IsKill =
MI.getOperand(Idx1).isKill();
189 bool Reg2IsKill =
MI.getOperand(Idx2).isKill();
190 bool Reg1IsUndef =
MI.getOperand(Idx1).isUndef();
191 bool Reg2IsUndef =
MI.getOperand(Idx2).isUndef();
192 bool Reg1IsInternal =
MI.getOperand(Idx1).isInternalRead();
193 bool Reg2IsInternal =
MI.getOperand(Idx2).isInternalRead();
197 ?
MI.getOperand(Idx1).isRenamable()
200 ?
MI.getOperand(Idx2).isRenamable()
204 if (HasDef && Reg0 == Reg1 &&
209 }
else if (HasDef && Reg0 == Reg2 &&
250 unsigned OpIdx2)
const {
257 "Precondition violation: MI must be commutable.");
264 unsigned &ResultIdx2,
265 unsigned CommutableOpIdx1,
266 unsigned CommutableOpIdx2) {
269 ResultIdx1 = CommutableOpIdx1;
270 ResultIdx2 = CommutableOpIdx2;
272 if (ResultIdx2 == CommutableOpIdx1)
273 ResultIdx1 = CommutableOpIdx2;
274 else if (ResultIdx2 == CommutableOpIdx2)
275 ResultIdx1 = CommutableOpIdx1;
279 if (ResultIdx1 == CommutableOpIdx1)
280 ResultIdx2 = CommutableOpIdx2;
281 else if (ResultIdx1 == CommutableOpIdx2)
282 ResultIdx2 = CommutableOpIdx1;
288 return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
289 (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
296 unsigned &SrcOpIdx2)
const {
298 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
306 unsigned CommutableOpIdx1 = MCID.
getNumDefs();
307 unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
309 CommutableOpIdx1, CommutableOpIdx2))
312 if (!
MI.getOperand(SrcOpIdx1).isReg() || !
MI.getOperand(SrcOpIdx2).isReg())
319 if (!
MI.isTerminator())
return false;
322 if (
MI.isBranch() && !
MI.isBarrier())
324 if (!
MI.isPredicable())
331 bool MadeChange =
false;
334 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
337 if (!
MI.isPredicable())
340 for (
unsigned j = 0,
i = 0,
e =
MI.getNumOperands();
i !=
e; ++
i) {
346 }
else if (MO.
isImm()) {
349 }
else if (MO.
isMBB()) {
362 size_t StartSize = Accesses.size();
364 oe =
MI.memoperands_end();
366 if ((*o)->isLoad() &&
367 isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
368 Accesses.push_back(*o);
370 return Accesses.size() != StartSize;
376 size_t StartSize = Accesses.size();
378 oe =
MI.memoperands_end();
380 if ((*o)->isStore() &&
381 isa_and_nonnull<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
382 Accesses.push_back(*o);
384 return Accesses.size() != StartSize;
388 unsigned SubIdx,
unsigned &Size,
403 if (BitOffset < 0 || BitOffset % 8)
407 Offset = (unsigned)BitOffset / 8;
423 MI->substituteRegister(
MI->getOperand(0).getReg(), DestReg, SubIdx,
TRI);
444 assert(
MI.isCopy() &&
"MI must be a COPY instruction");
445 if (
MI.getNumOperands() != 2)
447 assert(FoldIdx<2 &&
"FoldIdx refers no nonexistent operand");
475 std::pair<unsigned, unsigned>
477 switch (
MI.getOpcode()) {
478 case TargetOpcode::STACKMAP:
481 case TargetOpcode::PATCHPOINT:
485 case TargetOpcode::STATEPOINT:
496 unsigned StartIdx = 0;
497 unsigned NumDefs = 0;
499 std::tie(NumDefs, StartIdx) =
TII.getPatchpointUnfoldableRange(
MI);
501 unsigned DefToFoldIdx =
MI.getNumOperands();
505 for (
unsigned Op : Ops) {
507 assert(DefToFoldIdx ==
MI.getNumOperands() &&
"Folding multiple defs");
509 }
else if (
Op < StartIdx) {
512 if (
MI.getOperand(
Op).isTied())
521 for (
unsigned i = 0;
i < StartIdx; ++
i)
522 if (
i != DefToFoldIdx)
523 MIB.
add(
MI.getOperand(
i));
525 for (
unsigned i = StartIdx,
e =
MI.getNumOperands();
i <
e; ++
i) {
528 (void)
MI.isRegTiedToDefOperand(
i, &TiedTo);
531 assert(TiedTo ==
e &&
"Cannot fold tied operands");
533 unsigned SpillOffset;
538 TII.getStackSlotRange(RC, MO.
getSubReg(), SpillSize, SpillOffset, MF);
541 MIB.
addImm(StackMaps::IndirectMemRefOp);
548 assert(TiedTo < NumDefs &&
"Bad tied operand");
549 if (TiedTo > DefToFoldIdx)
563 for (
unsigned OpIdx : Ops)
568 assert(
MBB &&
"foldMemoryOperand needs an inserted instruction");
581 for (
unsigned OpIdx : Ops) {
584 if (
auto SubReg =
MI.getOperand(OpIdx).getSubReg()) {
586 if (SubRegSize > 0 && !(SubRegSize % 8))
587 OpSize = SubRegSize / 8;
590 MemSize =
std::max(MemSize, OpSize);
594 assert(MemSize &&
"Did not expect a zero-sized stack slot");
598 if (
MI.getOpcode() == TargetOpcode::STACKMAP ||
599 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
600 MI.getOpcode() == TargetOpcode::STATEPOINT) {
615 "Folded a def to a non-store!");
618 "Folded a use to a non-load!");
633 if (!
MI.isCopy() || Ops.size() != 1)
656 for (
unsigned OpIdx : Ops)
657 assert(
MI.getOperand(OpIdx).isUse() &&
"Folding load into def!");
667 if ((
MI.getOpcode() == TargetOpcode::STACKMAP ||
668 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
669 MI.getOpcode() == TargetOpcode::STATEPOINT) &&
684 if (
MI.memoperands_empty()) {
718 bool &Commuted)
const {
748 bool &Commuted)
const {
777 bool DoRegPressureReduce)
const {
820 unsigned OpIdx[4][4] = {
863 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
866 bool KillA = OpA.
isKill();
867 bool KillX = OpX.
isKill();
868 bool KillY = OpY.
isKill();
885 InsInstrs.push_back(MIB1);
886 InsInstrs.push_back(MIB2);
887 DelInstrs.push_back(&Prev);
888 DelInstrs.push_back(&Root);
913 assert(Prev &&
"Unknown pattern for machine combiner");
918 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
924 if (!
MI.getNumOperands() || !
MI.getOperand(0).isReg())
933 MI.readsVirtualRegister(DefReg))
945 if (
MI.isNotDuplicable() ||
MI.mayStore() ||
MI.mayRaiseFPException() ||
946 MI.hasUnmodeledSideEffects())
951 if (
MI.isInlineAsm())
955 if (
MI.mayLoad() && !
MI.isDereferenceableInvariantLoad(
AA))
961 if (!MO.isReg())
continue;
983 if (MO.isDef() &&
Reg != DefReg)
1000 bool StackGrowsDown =
1011 if ((!StackGrowsDown &&
MI.getOpcode() == FrameSetupOpcode) ||
1012 (StackGrowsDown &&
MI.getOpcode() == FrameDestroyOpcode))
1025 if (
MI.isTerminator() ||
MI.isPosition())
1077 BaseOps.size() != 1)
1079 BaseOp = BaseOps.front();
1089 SDNode *DefNode,
unsigned DefIdx,
1090 SDNode *UseNode,
unsigned UseIdx)
const {
1091 if (!ItinData || ItinData->
isEmpty())
1106 if (!ItinData || ItinData->
isEmpty())
1109 if (!
N->isMachineOpcode())
1121 if (!ItinData || ItinData->
isEmpty())
1124 unsigned Class =
MI.getDesc().getSchedClass();
1137 if (
DefMI.isTransient())
1139 if (
DefMI.mayLoad())
1152 unsigned *PredCost)
const {
1156 return MI.mayLoad() ? 2 : 1;
1163 unsigned DefIdx)
const {
1165 if (!ItinData || ItinData->
isEmpty())
1168 unsigned DefClass =
DefMI.getDesc().getSchedClass();
1170 return (DefCycle != -1 && DefCycle <= 1);
1180 bool OffsetIsScalable;
1188 Register DestReg = DestSrc->Destination->getReg();
1201 "TargetInstrInfo::describeLoadedValue can't describe super- or "
1202 "sub-regs for copy instructions");
1209 }
else if (
MI.hasOneMemOperand()) {
1224 if (!
TII->getMemOperandWithOffset(
MI, BaseOp, Offset, OffsetIsScalable,
1229 if (OffsetIsScalable)
1238 if (
MI.getNumExplicitDefs() != 1)
1245 Ops.push_back(dwarf::DW_OP_deref_size);
1246 Ops.push_back(MMO->
getSize());
1260 unsigned UseIdx)
const {
1261 unsigned DefClass =
DefMI.getDesc().getSchedClass();
1262 unsigned UseClass =
UseMI.getDesc().getSchedClass();
1270 MI.isRegSequenceLike()) &&
"Instruction do not have the proper type");
1272 if (!
MI.isRegSequence())
1277 assert(DefIdx == 0 &&
"REG_SEQUENCE only has one def");
1278 for (
unsigned OpIdx = 1, EndOpIdx =
MI.getNumOperands(); OpIdx != EndOpIdx;
1285 "One of the subindex of the reg_sequence is not an immediate");
1288 (
unsigned)MOSubIdx.
getImm()));
1297 MI.isExtractSubregLike()) &&
"Instruction do not have the proper type");
1299 if (!
MI.isExtractSubreg())
1304 assert(DefIdx == 0 &&
"EXTRACT_SUBREG only has one def");
1310 "The subindex of the extract_subreg is not an immediate");
1322 MI.isInsertSubregLike()) &&
"Instruction do not have the proper type");
1324 if (!
MI.isInsertSubreg())
1329 assert(DefIdx == 0 &&
"INSERT_SUBREG only has one def");
1336 "One of the subindex of the reg_sequence is not an immediate");
1340 InsertedReg.
Reg = MOInsertedReg.
getReg();
1351 if (!
MI.isInlineAsm())
1359 unsigned ExtraInfo =
Op.getImm();
1371 int FlagIdx =
MI.findInlineAsmFlagIdx(OpIdx);
1372 if (FlagIdx < 0 || (
unsigned)FlagIdx != OpIdx)
1375 assert(
Op.isImm() &&
"Expected flag operand to be an immediate");
1377 unsigned Flag =
Op.getImm();
1387 OS <<
":RC" << RCID;
1395 unsigned TiedTo = 0;
1397 OS <<
" tiedto:$" << TiedTo;
1405 Function &
F, std::vector<outliner::Candidate> &Candidates)
const {
1417 return C.getMF()->
getFunction().hasFnAttribute(Attribute::NoUnwind);
1419 F.addFnAttr(Attribute::NoUnwind);
1423 unsigned &Flags)
const {
1428 (
First->getOpcode() == TargetOpcode::FENTRY_CALL ||
1429 First->getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER))
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
bool hasProperty(Property P) const
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
StringRef getCommentString() const
MI-level stackmap operands.
void setIsInternalRead(bool Val=true)
const char * getSeparatorString() const
MachineInstrBuilder & UseMI
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Information about stack frame layout on the target.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
static Function * getFunction(Constant *C)
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
static StringRef getKindName(unsigned Kind)
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
This class is intended to be used as a base class for asm properties and features specific to the tar...
void setIsKill(bool Val=true)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Reg
All possible values of the reg field in the ModR/M byte.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Represents one node in the SelectionDAG.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
void setImm(int64_t immVal)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
A description of a memory reference used in the backend.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Instances of this class represent a single low-level machine instruction.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
MachineInstr & cloneMachineInstrBundle(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig)
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
const InstrItineraryData * getInstrItineraries() const
MI-level patchpoint operands.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
unsigned const TargetRegisterInfo * TRI
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class.
static bool isAsmComment(const char *Str, const MCAsmInfo &MAI)
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
A pair composed of a register and a sub-register index.
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
uint16_t getFlags() const
Return the MI flags bitvector.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
TargetInstrInfo - Interface to description of machine instruction set.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
MachineFunction * getMF() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
void setSubReg(unsigned subReg)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
const MachineFunctionProperties & getProperties() const
Get the function properties.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const HexagonInstrInfo * TII
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Describe properties that are true of each instruction in the target description file.
into llvm powi allowing the code generator to produce balanced multiplication trees First
MachineOperand class - Representation of each machine instruction operand.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
virtual ~TargetInstrInfo()
Flag
These should be considered private to the implementation of the MCInstrDesc class.
virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const
Optional target hook to create the LLVM IR attributes for the outlined function.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
const InstrItinerary * Itineraries
Array of itineraries selected.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Analysis containing CSE Info
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
Special value supplied for machine level alias analysis.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
static unsigned getKind(unsigned Flags)
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
static bool isMemKind(unsigned Flag)
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
virtual unsigned getMaxInstLength(const MCSubtargetInfo *STI=nullptr) const
Returns the maximum possible encoded instruction size in bytes.
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Provide an instruction scheduling machine model to CodeGen passes.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
An individual sequence of instructions to be replaced with a call to an outlined function.
bool isLittleEndian() const
Layout endianness...
static bool isImmKind(unsigned Flag)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
initializer< Ty > init(const Ty &Val)
MachineBasicBlock::iterator & front()
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
succ_iterator succ_begin()
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
virtual ~PipelinerLoopInfo()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
static unsigned getMemoryConstraintID(unsigned Flag)
const MCOperandInfo * OpInfo
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
virtual unsigned getPredicationCost(const MachineInstr &MI) const
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
iterator getFirstNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the first non-debug instruction in the basic block, or end().
StringRef - Represent a constant reference to a string, i.e.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
void setIsUndef(bool Val=true)
void setIsRenamable(bool Val=true)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static StringRef getMemConstraintName(unsigned Constraint)
const MachineBasicBlock * getParent() const
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
TargetSubtargetInfo - Generic base class for all target subtargets.
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
MI-level Statepoint operands.
unsigned getCallFrameDestroyOpcode() const
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual const TargetFrameLowering * getFrameLowering() const
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
uint64_t getSize() const
Return the size in bytes of the memory reference.
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
static std::vector< StringRef > getExtraInfoNames(unsigned ExtraInfo)
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Machine model for scheduling, bundling, and heuristics.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
@ MOStore
The memory access writes data.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
static const TargetRegisterClass * canFoldCopy(const MachineInstr &MI, unsigned FoldIdx)
bool isImmutableObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an immutable object.
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
virtual const TargetLowering * getTargetLowering() const
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumOperands() const
Retuns the total number of operands.
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
void setMBB(MachineBasicBlock *MBB)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
static const unsigned CommuteAnyOperandIndex
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
bool isEmpty() const
Returns true if there are no itineraries.
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
std::string & str()
Returns the string's reference.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
const PseudoSourceValue * getPseudoValue() const
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.