LLVM 17.0.0git
WebAssemblyRegisterInfo.cpp
Go to the documentation of this file.
1//===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file contains the WebAssembly implementation of the
11/// TargetRegisterInfo class.
12///
13//===----------------------------------------------------------------------===//
14
25#include "llvm/IR/Function.h"
28using namespace llvm;
29
30#define DEBUG_TYPE "wasm-reg-info"
31
32#define GET_REGINFO_TARGET_DESC
33#include "WebAssemblyGenRegisterInfo.inc"
34
36 : WebAssemblyGenRegisterInfo(0), TT(TT) {}
37
38const MCPhysReg *
40 static const MCPhysReg CalleeSavedRegs[] = {0};
41 return CalleeSavedRegs;
42}
43
46 BitVector Reserved(getNumRegs());
47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
48 WebAssembly::FP64})
49 Reserved.set(Reg);
50 return Reserved;
51}
52
54 MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
55 RegScavenger * /*RS*/) const {
56 assert(SPAdj == 0);
57 MachineInstr &MI = *II;
58
59 MachineBasicBlock &MBB = *MI.getParent();
62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
63 const MachineFrameInfo &MFI = MF.getFrameInfo();
64 int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
65
66 assert(MFI.getObjectSize(FrameIndex) != 0 &&
67 "We assume that variable-sized objects have already been lowered, "
68 "and don't use FrameIndex operands.");
69 Register FrameRegister = getFrameRegister(MF);
70
71 // If this is the address operand of a load or store, make it relative to SP
72 // and fold the frame offset directly in.
73 unsigned AddrOperandNum = WebAssembly::getNamedOperandIdx(
74 MI.getOpcode(), WebAssembly::OpName::addr);
75 if (AddrOperandNum == FIOperandNum) {
76 unsigned OffsetOperandNum = WebAssembly::getNamedOperandIdx(
77 MI.getOpcode(), WebAssembly::OpName::off);
78 assert(FrameOffset >= 0 && MI.getOperand(OffsetOperandNum).getImm() >= 0);
79 int64_t Offset = MI.getOperand(OffsetOperandNum).getImm() + FrameOffset;
80
81 if (static_cast<uint64_t>(Offset) <= std::numeric_limits<uint32_t>::max()) {
82 MI.getOperand(OffsetOperandNum).setImm(Offset);
83 MI.getOperand(FIOperandNum)
84 .ChangeToRegister(FrameRegister, /*isDef=*/false);
85 return false;
86 }
87 }
88
89 // If this is an address being added to a constant, fold the frame offset
90 // into the constant.
91 if (MI.getOpcode() == WebAssemblyFrameLowering::getOpcAdd(MF)) {
92 MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
93 if (OtherMO.isReg()) {
94 Register OtherMOReg = OtherMO.getReg();
95 if (OtherMOReg.isVirtual()) {
96 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
97 // TODO: For now we just opportunistically do this in the case where
98 // the CONST_I32/64 happens to have exactly one def and one use. We
99 // should generalize this to optimize in more cases.
100 if (Def && Def->getOpcode() ==
102 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
103 MachineOperand &ImmMO = Def->getOperand(1);
104 if (ImmMO.isImm()) {
105 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));
106 MI.getOperand(FIOperandNum)
107 .ChangeToRegister(FrameRegister, /*isDef=*/false);
108 return false;
109 }
110 }
111 }
112 }
113 }
114
115 // Otherwise create an i32/64.add SP, offset and make it the operand.
116 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
117
118 unsigned FIRegOperand = FrameRegister;
119 if (FrameOffset) {
120 // Create i32/64.add SP, offset and make it the operand.
121 const TargetRegisterClass *PtrRC =
122 MRI.getTargetRegisterInfo()->getPointerRegClass(MF);
123 Register OffsetOp = MRI.createVirtualRegister(PtrRC);
124 BuildMI(MBB, *II, II->getDebugLoc(),
126 OffsetOp)
127 .addImm(FrameOffset);
128 FIRegOperand = MRI.createVirtualRegister(PtrRC);
129 BuildMI(MBB, *II, II->getDebugLoc(),
131 FIRegOperand)
132 .addReg(FrameRegister)
133 .addReg(OffsetOp);
134 }
135 MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*isDef=*/false);
136 return false;
137}
138
141 // If the PReg has been replaced by a VReg, return that.
142 const auto &MFI = MF.getInfo<WebAssemblyFunctionInfo>();
143 if (MFI->isFrameBaseVirtual())
144 return MFI->getFrameBaseVreg();
145 static const unsigned Regs[2][2] = {
146 /* !isArch64Bit isArch64Bit */
147 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
148 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
149 const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
150 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
151}
152
155 unsigned Kind) const {
156 assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
158 return &WebAssembly::I64RegClass;
159 return &WebAssembly::I32RegClass;
160}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements WebAssembly-specific bits of TargetFrameLowering class.
This file contains the WebAssembly implementation of the TargetInstrInfo class.
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
This file contains the WebAssembly implementation of the WebAssemblyRegisterInfo class.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1469
static unsigned getOpcAdd(const MachineFunction &MF)
static unsigned getOpcConst(const MachineFunction &MF)
bool hasFP(const MachineFunction &MF) const override
Return true if the specified function should have a dedicated frame pointer register.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Register getFrameRegister(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.