29#define DEBUG_TYPE "si-pre-allocate-wwm-regs"
43 std::vector<unsigned> RegsToRewrite;
75 "SI Pre-allocate WWM Registers",
false,
false)
82char SIPreAllocateWWMRegs::
ID = 0;
87 return new SIPreAllocateWWMRegs();
95 if (!
TRI->isVGPR(*
MRI, Reg))
98 if (VRM->hasPhys(Reg))
103 for (
MCRegister PhysReg : RegClassInfo.getOrder(
MRI->getRegClass(Reg))) {
104 if (!
MRI->isPhysRegUsed(PhysReg) &&
106 Matrix->assign(LI, PhysReg);
108 RegsToRewrite.push_back(Reg);
127 if (!VRM->hasPhys(VirtReg))
130 Register PhysReg = VRM->getPhys(VirtReg);
133 PhysReg =
TRI->getSubReg(PhysReg,
SubReg);
145 for (
unsigned Reg : RegsToRewrite) {
146 LIS->removeInterval(Reg);
148 const Register PhysReg = VRM->getPhys(Reg);
154 RegsToRewrite.clear();
157 MRI->freezeReservedRegs(MF);
164 unsigned Opc =
MI.getOpcode();
166 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM ||
167 Opc == AMDGPU::ENTER_PSEUDO_WM) {
168 dbgs() <<
"Entering ";
170 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM ||
171 Opc == AMDGPU::EXIT_PSEUDO_WM);
172 dbgs() <<
"Exiting ";
175 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) {
176 dbgs() <<
"Strict WWM ";
177 }
else if (Opc == AMDGPU::ENTER_PSEUDO_WM || Opc == AMDGPU::EXIT_PSEUDO_WM) {
178 dbgs() <<
"Pseudo WWM/WQM ";
180 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM);
181 dbgs() <<
"Strict WQM ";
184 dbgs() <<
"region: " <<
MI;
194 TII =
ST.getInstrInfo();
195 TRI = &
TII->getRegisterInfo();
198 LIS = &getAnalysis<LiveIntervals>();
199 Matrix = &getAnalysis<LiveRegMatrix>();
200 VRM = &getAnalysis<VirtRegMap>();
202 RegClassInfo.runOnMachineFunction(MF);
204 bool RegsAssigned =
false;
216 if (
MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 ||
217 MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64)
218 RegsAssigned |= processDef(
MI.getOperand(0));
220 if (
MI.getOpcode() == AMDGPU::ENTER_STRICT_WWM ||
221 MI.getOpcode() == AMDGPU::ENTER_STRICT_WQM ||
222 MI.getOpcode() == AMDGPU::ENTER_PSEUDO_WM) {
228 if (
MI.getOpcode() == AMDGPU::EXIT_STRICT_WWM ||
229 MI.getOpcode() == AMDGPU::EXIT_STRICT_WQM ||
230 MI.getOpcode() == AMDGPU::EXIT_PSEUDO_WM) {
241 RegsAssigned |= processDef(DefOpnd);
unsigned const MachineRegisterInfo * MRI
Provides AMDGPU specific target descriptions.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI Pre allocate WWM Registers
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
LiveInterval - This class represents the liveness of a register, or stack slot.
@ IK_Free
No interference, go ahead and assign.
Wrapper class representing physical registers. Should be passed by value.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void reserveWWMRegister(Register Reg)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
char & SIPreAllocateWWMRegsID
FunctionPass * createSIPreAllocateWWMRegsPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)