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29 #define DEBUG_TYPE "si-pre-allocate-wwm-regs"
43 std::vector<unsigned> RegsToRewrite;
75 "SI Pre-allocate WWM Registers",
false,
false)
82 char SIPreAllocateWWMRegs::
ID = 0;
87 return new SIPreAllocateWWMRegs();
98 if (VRM->hasPhys(
Reg))
106 Matrix->assign(LI, PhysReg);
108 RegsToRewrite.push_back(
Reg);
127 if (!VRM->hasPhys(VirtReg))
130 Register PhysReg = VRM->getPhys(VirtReg);
145 for (
unsigned Reg : RegsToRewrite) {
146 LIS->removeInterval(
Reg);
154 RegsToRewrite.clear();
164 unsigned Opc =
MI.getOpcode();
166 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM) {
167 dbgs() <<
"Entering ";
169 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM);
170 dbgs() <<
"Exiting ";
173 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) {
174 dbgs() <<
"Strict WWM ";
176 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM);
177 dbgs() <<
"Strict WQM ";
180 dbgs() <<
"region: " <<
MI;
190 TII =
ST.getInstrInfo();
191 TRI = &
TII->getRegisterInfo();
194 LIS = &getAnalysis<LiveIntervals>();
195 Matrix = &getAnalysis<LiveRegMatrix>();
196 VRM = &getAnalysis<VirtRegMap>();
198 RegClassInfo.runOnMachineFunction(MF);
200 bool RegsAssigned =
false;
212 if (
MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 ||
213 MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64)
214 RegsAssigned |= processDef(
MI.getOperand(0));
216 if (
MI.getOpcode() == AMDGPU::ENTER_STRICT_WWM ||
217 MI.getOpcode() == AMDGPU::ENTER_STRICT_WQM) {
223 if (
MI.getOpcode() == AMDGPU::EXIT_STRICT_WWM ||
224 MI.getOpcode() == AMDGPU::EXIT_STRICT_WQM) {
235 RegsAssigned |= processDef(DefOpnd);
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This is an optimization pass for GlobalISel generic memory operations.
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
Reg
All possible values of the reg field in the ModR/M byte.
SI Pre allocate WWM Registers
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
FunctionPass * createSIPreAllocateWWMRegsPass()
INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE, "SI Pre-allocate WWM Registers", false, false) INITIALIZE_PASS_END(SIPreAllocateWWMRegs
char & SIPreAllocateWWMRegsID
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
@ IK_Free
No interference, go ahead and assign.
void setSubReg(unsigned subReg)
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
LiveInterval - This class represents the liveness of a register, or stack slot.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
void reserveWWMRegister(Register Reg)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StandardInstrumentations SI(Debug, VerifyEach)
Register getReg() const
getReg - Returns the register number.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setIsRenamable(bool Val=true)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
void setReg(Register Reg)
Change the register this operand corresponds to.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
FunctionPass class - This class is used to implement most global optimizations.
AnalysisUsage & addRequired()
Wrapper class representing physical registers. Should be passed by value.