LLVM  14.0.0git
GCNPreRAOptimizations.cpp
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1 //===-- GCNPreRAOptimizations.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass combines split register tuple initialization into a single psuedo:
11 ///
12 /// undef %0.sub1:sreg_64 = S_MOV_B32 1
13 /// %0.sub0:sreg_64 = S_MOV_B32 2
14 /// =>
15 /// %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 0x200000001
16 ///
17 /// This is to allow rematerialization of a value instead of spilling. It is
18 /// supposed to be done after register coalescer to allow it to do its job and
19 /// before actual register allocation to allow rematerialization.
20 ///
21 /// Right now the pass only handles 64 bit SGPRs with immediate initializers,
22 /// although the same shall be possible with other register classes and
23 /// instructions if necessary.
24 ///
25 //===----------------------------------------------------------------------===//
26 
27 #include "AMDGPU.h"
28 #include "GCNSubtarget.h"
32 #include "llvm/InitializePasses.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "amdgpu-pre-ra-optimizations"
37 
38 namespace {
39 
40 class GCNPreRAOptimizations : public MachineFunctionPass {
41 private:
42  const SIInstrInfo *TII;
44  LiveIntervals *LIS;
45 
46  bool processReg(Register Reg);
47 
48 public:
49  static char ID;
50 
51  GCNPreRAOptimizations() : MachineFunctionPass(ID) {
53  }
54 
55  bool runOnMachineFunction(MachineFunction &MF) override;
56 
57  StringRef getPassName() const override {
58  return "AMDGPU Pre-RA optimizations";
59  }
60 
61  void getAnalysisUsage(AnalysisUsage &AU) const override {
63  AU.setPreservesAll();
65  }
66 };
67 
68 } // End anonymous namespace.
69 
70 INITIALIZE_PASS_BEGIN(GCNPreRAOptimizations, DEBUG_TYPE,
71  "AMDGPU Pre-RA optimizations", false, false)
73 INITIALIZE_PASS_END(GCNPreRAOptimizations, DEBUG_TYPE, "Pre-RA optimizations",
75 
76 char GCNPreRAOptimizations::ID = 0;
77 
78 char &llvm::GCNPreRAOptimizationsID = GCNPreRAOptimizations::ID;
79 
81  return new GCNPreRAOptimizations();
82 }
83 
84 bool GCNPreRAOptimizations::processReg(Register Reg) {
85  MachineInstr *Def0 = nullptr;
86  MachineInstr *Def1 = nullptr;
87  uint64_t Init = 0;
88 
90  if (I.getOpcode() != AMDGPU::S_MOV_B32 || I.getOperand(0).getReg() != Reg ||
91  !I.getOperand(1).isImm() || I.getNumOperands() != 2)
92  return false;
93 
94  switch (I.getOperand(0).getSubReg()) {
95  default:
96  return false;
97  case AMDGPU::sub0:
98  if (Def0)
99  return false;
100  Def0 = &I;
101  Init |= I.getOperand(1).getImm() & 0xffffffff;
102  break;
103  case AMDGPU::sub1:
104  if (Def1)
105  return false;
106  Def1 = &I;
107  Init |= static_cast<uint64_t>(I.getOperand(1).getImm()) << 32;
108  break;
109  }
110  }
111 
112  if (!Def0 || !Def1 || Def0->getParent() != Def1->getParent())
113  return false;
114 
115  LLVM_DEBUG(dbgs() << "Combining:\n " << *Def0 << " " << *Def1
116  << " =>\n");
117 
118  if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1),
119  LIS->getInstructionIndex(*Def0)))
120  std::swap(Def0, Def1);
121 
122  LIS->RemoveMachineInstrFromMaps(*Def0);
123  LIS->RemoveMachineInstrFromMaps(*Def1);
124  auto NewI = BuildMI(*Def0->getParent(), *Def0, Def0->getDebugLoc(),
125  TII->get(AMDGPU::S_MOV_B64_IMM_PSEUDO), Reg)
126  .addImm(Init);
127 
128  Def0->eraseFromParent();
129  Def1->eraseFromParent();
130  LIS->InsertMachineInstrInMaps(*NewI);
131  LIS->removeInterval(Reg);
132  LIS->createAndComputeVirtRegInterval(Reg);
133 
134  LLVM_DEBUG(dbgs() << " " << *NewI);
135 
136  return true;
137 }
138 
139 bool GCNPreRAOptimizations::runOnMachineFunction(MachineFunction &MF) {
140  if (skipFunction(MF.getFunction()))
141  return false;
142 
143  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
144  TII = ST.getInstrInfo();
145  MRI = &MF.getRegInfo();
146  LIS = &getAnalysis<LiveIntervals>();
147  const SIRegisterInfo *TRI = ST.getRegisterInfo();
148 
149  bool Changed = false;
150 
151  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
153  if (!LIS->hasInterval(Reg))
154  continue;
155  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
156  if (RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC))
157  continue;
158  Changed |= processReg(Reg);
159  }
160 
161  return Changed;
162 }
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
llvm::MCRegisterClass::getSizeInBits
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
Definition: MCRegisterInfo.h:86
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(GCNPreRAOptimizations, DEBUG_TYPE, "AMDGPU Pre-RA optimizations", false, false) INITIALIZE_PASS_END(GCNPreRAOptimizations
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
GCNSubtarget.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::createGCNPreRAOptimizationsPass
FunctionPass * createGCNPreRAOptimizationsPass()
Definition: GCNPreRAOptimizations.cpp:80
llvm::SlotIndex::isEarlierInstr
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
Definition: SlotIndexes.h:203
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:28
optimizations
Pre RA optimizations
Definition: GCNPreRAOptimizations.cpp:73
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
AMDGPUMCTargetDesc.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
LiveIntervals.h
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:405
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
AMDGPU.h
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Init
Definition: Record.h:271
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
DEBUG_TYPE
#define DEBUG_TYPE
Definition: GCNPreRAOptimizations.cpp:36
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:78
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
InitializePasses.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37