LLVM  16.0.0git
SILowerSGPRSpills.cpp
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1 //===-- SILowerSGPRSPills.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Handle SGPR spills. This pass takes the place of PrologEpilogInserter for all
10 // SGPR spills, so must insert CSR SGPR spills as well as expand them.
11 //
12 // This pass must never create new SGPR virtual registers.
13 //
14 // FIXME: Must stop RegScavenger spills in later passes.
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #include "AMDGPU.h"
19 #include "GCNSubtarget.h"
21 #include "SIMachineFunctionInfo.h"
25 #include "llvm/InitializePasses.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "si-lower-sgpr-spills"
30 
32 
33 namespace {
34 
35 class SILowerSGPRSpills : public MachineFunctionPass {
36 private:
37  const SIRegisterInfo *TRI = nullptr;
38  const SIInstrInfo *TII = nullptr;
39  LiveIntervals *LIS = nullptr;
40  SlotIndexes *Indexes = nullptr;
41 
42  // Save and Restore blocks of the current function. Typically there is a
43  // single save block, unless Windows EH funclets are involved.
44  MBBVector SaveBlocks;
45  MBBVector RestoreBlocks;
46 
47 public:
48  static char ID;
49 
50  SILowerSGPRSpills() : MachineFunctionPass(ID) {}
51 
52  void calculateSaveRestoreBlocks(MachineFunction &MF);
53  bool spillCalleeSavedRegs(MachineFunction &MF);
54 
55  bool runOnMachineFunction(MachineFunction &MF) override;
56 
57  void getAnalysisUsage(AnalysisUsage &AU) const override {
58  AU.setPreservesAll();
60  }
61 };
62 
63 } // end anonymous namespace
64 
65 char SILowerSGPRSpills::ID = 0;
66 
67 INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE,
68  "SI lower SGPR spill instructions", false, false)
71 INITIALIZE_PASS_END(SILowerSGPRSpills, DEBUG_TYPE,
72  "SI lower SGPR spill instructions", false, false)
73 
74 char &llvm::SILowerSGPRSpillsID = SILowerSGPRSpills::ID;
75 
76 /// Insert spill code for the callee-saved registers used in the function.
77 static void insertCSRSaves(MachineBasicBlock &SaveBlock,
78  ArrayRef<CalleeSavedInfo> CSI, SlotIndexes *Indexes,
79  LiveIntervals *LIS) {
80  MachineFunction &MF = *SaveBlock.getParent();
85  const SIRegisterInfo *RI = ST.getRegisterInfo();
86 
87  MachineBasicBlock::iterator I = SaveBlock.begin();
88  if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
89  const MachineRegisterInfo &MRI = MF.getRegInfo();
90 
91  for (const CalleeSavedInfo &CS : CSI) {
92  // Insert the spill to the stack frame.
93  MCRegister Reg = CS.getReg();
94 
95  MachineInstrSpan MIS(I, &SaveBlock);
97  Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
98 
99  // If this value was already livein, we probably have a direct use of the
100  // incoming register value, so don't kill at the spill point. This happens
101  // since we pass some special inputs (workgroup IDs) in the callee saved
102  // range.
103  const bool IsLiveIn = MRI.isLiveIn(Reg);
104  TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
105  RC, TRI);
106 
107  if (Indexes) {
108  assert(std::distance(MIS.begin(), I) == 1);
109  MachineInstr &Inst = *std::prev(I);
110  Indexes->insertMachineInstrInMaps(Inst);
111  }
112 
113  if (LIS)
114  LIS->removeAllRegUnitsForPhysReg(Reg);
115  }
116  }
117 }
118 
119 /// Insert restore code for the callee-saved registers used in the function.
120 static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
122  SlotIndexes *Indexes, LiveIntervals *LIS) {
123  MachineFunction &MF = *RestoreBlock.getParent();
124  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
127  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
128  const SIRegisterInfo *RI = ST.getRegisterInfo();
129  // Restore all registers immediately before the return and any
130  // terminators that precede it.
132 
133  // FIXME: Just emit the readlane/writelane directly
134  if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) {
135  for (const CalleeSavedInfo &CI : reverse(CSI)) {
136  Register Reg = CI.getReg();
138  Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
139 
140  TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI);
141  assert(I != RestoreBlock.begin() &&
142  "loadRegFromStackSlot didn't insert any code!");
143  // Insert in reverse order. loadRegFromStackSlot can insert
144  // multiple instructions.
145 
146  if (Indexes) {
147  MachineInstr &Inst = *std::prev(I);
148  Indexes->insertMachineInstrInMaps(Inst);
149  }
150 
151  if (LIS)
153  }
154  }
155 }
156 
157 /// Compute the sets of entry and return blocks for saving and restoring
158 /// callee-saved registers, and placing prolog and epilog code.
159 void SILowerSGPRSpills::calculateSaveRestoreBlocks(MachineFunction &MF) {
160  const MachineFrameInfo &MFI = MF.getFrameInfo();
161 
162  // Even when we do not change any CSR, we still want to insert the
163  // prologue and epilogue of the function.
164  // So set the save points for those.
165 
166  // Use the points found by shrink-wrapping, if any.
167  if (MFI.getSavePoint()) {
168  SaveBlocks.push_back(MFI.getSavePoint());
169  assert(MFI.getRestorePoint() && "Both restore and save must be set");
170  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
171  // If RestoreBlock does not have any successor and is not a return block
172  // then the end point is unreachable and we do not need to insert any
173  // epilogue.
174  if (!RestoreBlock->succ_empty() || RestoreBlock->isReturnBlock())
175  RestoreBlocks.push_back(RestoreBlock);
176  return;
177  }
178 
179  // Save refs to entry and return blocks.
180  SaveBlocks.push_back(&MF.front());
181  for (MachineBasicBlock &MBB : MF) {
182  if (MBB.isEHFuncletEntry())
183  SaveBlocks.push_back(&MBB);
184  if (MBB.isReturnBlock())
185  RestoreBlocks.push_back(&MBB);
186  }
187 }
188 
189 // TODO: To support shrink wrapping, this would need to copy
190 // PrologEpilogInserter's updateLiveness.
192  MachineBasicBlock &EntryBB = MF.front();
193 
194  for (const CalleeSavedInfo &CSIReg : CSI)
195  EntryBB.addLiveIn(CSIReg.getReg());
196  EntryBB.sortUniqueLiveIns();
197 }
198 
199 bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
201  const Function &F = MF.getFunction();
202  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
203  const SIFrameLowering *TFI = ST.getFrameLowering();
204  MachineFrameInfo &MFI = MF.getFrameInfo();
205  RegScavenger *RS = nullptr;
206 
207  // Determine which of the registers in the callee save list should be saved.
208  BitVector SavedRegs;
209  TFI->determineCalleeSavesSGPR(MF, SavedRegs, RS);
210 
211  // Add the code to save and restore the callee saved registers.
212  if (!F.hasFnAttribute(Attribute::Naked)) {
213  // FIXME: This is a lie. The CalleeSavedInfo is incomplete, but this is
214  // necessary for verifier liveness checks.
215  MFI.setCalleeSavedInfoValid(true);
216 
217  std::vector<CalleeSavedInfo> CSI;
218  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
219 
220  for (unsigned I = 0; CSRegs[I]; ++I) {
221  MCRegister Reg = CSRegs[I];
222 
223  if (SavedRegs.test(Reg)) {
224  const TargetRegisterClass *RC =
226  int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
227  TRI->getSpillAlign(*RC), true);
228 
229  CSI.push_back(CalleeSavedInfo(Reg, JunkFI));
230  }
231  }
232 
233  if (!CSI.empty()) {
234  for (MachineBasicBlock *SaveBlock : SaveBlocks)
235  insertCSRSaves(*SaveBlock, CSI, Indexes, LIS);
236 
237  // Add live ins to save blocks.
238  assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
239  updateLiveness(MF, CSI);
240 
241  for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
242  insertCSRRestores(*RestoreBlock, CSI, Indexes, LIS);
243  return true;
244  }
245  }
246 
247  return false;
248 }
249 
250 bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
251  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
252  TII = ST.getInstrInfo();
253  TRI = &TII->getRegisterInfo();
254 
255  LIS = getAnalysisIfAvailable<LiveIntervals>();
256  Indexes = getAnalysisIfAvailable<SlotIndexes>();
257 
258  assert(SaveBlocks.empty() && RestoreBlocks.empty());
259 
260  // First, expose any CSR SGPR spills. This is mostly the same as what PEI
261  // does, but somewhat simpler.
262  calculateSaveRestoreBlocks(MF);
263  bool HasCSRs = spillCalleeSavedRegs(MF);
264 
265  MachineFrameInfo &MFI = MF.getFrameInfo();
268 
269  if (!MFI.hasStackObjects() && !HasCSRs) {
270  SaveBlocks.clear();
271  RestoreBlocks.clear();
272  return false;
273  }
274 
275  bool MadeChange = false;
276  bool NewReservedRegs = false;
277 
278  // TODO: CSR VGPRs will never be spilled to AGPRs. These can probably be
279  // handled as SpilledToReg in regular PrologEpilogInserter.
280  const bool HasSGPRSpillToVGPR = TRI->spillSGPRToVGPR() &&
281  (HasCSRs || FuncInfo->hasSpilledSGPRs());
282  if (HasSGPRSpillToVGPR) {
283  // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
284  // are spilled to VGPRs, in which case we can eliminate the stack usage.
285  //
286  // This operates under the assumption that only other SGPR spills are users
287  // of the frame index.
288 
289  // To track the spill frame indices handled in this pass.
290  BitVector SpillFIs(MFI.getObjectIndexEnd(), false);
291 
292  for (MachineBasicBlock &MBB : MF) {
294  if (!TII->isSGPRSpill(MI))
295  continue;
296 
297  int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
299  if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
300  NewReservedRegs = true;
301  bool Spilled = TRI->eliminateSGPRToVGPRSpillFrameIndex(
302  MI, FI, nullptr, Indexes, LIS);
303  (void)Spilled;
304  assert(Spilled && "failed to spill SGPR to VGPR when allocated");
305  SpillFIs.set(FI);
306  }
307  }
308  }
309 
310  // FIXME: Adding to live-ins redundant with reserving registers.
311  for (MachineBasicBlock &MBB : MF) {
312  for (auto SSpill : FuncInfo->getSGPRSpillVGPRs())
313  MBB.addLiveIn(SSpill.VGPR);
315 
316  // FIXME: The dead frame indices are replaced with a null register from
317  // the debug value instructions. We should instead, update it with the
318  // correct register value. But not sure the register value alone is
319  // adequate to lower the DIExpression. It should be worked out later.
320  for (MachineInstr &MI : MBB) {
321  if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
322  !MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
323  SpillFIs[MI.getOperand(0).getIndex()]) {
324  MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
325  }
326  }
327  }
328 
329  // All those frame indices which are dead by now should be removed from the
330  // function frame. Otherwise, there is a side effect such as re-mapping of
331  // free frame index ids by the later pass(es) like "stack slot coloring"
332  // which in turn could mess-up with the book keeping of "frame index to VGPR
333  // lane".
334  FuncInfo->removeDeadFrameIndices(MFI, /*ResetSGPRSpillStackIDs*/ false);
335 
336  MadeChange = true;
337  }
338 
339  SaveBlocks.clear();
340  RestoreBlocks.clear();
341 
342  // Updated the reserved registers with any VGPRs added for SGPR spills.
343  if (NewReservedRegs)
345 
346  return MadeChange;
347 }
llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs() const
Definition: SIMachineFunctionInfo.h:570
insertCSRSaves
static void insertCSRSaves(MachineBasicBlock &SaveBlock, ArrayRef< CalleeSavedInfo > CSI, SlotIndexes *Indexes, LiveIntervals *LIS)
Insert spill code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:77
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:74
SIMachineFunctionInfo.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::MachineInstrSpan
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Definition: MachineBasicBlock.h:1240
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:602
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
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Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:297
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:864
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:419
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:410
updateLiveness
static void updateLiveness(MachineFunction &MF, ArrayRef< CalleeSavedInfo > CSI)
Definition: SILowerSGPRSpills.cpp:191
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:350
llvm::MachineBasicBlock::push_back
void push_back(MachineInstr *MI)
Definition: MachineBasicBlock.h:902
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
GCNSubtarget.h
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Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::MachineFrameInfo::setCalleeSavedInfoValid
void setCalleeSavedInfoValid(bool v)
Definition: MachineFrameInfo.h:802
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetFrameLowering::spillCalleeSavedRegisters
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: TargetFrameLowering.h:255
llvm::MachineFrameInfo::getRestorePoint
MachineBasicBlock * getRestorePoint() const
Definition: MachineFrameInfo.h:806
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:731
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:319
llvm::MachineInstrSpan::begin
MachineBasicBlock::iterator begin()
Definition: MachineBasicBlock.h:1251
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:509
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:75
llvm::SIFrameLowering
Definition: SIFrameLowering.h:16
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:540
llvm::SIMachineFunctionInfo::hasSpilledSGPRs
bool hasSpilledSGPRs() const
Definition: SIMachineFunctionInfo.h:826
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
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inst_range instructions(Function *F)
Definition: InstIterator.h:133
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
AMDGPUMCTargetDesc.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
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llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:955
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:623
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetFrameLowering::restoreCalleeSavedRegisters
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: TargetFrameLowering.h:269
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:716
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SILowerSGPRSpills.cpp:29
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:384
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1000
AMDGPU.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:436
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFrameInfo::getSavePoint
MachineBasicBlock * getSavePoint() const
Definition: MachineFrameInfo.h:804
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:438
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:96
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:597
MachineFrameInfo.h
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE, "SI lower SGPR spill instructions", false, false) INITIALIZE_PASS_END(SILowerSGPRSpills
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:351
insertCSRRestores
static void insertCSRRestores(MachineBasicBlock &RestoreBlock, MutableArrayRef< CalleeSavedInfo > CSI, SlotIndexes *Indexes, LiveIntervals *LIS)
Insert restore code for the callee-saved registers used in the function.
Definition: SILowerSGPRSpills.cpp:120
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:485
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
spill
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Definition: README-SSE.txt:489
RegisterScavenging.h
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24