LLVM 17.0.0git
AMDGPUResourceUsageAnalysis.cpp
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1//===- AMDGPUResourceUsageAnalysis.h ---- analysis of resources -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// \brief Analyzes how many registers and other resources are used by
11/// functions.
12///
13/// The results of this analysis are used to fill the register usage, flat
14/// usage, etc. into hardware registers.
15///
16/// The analysis takes callees into account. E.g. if a function A that needs 10
17/// VGPRs calls a function B that needs 20 VGPRs, querying the VGPR usage of A
18/// will return 20.
19/// It is assumed that an indirect call can go into any function except
20/// hardware-entrypoints. Therefore the register usage of functions with
21/// indirect calls is estimated as the maximum of all non-entrypoint functions
22/// in the module.
23///
24//===----------------------------------------------------------------------===//
25
27#include "AMDGPU.h"
28#include "GCNSubtarget.h"
34#include "llvm/IR/GlobalAlias.h"
35#include "llvm/IR/GlobalValue.h"
37
38using namespace llvm;
39using namespace llvm::AMDGPU;
40
41#define DEBUG_TYPE "amdgpu-resource-usage"
42
45
46// In code object v4 and older, we need to tell the runtime some amount ahead of
47// time if we don't know the true stack size. Assume a smaller number if this is
48// only due to dynamic / non-entry block allocas.
50 "amdgpu-assume-external-call-stack-size",
51 cl::desc("Assumed stack use of any external call (in bytes)"), cl::Hidden,
52 cl::init(16384));
53
55 "amdgpu-assume-dynamic-stack-object-size",
56 cl::desc("Assumed extra stack use if there are any "
57 "variable sized objects (in bytes)"),
58 cl::Hidden, cl::init(4096));
59
61 "Function register usage analysis", true, true)
62
63static const Function *getCalleeFunction(const MachineOperand &Op) {
64 if (Op.isImm()) {
65 assert(Op.getImm() == 0);
66 return nullptr;
67 }
68 if (auto *GA = dyn_cast<GlobalAlias>(Op.getGlobal()))
69 return cast<Function>(GA->getOperand(0));
70 return cast<Function>(Op.getGlobal());
71}
72
74 const SIInstrInfo &TII, unsigned Reg) {
75 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
76 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
77 return true;
78 }
79
80 return false;
81}
82
84 const GCNSubtarget &ST) const {
85 return NumExplicitSGPR +
87 ST.getTargetID().isXnackOnOrAny());
88}
89
91 const GCNSubtarget &ST, int32_t ArgNumAGPR, int32_t ArgNumVGPR) const {
92 return AMDGPU::getTotalNumVGPRs(ST.hasGFX90AInsts(), ArgNumAGPR, ArgNumVGPR);
93}
94
96 const GCNSubtarget &ST) const {
97 return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
98}
99
101 auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
102 if (!TPC)
103 return false;
104
105 MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
106 const TargetMachine &TM = TPC->getTM<TargetMachine>();
107 bool HasIndirectCall = false;
108
109 CallGraph CG = CallGraph(M);
110 auto End = po_end(&CG);
111
112 // By default, for code object v5 and later, track only the minimum scratch
113 // size
115 if (!AssumedStackSizeForDynamicSizeObjects.getNumOccurrences())
117 if (!AssumedStackSizeForExternalCall.getNumOccurrences())
119 }
120
121 for (auto IT = po_begin(&CG); IT != End; ++IT) {
122 Function *F = IT->getFunction();
123 if (!F || F->isDeclaration())
124 continue;
125
127 assert(MF && "function must have been generated already");
128
129 auto CI =
130 CallGraphResourceInfo.insert(std::pair(F, SIFunctionResourceInfo()));
131 SIFunctionResourceInfo &Info = CI.first->second;
132 assert(CI.second && "should only be called once per function");
133 Info = analyzeResourceUsage(*MF, TM);
134 HasIndirectCall |= Info.HasIndirectCall;
135 }
136
137 // It's possible we have unreachable functions in the module which weren't
138 // visited by the PO traversal. Make sure we have some resource counts to
139 // report.
140 for (const auto &IT : CG) {
141 const Function *F = IT.first;
142 if (!F || F->isDeclaration())
143 continue;
144
145 auto CI =
146 CallGraphResourceInfo.insert(std::pair(F, SIFunctionResourceInfo()));
147 if (!CI.second) // Skip already visited functions
148 continue;
149
150 SIFunctionResourceInfo &Info = CI.first->second;
152 assert(MF && "function must have been generated already");
153 Info = analyzeResourceUsage(*MF, TM);
154 HasIndirectCall |= Info.HasIndirectCall;
155 }
156
157 if (HasIndirectCall)
158 propagateIndirectCallRegisterUsage();
159
160 return false;
161}
162
164AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
165 const MachineFunction &MF, const TargetMachine &TM) const {
166 SIFunctionResourceInfo Info;
167
169 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
170 const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
171 const MachineRegisterInfo &MRI = MF.getRegInfo();
172 const SIInstrInfo *TII = ST.getInstrInfo();
173 const SIRegisterInfo &TRI = TII->getRegisterInfo();
174
175 Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
176 MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI) ||
177 MRI.isLiveIn(MFI->getPreloadedReg(
179
180 // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
181 // instructions aren't used to access the scratch buffer. Inline assembly may
182 // need it though.
183 //
184 // If we only have implicit uses of flat_scr on flat instructions, it is not
185 // really needed.
186 if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
187 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
188 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
189 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
190 Info.UsesFlatScratch = false;
191 }
192
193 Info.PrivateSegmentSize = FrameInfo.getStackSize();
194
195 // Assume a big number if there are any unknown sized objects.
196 Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
197 if (Info.HasDynamicallySizedStack)
198 Info.PrivateSegmentSize += AssumedStackSizeForDynamicSizeObjects;
199
200 if (MFI->isStackRealigned())
201 Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
202
203 Info.UsesVCC =
204 MRI.isPhysRegUsed(AMDGPU::VCC_LO) || MRI.isPhysRegUsed(AMDGPU::VCC_HI);
205
206 // If there are no calls, MachineRegisterInfo can tell us the used register
207 // count easily.
208 // A tail call isn't considered a call for MachineFrameInfo's purposes.
209 if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
210 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
211 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
212 if (MRI.isPhysRegUsed(Reg)) {
213 HighestVGPRReg = Reg;
214 break;
215 }
216 }
217
218 if (ST.hasMAIInsts()) {
219 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
220 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
221 if (MRI.isPhysRegUsed(Reg)) {
222 HighestAGPRReg = Reg;
223 break;
224 }
225 }
226 Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister
227 ? 0
228 : TRI.getHWRegIndex(HighestAGPRReg) + 1;
229 }
230
231 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
232 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
233 if (MRI.isPhysRegUsed(Reg)) {
234 HighestSGPRReg = Reg;
235 break;
236 }
237 }
238
239 // We found the maximum register index. They start at 0, so add one to get
240 // the number of registers.
241 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister
242 ? 0
243 : TRI.getHWRegIndex(HighestVGPRReg) + 1;
244 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister
245 ? 0
246 : TRI.getHWRegIndex(HighestSGPRReg) + 1;
247
248 return Info;
249 }
250
251 int32_t MaxVGPR = -1;
252 int32_t MaxAGPR = -1;
253 int32_t MaxSGPR = -1;
254 uint64_t CalleeFrameSize = 0;
255
256 for (const MachineBasicBlock &MBB : MF) {
257 for (const MachineInstr &MI : MBB) {
258 // TODO: Check regmasks? Do they occur anywhere except calls?
259 for (const MachineOperand &MO : MI.operands()) {
260 unsigned Width = 0;
261 bool IsSGPR = false;
262 bool IsAGPR = false;
263
264 if (!MO.isReg())
265 continue;
266
267 Register Reg = MO.getReg();
268 switch (Reg) {
269 case AMDGPU::EXEC:
270 case AMDGPU::EXEC_LO:
271 case AMDGPU::EXEC_HI:
272 case AMDGPU::SCC:
273 case AMDGPU::M0:
274 case AMDGPU::M0_LO16:
275 case AMDGPU::M0_HI16:
276 case AMDGPU::SRC_SHARED_BASE_LO:
277 case AMDGPU::SRC_SHARED_BASE:
278 case AMDGPU::SRC_SHARED_LIMIT_LO:
279 case AMDGPU::SRC_SHARED_LIMIT:
280 case AMDGPU::SRC_PRIVATE_BASE_LO:
281 case AMDGPU::SRC_PRIVATE_BASE:
282 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
283 case AMDGPU::SRC_PRIVATE_LIMIT:
284 case AMDGPU::SGPR_NULL:
285 case AMDGPU::SGPR_NULL64:
286 case AMDGPU::MODE:
287 continue;
288
289 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
290 llvm_unreachable("src_pops_exiting_wave_id should not be used");
291
292 case AMDGPU::NoRegister:
293 assert(MI.isDebugInstr() &&
294 "Instruction uses invalid noreg register");
295 continue;
296
297 case AMDGPU::VCC:
298 case AMDGPU::VCC_LO:
299 case AMDGPU::VCC_HI:
300 case AMDGPU::VCC_LO_LO16:
301 case AMDGPU::VCC_LO_HI16:
302 case AMDGPU::VCC_HI_LO16:
303 case AMDGPU::VCC_HI_HI16:
304 Info.UsesVCC = true;
305 continue;
306
307 case AMDGPU::FLAT_SCR:
308 case AMDGPU::FLAT_SCR_LO:
309 case AMDGPU::FLAT_SCR_HI:
310 continue;
311
312 case AMDGPU::XNACK_MASK:
313 case AMDGPU::XNACK_MASK_LO:
314 case AMDGPU::XNACK_MASK_HI:
315 llvm_unreachable("xnack_mask registers should not be used");
316
317 case AMDGPU::LDS_DIRECT:
318 llvm_unreachable("lds_direct register should not be used");
319
320 case AMDGPU::TBA:
321 case AMDGPU::TBA_LO:
322 case AMDGPU::TBA_HI:
323 case AMDGPU::TMA:
324 case AMDGPU::TMA_LO:
325 case AMDGPU::TMA_HI:
326 llvm_unreachable("trap handler registers should not be used");
327
328 case AMDGPU::SRC_VCCZ:
329 llvm_unreachable("src_vccz register should not be used");
330
331 case AMDGPU::SRC_EXECZ:
332 llvm_unreachable("src_execz register should not be used");
333
334 case AMDGPU::SRC_SCC:
335 llvm_unreachable("src_scc register should not be used");
336
337 default:
338 break;
339 }
340
341 if (AMDGPU::SGPR_32RegClass.contains(Reg) ||
342 AMDGPU::SGPR_LO16RegClass.contains(Reg) ||
343 AMDGPU::SGPR_HI16RegClass.contains(Reg)) {
344 IsSGPR = true;
345 Width = 1;
346 } else if (AMDGPU::VGPR_32RegClass.contains(Reg) ||
347 AMDGPU::VGPR_LO16RegClass.contains(Reg) ||
348 AMDGPU::VGPR_HI16RegClass.contains(Reg)) {
349 IsSGPR = false;
350 Width = 1;
351 } else if (AMDGPU::AGPR_32RegClass.contains(Reg) ||
352 AMDGPU::AGPR_LO16RegClass.contains(Reg)) {
353 IsSGPR = false;
354 IsAGPR = true;
355 Width = 1;
356 } else if (AMDGPU::SGPR_64RegClass.contains(Reg)) {
357 IsSGPR = true;
358 Width = 2;
359 } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
360 IsSGPR = false;
361 Width = 2;
362 } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
363 IsSGPR = false;
364 IsAGPR = true;
365 Width = 2;
366 } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
367 IsSGPR = false;
368 Width = 3;
369 } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
370 IsSGPR = true;
371 Width = 3;
372 } else if (AMDGPU::AReg_96RegClass.contains(Reg)) {
373 IsSGPR = false;
374 IsAGPR = true;
375 Width = 3;
376 } else if (AMDGPU::SGPR_128RegClass.contains(Reg)) {
377 IsSGPR = true;
378 Width = 4;
379 } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
380 IsSGPR = false;
381 Width = 4;
382 } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
383 IsSGPR = false;
384 IsAGPR = true;
385 Width = 4;
386 } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
387 IsSGPR = false;
388 Width = 5;
389 } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
390 IsSGPR = true;
391 Width = 5;
392 } else if (AMDGPU::AReg_160RegClass.contains(Reg)) {
393 IsSGPR = false;
394 IsAGPR = true;
395 Width = 5;
396 } else if (AMDGPU::VReg_192RegClass.contains(Reg)) {
397 IsSGPR = false;
398 Width = 6;
399 } else if (AMDGPU::SReg_192RegClass.contains(Reg)) {
400 IsSGPR = true;
401 Width = 6;
402 } else if (AMDGPU::AReg_192RegClass.contains(Reg)) {
403 IsSGPR = false;
404 IsAGPR = true;
405 Width = 6;
406 } else if (AMDGPU::VReg_224RegClass.contains(Reg)) {
407 IsSGPR = false;
408 Width = 7;
409 } else if (AMDGPU::SReg_224RegClass.contains(Reg)) {
410 IsSGPR = true;
411 Width = 7;
412 } else if (AMDGPU::AReg_224RegClass.contains(Reg)) {
413 IsSGPR = false;
414 IsAGPR = true;
415 Width = 7;
416 } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
417 IsSGPR = true;
418 Width = 8;
419 } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
420 IsSGPR = false;
421 Width = 8;
422 } else if (AMDGPU::AReg_256RegClass.contains(Reg)) {
423 IsSGPR = false;
424 IsAGPR = true;
425 Width = 8;
426 } else if (AMDGPU::VReg_288RegClass.contains(Reg)) {
427 IsSGPR = false;
428 Width = 9;
429 } else if (AMDGPU::SReg_288RegClass.contains(Reg)) {
430 IsSGPR = true;
431 Width = 9;
432 } else if (AMDGPU::AReg_288RegClass.contains(Reg)) {
433 IsSGPR = false;
434 IsAGPR = true;
435 Width = 9;
436 } else if (AMDGPU::VReg_320RegClass.contains(Reg)) {
437 IsSGPR = false;
438 Width = 10;
439 } else if (AMDGPU::SReg_320RegClass.contains(Reg)) {
440 IsSGPR = true;
441 Width = 10;
442 } else if (AMDGPU::AReg_320RegClass.contains(Reg)) {
443 IsSGPR = false;
444 IsAGPR = true;
445 Width = 10;
446 } else if (AMDGPU::VReg_352RegClass.contains(Reg)) {
447 IsSGPR = false;
448 Width = 11;
449 } else if (AMDGPU::SReg_352RegClass.contains(Reg)) {
450 IsSGPR = true;
451 Width = 11;
452 } else if (AMDGPU::AReg_352RegClass.contains(Reg)) {
453 IsSGPR = false;
454 IsAGPR = true;
455 Width = 11;
456 } else if (AMDGPU::VReg_384RegClass.contains(Reg)) {
457 IsSGPR = false;
458 Width = 12;
459 } else if (AMDGPU::SReg_384RegClass.contains(Reg)) {
460 IsSGPR = true;
461 Width = 12;
462 } else if (AMDGPU::AReg_384RegClass.contains(Reg)) {
463 IsSGPR = false;
464 IsAGPR = true;
465 Width = 12;
466 } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
467 IsSGPR = true;
468 Width = 16;
469 } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
470 IsSGPR = false;
471 Width = 16;
472 } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
473 IsSGPR = false;
474 IsAGPR = true;
475 Width = 16;
476 } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
477 IsSGPR = true;
478 Width = 32;
479 } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
480 IsSGPR = false;
481 Width = 32;
482 } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
483 IsSGPR = false;
484 IsAGPR = true;
485 Width = 32;
486 } else {
487 // We only expect TTMP registers or registers that do not belong to
488 // any RC.
489 assert((AMDGPU::TTMP_32RegClass.contains(Reg) ||
490 AMDGPU::TTMP_64RegClass.contains(Reg) ||
491 AMDGPU::TTMP_128RegClass.contains(Reg) ||
492 AMDGPU::TTMP_256RegClass.contains(Reg) ||
493 AMDGPU::TTMP_512RegClass.contains(Reg) ||
494 !TRI.getPhysRegBaseClass(Reg)) &&
495 "Unknown register class");
496 }
497 unsigned HWReg = TRI.getHWRegIndex(Reg);
498 int MaxUsed = HWReg + Width - 1;
499 if (IsSGPR) {
500 MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
501 } else if (IsAGPR) {
502 MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
503 } else {
504 MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
505 }
506 }
507
508 if (MI.isCall()) {
509 // Pseudo used just to encode the underlying global. Is there a better
510 // way to track this?
511
512 const MachineOperand *CalleeOp =
513 TII->getNamedOperand(MI, AMDGPU::OpName::callee);
514
515 const Function *Callee = getCalleeFunction(*CalleeOp);
517 CallGraphResourceInfo.end();
518
519 // Avoid crashing on undefined behavior with an illegal call to a
520 // kernel. If a callsite's calling convention doesn't match the
521 // function's, it's undefined behavior. If the callsite calling
522 // convention does match, that would have errored earlier.
523 if (Callee && AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
524 report_fatal_error("invalid call to entry function");
525
526 bool IsIndirect = !Callee || Callee->isDeclaration();
527 if (!IsIndirect)
528 I = CallGraphResourceInfo.find(Callee);
529
530 // FIXME: Call site could have norecurse on it
531 if (!Callee || !Callee->doesNotRecurse()) {
532 Info.HasRecursion = true;
533
534 // TODO: If we happen to know there is no stack usage in the
535 // callgraph, we don't need to assume an infinitely growing stack.
536 if (!MI.isReturn()) {
537 // We don't need to assume an unknown stack size for tail calls.
538
539 // FIXME: This only benefits in the case where the kernel does not
540 // directly call the tail called function. If a kernel directly
541 // calls a tail recursive function, we'll assume maximum stack size
542 // based on the regular call instruction.
543 CalleeFrameSize =
544 std::max(CalleeFrameSize,
546 }
547 }
548
549 if (IsIndirect || I == CallGraphResourceInfo.end()) {
550 CalleeFrameSize =
551 std::max(CalleeFrameSize,
553
554 // Register usage of indirect calls gets handled later
555 Info.UsesVCC = true;
556 Info.UsesFlatScratch = ST.hasFlatAddressSpace();
557 Info.HasDynamicallySizedStack = true;
558 Info.HasIndirectCall = true;
559 } else {
560 // We force CodeGen to run in SCC order, so the callee's register
561 // usage etc. should be the cumulative usage of all callees.
562 MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
563 MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
564 MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
565 CalleeFrameSize =
566 std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
567 Info.UsesVCC |= I->second.UsesVCC;
568 Info.UsesFlatScratch |= I->second.UsesFlatScratch;
569 Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
570 Info.HasRecursion |= I->second.HasRecursion;
571 Info.HasIndirectCall |= I->second.HasIndirectCall;
572 }
573 }
574 }
575 }
576
577 Info.NumExplicitSGPR = MaxSGPR + 1;
578 Info.NumVGPR = MaxVGPR + 1;
579 Info.NumAGPR = MaxAGPR + 1;
580 Info.PrivateSegmentSize += CalleeFrameSize;
581
582 return Info;
583}
584
585void AMDGPUResourceUsageAnalysis::propagateIndirectCallRegisterUsage() {
586 // Collect the maximum number of registers from non-hardware-entrypoints.
587 // All these functions are potential targets for indirect calls.
588 int32_t NonKernelMaxSGPRs = 0;
589 int32_t NonKernelMaxVGPRs = 0;
590 int32_t NonKernelMaxAGPRs = 0;
591
592 for (const auto &I : CallGraphResourceInfo) {
593 if (!AMDGPU::isEntryFunctionCC(I.getFirst()->getCallingConv())) {
594 auto &Info = I.getSecond();
595 NonKernelMaxSGPRs = std::max(NonKernelMaxSGPRs, Info.NumExplicitSGPR);
596 NonKernelMaxVGPRs = std::max(NonKernelMaxVGPRs, Info.NumVGPR);
597 NonKernelMaxAGPRs = std::max(NonKernelMaxAGPRs, Info.NumAGPR);
598 }
599 }
600
601 // Add register usage for functions with indirect calls.
602 // For calls to unknown functions, we assume the maximum register usage of
603 // all non-hardware-entrypoints in the current module.
604 for (auto &I : CallGraphResourceInfo) {
605 auto &Info = I.getSecond();
606 if (Info.HasIndirectCall) {
607 Info.NumExplicitSGPR = std::max(Info.NumExplicitSGPR, NonKernelMaxSGPRs);
608 Info.NumVGPR = std::max(Info.NumVGPR, NonKernelMaxVGPRs);
609 Info.NumAGPR = std::max(Info.NumAGPR, NonKernelMaxAGPRs);
610 }
611 }
612}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
amdgpu Simplify well known AMD library false FunctionCallee Callee
static cl::opt< uint32_t > AssumedStackSizeForExternalCall("amdgpu-assume-external-call-stack-size", cl::desc("Assumed stack use of any external call (in bytes)"), cl::Hidden, cl::init(16384))
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
static cl::opt< uint32_t > AssumedStackSizeForDynamicSizeObjects("amdgpu-assume-dynamic-stack-object-size", cl::desc("Assumed extra stack use if there are any " "variable sized objects (in bytes)"), cl::Hidden, cl::init(4096))
#define DEBUG_TYPE
Analyzes how many registers and other resources are used by functions.
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file provides interfaces used to build and manipulate a call graph, which is a very useful tool ...
bool End
Definition: ELF_riscv.cpp:464
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:470
The basic data container for the call graph of a Module of IR.
Definition: CallGraph.h:72
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
Definition: MachineInstr.h:68
This class contains meta information specific to a module.
MachineFunction * getMachineFunction(const Function &F) const
Returns the MachineFunction associated to IR function F if there is one, otherwise nullptr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
unsigned getCodeObjectVersion(const Module &M)
bool isEntryFunctionCC(CallingConv::ID CC)
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
char & AMDGPUResourceUsageAnalysisID
po_iterator< T > po_begin(const T &G)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:511
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
po_iterator< T > po_end(const T &G)
int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR, int32_t NumVGPR) const
bool runOnModule(Module &M) override
runOnModule - Virtual method overriden by subclasses to process the module being operated on.