LLVM 18.0.0git
AVRISelLowering.h
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1//===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_AVR_ISEL_LOWERING_H
15#define LLVM_AVR_ISEL_LOWERING_H
16
19
20namespace llvm {
21
22namespace AVRISD {
23
24/// AVR Specific DAG Nodes
26 /// Start the numbering where the builtin ops leave off.
28 /// Return from subroutine.
30 /// Return from ISR.
32 /// Represents an abstract call instruction,
33 /// which includes a bunch of information.
35 /// A wrapper node for TargetConstantPool,
36 /// TargetExternalSymbol, and TargetGlobalAddress.
38 LSL, ///< Logical shift left.
39 LSLBN, ///< Byte logical shift left N bits.
40 LSLWN, ///< Word logical shift left N bits.
41 LSLHI, ///< Higher 8-bit of word logical shift left.
42 LSLW, ///< Wide logical shift left.
43 LSR, ///< Logical shift right.
44 LSRBN, ///< Byte logical shift right N bits.
45 LSRWN, ///< Word logical shift right N bits.
46 LSRLO, ///< Lower 8-bit of word logical shift right.
47 LSRW, ///< Wide logical shift right.
48 ASR, ///< Arithmetic shift right.
49 ASRBN, ///< Byte arithmetic shift right N bits.
50 ASRWN, ///< Word arithmetic shift right N bits.
51 ASRLO, ///< Lower 8-bit of word arithmetic shift right.
52 ASRW, ///< Wide arithmetic shift right.
53 ROR, ///< Bit rotate right.
54 ROL, ///< Bit rotate left.
55 LSLLOOP, ///< A loop of single logical shift left instructions.
56 LSRLOOP, ///< A loop of single logical shift right instructions.
57 ROLLOOP, ///< A loop of single left bit rotate instructions.
58 RORLOOP, ///< A loop of single right bit rotate instructions.
59 ASRLOOP, ///< A loop of single arithmetic shift right instructions.
60 /// AVR conditional branches. Operand 0 is the chain operand, operand 1
61 /// is the block to branch if condition is true, operand 2 is the
62 /// condition code, and operand 3 is the flag operand produced by a CMP
63 /// or TEST instruction.
65 /// Compare instruction.
67 /// Compare with carry instruction.
69 /// Test for zero or minus instruction.
71 /// Swap Rd[7:4] <-> Rd[3:0].
73 /// Operand 0 and operand 1 are selection variable, operand 2
74 /// is condition code and operand 3 is flag operand.
76};
77
78} // end of namespace AVRISD
79
80class AVRSubtarget;
81class AVRTargetMachine;
82
83/// Performs target lowering for the AVR.
85public:
87 const AVRSubtarget &STI);
88
89public:
90 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
91 return MVT::i8;
92 }
93
95 return MVT::i8;
96 }
97
98 const char *getTargetNodeName(unsigned Opcode) const override;
99
100 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
101
103 SelectionDAG &DAG) const override;
104
105 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
106 unsigned AS,
107 Instruction *I = nullptr) const override;
108
111 SelectionDAG &DAG) const override;
112
115 SelectionDAG &DAG) const override;
116
117 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
118
120 EVT VT) const override;
121
124 MachineBasicBlock *MBB) const override;
125
126 ConstraintType getConstraintType(StringRef Constraint) const override;
127
129 getSingleConstraintMatchWeight(AsmOperandInfo &info,
130 const char *constraint) const override;
131
132 std::pair<unsigned, const TargetRegisterClass *>
134 StringRef Constraint, MVT VT) const override;
135
137 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
138
140 std::vector<SDValue> &Ops,
141 SelectionDAG &DAG) const override;
142
143 Register getRegisterByName(const char *RegName, LLT VT,
144 const MachineFunction &MF) const override;
145
147 const DataLayout &DL) const override {
148 return false;
149 }
150
153 unsigned ExpansionFactor) const override {
155 }
156
157private:
158 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
159 SelectionDAG &DAG, SDLoc dl) const;
160 SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
161 SDLoc dl) const;
162 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
164 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
165 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
171
172 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
173 bool isVarArg,
175 LLVMContext &Context) const override;
176
177 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
179 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
180 SelectionDAG &DAG) const override;
181 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
182 bool isVarArg,
184 const SDLoc &dl, SelectionDAG &DAG,
185 SmallVectorImpl<SDValue> &InVals) const override;
187 SmallVectorImpl<SDValue> &InVals) const override;
188 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
189 CallingConv::ID CallConv, bool isVarArg,
191 const SDLoc &dl, SelectionDAG &DAG,
192 SmallVectorImpl<SDValue> &InVals) const;
193
194protected:
196
197private:
199 bool Tiny) const;
200 MachineBasicBlock *insertWideShift(MachineInstr &MI,
201 MachineBasicBlock *BB) const;
202 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
203 MachineBasicBlock *insertCopyZero(MachineInstr &MI,
204 MachineBasicBlock *BB) const;
205 MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
207 unsigned Opcode, int Width) const;
208};
209
210} // end namespace llvm
211
212#endif // LLVM_AVR_ISEL_LOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
static constexpr uint32_t Opcode
Definition: aarch32.h:200
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
Performs target lowering for the AVR.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const override
For most targets, an LLVM type must be broken down into multiple smaller types.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
const AVRSubtarget & Subtarget
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
A generic AVR implementation.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
NodeType
AVR Specific DAG Nodes.
@ ASRWN
Word arithmetic shift right N bits.
@ RET_GLUE
Return from subroutine.
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
@ RETI_GLUE
Return from ISR.
@ LSLW
Wide logical shift left.
@ ROLLOOP
A loop of single left bit rotate instructions.
@ ASRLO
Lower 8-bit of word arithmetic shift right.
@ ASRLOOP
A loop of single arithmetic shift right instructions.
@ LSRLOOP
A loop of single logical shift right instructions.
@ ROL
Bit rotate left.
@ LSR
Logical shift right.
@ LSRLO
Lower 8-bit of word logical shift right.
@ TST
Test for zero or minus instruction.
@ LSRBN
Byte logical shift right N bits.
@ ASRW
Wide arithmetic shift right.
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
@ CMPC
Compare with carry instruction.
@ LSLWN
Word logical shift left N bits.
@ RORLOOP
A loop of single right bit rotate instructions.
@ FIRST_NUMBER
Start the numbering where the builtin ops leave off.
@ CMP
Compare instruction.
@ ASRBN
Byte arithmetic shift right N bits.
@ ROR
Bit rotate right.
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
@ ASR
Arithmetic shift right.
@ LSRW
Wide logical shift right.
@ LSL
Logical shift left.
@ LSLBN
Byte logical shift left N bits.
@ LSLHI
Higher 8-bit of word logical shift left.
@ LSRWN
Word logical shift right N bits.
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ LSLLOOP
A loop of single logical shift left instructions.
@ BRCOND
AVR conditional branches.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1383
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1455
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1506
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
#define N
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.