LLVM  13.0.0git
ARCISelLowering.cpp
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1 //===- ARCISelLowering.cpp - ARC DAG Lowering Impl --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARCTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARCISelLowering.h"
14 #include "ARC.h"
15 #include "ARCMachineFunctionInfo.h"
16 #include "ARCSubtarget.h"
17 #include "ARCTargetMachine.h"
18 #include "MCTargetDesc/ARCInfo.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include <algorithm>
30 
31 #define DEBUG_TYPE "arc-lower"
32 
33 using namespace llvm;
34 
35 static SDValue lowerCallResult(SDValue Chain, SDValue InFlag,
36  const SmallVectorImpl<CCValAssign> &RVLocs,
37  SDLoc dl, SelectionDAG &DAG,
38  SmallVectorImpl<SDValue> &InVals);
39 
41  switch (isdCC) {
42  case ISD::SETUEQ:
43  return ARCCC::EQ;
44  case ISD::SETUGT:
45  return ARCCC::HI;
46  case ISD::SETUGE:
47  return ARCCC::HS;
48  case ISD::SETULT:
49  return ARCCC::LO;
50  case ISD::SETULE:
51  return ARCCC::LS;
52  case ISD::SETUNE:
53  return ARCCC::NE;
54  case ISD::SETEQ:
55  return ARCCC::EQ;
56  case ISD::SETGT:
57  return ARCCC::GT;
58  case ISD::SETGE:
59  return ARCCC::GE;
60  case ISD::SETLT:
61  return ARCCC::LT;
62  case ISD::SETLE:
63  return ARCCC::LE;
64  case ISD::SETNE:
65  return ARCCC::NE;
66  default:
67  llvm_unreachable("Unhandled ISDCC code.");
68  }
69 }
70 
72  const ARCSubtarget &Subtarget)
73  : TargetLowering(TM), Subtarget(Subtarget) {
74  // Set up the register classes.
75  addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
76 
77  // Compute derived properties from the register classes
79 
81 
83 
84  // Use i32 for setcc operations results (slt, sgt, ...).
87 
88  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
90 
91  // Operations to get us off of the ground.
92  // Basic.
98 
99  // Need barrel shifter.
104 
107 
108  // Need multiplier
114 
120 
121  // Have pseudo instruction for frame addresses.
123  // Custom lower global addresses.
125 
126  // Expand var-args ops.
131 
132  // Other expansions
135 
136  // Sign extend inreg
138 }
139 
140 const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {
141  switch (Opcode) {
142  case ARCISD::BL:
143  return "ARCISD::BL";
144  case ARCISD::CMOV:
145  return "ARCISD::CMOV";
146  case ARCISD::CMP:
147  return "ARCISD::CMP";
148  case ARCISD::BRcc:
149  return "ARCISD::BRcc";
150  case ARCISD::RET:
151  return "ARCISD::RET";
152  case ARCISD::GAWRAPPER:
153  return "ARCISD::GAWRAPPER";
154  }
155  return nullptr;
156 }
157 
158 //===----------------------------------------------------------------------===//
159 // Misc Lower Operation implementation
160 //===----------------------------------------------------------------------===//
161 
162 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
163  SDValue LHS = Op.getOperand(0);
164  SDValue RHS = Op.getOperand(1);
165  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
166  SDValue TVal = Op.getOperand(2);
167  SDValue FVal = Op.getOperand(3);
168  SDLoc dl(Op);
169  ARCCC::CondCode ArcCC = ISDCCtoARCCC(CC);
170  assert(LHS.getValueType() == MVT::i32 && "Only know how to SELECT_CC i32");
171  SDValue Cmp = DAG.getNode(ARCISD::CMP, dl, MVT::Glue, LHS, RHS);
172  return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal,
173  DAG.getConstant(ArcCC, dl, MVT::i32), Cmp);
174 }
175 
176 SDValue ARCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
177  SelectionDAG &DAG) const {
178  SDValue Op0 = Op.getOperand(0);
179  SDLoc dl(Op);
180  assert(Op.getValueType() == MVT::i32 &&
181  "Unhandled target sign_extend_inreg.");
182  // These are legal
183  unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
184  if (Width == 16 || Width == 8)
185  return Op;
186  if (Width >= 32) {
187  return {};
188  }
189  SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0,
190  DAG.getConstant(32 - Width, dl, MVT::i32));
191  SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS,
192  DAG.getConstant(32 - Width, dl, MVT::i32));
193  return SR;
194 }
195 
196 SDValue ARCTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
197  SDValue Chain = Op.getOperand(0);
198  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
199  SDValue LHS = Op.getOperand(2);
200  SDValue RHS = Op.getOperand(3);
201  SDValue Dest = Op.getOperand(4);
202  SDLoc dl(Op);
203  ARCCC::CondCode arcCC = ISDCCtoARCCC(CC);
204  assert(LHS.getValueType() == MVT::i32 && "Only know how to BR_CC i32");
205  return DAG.getNode(ARCISD::BRcc, dl, MVT::Other, Chain, Dest, LHS, RHS,
206  DAG.getConstant(arcCC, dl, MVT::i32));
207 }
208 
209 SDValue ARCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
210  auto *N = cast<JumpTableSDNode>(Op);
211  SDValue GA = DAG.getTargetJumpTable(N->getIndex(), MVT::i32);
212  return DAG.getNode(ARCISD::GAWRAPPER, SDLoc(N), MVT::i32, GA);
213 }
214 
215 #include "ARCGenCallingConv.inc"
216 
217 //===----------------------------------------------------------------------===//
218 // Call Calling Convention Implementation
219 //===----------------------------------------------------------------------===//
220 
221 /// ARC call implementation
222 SDValue ARCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
223  SmallVectorImpl<SDValue> &InVals) const {
224  SelectionDAG &DAG = CLI.DAG;
225  SDLoc &dl = CLI.DL;
227  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
229  SDValue Chain = CLI.Chain;
230  SDValue Callee = CLI.Callee;
231  CallingConv::ID CallConv = CLI.CallConv;
232  bool IsVarArg = CLI.IsVarArg;
233  bool &IsTailCall = CLI.IsTailCall;
234 
235  IsTailCall = false; // Do not support tail calls yet.
236 
238  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
239  *DAG.getContext());
240 
241  CCInfo.AnalyzeCallOperands(Outs, CC_ARC);
242 
244  // Analyze return values to determine the number of bytes of stack required.
245  CCState RetCCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
246  *DAG.getContext());
247  RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), Align(4));
248  RetCCInfo.AnalyzeCallResult(Ins, RetCC_ARC);
249 
250  // Get a count of how many bytes are to be pushed on the stack.
251  unsigned NumBytes = RetCCInfo.getNextStackOffset();
252  auto PtrVT = getPointerTy(DAG.getDataLayout());
253 
254  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
255 
257  SmallVector<SDValue, 12> MemOpChains;
258 
260  // Walk the register/memloc assignments, inserting copies/loads.
261  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
262  CCValAssign &VA = ArgLocs[i];
263  SDValue Arg = OutVals[i];
264 
265  // Promote the value if needed.
266  switch (VA.getLocInfo()) {
267  default:
268  llvm_unreachable("Unknown loc info!");
269  case CCValAssign::Full:
270  break;
271  case CCValAssign::SExt:
272  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
273  break;
274  case CCValAssign::ZExt:
275  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
276  break;
277  case CCValAssign::AExt:
278  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
279  break;
280  }
281 
282  // Arguments that can be passed on register must be kept at
283  // RegsToPass vector
284  if (VA.isRegLoc()) {
285  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
286  } else {
287  assert(VA.isMemLoc() && "Must be register or memory argument.");
288  if (!StackPtr.getNode())
289  StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP,
290  getPointerTy(DAG.getDataLayout()));
291  // Calculate the stack position.
292  SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
293  SDValue PtrOff = DAG.getNode(
294  ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset);
295 
296  SDValue Store =
297  DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
298  MemOpChains.push_back(Store);
299  IsTailCall = false;
300  }
301  }
302 
303  // Transform all store nodes into one single node because
304  // all store nodes are independent of each other.
305  if (!MemOpChains.empty())
306  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
307 
308  // Build a sequence of copy-to-reg nodes chained together with token
309  // chain and flag operands which copy the outgoing args into registers.
310  // The InFlag in necessary since all emitted instructions must be
311  // stuck together.
312  SDValue Glue;
313  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
314  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
315  RegsToPass[i].second, Glue);
316  Glue = Chain.getValue(1);
317  }
318 
319  // If the callee is a GlobalAddress node (quite common, every direct call is)
320  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
321  // Likewise ExternalSymbol -> TargetExternalSymbol.
322  bool IsDirect = true;
323  if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
324  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
325  else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee))
326  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
327  else
328  IsDirect = false;
329  // Branch + Link = #chain, #target_address, #opt_in_flags...
330  // = Chain, Callee, Reg#1, Reg#2, ...
331  //
332  // Returns a chain & a flag for retval copy to use.
333  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
335  Ops.push_back(Chain);
336  Ops.push_back(Callee);
337 
338  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
339  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
340  RegsToPass[i].second.getValueType()));
341 
342  // Add a register mask operand representing the call-preserved registers.
343  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
344  const uint32_t *Mask =
345  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
346  assert(Mask && "Missing call preserved mask for calling convention");
347  Ops.push_back(DAG.getRegisterMask(Mask));
348 
349  if (Glue.getNode())
350  Ops.push_back(Glue);
351 
352  Chain = DAG.getNode(IsDirect ? ARCISD::BL : ARCISD::JL, dl, NodeTys, Ops);
353  Glue = Chain.getValue(1);
354 
355  // Create the CALLSEQ_END node.
356  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
357  DAG.getConstant(0, dl, PtrVT, true), Glue, dl);
358  Glue = Chain.getValue(1);
359 
360  // Handle result values, copying them out of physregs into vregs that we
361  // return.
362  if (IsTailCall)
363  return Chain;
364  return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals);
365 }
366 
367 /// Lower the result values of a call into the appropriate copies out of
368 /// physical registers / memory locations.
370  const SmallVectorImpl<CCValAssign> &RVLocs,
371  SDLoc dl, SelectionDAG &DAG,
372  SmallVectorImpl<SDValue> &InVals) {
373  SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
374  // Copy results out of physical registers.
375  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
376  const CCValAssign &VA = RVLocs[i];
377  if (VA.isRegLoc()) {
378  SDValue RetValue;
379  RetValue =
380  DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue);
381  Chain = RetValue.getValue(1);
382  Glue = RetValue.getValue(2);
383  InVals.push_back(RetValue);
384  } else {
385  assert(VA.isMemLoc() && "Must be memory location.");
386  ResultMemLocs.push_back(
387  std::make_pair(VA.getLocMemOffset(), InVals.size()));
388 
389  // Reserve space for this result.
390  InVals.push_back(SDValue());
391  }
392  }
393 
394  // Copy results out of memory.
395  SmallVector<SDValue, 4> MemOpChains;
396  for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
397  int Offset = ResultMemLocs[i].first;
398  unsigned Index = ResultMemLocs[i].second;
399  SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32);
400  SDValue SpLoc = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
401  DAG.getConstant(Offset, dl, MVT::i32));
402  SDValue Load =
403  DAG.getLoad(MVT::i32, dl, Chain, SpLoc, MachinePointerInfo());
404  InVals[Index] = Load;
405  MemOpChains.push_back(Load.getValue(1));
406  }
407 
408  // Transform all loads nodes into one single node because
409  // all load nodes are independent of each other.
410  if (!MemOpChains.empty())
411  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
412 
413  return Chain;
414 }
415 
416 //===----------------------------------------------------------------------===//
417 // Formal Arguments Calling Convention Implementation
418 //===----------------------------------------------------------------------===//
419 
420 namespace {
421 
422 struct ArgDataPair {
423  SDValue SDV;
424  ISD::ArgFlagsTy Flags;
425 };
426 
427 } // end anonymous namespace
428 
429 /// ARC formal arguments implementation
430 SDValue ARCTargetLowering::LowerFormalArguments(
431  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
432  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
433  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
434  switch (CallConv) {
435  default:
436  llvm_unreachable("Unsupported calling convention");
437  case CallingConv::C:
438  case CallingConv::Fast:
439  return LowerCallArguments(Chain, CallConv, IsVarArg, Ins, dl, DAG, InVals);
440  }
441 }
442 
443 /// Transform physical registers into virtual registers, and generate load
444 /// operations for argument places on the stack.
445 SDValue ARCTargetLowering::LowerCallArguments(
446  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
448  SmallVectorImpl<SDValue> &InVals) const {
450  MachineFrameInfo &MFI = MF.getFrameInfo();
451  MachineRegisterInfo &RegInfo = MF.getRegInfo();
452  auto *AFI = MF.getInfo<ARCFunctionInfo>();
453 
454  // Assign locations to all of the incoming arguments.
456  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
457  *DAG.getContext());
458 
459  CCInfo.AnalyzeFormalArguments(Ins, CC_ARC);
460 
461  unsigned StackSlotSize = 4;
462 
463  if (!IsVarArg)
464  AFI->setReturnStackOffset(CCInfo.getNextStackOffset());
465 
466  // All getCopyFromReg ops must precede any getMemcpys to prevent the
467  // scheduler clobbering a register before it has been copied.
468  // The stages are:
469  // 1. CopyFromReg (and load) arg & vararg registers.
470  // 2. Chain CopyFromReg nodes into a TokenFactor.
471  // 3. Memcpy 'byVal' args & push final InVals.
472  // 4. Chain mem ops nodes into a TokenFactor.
473  SmallVector<SDValue, 4> CFRegNode;
476 
477  // 1a. CopyFromReg (and load) arg registers.
478  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
479  CCValAssign &VA = ArgLocs[i];
480  SDValue ArgIn;
481 
482  if (VA.isRegLoc()) {
483  // Arguments passed in registers
484  EVT RegVT = VA.getLocVT();
485  switch (RegVT.getSimpleVT().SimpleTy) {
486  default: {
487  LLVM_DEBUG(errs() << "LowerFormalArguments Unhandled argument type: "
488  << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
489  llvm_unreachable("Unhandled LowerFormalArguments type.");
490  }
491  case MVT::i32:
492  unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
493  RegInfo.addLiveIn(VA.getLocReg(), VReg);
494  ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
495  CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
496  }
497  } else {
498  // sanity check
499  assert(VA.isMemLoc());
500  // Load the argument to a virtual register
501  unsigned ObjSize = VA.getLocVT().getStoreSize();
502  assert((ObjSize <= StackSlotSize) && "Unhandled argument");
503 
504  // Create the frame index object for this incoming parameter...
505  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
506 
507  // Create the SelectionDAG nodes corresponding to a load
508  // from this parameter
509  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
510  ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
512  }
513  const ArgDataPair ADP = {ArgIn, Ins[i].Flags};
514  ArgData.push_back(ADP);
515  }
516 
517  // 1b. CopyFromReg vararg registers.
518  if (IsVarArg) {
519  // Argument registers
520  static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3,
521  ARC::R4, ARC::R5, ARC::R6, ARC::R7};
522  auto *AFI = MF.getInfo<ARCFunctionInfo>();
523  unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
524  if (FirstVAReg < array_lengthof(ArgRegs)) {
525  int Offset = 0;
526  // Save remaining registers, storing higher register numbers at a higher
527  // address
528  // There are (array_lengthof(ArgRegs) - FirstVAReg) registers which
529  // need to be saved.
530  int VarFI =
531  MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4,
532  CCInfo.getNextStackOffset(), true);
533  AFI->setVarArgsFrameIndex(VarFI);
534  SDValue FIN = DAG.getFrameIndex(VarFI, MVT::i32);
535  for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) {
536  // Move argument from phys reg -> virt reg
537  unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
538  RegInfo.addLiveIn(ArgRegs[i], VReg);
539  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
540  CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
541  SDValue VAObj = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
542  DAG.getConstant(Offset, dl, MVT::i32));
543  // Move argument from virt reg -> stack
544  SDValue Store =
545  DAG.getStore(Val.getValue(1), dl, Val, VAObj, MachinePointerInfo());
546  MemOps.push_back(Store);
547  Offset += 4;
548  }
549  } else {
550  llvm_unreachable("Too many var args parameters.");
551  }
552  }
553 
554  // 2. Chain CopyFromReg nodes into a TokenFactor.
555  if (!CFRegNode.empty())
556  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
557 
558  // 3. Memcpy 'byVal' args & push final InVals.
559  // Aggregates passed "byVal" need to be copied by the callee.
560  // The callee will use a pointer to this copy, rather than the original
561  // pointer.
562  for (const auto &ArgDI : ArgData) {
563  if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) {
564  unsigned Size = ArgDI.Flags.getByValSize();
565  Align Alignment =
566  std::max(Align(StackSlotSize), ArgDI.Flags.getNonZeroByValAlign());
567  // Create a new object on the stack and copy the pointee into it.
568  int FI = MFI.CreateStackObject(Size, Alignment, false);
569  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
570  InVals.push_back(FIN);
571  MemOps.push_back(DAG.getMemcpy(
572  Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32),
573  Alignment, false, false, false, MachinePointerInfo(),
574  MachinePointerInfo()));
575  } else {
576  InVals.push_back(ArgDI.SDV);
577  }
578  }
579 
580  // 4. Chain mem ops nodes into a TokenFactor.
581  if (!MemOps.empty()) {
582  MemOps.push_back(Chain);
583  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
584  }
585 
586  return Chain;
587 }
588 
589 //===----------------------------------------------------------------------===//
590 // Return Value Calling Convention Implementation
591 //===----------------------------------------------------------------------===//
592 
593 bool ARCTargetLowering::CanLowerReturn(
594  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
597  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
598  if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
599  return false;
600  if (CCInfo.getNextStackOffset() != 0 && IsVarArg)
601  return false;
602  return true;
603 }
604 
605 SDValue
606 ARCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
607  bool IsVarArg,
609  const SmallVectorImpl<SDValue> &OutVals,
610  const SDLoc &dl, SelectionDAG &DAG) const {
611  auto *AFI = DAG.getMachineFunction().getInfo<ARCFunctionInfo>();
613 
614  // CCValAssign - represent the assignment of
615  // the return value to a location
617 
618  // CCState - Info about the registers and stack slot.
619  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
620  *DAG.getContext());
621 
622  // Analyze return values.
623  if (!IsVarArg)
624  CCInfo.AllocateStack(AFI->getReturnStackOffset(), Align(4));
625 
626  CCInfo.AnalyzeReturn(Outs, RetCC_ARC);
627 
628  SDValue Flag;
629  SmallVector<SDValue, 4> RetOps(1, Chain);
630  SmallVector<SDValue, 4> MemOpChains;
631  // Handle return values that must be copied to memory.
632  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
633  CCValAssign &VA = RVLocs[i];
634  if (VA.isRegLoc())
635  continue;
636  assert(VA.isMemLoc());
637  if (IsVarArg) {
638  report_fatal_error("Can't return value from vararg function in memory");
639  }
640 
641  int Offset = VA.getLocMemOffset();
642  unsigned ObjSize = VA.getLocVT().getStoreSize();
643  // Create the frame index object for the memory location.
644  int FI = MFI.CreateFixedObject(ObjSize, Offset, false);
645 
646  // Create a SelectionDAG node corresponding to a store
647  // to this memory location.
648  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
649  MemOpChains.push_back(DAG.getStore(
650  Chain, dl, OutVals[i], FIN,
652  }
653 
654  // Transform all store nodes into one single node because
655  // all stores are independent of each other.
656  if (!MemOpChains.empty())
657  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
658 
659  // Now handle return values copied to registers.
660  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
661  CCValAssign &VA = RVLocs[i];
662  if (!VA.isRegLoc())
663  continue;
664  // Copy the result values into the output registers.
665  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
666 
667  // guarantee that all emitted copies are
668  // stuck together, avoiding something bad
669  Flag = Chain.getValue(1);
670  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
671  }
672 
673  RetOps[0] = Chain; // Update chain.
674 
675  // Add the flag if we have it.
676  if (Flag.getNode())
677  RetOps.push_back(Flag);
678 
679  // What to do with the RetOps?
680  return DAG.getNode(ARCISD::RET, dl, MVT::Other, RetOps);
681 }
682 
683 //===----------------------------------------------------------------------===//
684 // Target Optimization Hooks
685 //===----------------------------------------------------------------------===//
686 
687 SDValue ARCTargetLowering::PerformDAGCombine(SDNode *N,
688  DAGCombinerInfo &DCI) const {
689  return {};
690 }
691 
692 //===----------------------------------------------------------------------===//
693 // Addressing mode description hooks
694 //===----------------------------------------------------------------------===//
695 
696 /// Return true if the addressing mode represented by AM is legal for this
697 /// target, for a load/store of the specified type.
699  const AddrMode &AM, Type *Ty,
700  unsigned AS,
701  Instruction *I) const {
702  return AM.Scale == 0;
703 }
704 
705 // Don't emit tail calls for the time being.
706 bool ARCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
707  return false;
708 }
709 
710 SDValue ARCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
711  const ARCRegisterInfo &ARI = *Subtarget.getRegisterInfo();
713  MachineFrameInfo &MFI = MF.getFrameInfo();
714  MFI.setFrameAddressIsTaken(true);
715 
716  EVT VT = Op.getValueType();
717  SDLoc dl(Op);
718  assert(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0 &&
719  "Only support lowering frame addr of current frame.");
720  Register FrameReg = ARI.getFrameRegister(MF);
721  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
722 }
723 
724 SDValue ARCTargetLowering::LowerGlobalAddress(SDValue Op,
725  SelectionDAG &DAG) const {
726  const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
727  const GlobalValue *GV = GN->getGlobal();
728  SDLoc dl(GN);
729  int64_t Offset = GN->getOffset();
730  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, Offset);
731  return DAG.getNode(ARCISD::GAWRAPPER, dl, MVT::i32, GA);
732 }
733 
736  auto *FuncInfo = MF.getInfo<ARCFunctionInfo>();
737 
738  // vastart just stores the address of the VarArgsFrameIndex slot into the
739  // memory location argument.
740  SDLoc dl(Op);
742  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
743  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
744  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
745  MachinePointerInfo(SV));
746 }
747 
749  switch (Op.getOpcode()) {
750  case ISD::GlobalAddress:
751  return LowerGlobalAddress(Op, DAG);
752  case ISD::FRAMEADDR:
753  return LowerFRAMEADDR(Op, DAG);
754  case ISD::SELECT_CC:
755  return LowerSELECT_CC(Op, DAG);
756  case ISD::BR_CC:
757  return LowerBR_CC(Op, DAG);
759  return LowerSIGN_EXTEND_INREG(Op, DAG);
760  case ISD::JumpTable:
761  return LowerJumpTable(Op, DAG);
762  case ISD::VASTART:
763  return LowerVASTART(Op, DAG);
764  default:
765  llvm_unreachable("unimplemented operand");
766  }
767 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:929
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1354
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
ValueTypes.h
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2093
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:919
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1365
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1014
llvm
Definition: AllocatorList.h:23
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:74
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:193
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1362
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1366
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:936
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:735
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
Definition: SelectionDAG.cpp:6633
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1578
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1361
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1002
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:7976
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ARCISD::GAWRAPPER
@ GAWRAPPER
Definition: ARCISelLowering.h:49
llvm::ARCISD::BRcc
@ BRcc
Definition: ARCISelLowering.h:46
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::ARCCC::NE
@ NE
Definition: ARCInfo.h:27
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:247
llvm::ARCCC::LE
@ LE
Definition: ARCInfo.h:37
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
ARCSubtarget.h
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1356
MachineJumpTableInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7305
ARCISelLowering.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1031
llvm::ARCRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARCRegisterInfo.cpp:221
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1352
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:617
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::ARCCC::LS
@ LS
Definition: ARCInfo.h:39
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:946
MachineRegisterInfo.h
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1953
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:953
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7255
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3697
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
LowerVASTART
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
Definition: ARCISelLowering.cpp:734
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:71
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:684
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ARCCC::GT
@ GT
Definition: ARCInfo.h:34
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:69
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::ARCTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: ARCISelLowering.cpp:748
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1363
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:737
llvm::ARCSubtarget
Definition: ARCSubtarget.h:31
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:443
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
Intrinsics.h
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1347
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:302
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:648
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2140
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1704
ARCInfo.h
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2088
llvm::ARCISD::JL
@ JL
Definition: ARCISelLowering.h:37
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1348
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ARCTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: ARCISelLowering.cpp:698
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1353
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:683
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:3720
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1357
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2157
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:616
ARCMachineFunctionInfo.h
llvm::ARCCC::EQ
@ EQ
Definition: ARCInfo.h:26
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::ARCCC::LO
@ LO
Definition: ARCInfo.h:30
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:911
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:3693
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1471
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:761
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:3714
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2106
llvm::ARCCC::CondCode
CondCode
Definition: ARCInfo.h:24
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:7741
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:3718
llvm::GlobalAddressSDNode::getOffset
int64_t getOffset() const
Definition: SelectionDAGNodes.h:1705
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3692
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:612
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::ARCCC::GE
@ GE
Definition: ARCInfo.h:35
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1355
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::ARCISD::CMOV
@ CMOV
Definition: ARCISelLowering.h:43
R6
#define R6(n)
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1032
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:931
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:3722
llvm::ARCSubtarget::getRegisterInfo
const ARCRegisterInfo * getRegisterInfo() const override
Definition: ARCSubtarget.h:55
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3717
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:98
ISDCCtoARCCC
static ARCCC::CondCode ISDCCtoARCCC(ISD::CondCode isdCC)
Definition: ARCISelLowering.cpp:40
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
ARCTargetMachine.h
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::UNDEF
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:204
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:693
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:87
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
CallingConv.h
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:3708
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1364
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:146
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1692
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2325
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
MachineFrameInfo.h
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:516
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:245
llvm::ARCRegisterInfo
Definition: ARCRegisterInfo.h:25
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:197
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1728
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::ARCTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: ARCISelLowering.cpp:140
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:955
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:229
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:912
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1027
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2074
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:647
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:195
llvm::ARCTargetLowering::ARCTargetLowering
ARCTargetLowering(const TargetMachine &TM, const ARCSubtarget &Subtarget)
Definition: ARCISelLowering.cpp:71
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1255
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:649
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:1968
ARC.h
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2321
llvm::ARCCC::HI
@ HI
Definition: ARCInfo.h:38
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:611
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:3721
lowerCallResult
static SDValue lowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
Lower the result values of a call into the appropriate copies out of physical registers / memory loca...
Definition: ARCISelLowering.cpp:369
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:3715
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1022
llvm::ARCCC::LT
@ LT
Definition: ARCInfo.h:36
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:367
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
MachineFunction.h
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:998
llvm::ARCFunctionInfo
ARCFunctionInfo - This class is derived from MachineFunction private ARC target-specific information ...
Definition: ARCMachineFunctionInfo.h:23
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:651
Debug.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:342
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::ARCCC::HS
@ HS
Definition: ARCInfo.h:31