275 EVT VT =
Op.getValueType();
278 "Expected power-of-2 shift amount");
281 if (!isa<ConstantSDNode>(
N->getOperand(1))) {
282 switch (
Op.getOpcode()) {
299 SDValue Amt =
N->getOperand(1);
300 EVT AmtVT = Amt.getValueType();
311 uint64_t ShiftAmount = cast<ConstantSDNode>(
N->getOperand(1))->getZExtValue();
312 SDValue Victim =
N->getOperand(0);
314 switch (
Op.getOpcode()) {
338 if (
Op.getOpcode() ==
ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
344 }
else if (
Op.getOpcode() ==
ISD::SRL && 4 <= ShiftAmount &&
351 }
else if (
Op.getOpcode() ==
ISD::SHL && ShiftAmount == 7) {
356 }
else if (
Op.getOpcode() ==
ISD::SRL && ShiftAmount == 7) {
361 }
else if (
Op.getOpcode() ==
ISD::SRA && ShiftAmount == 6) {
366 }
else if (
Op.getOpcode() ==
ISD::SRA && ShiftAmount == 7) {
375 switch (ShiftAmount) {
394 if (4 <= ShiftAmount && ShiftAmount < 8)
395 switch (
Op.getOpcode()) {
409 else if (8 <= ShiftAmount && ShiftAmount < 12)
410 switch (
Op.getOpcode()) {
435 else if (12 <= ShiftAmount)
436 switch (
Op.getOpcode()) {
463 while (ShiftAmount--) {
464 Victim = DAG.
getNode(Opc8, dl, VT, Victim);
470 SDValue AVRTargetLowering::LowerDivRem(SDValue
Op, SelectionDAG &DAG)
const {
471 unsigned Opcode =
Op->getOpcode();
473 "Invalid opcode for Div/Rem lowering");
475 EVT VT =
Op->getValueType(0);
476 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
479 switch (VT.getSimpleVT().SimpleTy) {
483 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
486 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
489 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
493 SDValue InChain = DAG.getEntryNode();
496 TargetLowering::ArgListEntry Entry;
497 for (SDValue
const &
Value :
Op->op_values()) {
499 Entry.Ty =
Value.getValueType().getTypeForEVT(*DAG.getContext());
500 Entry.IsSExt = IsSigned;
501 Entry.IsZExt = !IsSigned;
502 Args.push_back(Entry);
511 TargetLowering::CallLoweringInfo CLI(DAG);
516 .setSExtResult(IsSigned)
517 .setZExtResult(!IsSigned);
519 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
520 return CallInfo.first;
523 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue
Op,
524 SelectionDAG &DAG)
const {
525 auto DL = DAG.getDataLayout();
527 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
528 int64_t
Offset = cast<GlobalAddressSDNode>(
Op)->getOffset();
536 SDValue AVRTargetLowering::LowerBlockAddress(SDValue
Op,
537 SelectionDAG &DAG)
const {
538 auto DL = DAG.getDataLayout();
539 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
567 SDValue AVRTargetLowering::getAVRCmp(SDValue
LHS, SDValue
RHS,
568 SelectionDAG &DAG, SDLoc
DL)
const {
569 assert((
LHS.getSimpleValueType() ==
RHS.getSimpleValueType()) &&
570 "LHS and RHS have different types");
573 "invalid comparison type");
577 if (
LHS.getSimpleValueType() ==
MVT::i16 && isa<ConstantSDNode>(
RHS)) {
580 DAG.getIntPtrConstant(0,
DL));
582 DAG.getIntPtrConstant(1,
DL));
584 DAG.getIntPtrConstant(0,
DL));
586 DAG.getIntPtrConstant(1,
DL));
600 SDValue &AVRcc, SelectionDAG &DAG,
603 EVT VT =
LHS.getValueType();
604 bool UseTest =
false;
616 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(
RHS)) {
617 switch (
C->getSExtValue()) {
629 LHS = DAG.getConstant(0,
DL, VT);
636 RHS = DAG.getConstant(
C->getSExtValue() + 1,
DL, VT);
649 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(
RHS)) {
650 switch (
C->getSExtValue()) {
655 LHS = DAG.getConstant(0,
DL, VT);
679 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(
RHS)) {
680 RHS = DAG.getConstant(
C->getSExtValue() + 1,
DL, VT);
695 DAG.getIntPtrConstant(0,
DL));
697 DAG.getIntPtrConstant(1,
DL));
699 DAG.getIntPtrConstant(0,
DL));
701 DAG.getIntPtrConstant(1,
DL));
706 DAG.getIntPtrConstant(1,
DL));
709 Cmp = getAVRCmp(LHSlo, RHSlo, DAG,
DL);
714 DAG.getIntPtrConstant(0,
DL));
716 DAG.getIntPtrConstant(1,
DL));
719 DAG.getIntPtrConstant(0,
DL));
721 DAG.getIntPtrConstant(1,
DL));
723 DAG.getIntPtrConstant(0,
DL));
725 DAG.getIntPtrConstant(1,
DL));
728 DAG.getIntPtrConstant(0,
DL));
730 DAG.getIntPtrConstant(1,
DL));
733 DAG.getIntPtrConstant(0,
DL));
735 DAG.getIntPtrConstant(1,
DL));
737 DAG.getIntPtrConstant(0,
DL));
739 DAG.getIntPtrConstant(1,
DL));
744 DAG.getIntPtrConstant(1,
DL));
747 Cmp = getAVRCmp(LHS0, RHS0, DAG,
DL);
759 LHS, DAG.getIntPtrConstant(1,
DL)));
775 SDValue AVRTargetLowering::LowerBR_CC(SDValue
Op, SelectionDAG &DAG)
const {
776 SDValue Chain =
Op.getOperand(0);
778 SDValue
LHS =
Op.getOperand(2);
779 SDValue
RHS =
Op.getOperand(3);
780 SDValue Dest =
Op.getOperand(4);
784 SDValue
Cmp = getAVRCmp(
LHS,
RHS, CC, TargetCC, DAG, dl);
790 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue
Op, SelectionDAG &DAG)
const {
791 SDValue
LHS =
Op.getOperand(0);
792 SDValue
RHS =
Op.getOperand(1);
793 SDValue TrueV =
Op.getOperand(2);
794 SDValue FalseV =
Op.getOperand(3);
799 SDValue
Cmp = getAVRCmp(
LHS,
RHS, CC, TargetCC, DAG, dl);
801 SDVTList VTs = DAG.getVTList(
Op.getValueType(),
MVT::Glue);
802 SDValue Ops[] = {TrueV, FalseV, TargetCC,
Cmp};
807 SDValue AVRTargetLowering::LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const {
808 SDValue
LHS =
Op.getOperand(0);
809 SDValue
RHS =
Op.getOperand(1);
814 SDValue
Cmp = getAVRCmp(
LHS,
RHS, CC, TargetCC, DAG,
DL);
816 SDValue TrueV = DAG.getConstant(1,
DL,
Op.getValueType());
817 SDValue FalseV = DAG.getConstant(0,
DL,
Op.getValueType());
818 SDVTList VTs = DAG.getVTList(
Op.getValueType(),
MVT::Glue);
819 SDValue Ops[] = {TrueV, FalseV, TargetCC,
Cmp};
824 SDValue AVRTargetLowering::LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const {
825 const MachineFunction &MF = DAG.getMachineFunction();
826 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
827 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
828 auto DL = DAG.getDataLayout();
833 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
getPointerTy(
DL));
835 return DAG.getStore(
Op.getOperand(0), dl, FI,
Op.getOperand(1),
836 MachinePointerInfo(SV));
840 switch (
Op.getOpcode()) {
848 return LowerShifts(
Op, DAG);
850 return LowerGlobalAddress(
Op, DAG);
852 return LowerBlockAddress(
Op, DAG);
854 return LowerBR_CC(
Op, DAG);
856 return LowerSELECT_CC(
Op, DAG);
858 return LowerSETCC(
Op, DAG);
860 return LowerVASTART(
Op, DAG);
863 return LowerDivRem(
Op, DAG);
876 switch (
N->getOpcode()) {
939 VT =
LD->getMemoryVT();
940 Op =
LD->getBasePtr().getNode();
947 VT =
ST->getMemoryVT();
948 Op =
ST->getBasePtr().getNode();
965 int RHSC =
RHS->getSExtValue();
995 VT =
LD->getMemoryVT();
999 VT =
ST->getMemoryVT();
1016 int RHSC =
RHS->getSExtValue();
1023 Base =
Op->getOperand(0);
1042 #include "AVRGenCallingConv.inc"
1047 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1048 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1049 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1051 AVR::R22, AVR::R21, AVR::R20};
1053 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1054 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1055 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1056 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1058 AVR::R24R23, AVR::R23R22,
1059 AVR::R22R21, AVR::R21R20};
1062 "8-bit and 16-bit register arrays must be of equal length");
1064 "8-bit and 16-bit register arrays must be of equal length");
1070 template <
typename ArgT>
1087 unsigned NumArgs =
Args.size();
1090 int RegLastIdx = -1;
1092 bool UseStack =
false;
1093 for (
unsigned i = 0;
i != NumArgs;) {
1099 unsigned ArgIndex =
Args[
i].OrigArgIndex;
1102 for (;
j != NumArgs; ++
j) {
1103 if (
Args[
j].OrigArgIndex != ArgIndex)
1105 TotalBytes +=
Args[
j].VT.getStoreSize();
1108 TotalBytes =
alignTo(TotalBytes, 2);
1110 if (TotalBytes == 0)
1113 unsigned RegIdx = RegLastIdx + TotalBytes;
1114 RegLastIdx = RegIdx;
1116 if (RegIdx >= RegList8.
size()) {
1119 for (;
i !=
j; ++
i) {
1136 "calling convention can only manage i8 and i16 types");
1138 assert(
Reg &&
"register not available in calling convention");
1149 template <
typename ArgT>
1152 unsigned TotalBytes = 0;
1154 for (
const ArgT &
Arg :
Args) {
1155 TotalBytes +=
Arg.VT.getStoreSize();
1163 template <
typename ArgT>
1166 unsigned NumArgs =
Args.size();
1169 assert(TotalBytes <= 8 &&
1170 "return values greater than 8 bytes cannot be lowered");
1185 if (TotalBytes > 4) {
1188 TotalBytes =
alignTo(TotalBytes, 2);
1192 int RegIdx = TotalBytes - 1;
1193 for (
unsigned i = 0;
i != NumArgs; ++
i) {
1203 assert(
Reg &&
"register not available in calling convention");
1210 SDValue AVRTargetLowering::LowerFormalArguments(
1212 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
1213 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const {
1214 MachineFunction &MF = DAG.getMachineFunction();
1215 MachineFrameInfo &MFI = MF.getFrameInfo();
1216 auto DL = DAG.getDataLayout();
1219 SmallVector<CCValAssign, 16> ArgLocs;
1220 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1225 CCInfo.AnalyzeFormalArguments(
Ins, ArgCC_AVR_Vararg);
1232 for (CCValAssign &VA : ArgLocs) {
1235 if (VA.isRegLoc()) {
1236 EVT RegVT = VA.getLocVT();
1237 const TargetRegisterClass *RC;
1239 RC = &AVR::GPR8RegClass;
1241 RC = &AVR::DREGSRegClass;
1247 ArgValue = DAG.getCopyFromReg(Chain, dl,
Reg, RegVT);
1255 switch (VA.getLocInfo()) {
1261 ArgValue = DAG.getNode(
ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1265 DAG.getValueType(VA.getValVT()));
1266 ArgValue = DAG.getNode(
ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1270 DAG.getValueType(VA.getValVT()));
1271 ArgValue = DAG.getNode(
ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1275 InVals.push_back(ArgValue);
1280 EVT LocVT = VA.getLocVT();
1283 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1284 VA.getLocMemOffset(),
true);
1289 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1297 unsigned StackSize = CCInfo.getNextStackOffset();
1298 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1300 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize,
true));
1310 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1311 SmallVectorImpl<SDValue> &InVals)
const {
1312 SelectionDAG &DAG = CLI.DAG;
1314 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1315 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1316 SmallVectorImpl<ISD::InputArg> &
Ins = CLI.Ins;
1317 SDValue Chain = CLI.Chain;
1318 SDValue
Callee = CLI.Callee;
1319 bool &isTailCall = CLI.IsTailCall;
1321 bool isVarArg = CLI.IsVarArg;
1323 MachineFunction &MF = DAG.getMachineFunction();
1329 SmallVector<CCValAssign, 16> ArgLocs;
1330 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1337 if (
const GlobalAddressSDNode *
G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1338 const GlobalValue *GV =
G->getGlobal();
1339 if (isa<Function>(GV))
1340 F = cast<Function>(GV);
1342 DAG.getTargetGlobalAddress(GV,
DL,
getPointerTy(DAG.getDataLayout()));
1343 }
else if (
const ExternalSymbolSDNode *ES =
1344 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1345 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1351 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1358 unsigned NumBytes = CCInfo.getNextStackOffset();
1360 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0,
DL);
1362 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1366 bool HasStackArgs =
false;
1367 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1368 CCValAssign &VA = ArgLocs[AI];
1369 EVT RegVT = VA.getLocVT();
1370 SDValue
Arg = OutVals[AI];
1373 switch (VA.getLocInfo()) {
1394 if (VA.isMemLoc()) {
1395 HasStackArgs =
true;
1401 RegsToPass.push_back(std::make_pair(VA.getLocReg(),
Arg));
1411 SmallVector<SDValue, 8> MemOpChains;
1412 for (; AI != AE; AI++) {
1413 CCValAssign &VA = ArgLocs[AI];
1414 SDValue
Arg = OutVals[AI];
1419 SDValue PtrOff = DAG.getNode(
1421 DAG.getRegister(AVR::SP,
getPointerTy(DAG.getDataLayout())),
1422 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1,
DL));
1424 MemOpChains.push_back(
1425 DAG.getStore(Chain,
DL,
Arg, PtrOff,
1429 if (!MemOpChains.empty())
1437 for (
auto Reg : RegsToPass) {
1438 Chain = DAG.getCopyToReg(Chain,
DL,
Reg.first,
Reg.second, InFlag);
1439 InFlag = Chain.getValue(1);
1444 SmallVector<SDValue, 8> Ops;
1445 Ops.push_back(Chain);
1446 Ops.push_back(Callee);
1450 for (
auto Reg : RegsToPass) {
1451 Ops.push_back(DAG.getRegister(
Reg.first,
Reg.second.getValueType()));
1457 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1458 assert(
Mask &&
"Missing call preserved mask for calling convention");
1459 Ops.push_back(DAG.getRegisterMask(
Mask));
1461 if (InFlag.getNode()) {
1462 Ops.push_back(InFlag);
1466 InFlag = Chain.getValue(1);
1469 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes,
DL,
true),
1470 DAG.getIntPtrConstant(0,
DL,
true), InFlag,
DL);
1473 InFlag = Chain.getValue(1);
1478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
Ins,
DL, DAG,
1485 SDValue AVRTargetLowering::LowerCallResult(
1486 SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv,
bool isVarArg,
1487 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
1488 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const {
1491 SmallVector<CCValAssign, 16> RVLocs;
1492 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1497 CCInfo.AnalyzeCallResult(
Ins, RetCC_AVR_BUILTIN);
1503 for (CCValAssign
const &RVLoc : RVLocs) {
1504 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1507 InFlag = Chain.getValue(2);
1508 InVals.push_back(Chain.getValue(0));
1518 bool AVRTargetLowering::CanLowerReturn(
1520 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &
Context)
const {
1522 SmallVector<CCValAssign, 16> RVLocs;
1523 CCState CCInfo(CallConv, isVarArg, MF, RVLocs,
Context);
1524 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1528 return TotalBytes <= 8;
1532 AVRTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
1534 const SmallVectorImpl<ISD::OutputArg> &Outs,
1535 const SmallVectorImpl<SDValue> &OutVals,
1536 const SDLoc &dl, SelectionDAG &DAG)
const {
1538 SmallVector<CCValAssign, 16> RVLocs;
1541 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1544 MachineFunction &MF = DAG.getMachineFunction();
1548 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1554 SmallVector<SDValue, 4> RetOps(1, Chain);
1556 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
1557 CCValAssign &VA = RVLocs[
i];
1558 assert(VA.isRegLoc() &&
"Can only return in registers!");
1560 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[
i],
Flag);
1563 Flag = Chain.getValue(1);
1564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1569 if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1573 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1580 if (
Flag.getNode()) {
1581 RetOps.push_back(
Flag);
1584 return DAG.getNode(RetOpc, dl,
MVT::Other, RetOps);
1591 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &
MI,
1592 MachineBasicBlock *
BB)
const {
1594 const TargetRegisterClass *RC;
1595 bool HasRepeatedOperand =
false;
1596 MachineFunction *
F =
BB->getParent();
1597 MachineRegisterInfo &RI =
F->getRegInfo();
1599 DebugLoc dl =
MI.getDebugLoc();
1601 switch (
MI.getOpcode()) {
1606 RC = &AVR::GPR8RegClass;
1607 HasRepeatedOperand =
true;
1611 RC = &AVR::DREGSRegClass;
1615 RC = &AVR::GPR8RegClass;
1619 RC = &AVR::DREGSRegClass;
1623 RC = &AVR::GPR8RegClass;
1627 RC = &AVR::DREGSRegClass;
1631 RC = &AVR::GPR8RegClass;
1635 RC = &AVR::DREGSRegClass;
1639 RC = &AVR::GPR8RegClass;
1643 RC = &AVR::DREGSRegClass;
1650 for (
I =
BB->getIterator();
I !=
F->end() && &(*
I) !=
BB; ++
I)
1656 MachineBasicBlock *LoopBB =
F->CreateMachineBasicBlock(LLVM_BB);
1657 MachineBasicBlock *CheckBB =
F->CreateMachineBasicBlock(LLVM_BB);
1658 MachineBasicBlock *RemBB =
F->CreateMachineBasicBlock(LLVM_BB);
1660 F->insert(
I, LoopBB);
1661 F->insert(
I, CheckBB);
1662 F->insert(
I, RemBB);
1668 RemBB->transferSuccessorsAndUpdatePHIs(
BB);
1671 BB->addSuccessor(CheckBB);
1672 LoopBB->addSuccessor(CheckBB);
1673 CheckBB->addSuccessor(LoopBB);
1674 CheckBB->addSuccessor(RemBB);
1676 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1677 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1678 Register ShiftReg = RI.createVirtualRegister(RC);
1679 Register ShiftReg2 = RI.createVirtualRegister(RC);
1680 Register ShiftAmtSrcReg =
MI.getOperand(2).getReg();
1690 auto ShiftMI =
BuildMI(LoopBB, dl,
TII.get(Opc), ShiftReg2).
addReg(ShiftReg);
1691 if (HasRepeatedOperand)
1692 ShiftMI.
addReg(ShiftReg);
1700 BuildMI(CheckBB, dl,
TII.get(AVR::PHI), ShiftReg)
1705 BuildMI(CheckBB, dl,
TII.get(AVR::PHI), ShiftAmtReg)
1710 BuildMI(CheckBB, dl,
TII.get(AVR::PHI), DstReg)
1716 BuildMI(CheckBB, dl,
TII.get(AVR::DECRd), ShiftAmtReg2).
addReg(ShiftAmtReg);
1719 MI.eraseFromParent();
1724 if (
I->getOpcode() == AVR::COPY) {
1725 Register SrcReg =
I->getOperand(1).getReg();
1726 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1735 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &
MI,
1736 MachineBasicBlock *
BB)
const {
1752 AVRTargetLowering::insertCopyR1(MachineInstr &
MI, MachineBasicBlock *
BB)
const {
1756 .
add(
MI.getOperand(0))
1758 MI.eraseFromParent();
1764 MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
1765 MachineInstr &
MI, MachineBasicBlock *
BB,
unsigned Opcode,
int Width)
const {
1766 MachineRegisterInfo &
MRI =
BB->getParent()->getRegInfo();
1769 const Register SCRATCH_REGISTER = AVR::R0;
1770 DebugLoc dl =
MI.getDebugLoc();
1781 const TargetRegisterClass *RC =
1782 (
Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
1783 unsigned LoadOpcode = (
Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
1784 unsigned StoreOpcode = (
Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
1793 .
add(
MI.getOperand(1));
1799 .
add(
MI.getOperand(2));
1803 .
add(
MI.getOperand(1))
1809 .
addReg(SCRATCH_REGISTER);
1812 MI.eraseFromParent();
1819 int Opc =
MI.getOpcode();
1834 return insertShift(
MI,
MBB);
1837 return insertMul(
MI,
MBB);
1839 return insertCopyR1(
MI,
MBB);
1840 case AVR::AtomicLoadAdd8:
1841 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ADDRdRr, 8);
1842 case AVR::AtomicLoadAdd16:
1843 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ADDWRdRr, 16);
1844 case AVR::AtomicLoadSub8:
1845 return insertAtomicArithmeticOp(
MI,
MBB, AVR::SUBRdRr, 8);
1846 case AVR::AtomicLoadSub16:
1847 return insertAtomicArithmeticOp(
MI,
MBB, AVR::SUBWRdRr, 16);
1848 case AVR::AtomicLoadAnd8:
1849 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ANDRdRr, 8);
1850 case AVR::AtomicLoadAnd16:
1851 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ANDWRdRr, 16);
1852 case AVR::AtomicLoadOr8:
1853 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ORRdRr, 8);
1854 case AVR::AtomicLoadOr16:
1855 return insertAtomicArithmeticOp(
MI,
MBB, AVR::ORWRdRr, 16);
1856 case AVR::AtomicLoadXor8:
1857 return insertAtomicArithmeticOp(
MI,
MBB, AVR::EORRdRr, 8);
1858 case AVR::AtomicLoadXor16:
1859 return insertAtomicArithmeticOp(
MI,
MBB, AVR::EORWRdRr, 16);
1862 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1863 "Unexpected instr type to insert");
1884 if (FallThrough !=
nullptr) {
1909 MBB->addSuccessor(falseMBB);
1910 MBB->addSuccessor(trueMBB);
1918 MI.getOperand(0).getReg())
1924 MI.eraseFromParent();
1934 if (Constraint.
size() == 1) {
1936 switch (Constraint[0]) {
1979 switch (ConstraintCode[0]) {
1990 Value *CallOperandVal =
info.CallOperandVal;
1995 if (!CallOperandVal) {
2000 switch (*constraint) {
2024 if (
const ConstantFP *
C = dyn_cast<ConstantFP>(CallOperandVal)) {
2031 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2032 if (isUInt<6>(
C->getZExtValue())) {
2038 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2039 if ((
C->getSExtValue() >= -63) && (
C->getSExtValue() <= 0)) {
2045 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2046 if (
C->getZExtValue() == 2) {
2052 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2053 if (
C->getZExtValue() == 0) {
2059 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2066 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2067 if (
C->getSExtValue() == -1) {
2073 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2074 if ((
C->getZExtValue() == 8) || (
C->getZExtValue() == 16) ||
2075 (
C->getZExtValue() == 24)) {
2081 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2082 if (
C->getZExtValue() == 1) {
2088 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
2089 if ((
C->getSExtValue() >= -6) && (
C->getSExtValue() <= 5)) {
2102 std::pair<unsigned, const TargetRegisterClass *>
2106 if (Constraint.
size() == 1) {
2107 switch (Constraint[0]) {
2110 return std::make_pair(0U, &AVR::LD8loRegClass);
2112 return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
2116 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
2120 return std::make_pair(0U, &AVR::LD8RegClass);
2122 return std::make_pair(0U, &AVR::DLDREGSRegClass);
2126 return std::make_pair(0U, &AVR::GPR8loRegClass);
2128 return std::make_pair(0U, &AVR::DREGSloRegClass);
2132 return std::make_pair(0U, &AVR::PTRREGSRegClass);
2135 return std::make_pair(0U, &AVR::GPRSPRegClass);
2138 return std::make_pair(0U, &AVR::GPR8RegClass);
2140 return std::make_pair(0U, &AVR::DREGSRegClass);
2144 return std::make_pair(
unsigned(AVR::R0), &AVR::GPR8RegClass);
2148 return std::make_pair(0U, &AVR::IWREGSRegClass);
2153 return std::make_pair(
unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2158 return std::make_pair(
unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2163 return std::make_pair(
unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2175 std::string &Constraint,
2176 std::vector<SDValue> &Ops,
2180 EVT Ty =
Op.getValueType();
2183 if (Constraint.length() != 1) {
2187 char ConstraintLetter = Constraint[0];
2188 switch (ConstraintLetter) {
2206 int64_t CVal64 =
C->getSExtValue();
2208 switch (ConstraintLetter) {
2210 if (!isUInt<6>(CUVal64))
2215 if (CVal64 < -63 || CVal64 > 0)
2246 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2256 if (CVal64 < -6 || CVal64 > 5)
2266 if (!
FC || !
FC->isZero())
2273 if (Result.getNode()) {
2274 Ops.push_back(Result);
2287 .
Case(
"r0", AVR::R0)
2288 .
Case(
"r1", AVR::R1)
2292 .
Case(
"r0", AVR::R1R0)
2293 .
Case(
"sp", AVR::SP)