LLVM  15.0.0git
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/IR/Function.h"
27 
28 #include "AVR.h"
29 #include "AVRMachineFunctionInfo.h"
30 #include "AVRSubtarget.h"
31 #include "AVRTargetMachine.h"
33 
34 namespace llvm {
35 
37  const AVRSubtarget &STI)
38  : TargetLowering(TM), Subtarget(STI) {
39  // Set up the register classes.
40  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
41  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
42 
43  // Compute derived properties from the register classes.
45 
51 
54 
59 
60  for (MVT VT : MVT::integer_valuetypes()) {
61  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
64  }
65  }
66 
68 
69  for (MVT VT : MVT::integer_valuetypes()) {
74  }
75 
76  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
77  // revert into a sub since we don't have an add with immediate instruction.
80 
81  // our shift instructions are only able to shift 1 bit at a time, so handle
82  // this in a custom way.
92 
97 
103 
114 
116 
117  // Add support for postincrement and predecrement load/stores.
126 
128 
133 
134  // Atomic operations which must be lowered to rtlib calls
135  for (MVT VT : MVT::integer_valuetypes()) {
143  }
144 
145  // Division/remainder
154 
155  // Make division and modulus custom
162 
163  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
166 
167  // Expand 16 bit multiplications.
170 
171  // Expand multiplications to libcalls when there is
172  // no hardware MUL.
176  }
177 
178  for (MVT VT : MVT::integer_valuetypes()) {
181  }
182 
183  for (MVT VT : MVT::integer_valuetypes()) {
187  }
188 
189  for (MVT VT : MVT::integer_valuetypes()) {
191  // TODO: The generated code is pretty poor. Investigate using the
192  // same "shift and subtract with carry" trick that we do for
193  // extending 8-bit to 16-bit. This may require infrastructure
194  // improvements in how we treat 16-bit "registers" to be feasible.
195  }
196 
197  // Division rtlib functions (not supported), use divmod functions instead
198  setLibcallName(RTLIB::SDIV_I8, nullptr);
199  setLibcallName(RTLIB::SDIV_I16, nullptr);
200  setLibcallName(RTLIB::SDIV_I32, nullptr);
201  setLibcallName(RTLIB::UDIV_I8, nullptr);
202  setLibcallName(RTLIB::UDIV_I16, nullptr);
203  setLibcallName(RTLIB::UDIV_I32, nullptr);
204 
205  // Modulus rtlib functions (not supported), use divmod functions instead
206  setLibcallName(RTLIB::SREM_I8, nullptr);
207  setLibcallName(RTLIB::SREM_I16, nullptr);
208  setLibcallName(RTLIB::SREM_I32, nullptr);
209  setLibcallName(RTLIB::UREM_I8, nullptr);
210  setLibcallName(RTLIB::UREM_I16, nullptr);
211  setLibcallName(RTLIB::UREM_I32, nullptr);
212 
213  // Division and modulus rtlib functions
214  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
215  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
216  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
217  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
218  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
219  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
220 
221  // Several of the runtime library functions use a special calling conv
223  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
225  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
226 
227  // Trigonometric rtlib functions
228  setLibcallName(RTLIB::SIN_F32, "sin");
229  setLibcallName(RTLIB::COS_F32, "cos");
230 
232  setMinimumJumpTableEntries(UINT_MAX);
233 }
234 
235 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
236 #define NODE(name) \
237  case AVRISD::name: \
238  return #name
239 
240  switch (Opcode) {
241  default:
242  return nullptr;
243  NODE(RET_FLAG);
244  NODE(RETI_FLAG);
245  NODE(CALL);
246  NODE(WRAPPER);
247  NODE(LSL);
248  NODE(LSR);
249  NODE(ROL);
250  NODE(ROR);
251  NODE(ASR);
252  NODE(LSLLOOP);
253  NODE(LSRLOOP);
254  NODE(ROLLOOP);
255  NODE(RORLOOP);
256  NODE(ASRLOOP);
257  NODE(BRCOND);
258  NODE(CMP);
259  NODE(CMPC);
260  NODE(TST);
261  NODE(SELECT_CC);
262 #undef NODE
263  }
264 }
265 
267  EVT VT) const {
268  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
269  return MVT::i8;
270 }
271 
272 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
273  unsigned Opc8;
274  const SDNode *N = Op.getNode();
275  EVT VT = Op.getValueType();
276  SDLoc dl(N);
278  "Expected power-of-2 shift amount");
279 
280  // Expand non-constant shifts to loops.
281  if (!isa<ConstantSDNode>(N->getOperand(1))) {
282  switch (Op.getOpcode()) {
283  default:
284  llvm_unreachable("Invalid shift opcode!");
285  case ISD::SHL:
286  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
287  N->getOperand(1));
288  case ISD::SRL:
289  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
290  N->getOperand(1));
291  case ISD::ROTL: {
292  SDValue Amt = N->getOperand(1);
293  EVT AmtVT = Amt.getValueType();
294  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
295  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
296  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
297  }
298  case ISD::ROTR: {
299  SDValue Amt = N->getOperand(1);
300  EVT AmtVT = Amt.getValueType();
301  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
302  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
303  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
304  }
305  case ISD::SRA:
306  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
307  N->getOperand(1));
308  }
309  }
310 
311  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
312  SDValue Victim = N->getOperand(0);
313 
314  switch (Op.getOpcode()) {
315  case ISD::SRA:
316  Opc8 = AVRISD::ASR;
317  break;
318  case ISD::ROTL:
319  Opc8 = AVRISD::ROL;
320  ShiftAmount = ShiftAmount % VT.getSizeInBits();
321  break;
322  case ISD::ROTR:
323  Opc8 = AVRISD::ROR;
324  ShiftAmount = ShiftAmount % VT.getSizeInBits();
325  break;
326  case ISD::SRL:
327  Opc8 = AVRISD::LSR;
328  break;
329  case ISD::SHL:
330  Opc8 = AVRISD::LSL;
331  break;
332  default:
333  llvm_unreachable("Invalid shift opcode");
334  }
335 
336  // Optimize int8/int16 shifts.
337  if (VT.getSizeInBits() == 8) {
338  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
339  // Optimize LSL when 4 <= ShiftAmount <= 6.
340  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
341  Victim =
342  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
343  ShiftAmount -= 4;
344  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
345  ShiftAmount < 7) {
346  // Optimize LSR when 4 <= ShiftAmount <= 6.
347  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
348  Victim =
349  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
350  ShiftAmount -= 4;
351  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
352  // Optimize LSL when ShiftAmount == 7.
353  Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
354  DAG.getConstant(7, dl, VT));
355  ShiftAmount = 0;
356  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
357  // Optimize LSR when ShiftAmount == 7.
358  Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
359  DAG.getConstant(7, dl, VT));
360  ShiftAmount = 0;
361  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
362  // Optimize ASR when ShiftAmount == 6.
363  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
364  DAG.getConstant(6, dl, VT));
365  ShiftAmount = 0;
366  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
367  // Optimize ASR when ShiftAmount == 7.
368  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
369  DAG.getConstant(7, dl, VT));
370  ShiftAmount = 0;
371  }
372  } else if (VT.getSizeInBits() == 16) {
373  if (Op.getOpcode() == ISD::SRA)
374  // Special optimization for int16 arithmetic right shift.
375  switch (ShiftAmount) {
376  case 15:
377  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
378  DAG.getConstant(15, dl, VT));
379  ShiftAmount = 0;
380  break;
381  case 14:
382  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
383  DAG.getConstant(14, dl, VT));
384  ShiftAmount = 0;
385  break;
386  case 7:
387  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
388  DAG.getConstant(7, dl, VT));
389  ShiftAmount = 0;
390  break;
391  default:
392  break;
393  }
394  if (4 <= ShiftAmount && ShiftAmount < 8)
395  switch (Op.getOpcode()) {
396  case ISD::SHL:
397  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
398  DAG.getConstant(4, dl, VT));
399  ShiftAmount -= 4;
400  break;
401  case ISD::SRL:
402  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
403  DAG.getConstant(4, dl, VT));
404  ShiftAmount -= 4;
405  break;
406  default:
407  break;
408  }
409  else if (8 <= ShiftAmount && ShiftAmount < 12)
410  switch (Op.getOpcode()) {
411  case ISD::SHL:
412  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
413  DAG.getConstant(8, dl, VT));
414  ShiftAmount -= 8;
415  // Only operate on the higher byte for remaining shift bits.
416  Opc8 = AVRISD::LSLHI;
417  break;
418  case ISD::SRL:
419  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
420  DAG.getConstant(8, dl, VT));
421  ShiftAmount -= 8;
422  // Only operate on the lower byte for remaining shift bits.
423  Opc8 = AVRISD::LSRLO;
424  break;
425  case ISD::SRA:
426  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
427  DAG.getConstant(8, dl, VT));
428  ShiftAmount -= 8;
429  // Only operate on the lower byte for remaining shift bits.
430  Opc8 = AVRISD::ASRLO;
431  break;
432  default:
433  break;
434  }
435  else if (12 <= ShiftAmount)
436  switch (Op.getOpcode()) {
437  case ISD::SHL:
438  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
439  DAG.getConstant(12, dl, VT));
440  ShiftAmount -= 12;
441  // Only operate on the higher byte for remaining shift bits.
442  Opc8 = AVRISD::LSLHI;
443  break;
444  case ISD::SRL:
445  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
446  DAG.getConstant(12, dl, VT));
447  ShiftAmount -= 12;
448  // Only operate on the lower byte for remaining shift bits.
449  Opc8 = AVRISD::LSRLO;
450  break;
451  case ISD::SRA:
452  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
453  DAG.getConstant(8, dl, VT));
454  ShiftAmount -= 8;
455  // Only operate on the lower byte for remaining shift bits.
456  Opc8 = AVRISD::ASRLO;
457  break;
458  default:
459  break;
460  }
461  }
462 
463  while (ShiftAmount--) {
464  Victim = DAG.getNode(Opc8, dl, VT, Victim);
465  }
466 
467  return Victim;
468 }
469 
470 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
471  unsigned Opcode = Op->getOpcode();
472  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
473  "Invalid opcode for Div/Rem lowering");
474  bool IsSigned = (Opcode == ISD::SDIVREM);
475  EVT VT = Op->getValueType(0);
476  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
477 
478  RTLIB::Libcall LC;
479  switch (VT.getSimpleVT().SimpleTy) {
480  default:
481  llvm_unreachable("Unexpected request for libcall!");
482  case MVT::i8:
483  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
484  break;
485  case MVT::i16:
486  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
487  break;
488  case MVT::i32:
489  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
490  break;
491  }
492 
493  SDValue InChain = DAG.getEntryNode();
494 
496  TargetLowering::ArgListEntry Entry;
497  for (SDValue const &Value : Op->op_values()) {
498  Entry.Node = Value;
499  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
500  Entry.IsSExt = IsSigned;
501  Entry.IsZExt = !IsSigned;
502  Args.push_back(Entry);
503  }
504 
505  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
506  getPointerTy(DAG.getDataLayout()));
507 
508  Type *RetTy = (Type *)StructType::get(Ty, Ty);
509 
510  SDLoc dl(Op);
511  TargetLowering::CallLoweringInfo CLI(DAG);
512  CLI.setDebugLoc(dl)
513  .setChain(InChain)
514  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
515  .setInRegister()
516  .setSExtResult(IsSigned)
517  .setZExtResult(!IsSigned);
518 
519  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
520  return CallInfo.first;
521 }
522 
523 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
524  SelectionDAG &DAG) const {
525  auto DL = DAG.getDataLayout();
526 
527  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
528  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
529 
530  // Create the TargetGlobalAddress node, folding in the constant offset.
531  SDValue Result =
532  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
533  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
534 }
535 
536 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
537  SelectionDAG &DAG) const {
538  auto DL = DAG.getDataLayout();
539  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
540 
541  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
542 
543  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
544 }
545 
546 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
548  switch (CC) {
549  default:
550  llvm_unreachable("Unknown condition code!");
551  case ISD::SETEQ:
552  return AVRCC::COND_EQ;
553  case ISD::SETNE:
554  return AVRCC::COND_NE;
555  case ISD::SETGE:
556  return AVRCC::COND_GE;
557  case ISD::SETLT:
558  return AVRCC::COND_LT;
559  case ISD::SETUGE:
560  return AVRCC::COND_SH;
561  case ISD::SETULT:
562  return AVRCC::COND_LO;
563  }
564 }
565 
566 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
567 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
568  SelectionDAG &DAG, SDLoc DL) const {
569  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
570  "LHS and RHS have different types");
571  assert(((LHS.getSimpleValueType() == MVT::i16) ||
572  (LHS.getSimpleValueType() == MVT::i8)) &&
573  "invalid comparison type");
574 
575  SDValue Cmp;
576 
577  if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
578  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
579  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
580  DAG.getIntPtrConstant(0, DL));
581  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
582  DAG.getIntPtrConstant(1, DL));
583  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
584  DAG.getIntPtrConstant(0, DL));
585  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
586  DAG.getIntPtrConstant(1, DL));
587  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
588  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
589  } else {
590  // Generate ordinary 16-bit comparison.
591  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
592  }
593 
594  return Cmp;
595 }
596 
597 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
598 /// the given operands.
599 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
600  SDValue &AVRcc, SelectionDAG &DAG,
601  SDLoc DL) const {
602  SDValue Cmp;
603  EVT VT = LHS.getValueType();
604  bool UseTest = false;
605 
606  switch (CC) {
607  default:
608  break;
609  case ISD::SETLE: {
610  // Swap operands and reverse the branching condition.
611  std::swap(LHS, RHS);
612  CC = ISD::SETGE;
613  break;
614  }
615  case ISD::SETGT: {
616  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
617  switch (C->getSExtValue()) {
618  case -1: {
619  // When doing lhs > -1 use a tst instruction on the top part of lhs
620  // and use brpl instead of using a chain of cp/cpc.
621  UseTest = true;
622  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
623  break;
624  }
625  case 0: {
626  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
627  // __zero_reg__ in lhs.
628  RHS = LHS;
629  LHS = DAG.getConstant(0, DL, VT);
630  CC = ISD::SETLT;
631  break;
632  }
633  default: {
634  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
635  // us to fold the constant into the cmp instruction.
636  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
637  CC = ISD::SETGE;
638  break;
639  }
640  }
641  break;
642  }
643  // Swap operands and reverse the branching condition.
644  std::swap(LHS, RHS);
645  CC = ISD::SETLT;
646  break;
647  }
648  case ISD::SETLT: {
649  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
650  switch (C->getSExtValue()) {
651  case 1: {
652  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
653  // __zero_reg__ in lhs.
654  RHS = LHS;
655  LHS = DAG.getConstant(0, DL, VT);
656  CC = ISD::SETGE;
657  break;
658  }
659  case 0: {
660  // When doing lhs < 0 use a tst instruction on the top part of lhs
661  // and use brmi instead of using a chain of cp/cpc.
662  UseTest = true;
663  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
664  break;
665  }
666  }
667  }
668  break;
669  }
670  case ISD::SETULE: {
671  // Swap operands and reverse the branching condition.
672  std::swap(LHS, RHS);
673  CC = ISD::SETUGE;
674  break;
675  }
676  case ISD::SETUGT: {
677  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
678  // fold the constant into the cmp instruction.
679  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
680  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
681  CC = ISD::SETUGE;
682  break;
683  }
684  // Swap operands and reverse the branching condition.
685  std::swap(LHS, RHS);
686  CC = ISD::SETULT;
687  break;
688  }
689  }
690 
691  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
692  // using the default and/or/xor expansion code which is much longer.
693  if (VT == MVT::i32) {
694  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
695  DAG.getIntPtrConstant(0, DL));
696  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
697  DAG.getIntPtrConstant(1, DL));
698  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
699  DAG.getIntPtrConstant(0, DL));
700  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
701  DAG.getIntPtrConstant(1, DL));
702 
703  if (UseTest) {
704  // When using tst we only care about the highest part.
705  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
706  DAG.getIntPtrConstant(1, DL));
707  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
708  } else {
709  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
710  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
711  }
712  } else if (VT == MVT::i64) {
713  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
714  DAG.getIntPtrConstant(0, DL));
715  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
716  DAG.getIntPtrConstant(1, DL));
717 
718  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
719  DAG.getIntPtrConstant(0, DL));
720  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
721  DAG.getIntPtrConstant(1, DL));
722  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
723  DAG.getIntPtrConstant(0, DL));
724  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
725  DAG.getIntPtrConstant(1, DL));
726 
727  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
728  DAG.getIntPtrConstant(0, DL));
729  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
730  DAG.getIntPtrConstant(1, DL));
731 
732  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
733  DAG.getIntPtrConstant(0, DL));
734  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
735  DAG.getIntPtrConstant(1, DL));
736  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
737  DAG.getIntPtrConstant(0, DL));
738  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
739  DAG.getIntPtrConstant(1, DL));
740 
741  if (UseTest) {
742  // When using tst we only care about the highest part.
743  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
744  DAG.getIntPtrConstant(1, DL));
745  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
746  } else {
747  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
748  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
749  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
750  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
751  }
752  } else if (VT == MVT::i8 || VT == MVT::i16) {
753  if (UseTest) {
754  // When using tst we only care about the highest part.
755  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
756  (VT == MVT::i8)
757  ? LHS
758  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
759  LHS, DAG.getIntPtrConstant(1, DL)));
760  } else {
761  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
762  }
763  } else {
764  llvm_unreachable("Invalid comparison size");
765  }
766 
767  // When using a test instruction AVRcc is already set.
768  if (!UseTest) {
769  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
770  }
771 
772  return Cmp;
773 }
774 
775 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
776  SDValue Chain = Op.getOperand(0);
777  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
778  SDValue LHS = Op.getOperand(2);
779  SDValue RHS = Op.getOperand(3);
780  SDValue Dest = Op.getOperand(4);
781  SDLoc dl(Op);
782 
783  SDValue TargetCC;
784  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
785 
786  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
787  Cmp);
788 }
789 
790 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
791  SDValue LHS = Op.getOperand(0);
792  SDValue RHS = Op.getOperand(1);
793  SDValue TrueV = Op.getOperand(2);
794  SDValue FalseV = Op.getOperand(3);
795  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
796  SDLoc dl(Op);
797 
798  SDValue TargetCC;
799  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
800 
801  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
802  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
803 
804  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
805 }
806 
807 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
808  SDValue LHS = Op.getOperand(0);
809  SDValue RHS = Op.getOperand(1);
810  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
811  SDLoc DL(Op);
812 
813  SDValue TargetCC;
814  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
815 
816  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
817  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
818  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
819  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
820 
821  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
822 }
823 
824 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
825  const MachineFunction &MF = DAG.getMachineFunction();
826  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
827  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
828  auto DL = DAG.getDataLayout();
829  SDLoc dl(Op);
830 
831  // Vastart just stores the address of the VarArgsFrameIndex slot into the
832  // memory location argument.
833  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
834 
835  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
836  MachinePointerInfo(SV));
837 }
838 
840  switch (Op.getOpcode()) {
841  default:
842  llvm_unreachable("Don't know how to custom lower this!");
843  case ISD::SHL:
844  case ISD::SRA:
845  case ISD::SRL:
846  case ISD::ROTL:
847  case ISD::ROTR:
848  return LowerShifts(Op, DAG);
849  case ISD::GlobalAddress:
850  return LowerGlobalAddress(Op, DAG);
851  case ISD::BlockAddress:
852  return LowerBlockAddress(Op, DAG);
853  case ISD::BR_CC:
854  return LowerBR_CC(Op, DAG);
855  case ISD::SELECT_CC:
856  return LowerSELECT_CC(Op, DAG);
857  case ISD::SETCC:
858  return LowerSETCC(Op, DAG);
859  case ISD::VASTART:
860  return LowerVASTART(Op, DAG);
861  case ISD::SDIVREM:
862  case ISD::UDIVREM:
863  return LowerDivRem(Op, DAG);
864  }
865 
866  return SDValue();
867 }
868 
869 /// Replace a node with an illegal result type
870 /// with a new node built out of custom code.
873  SelectionDAG &DAG) const {
874  SDLoc DL(N);
875 
876  switch (N->getOpcode()) {
877  case ISD::ADD: {
878  // Convert add (x, imm) into sub (x, -imm).
879  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
880  SDValue Sub = DAG.getNode(
881  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
882  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
883  Results.push_back(Sub);
884  }
885  break;
886  }
887  default: {
888  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
889 
890  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
891  Results.push_back(Res.getValue(I));
892 
893  break;
894  }
895  }
896 }
897 
898 /// Return true if the addressing mode represented
899 /// by AM is legal for this target, for a load/store of the specified type.
901  const AddrMode &AM, Type *Ty,
902  unsigned AS,
903  Instruction *I) const {
904  int64_t Offs = AM.BaseOffs;
905 
906  // Allow absolute addresses.
907  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
908  return true;
909  }
910 
911  // Flash memory instructions only allow zero offsets.
912  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
913  return false;
914  }
915 
916  // Allow reg+<6bit> offset.
917  if (Offs < 0)
918  Offs = -Offs;
919  if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
920  isUInt<6>(Offs)) {
921  return true;
922  }
923 
924  return false;
925 }
926 
927 /// Returns true by value, base pointer and
928 /// offset pointer and addressing mode by reference if the node's address
929 /// can be legally represented as pre-indexed load / store address.
931  SDValue &Offset,
933  SelectionDAG &DAG) const {
934  EVT VT;
935  const SDNode *Op;
936  SDLoc DL(N);
937 
938  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
939  VT = LD->getMemoryVT();
940  Op = LD->getBasePtr().getNode();
941  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
942  return false;
944  return false;
945  }
946  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
947  VT = ST->getMemoryVT();
948  Op = ST->getBasePtr().getNode();
950  return false;
951  }
952  } else {
953  return false;
954  }
955 
956  if (VT != MVT::i8 && VT != MVT::i16) {
957  return false;
958  }
959 
960  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
961  return false;
962  }
963 
964  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
965  int RHSC = RHS->getSExtValue();
966  if (Op->getOpcode() == ISD::SUB)
967  RHSC = -RHSC;
968 
969  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
970  return false;
971  }
972 
973  Base = Op->getOperand(0);
974  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
975  AM = ISD::PRE_DEC;
976 
977  return true;
978  }
979 
980  return false;
981 }
982 
983 /// Returns true by value, base pointer and
984 /// offset pointer and addressing mode by reference if this node can be
985 /// combined with a load / store to form a post-indexed load / store.
987  SDValue &Base,
988  SDValue &Offset,
990  SelectionDAG &DAG) const {
991  EVT VT;
992  SDLoc DL(N);
993 
994  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
995  VT = LD->getMemoryVT();
996  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
997  return false;
998  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
999  VT = ST->getMemoryVT();
1001  return false;
1002  }
1003  } else {
1004  return false;
1005  }
1006 
1007  if (VT != MVT::i8 && VT != MVT::i16) {
1008  return false;
1009  }
1010 
1011  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1012  return false;
1013  }
1014 
1015  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1016  int RHSC = RHS->getSExtValue();
1017  if (Op->getOpcode() == ISD::SUB)
1018  RHSC = -RHSC;
1019  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1020  return false;
1021  }
1022 
1023  Base = Op->getOperand(0);
1024  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1025  AM = ISD::POST_INC;
1026 
1027  return true;
1028  }
1029 
1030  return false;
1031 }
1032 
1034  const GlobalAddressSDNode *GA) const {
1035  return true;
1036 }
1037 
1038 //===----------------------------------------------------------------------===//
1039 // Formal Arguments Calling Convention Implementation
1040 //===----------------------------------------------------------------------===//
1041 
1042 #include "AVRGenCallingConv.inc"
1043 
1044 /// Registers for calling conventions, ordered in reverse as required by ABI.
1045 /// Both arrays must be of the same length.
1046 static const MCPhysReg RegList8AVR[] = {
1047  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1048  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1049  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1050 static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1051  AVR::R22, AVR::R21, AVR::R20};
1052 static const MCPhysReg RegList16AVR[] = {
1053  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1054  AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1055  AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1056  AVR::R11R10, AVR::R10R9, AVR::R9R8};
1057 static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1058  AVR::R24R23, AVR::R23R22,
1059  AVR::R22R21, AVR::R21R20};
1060 
1062  "8-bit and 16-bit register arrays must be of equal length");
1064  "8-bit and 16-bit register arrays must be of equal length");
1065 
1066 /// Analyze incoming and outgoing function arguments. We need custom C++ code
1067 /// to handle special constraints in the ABI.
1068 /// In addition, all pieces of a certain argument have to be passed either
1069 /// using registers or the stack but never mixing both.
1070 template <typename ArgT>
1072  const Function *F, const DataLayout *TD,
1073  const SmallVectorImpl<ArgT> &Args,
1075  CCState &CCInfo, bool Tiny) {
1076  // Choose the proper register list for argument passing according to the ABI.
1077  ArrayRef<MCPhysReg> RegList8;
1078  ArrayRef<MCPhysReg> RegList16;
1079  if (Tiny) {
1082  } else {
1085  }
1086 
1087  unsigned NumArgs = Args.size();
1088  // This is the index of the last used register, in RegList*.
1089  // -1 means R26 (R26 is never actually used in CC).
1090  int RegLastIdx = -1;
1091  // Once a value is passed to the stack it will always be used
1092  bool UseStack = false;
1093  for (unsigned i = 0; i != NumArgs;) {
1094  MVT VT = Args[i].VT;
1095  // We have to count the number of bytes for each function argument, that is
1096  // those Args with the same OrigArgIndex. This is important in case the
1097  // function takes an aggregate type.
1098  // Current argument will be between [i..j).
1099  unsigned ArgIndex = Args[i].OrigArgIndex;
1100  unsigned TotalBytes = VT.getStoreSize();
1101  unsigned j = i + 1;
1102  for (; j != NumArgs; ++j) {
1103  if (Args[j].OrigArgIndex != ArgIndex)
1104  break;
1105  TotalBytes += Args[j].VT.getStoreSize();
1106  }
1107  // Round up to even number of bytes.
1108  TotalBytes = alignTo(TotalBytes, 2);
1109  // Skip zero sized arguments
1110  if (TotalBytes == 0)
1111  continue;
1112  // The index of the first register to be used
1113  unsigned RegIdx = RegLastIdx + TotalBytes;
1114  RegLastIdx = RegIdx;
1115  // If there are not enough registers, use the stack
1116  if (RegIdx >= RegList8.size()) {
1117  UseStack = true;
1118  }
1119  for (; i != j; ++i) {
1120  MVT VT = Args[i].VT;
1121 
1122  if (UseStack) {
1123  auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1124  unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1125  TD->getABITypeAlign(evt));
1126  CCInfo.addLoc(
1127  CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
1128  } else {
1129  unsigned Reg;
1130  if (VT == MVT::i8) {
1131  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1132  } else if (VT == MVT::i16) {
1133  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1134  } else {
1136  "calling convention can only manage i8 and i16 types");
1137  }
1138  assert(Reg && "register not available in calling convention");
1139  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1140  // Registers inside a particular argument are sorted in increasing order
1141  // (remember the array is reversed).
1142  RegIdx -= VT.getStoreSize();
1143  }
1144  }
1145  }
1146 }
1147 
1148 /// Count the total number of bytes needed to pass or return these arguments.
1149 template <typename ArgT>
1150 static unsigned
1152  unsigned TotalBytes = 0;
1153 
1154  for (const ArgT &Arg : Args) {
1155  TotalBytes += Arg.VT.getStoreSize();
1156  }
1157  return TotalBytes;
1158 }
1159 
1160 /// Analyze incoming and outgoing value of returning from a function.
1161 /// The algorithm is similar to analyzeArguments, but there can only be
1162 /// one value, possibly an aggregate, and it is limited to 8 bytes.
1163 template <typename ArgT>
1165  CCState &CCInfo, bool Tiny) {
1166  unsigned NumArgs = Args.size();
1167  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1168  // CanLowerReturn() guarantees this assertion.
1169  assert(TotalBytes <= 8 &&
1170  "return values greater than 8 bytes cannot be lowered");
1171 
1172  // Choose the proper register list for argument passing according to the ABI.
1173  ArrayRef<MCPhysReg> RegList8;
1174  ArrayRef<MCPhysReg> RegList16;
1175  if (Tiny) {
1178  } else {
1181  }
1182 
1183  // GCC-ABI says that the size is rounded up to the next even number,
1184  // but actually once it is more than 4 it will always round up to 8.
1185  if (TotalBytes > 4) {
1186  TotalBytes = 8;
1187  } else {
1188  TotalBytes = alignTo(TotalBytes, 2);
1189  }
1190 
1191  // The index of the first register to use.
1192  int RegIdx = TotalBytes - 1;
1193  for (unsigned i = 0; i != NumArgs; ++i) {
1194  MVT VT = Args[i].VT;
1195  unsigned Reg;
1196  if (VT == MVT::i8) {
1197  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1198  } else if (VT == MVT::i16) {
1199  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1200  } else {
1201  llvm_unreachable("calling convention can only manage i8 and i16 types");
1202  }
1203  assert(Reg && "register not available in calling convention");
1204  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1205  // Registers sort in increasing order
1206  RegIdx -= VT.getStoreSize();
1207  }
1208 }
1209 
1210 SDValue AVRTargetLowering::LowerFormalArguments(
1211  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1212  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1213  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1214  MachineFunction &MF = DAG.getMachineFunction();
1215  MachineFrameInfo &MFI = MF.getFrameInfo();
1216  auto DL = DAG.getDataLayout();
1217 
1218  // Assign locations to all of the incoming arguments.
1219  SmallVector<CCValAssign, 16> ArgLocs;
1220  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1221  *DAG.getContext());
1222 
1223  // Variadic functions do not need all the analysis below.
1224  if (isVarArg) {
1225  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1226  } else {
1227  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo,
1229  }
1230 
1231  SDValue ArgValue;
1232  for (CCValAssign &VA : ArgLocs) {
1233 
1234  // Arguments stored on registers.
1235  if (VA.isRegLoc()) {
1236  EVT RegVT = VA.getLocVT();
1237  const TargetRegisterClass *RC;
1238  if (RegVT == MVT::i8) {
1239  RC = &AVR::GPR8RegClass;
1240  } else if (RegVT == MVT::i16) {
1241  RC = &AVR::DREGSRegClass;
1242  } else {
1243  llvm_unreachable("Unknown argument type!");
1244  }
1245 
1246  Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
1247  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1248 
1249  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1250  // following code will handle zexts or sexts generated by other
1251  // front ends. Otherwise:
1252  // If this is an 8 bit value, it is really passed promoted
1253  // to 16 bits. Insert an assert[sz]ext to capture this, then
1254  // truncate to the right size.
1255  switch (VA.getLocInfo()) {
1256  default:
1257  llvm_unreachable("Unknown loc info!");
1258  case CCValAssign::Full:
1259  break;
1260  case CCValAssign::BCvt:
1261  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1262  break;
1263  case CCValAssign::SExt:
1264  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1265  DAG.getValueType(VA.getValVT()));
1266  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1267  break;
1268  case CCValAssign::ZExt:
1269  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1270  DAG.getValueType(VA.getValVT()));
1271  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1272  break;
1273  }
1274 
1275  InVals.push_back(ArgValue);
1276  } else {
1277  // Only arguments passed on the stack should make it here.
1278  assert(VA.isMemLoc());
1279 
1280  EVT LocVT = VA.getLocVT();
1281 
1282  // Create the frame index object for this incoming parameter.
1283  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1284  VA.getLocMemOffset(), true);
1285 
1286  // Create the SelectionDAG nodes corresponding to a load
1287  // from this parameter.
1288  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1289  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1291  }
1292  }
1293 
1294  // If the function takes variable number of arguments, make a frame index for
1295  // the start of the first vararg value... for expansion of llvm.va_start.
1296  if (isVarArg) {
1297  unsigned StackSize = CCInfo.getNextStackOffset();
1298  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1299 
1300  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1301  }
1302 
1303  return Chain;
1304 }
1305 
1306 //===----------------------------------------------------------------------===//
1307 // Call Calling Convention Implementation
1308 //===----------------------------------------------------------------------===//
1309 
1310 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1311  SmallVectorImpl<SDValue> &InVals) const {
1312  SelectionDAG &DAG = CLI.DAG;
1313  SDLoc &DL = CLI.DL;
1314  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1315  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1316  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1317  SDValue Chain = CLI.Chain;
1318  SDValue Callee = CLI.Callee;
1319  bool &isTailCall = CLI.IsTailCall;
1320  CallingConv::ID CallConv = CLI.CallConv;
1321  bool isVarArg = CLI.IsVarArg;
1322 
1323  MachineFunction &MF = DAG.getMachineFunction();
1324 
1325  // AVR does not yet support tail call optimization.
1326  isTailCall = false;
1327 
1328  // Analyze operands of the call, assigning locations to each operand.
1329  SmallVector<CCValAssign, 16> ArgLocs;
1330  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1331  *DAG.getContext());
1332 
1333  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1334  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1335  // node so that legalize doesn't hack it.
1336  const Function *F = nullptr;
1337  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1338  const GlobalValue *GV = G->getGlobal();
1339  if (isa<Function>(GV))
1340  F = cast<Function>(GV);
1341  Callee =
1342  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1343  } else if (const ExternalSymbolSDNode *ES =
1344  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1345  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1346  getPointerTy(DAG.getDataLayout()));
1347  }
1348 
1349  // Variadic functions do not need all the analysis below.
1350  if (isVarArg) {
1351  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1352  } else {
1353  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo,
1355  }
1356 
1357  // Get a count of how many bytes are to be pushed on the stack.
1358  unsigned NumBytes = CCInfo.getNextStackOffset();
1359 
1360  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1361 
1362  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1363 
1364  // First, walk the register assignments, inserting copies.
1365  unsigned AI, AE;
1366  bool HasStackArgs = false;
1367  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1368  CCValAssign &VA = ArgLocs[AI];
1369  EVT RegVT = VA.getLocVT();
1370  SDValue Arg = OutVals[AI];
1371 
1372  // Promote the value if needed. With Clang this should not happen.
1373  switch (VA.getLocInfo()) {
1374  default:
1375  llvm_unreachable("Unknown loc info!");
1376  case CCValAssign::Full:
1377  break;
1378  case CCValAssign::SExt:
1379  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1380  break;
1381  case CCValAssign::ZExt:
1382  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1383  break;
1384  case CCValAssign::AExt:
1385  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1386  break;
1387  case CCValAssign::BCvt:
1388  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1389  break;
1390  }
1391 
1392  // Stop when we encounter a stack argument, we need to process them
1393  // in reverse order in the loop below.
1394  if (VA.isMemLoc()) {
1395  HasStackArgs = true;
1396  break;
1397  }
1398 
1399  // Arguments that can be passed on registers must be kept in the RegsToPass
1400  // vector.
1401  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1402  }
1403 
1404  // Second, stack arguments have to walked.
1405  // Previously this code created chained stores but those chained stores appear
1406  // to be unchained in the legalization phase. Therefore, do not attempt to
1407  // chain them here. In fact, chaining them here somehow causes the first and
1408  // second store to be reversed which is the exact opposite of the intended
1409  // effect.
1410  if (HasStackArgs) {
1411  SmallVector<SDValue, 8> MemOpChains;
1412  for (; AI != AE; AI++) {
1413  CCValAssign &VA = ArgLocs[AI];
1414  SDValue Arg = OutVals[AI];
1415 
1416  assert(VA.isMemLoc());
1417 
1418  // SP points to one stack slot further so add one to adjust it.
1419  SDValue PtrOff = DAG.getNode(
1420  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1421  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1422  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1423 
1424  MemOpChains.push_back(
1425  DAG.getStore(Chain, DL, Arg, PtrOff,
1426  MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1427  }
1428 
1429  if (!MemOpChains.empty())
1430  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1431  }
1432 
1433  // Build a sequence of copy-to-reg nodes chained together with token chain and
1434  // flag operands which copy the outgoing args into registers. The InFlag in
1435  // necessary since all emited instructions must be stuck together.
1436  SDValue InFlag;
1437  for (auto Reg : RegsToPass) {
1438  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1439  InFlag = Chain.getValue(1);
1440  }
1441 
1442  // Returns a chain & a flag for retval copy to use.
1443  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1444  SmallVector<SDValue, 8> Ops;
1445  Ops.push_back(Chain);
1446  Ops.push_back(Callee);
1447 
1448  // Add argument registers to the end of the list so that they are known live
1449  // into the call.
1450  for (auto Reg : RegsToPass) {
1451  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1452  }
1453 
1454  // Add a register mask operand representing the call-preserved registers.
1455  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1456  const uint32_t *Mask =
1457  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1458  assert(Mask && "Missing call preserved mask for calling convention");
1459  Ops.push_back(DAG.getRegisterMask(Mask));
1460 
1461  if (InFlag.getNode()) {
1462  Ops.push_back(InFlag);
1463  }
1464 
1465  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1466  InFlag = Chain.getValue(1);
1467 
1468  // Create the CALLSEQ_END node.
1469  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1470  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1471 
1472  if (!Ins.empty()) {
1473  InFlag = Chain.getValue(1);
1474  }
1475 
1476  // Handle result values, copying them out of physregs into vregs that we
1477  // return.
1478  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1479  InVals);
1480 }
1481 
1482 /// Lower the result values of a call into the
1483 /// appropriate copies out of appropriate physical registers.
1484 ///
1485 SDValue AVRTargetLowering::LowerCallResult(
1486  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1487  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1488  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1489 
1490  // Assign locations to each value returned by this call.
1491  SmallVector<CCValAssign, 16> RVLocs;
1492  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1493  *DAG.getContext());
1494 
1495  // Handle runtime calling convs.
1496  if (CallConv == CallingConv::AVR_BUILTIN) {
1497  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1498  } else {
1500  }
1501 
1502  // Copy all of the result registers out of their specified physreg.
1503  for (CCValAssign const &RVLoc : RVLocs) {
1504  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1505  InFlag)
1506  .getValue(1);
1507  InFlag = Chain.getValue(2);
1508  InVals.push_back(Chain.getValue(0));
1509  }
1510 
1511  return Chain;
1512 }
1513 
1514 //===----------------------------------------------------------------------===//
1515 // Return Value Calling Convention Implementation
1516 //===----------------------------------------------------------------------===//
1517 
1518 bool AVRTargetLowering::CanLowerReturn(
1519  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1520  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1521  if (CallConv == CallingConv::AVR_BUILTIN) {
1522  SmallVector<CCValAssign, 16> RVLocs;
1523  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1524  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1525  }
1526 
1527  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1528  return TotalBytes <= 8;
1529 }
1530 
1531 SDValue
1532 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1533  bool isVarArg,
1534  const SmallVectorImpl<ISD::OutputArg> &Outs,
1535  const SmallVectorImpl<SDValue> &OutVals,
1536  const SDLoc &dl, SelectionDAG &DAG) const {
1537  // CCValAssign - represent the assignment of the return value to locations.
1538  SmallVector<CCValAssign, 16> RVLocs;
1539 
1540  // CCState - Info about the registers and stack slot.
1541  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1542  *DAG.getContext());
1543 
1544  MachineFunction &MF = DAG.getMachineFunction();
1545 
1546  // Analyze return values.
1547  if (CallConv == CallingConv::AVR_BUILTIN) {
1548  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1549  } else {
1551  }
1552 
1553  SDValue Flag;
1554  SmallVector<SDValue, 4> RetOps(1, Chain);
1555  // Copy the result values into the output registers.
1556  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1557  CCValAssign &VA = RVLocs[i];
1558  assert(VA.isRegLoc() && "Can only return in registers!");
1559 
1560  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1561 
1562  // Guarantee that all emitted copies are stuck together with flags.
1563  Flag = Chain.getValue(1);
1564  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1565  }
1566 
1567  // Don't emit the ret/reti instruction when the naked attribute is present in
1568  // the function being compiled.
1569  if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1570  return Chain;
1571  }
1572 
1573  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1574 
1575  unsigned RetOpc =
1576  AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
1577 
1578  RetOps[0] = Chain; // Update chain.
1579 
1580  if (Flag.getNode()) {
1581  RetOps.push_back(Flag);
1582  }
1583 
1584  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1585 }
1586 
1587 //===----------------------------------------------------------------------===//
1588 // Custom Inserters
1589 //===----------------------------------------------------------------------===//
1590 
1591 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1592  MachineBasicBlock *BB) const {
1593  unsigned Opc;
1594  const TargetRegisterClass *RC;
1595  bool HasRepeatedOperand = false;
1596  MachineFunction *F = BB->getParent();
1597  MachineRegisterInfo &RI = F->getRegInfo();
1598  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1599  DebugLoc dl = MI.getDebugLoc();
1600 
1601  switch (MI.getOpcode()) {
1602  default:
1603  llvm_unreachable("Invalid shift opcode!");
1604  case AVR::Lsl8:
1605  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1606  RC = &AVR::GPR8RegClass;
1607  HasRepeatedOperand = true;
1608  break;
1609  case AVR::Lsl16:
1610  Opc = AVR::LSLWRd;
1611  RC = &AVR::DREGSRegClass;
1612  break;
1613  case AVR::Asr8:
1614  Opc = AVR::ASRRd;
1615  RC = &AVR::GPR8RegClass;
1616  break;
1617  case AVR::Asr16:
1618  Opc = AVR::ASRWRd;
1619  RC = &AVR::DREGSRegClass;
1620  break;
1621  case AVR::Lsr8:
1622  Opc = AVR::LSRRd;
1623  RC = &AVR::GPR8RegClass;
1624  break;
1625  case AVR::Lsr16:
1626  Opc = AVR::LSRWRd;
1627  RC = &AVR::DREGSRegClass;
1628  break;
1629  case AVR::Rol8:
1630  Opc = AVR::ROLBRd;
1631  RC = &AVR::GPR8RegClass;
1632  break;
1633  case AVR::Rol16:
1634  Opc = AVR::ROLWRd;
1635  RC = &AVR::DREGSRegClass;
1636  break;
1637  case AVR::Ror8:
1638  Opc = AVR::RORBRd;
1639  RC = &AVR::GPR8RegClass;
1640  break;
1641  case AVR::Ror16:
1642  Opc = AVR::RORWRd;
1643  RC = &AVR::DREGSRegClass;
1644  break;
1645  }
1646 
1647  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1648 
1650  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1651  ;
1652  if (I != F->end())
1653  ++I;
1654 
1655  // Create loop block.
1656  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1657  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1658  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1659 
1660  F->insert(I, LoopBB);
1661  F->insert(I, CheckBB);
1662  F->insert(I, RemBB);
1663 
1664  // Update machine-CFG edges by transferring all successors of the current
1665  // block to the block containing instructions after shift.
1666  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1667  BB->end());
1668  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1669 
1670  // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1671  BB->addSuccessor(CheckBB);
1672  LoopBB->addSuccessor(CheckBB);
1673  CheckBB->addSuccessor(LoopBB);
1674  CheckBB->addSuccessor(RemBB);
1675 
1676  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1677  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1678  Register ShiftReg = RI.createVirtualRegister(RC);
1679  Register ShiftReg2 = RI.createVirtualRegister(RC);
1680  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1681  Register SrcReg = MI.getOperand(1).getReg();
1682  Register DstReg = MI.getOperand(0).getReg();
1683 
1684  // BB:
1685  // rjmp CheckBB
1686  BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1687 
1688  // LoopBB:
1689  // ShiftReg2 = shift ShiftReg
1690  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1691  if (HasRepeatedOperand)
1692  ShiftMI.addReg(ShiftReg);
1693 
1694  // CheckBB:
1695  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1696  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1697  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1698  // ShiftAmt2 = ShiftAmt - 1;
1699  // if (ShiftAmt2 >= 0) goto LoopBB;
1700  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1701  .addReg(SrcReg)
1702  .addMBB(BB)
1703  .addReg(ShiftReg2)
1704  .addMBB(LoopBB);
1705  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1706  .addReg(ShiftAmtSrcReg)
1707  .addMBB(BB)
1708  .addReg(ShiftAmtReg2)
1709  .addMBB(LoopBB);
1710  BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1711  .addReg(SrcReg)
1712  .addMBB(BB)
1713  .addReg(ShiftReg2)
1714  .addMBB(LoopBB);
1715 
1716  BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1717  BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1718 
1719  MI.eraseFromParent(); // The pseudo instruction is gone now.
1720  return RemBB;
1721 }
1722 
1724  if (I->getOpcode() == AVR::COPY) {
1725  Register SrcReg = I->getOperand(1).getReg();
1726  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1727  }
1728 
1729  return false;
1730 }
1731 
1732 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1733 // after the result has been evacuated. This is probably not the best way to do
1734 // it, but it works for now.
1735 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1736  MachineBasicBlock *BB) const {
1737  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1739  ++I; // in any case insert *after* the mul instruction
1740  if (isCopyMulResult(I))
1741  ++I;
1742  if (isCopyMulResult(I))
1743  ++I;
1744  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1745  .addReg(AVR::R1)
1746  .addReg(AVR::R1);
1747  return BB;
1748 }
1749 
1750 // Insert a read from R1, which almost always contains the value 0.
1751 MachineBasicBlock *
1752 AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
1753  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1755  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
1756  .add(MI.getOperand(0))
1757  .addReg(AVR::R1);
1758  MI.eraseFromParent();
1759  return BB;
1760 }
1761 
1762 // Lower atomicrmw operation to disable interrupts, do operation, and restore
1763 // interrupts. This works because all AVR microcontrollers are single core.
1764 MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
1765  MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
1766  MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1767  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1769  const Register SCRATCH_REGISTER = AVR::R0;
1770  DebugLoc dl = MI.getDebugLoc();
1771 
1772  // Example instruction sequence, for an atomic 8-bit add:
1773  // ldi r25, 5
1774  // in r0, SREG
1775  // cli
1776  // ld r24, X
1777  // add r25, r24
1778  // st X, r25
1779  // out SREG, r0
1780 
1781  const TargetRegisterClass *RC =
1782  (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
1783  unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
1784  unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
1785 
1786  // Disable interrupts.
1787  BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER)
1789  BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);
1790 
1791  // Load the original value.
1792  BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
1793  .add(MI.getOperand(1));
1794 
1795  // Do the arithmetic operation.
1796  Register Result = MRI.createVirtualRegister(RC);
1797  BuildMI(*BB, I, dl, TII.get(Opcode), Result)
1798  .addReg(MI.getOperand(0).getReg())
1799  .add(MI.getOperand(2));
1800 
1801  // Store the result.
1802  BuildMI(*BB, I, dl, TII.get(StoreOpcode))
1803  .add(MI.getOperand(1))
1804  .addReg(Result);
1805 
1806  // Restore interrupts.
1807  BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
1809  .addReg(SCRATCH_REGISTER);
1810 
1811  // Remove the pseudo instruction.
1812  MI.eraseFromParent();
1813  return BB;
1814 }
1815 
1816 MachineBasicBlock *
1818  MachineBasicBlock *MBB) const {
1819  int Opc = MI.getOpcode();
1820 
1821  // Pseudo shift instructions with a non constant shift amount are expanded
1822  // into a loop.
1823  switch (Opc) {
1824  case AVR::Lsl8:
1825  case AVR::Lsl16:
1826  case AVR::Lsr8:
1827  case AVR::Lsr16:
1828  case AVR::Rol8:
1829  case AVR::Rol16:
1830  case AVR::Ror8:
1831  case AVR::Ror16:
1832  case AVR::Asr8:
1833  case AVR::Asr16:
1834  return insertShift(MI, MBB);
1835  case AVR::MULRdRr:
1836  case AVR::MULSRdRr:
1837  return insertMul(MI, MBB);
1838  case AVR::CopyR1:
1839  return insertCopyR1(MI, MBB);
1840  case AVR::AtomicLoadAdd8:
1841  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
1842  case AVR::AtomicLoadAdd16:
1843  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
1844  case AVR::AtomicLoadSub8:
1845  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
1846  case AVR::AtomicLoadSub16:
1847  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
1848  case AVR::AtomicLoadAnd8:
1849  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8);
1850  case AVR::AtomicLoadAnd16:
1851  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16);
1852  case AVR::AtomicLoadOr8:
1853  return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8);
1854  case AVR::AtomicLoadOr16:
1855  return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16);
1856  case AVR::AtomicLoadXor8:
1857  return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8);
1858  case AVR::AtomicLoadXor16:
1859  return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16);
1860  }
1861 
1862  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1863  "Unexpected instr type to insert");
1864 
1865  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1866  ->getParent()
1867  ->getSubtarget()
1868  .getInstrInfo();
1869  DebugLoc dl = MI.getDebugLoc();
1870 
1871  // To "insert" a SELECT instruction, we insert the diamond
1872  // control-flow pattern. The incoming instruction knows the
1873  // destination vreg to set, the condition code register to branch
1874  // on, the true/false values to select between, and a branch opcode
1875  // to use.
1876 
1877  MachineFunction *MF = MBB->getParent();
1878  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1879  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1880 
1881  // If the current basic block falls through to another basic block,
1882  // we must insert an unconditional branch to the fallthrough destination
1883  // if we are to insert basic blocks at the prior fallthrough point.
1884  if (FallThrough != nullptr) {
1885  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1886  }
1887 
1888  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1889  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1890 
1892  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
1893  ;
1894  if (I != MF->end())
1895  ++I;
1896  MF->insert(I, trueMBB);
1897  MF->insert(I, falseMBB);
1898 
1899  // Transfer remaining instructions and all successors of the current
1900  // block to the block which will contain the Phi node for the
1901  // select.
1902  trueMBB->splice(trueMBB->begin(), MBB,
1903  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1905 
1906  AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1907  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1908  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1909  MBB->addSuccessor(falseMBB);
1910  MBB->addSuccessor(trueMBB);
1911 
1912  // Unconditionally flow back to the true block
1913  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1914  falseMBB->addSuccessor(trueMBB);
1915 
1916  // Set up the Phi node to determine where we came from
1917  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
1918  MI.getOperand(0).getReg())
1919  .addReg(MI.getOperand(1).getReg())
1920  .addMBB(MBB)
1921  .addReg(MI.getOperand(2).getReg())
1922  .addMBB(falseMBB);
1923 
1924  MI.eraseFromParent(); // The pseudo instruction is gone now.
1925  return trueMBB;
1926 }
1927 
1928 //===----------------------------------------------------------------------===//
1929 // Inline Asm Support
1930 //===----------------------------------------------------------------------===//
1931 
1934  if (Constraint.size() == 1) {
1935  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1936  switch (Constraint[0]) {
1937  default:
1938  break;
1939  case 'a': // Simple upper registers
1940  case 'b': // Base pointer registers pairs
1941  case 'd': // Upper register
1942  case 'l': // Lower registers
1943  case 'e': // Pointer register pairs
1944  case 'q': // Stack pointer register
1945  case 'r': // Any register
1946  case 'w': // Special upper register pairs
1947  return C_RegisterClass;
1948  case 't': // Temporary register
1949  case 'x':
1950  case 'X': // Pointer register pair X
1951  case 'y':
1952  case 'Y': // Pointer register pair Y
1953  case 'z':
1954  case 'Z': // Pointer register pair Z
1955  return C_Register;
1956  case 'Q': // A memory address based on Y or Z pointer with displacement.
1957  return C_Memory;
1958  case 'G': // Floating point constant
1959  case 'I': // 6-bit positive integer constant
1960  case 'J': // 6-bit negative integer constant
1961  case 'K': // Integer constant (Range: 2)
1962  case 'L': // Integer constant (Range: 0)
1963  case 'M': // 8-bit integer constant
1964  case 'N': // Integer constant (Range: -1)
1965  case 'O': // Integer constant (Range: 8, 16, 24)
1966  case 'P': // Integer constant (Range: 1)
1967  case 'R': // Integer constant (Range: -6 to 5)x
1968  return C_Immediate;
1969  }
1970  }
1971 
1972  return TargetLowering::getConstraintType(Constraint);
1973 }
1974 
1975 unsigned
1977  // Not sure if this is actually the right thing to do, but we got to do
1978  // *something* [agnat]
1979  switch (ConstraintCode[0]) {
1980  case 'Q':
1981  return InlineAsm::Constraint_Q;
1982  }
1983  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1984 }
1985 
1988  AsmOperandInfo &info, const char *constraint) const {
1989  ConstraintWeight weight = CW_Invalid;
1990  Value *CallOperandVal = info.CallOperandVal;
1991 
1992  // If we don't have a value, we can't do a match,
1993  // but allow it at the lowest weight.
1994  // (this behaviour has been copied from the ARM backend)
1995  if (!CallOperandVal) {
1996  return CW_Default;
1997  }
1998 
1999  // Look at the constraint type.
2000  switch (*constraint) {
2001  default:
2003  break;
2004  case 'd':
2005  case 'r':
2006  case 'l':
2007  weight = CW_Register;
2008  break;
2009  case 'a':
2010  case 'b':
2011  case 'e':
2012  case 'q':
2013  case 't':
2014  case 'w':
2015  case 'x':
2016  case 'X':
2017  case 'y':
2018  case 'Y':
2019  case 'z':
2020  case 'Z':
2021  weight = CW_SpecificReg;
2022  break;
2023  case 'G':
2024  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
2025  if (C->isZero()) {
2026  weight = CW_Constant;
2027  }
2028  }
2029  break;
2030  case 'I':
2031  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2032  if (isUInt<6>(C->getZExtValue())) {
2033  weight = CW_Constant;
2034  }
2035  }
2036  break;
2037  case 'J':
2038  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2039  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2040  weight = CW_Constant;
2041  }
2042  }
2043  break;
2044  case 'K':
2045  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2046  if (C->getZExtValue() == 2) {
2047  weight = CW_Constant;
2048  }
2049  }
2050  break;
2051  case 'L':
2052  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2053  if (C->getZExtValue() == 0) {
2054  weight = CW_Constant;
2055  }
2056  }
2057  break;
2058  case 'M':
2059  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2060  if (isUInt<8>(C->getZExtValue())) {
2061  weight = CW_Constant;
2062  }
2063  }
2064  break;
2065  case 'N':
2066  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2067  if (C->getSExtValue() == -1) {
2068  weight = CW_Constant;
2069  }
2070  }
2071  break;
2072  case 'O':
2073  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2074  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2075  (C->getZExtValue() == 24)) {
2076  weight = CW_Constant;
2077  }
2078  }
2079  break;
2080  case 'P':
2081  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2082  if (C->getZExtValue() == 1) {
2083  weight = CW_Constant;
2084  }
2085  }
2086  break;
2087  case 'R':
2088  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2089  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2090  weight = CW_Constant;
2091  }
2092  }
2093  break;
2094  case 'Q':
2095  weight = CW_Memory;
2096  break;
2097  }
2098 
2099  return weight;
2100 }
2101 
2102 std::pair<unsigned, const TargetRegisterClass *>
2104  StringRef Constraint,
2105  MVT VT) const {
2106  if (Constraint.size() == 1) {
2107  switch (Constraint[0]) {
2108  case 'a': // Simple upper registers r16..r23.
2109  if (VT == MVT::i8)
2110  return std::make_pair(0U, &AVR::LD8loRegClass);
2111  else if (VT == MVT::i16)
2112  return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
2113  break;
2114  case 'b': // Base pointer registers: y, z.
2115  if (VT == MVT::i8 || VT == MVT::i16)
2116  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
2117  break;
2118  case 'd': // Upper registers r16..r31.
2119  if (VT == MVT::i8)
2120  return std::make_pair(0U, &AVR::LD8RegClass);
2121  else if (VT == MVT::i16)
2122  return std::make_pair(0U, &AVR::DLDREGSRegClass);
2123  break;
2124  case 'l': // Lower registers r0..r15.
2125  if (VT == MVT::i8)
2126  return std::make_pair(0U, &AVR::GPR8loRegClass);
2127  else if (VT == MVT::i16)
2128  return std::make_pair(0U, &AVR::DREGSloRegClass);
2129  break;
2130  case 'e': // Pointer register pairs: x, y, z.
2131  if (VT == MVT::i8 || VT == MVT::i16)
2132  return std::make_pair(0U, &AVR::PTRREGSRegClass);
2133  break;
2134  case 'q': // Stack pointer register: SPH:SPL.
2135  return std::make_pair(0U, &AVR::GPRSPRegClass);
2136  case 'r': // Any register: r0..r31.
2137  if (VT == MVT::i8)
2138  return std::make_pair(0U, &AVR::GPR8RegClass);
2139  else if (VT == MVT::i16)
2140  return std::make_pair(0U, &AVR::DREGSRegClass);
2141  break;
2142  case 't': // Temporary register: r0.
2143  if (VT == MVT::i8)
2144  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
2145  break;
2146  case 'w': // Special upper register pairs: r24, r26, r28, r30.
2147  if (VT == MVT::i8 || VT == MVT::i16)
2148  return std::make_pair(0U, &AVR::IWREGSRegClass);
2149  break;
2150  case 'x': // Pointer register pair X: r27:r26.
2151  case 'X':
2152  if (VT == MVT::i8 || VT == MVT::i16)
2153  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2154  break;
2155  case 'y': // Pointer register pair Y: r29:r28.
2156  case 'Y':
2157  if (VT == MVT::i8 || VT == MVT::i16)
2158  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2159  break;
2160  case 'z': // Pointer register pair Z: r31:r30.
2161  case 'Z':
2162  if (VT == MVT::i8 || VT == MVT::i16)
2163  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2164  break;
2165  default:
2166  break;
2167  }
2168  }
2169 
2171  Subtarget.getRegisterInfo(), Constraint, VT);
2172 }
2173 
2175  std::string &Constraint,
2176  std::vector<SDValue> &Ops,
2177  SelectionDAG &DAG) const {
2178  SDValue Result;
2179  SDLoc DL(Op);
2180  EVT Ty = Op.getValueType();
2181 
2182  // Currently only support length 1 constraints.
2183  if (Constraint.length() != 1) {
2184  return;
2185  }
2186 
2187  char ConstraintLetter = Constraint[0];
2188  switch (ConstraintLetter) {
2189  default:
2190  break;
2191  // Deal with integers first:
2192  case 'I':
2193  case 'J':
2194  case 'K':
2195  case 'L':
2196  case 'M':
2197  case 'N':
2198  case 'O':
2199  case 'P':
2200  case 'R': {
2201  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2202  if (!C) {
2203  return;
2204  }
2205 
2206  int64_t CVal64 = C->getSExtValue();
2207  uint64_t CUVal64 = C->getZExtValue();
2208  switch (ConstraintLetter) {
2209  case 'I': // 0..63
2210  if (!isUInt<6>(CUVal64))
2211  return;
2212  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2213  break;
2214  case 'J': // -63..0
2215  if (CVal64 < -63 || CVal64 > 0)
2216  return;
2217  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2218  break;
2219  case 'K': // 2
2220  if (CUVal64 != 2)
2221  return;
2222  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2223  break;
2224  case 'L': // 0
2225  if (CUVal64 != 0)
2226  return;
2227  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2228  break;
2229  case 'M': // 0..255
2230  if (!isUInt<8>(CUVal64))
2231  return;
2232  // i8 type may be printed as a negative number,
2233  // e.g. 254 would be printed as -2,
2234  // so we force it to i16 at least.
2235  if (Ty.getSimpleVT() == MVT::i8) {
2236  Ty = MVT::i16;
2237  }
2238  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2239  break;
2240  case 'N': // -1
2241  if (CVal64 != -1)
2242  return;
2243  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2244  break;
2245  case 'O': // 8, 16, 24
2246  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2247  return;
2248  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2249  break;
2250  case 'P': // 1
2251  if (CUVal64 != 1)
2252  return;
2253  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2254  break;
2255  case 'R': // -6..5
2256  if (CVal64 < -6 || CVal64 > 5)
2257  return;
2258  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2259  break;
2260  }
2261 
2262  break;
2263  }
2264  case 'G':
2265  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2266  if (!FC || !FC->isZero())
2267  return;
2268  // Soften float to i8 0
2269  Result = DAG.getTargetConstant(0, DL, MVT::i8);
2270  break;
2271  }
2272 
2273  if (Result.getNode()) {
2274  Ops.push_back(Result);
2275  return;
2276  }
2277 
2278  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2279 }
2280 
2282  const MachineFunction &MF) const {
2283  Register Reg;
2284 
2285  if (VT == LLT::scalar(8)) {
2287  .Case("r0", AVR::R0)
2288  .Case("r1", AVR::R1)
2289  .Default(0);
2290  } else {
2292  .Case("r0", AVR::R1R0)
2293  .Case("sp", AVR::SP)
2294  .Default(0);
2295  }
2296 
2297  if (Reg)
2298  return Reg;
2299 
2301  Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2302 }
2303 
2304 } // end of namespace llvm
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1417
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:1033
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2192
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1428
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1076
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1353
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:50
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::StructType::get
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:406
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1425
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:35
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1429
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:1976
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:5337
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:266
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4362
llvm::AVRSubtarget::hasTinyEncoding
bool hasTinyEncoding() const
Definition: AVRSubtarget.h:81
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:984
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1188
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:235
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1353
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:969
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1424
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1050
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:824
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:54
llvm::AVR::ProgramMemory
@ ProgramMemory
Definition: AVR.h:43
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::isCopyMulResult
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
Definition: AVRISelLowering.cpp:1723
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:3030
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4384
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2314
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:72
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetLowering::C_Memory
@ C_Memory
Definition: TargetLowering.h:4365
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1419
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2437
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:841
llvm::AVRISD::LSLHI
@ LSLHI
Higher 8-bit of word logical shift left.
Definition: AVRISelLowering.h:41
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::AVRISD::ASRWN
@ ASRWN
Word arithmetic shift right N bits.
Definition: AVRISelLowering.h:48
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2400
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9683
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:65
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:52
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:930
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:871
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3047
STLExtras.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1079
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1384
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::analyzeArguments
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing function arguments.
Definition: AVRISelLowering.cpp:1071
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSLWN
@ LSLWN
Word logical shift left N bits.
Definition: AVRISelLowering.h:40
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:259
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2320
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:994
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:804
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2303
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1422
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:747
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:46
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2256
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:68
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1426
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2467
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3362
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:69
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2239
llvm::Instruction
Definition: Instruction.h:42
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:36
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:829
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1187
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:2174
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4363
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:255
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:822
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4367
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2187
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLArrayExtras.h:29
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:38
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1817
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:1987
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1416
llvm::Sched::RegPressure
@ RegPressure
Definition: TargetLowering.h:100
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:67
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1353
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3024
llvm::analyzeReturnValues
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing value of returning from a function.
Definition: AVRISelLowering.cpp:1164
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::TargetLowering::CW_SpecificReg
@ CW_SpecificReg
Definition: TargetLowering.h:4381
NODE
#define NODE(name)
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1933
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:405
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:56
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1185
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1613
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::getTotalArgumentsSizeInBytes
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
Definition: AVRISelLowering.cpp:1151
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2205
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1184
llvm::TargetLowering::CW_Register
@ CW_Register
Definition: TargetLowering.h:4382
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8786
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1163
llvm::AVRISD::LSRBN
@ LSRBN
Byte logical shift right N bits.
Definition: AVRISelLowering.h:43
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4389
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:441
ArrayRef.h
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:100
AVRTargetMachine.h
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:839
llvm::RegList16AVR
static const MCPhysReg RegList16AVR[]
Definition: AVRISelLowering.cpp:1052
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2342
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:51
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:2103
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3952
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::AVRISD::LSRWN
@ LSRWN
Word logical shift right N bits.
Definition: AVRISelLowering.h:44
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::AVRSubtarget::supportsMultiplication
bool supportsMultiplication() const
Definition: AVRSubtarget.h:79
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:900
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1418
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1404
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
AVRMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:986
llvm::TargetLowering::CW_Memory
@ CW_Memory
Definition: TargetLowering.h:4383
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1080
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4385
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:36
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::CallingConv::AVR_BUILTIN
@ AVR_BUILTIN
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:199
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:185
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:61
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:42
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:349
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
AVRSubtarget.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4972
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2465
uint32_t
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5049
llvm::AVRISD::ASRBN
@ ASRBN
Byte arithmetic shift right N bits.
Definition: AVRISelLowering.h:47
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2293
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG(void) const
Definition: AVRSubtarget.h:99
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1177
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1384
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4364
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:310
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
j
return j(j<< 16)
llvm::AArch64_AM::ASR
@ ASR
Definition: AArch64AddressingModes.h:37
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1427
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2466
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
uint16_t
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2468
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:337
llvm::RegList8Tiny
static const MCPhysReg RegList8Tiny[]
Definition: AVRISelLowering.cpp:1050
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4372
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:967
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
StringSwitch.h
AVR.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4374
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1075
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::intCCToAVRCC
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Definition: AVRISelLowering.cpp:547
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:428
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2173
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::RegList16Tiny
static const MCPhysReg RegList16Tiny[]
Definition: AVRISelLowering.cpp:1057
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::RegList8AVR
static const MCPhysReg RegList8AVR[]
Registers for calling conventions, ordered in reverse as required by ABI.
Definition: AVRISelLowering.cpp:1046
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:77
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2281
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1248
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1978
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4464
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::AVRInstrInfo
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
llvm::AVRISD::LSRLO
@ LSRLO
Lower 8-bit of word logical shift right.
Definition: AVRISelLowering.h:45
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2464
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:53
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::AVRISD::ASRLO
@ ASRLO
Lower 8-bit of word arithmetic shift right.
Definition: AVRISelLowering.h:49
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:886
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:63
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:649
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2271
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1070
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3052
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1046
AVRISelLowering.h
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
llvm::AVRISD::LSLBN
@ LSLBN
Byte logical shift left N bits.
Definition: AVRISelLowering.h:39
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4910
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:352
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1186
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
llvm::AVR::isProgramMemoryAccess
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:73
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
TargetLoweringObjectFileImpl.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:55