LLVM  14.0.0git
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRSubtarget.h"
30 #include "AVRTargetMachine.h"
32 
33 namespace llvm {
34 
36  const AVRSubtarget &STI)
37  : TargetLowering(TM), Subtarget(STI) {
38  // Set up the register classes.
39  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41 
42  // Compute derived properties from the register classes.
44 
50 
53 
58 
59  for (MVT VT : MVT::integer_valuetypes()) {
60  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63  }
64  }
65 
67 
68  for (MVT VT : MVT::integer_valuetypes()) {
73  }
74 
75  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76  // revert into a sub since we don't have an add with immediate instruction.
79 
80  // our shift instructions are only able to shift 1 bit at a time, so handle
81  // this in a custom way.
91 
96 
102 
113 
115 
116  // Add support for postincrement and predecrement load/stores.
125 
127 
132 
133  // Atomic operations which must be lowered to rtlib calls
134  for (MVT VT : MVT::integer_valuetypes()) {
142  }
143 
144  // Division/remainder
153 
154  // Make division and modulus custom
161 
162  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
165 
166  // Expand 16 bit multiplications.
169 
170  // Expand multiplications to libcalls when there is
171  // no hardware MUL.
175  }
176 
177  for (MVT VT : MVT::integer_valuetypes()) {
180  }
181 
182  for (MVT VT : MVT::integer_valuetypes()) {
186  }
187 
188  for (MVT VT : MVT::integer_valuetypes()) {
190  // TODO: The generated code is pretty poor. Investigate using the
191  // same "shift and subtract with carry" trick that we do for
192  // extending 8-bit to 16-bit. This may require infrastructure
193  // improvements in how we treat 16-bit "registers" to be feasible.
194  }
195 
196  // Division rtlib functions (not supported), use divmod functions instead
197  setLibcallName(RTLIB::SDIV_I8, nullptr);
198  setLibcallName(RTLIB::SDIV_I16, nullptr);
199  setLibcallName(RTLIB::SDIV_I32, nullptr);
200  setLibcallName(RTLIB::UDIV_I8, nullptr);
201  setLibcallName(RTLIB::UDIV_I16, nullptr);
202  setLibcallName(RTLIB::UDIV_I32, nullptr);
203 
204  // Modulus rtlib functions (not supported), use divmod functions instead
205  setLibcallName(RTLIB::SREM_I8, nullptr);
206  setLibcallName(RTLIB::SREM_I16, nullptr);
207  setLibcallName(RTLIB::SREM_I32, nullptr);
208  setLibcallName(RTLIB::UREM_I8, nullptr);
209  setLibcallName(RTLIB::UREM_I16, nullptr);
210  setLibcallName(RTLIB::UREM_I32, nullptr);
211 
212  // Division and modulus rtlib functions
213  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219 
220  // Several of the runtime library functions use a special calling conv
222  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
224  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225 
226  // Trigonometric rtlib functions
227  setLibcallName(RTLIB::SIN_F32, "sin");
228  setLibcallName(RTLIB::COS_F32, "cos");
229 
231  setMinimumJumpTableEntries(UINT_MAX);
232 }
233 
234 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235 #define NODE(name) \
236  case AVRISD::name: \
237  return #name
238 
239  switch (Opcode) {
240  default:
241  return nullptr;
242  NODE(RET_FLAG);
243  NODE(RETI_FLAG);
244  NODE(CALL);
245  NODE(WRAPPER);
246  NODE(LSL);
247  NODE(LSR);
248  NODE(ROL);
249  NODE(ROR);
250  NODE(ASR);
251  NODE(LSLLOOP);
252  NODE(LSRLOOP);
253  NODE(ROLLOOP);
254  NODE(RORLOOP);
255  NODE(ASRLOOP);
256  NODE(BRCOND);
257  NODE(CMP);
258  NODE(CMPC);
259  NODE(TST);
260  NODE(SELECT_CC);
261 #undef NODE
262  }
263 }
264 
266  EVT VT) const {
267  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
268  return MVT::i8;
269 }
270 
271 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272  //: TODO: this function has to be completely rewritten to produce optimal
273  // code, for now it's producing very long but correct code.
274  unsigned Opc8;
275  const SDNode *N = Op.getNode();
276  EVT VT = Op.getValueType();
277  SDLoc dl(N);
279  "Expected power-of-2 shift amount");
280 
281  // Expand non-constant shifts to loops.
282  if (!isa<ConstantSDNode>(N->getOperand(1))) {
283  switch (Op.getOpcode()) {
284  default:
285  llvm_unreachable("Invalid shift opcode!");
286  case ISD::SHL:
287  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288  N->getOperand(1));
289  case ISD::SRL:
290  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291  N->getOperand(1));
292  case ISD::ROTL: {
293  SDValue Amt = N->getOperand(1);
294  EVT AmtVT = Amt.getValueType();
295  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298  }
299  case ISD::ROTR: {
300  SDValue Amt = N->getOperand(1);
301  EVT AmtVT = Amt.getValueType();
302  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305  }
306  case ISD::SRA:
307  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308  N->getOperand(1));
309  }
310  }
311 
312  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313  SDValue Victim = N->getOperand(0);
314 
315  switch (Op.getOpcode()) {
316  case ISD::SRA:
317  Opc8 = AVRISD::ASR;
318  break;
319  case ISD::ROTL:
320  Opc8 = AVRISD::ROL;
321  ShiftAmount = ShiftAmount % VT.getSizeInBits();
322  break;
323  case ISD::ROTR:
324  Opc8 = AVRISD::ROR;
325  ShiftAmount = ShiftAmount % VT.getSizeInBits();
326  break;
327  case ISD::SRL:
328  Opc8 = AVRISD::LSR;
329  break;
330  case ISD::SHL:
331  Opc8 = AVRISD::LSL;
332  break;
333  default:
334  llvm_unreachable("Invalid shift opcode");
335  }
336 
337  // Optimize int8/int16 shifts.
338  if (VT.getSizeInBits() == 8) {
339  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340  // Optimize LSL when 4 <= ShiftAmount <= 6.
341  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
342  Victim =
343  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
344  ShiftAmount -= 4;
345  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
346  ShiftAmount < 7) {
347  // Optimize LSR when 4 <= ShiftAmount <= 6.
348  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
349  Victim =
350  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
351  ShiftAmount -= 4;
352  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
353  // Optimize LSL when ShiftAmount == 7.
354  Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
355  DAG.getConstant(7, dl, VT));
356  ShiftAmount = 0;
357  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
358  // Optimize LSR when ShiftAmount == 7.
359  Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
360  DAG.getConstant(7, dl, VT));
361  ShiftAmount = 0;
362  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
363  // Optimize ASR when ShiftAmount == 7.
364  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
365  DAG.getConstant(7, dl, VT));
366  ShiftAmount = 0;
367  }
368  } else if (VT.getSizeInBits() == 16) {
369  if (4 <= ShiftAmount && ShiftAmount < 8)
370  switch (Op.getOpcode()) {
371  case ISD::SHL:
372  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
373  DAG.getConstant(4, dl, VT));
374  ShiftAmount -= 4;
375  break;
376  case ISD::SRL:
377  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
378  DAG.getConstant(4, dl, VT));
379  ShiftAmount -= 4;
380  break;
381  default:
382  break;
383  }
384  else if (8 <= ShiftAmount && ShiftAmount < 12)
385  switch (Op.getOpcode()) {
386  case ISD::SHL:
387  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
388  DAG.getConstant(8, dl, VT));
389  ShiftAmount -= 8;
390  break;
391  case ISD::SRL:
392  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
393  DAG.getConstant(8, dl, VT));
394  ShiftAmount -= 8;
395  break;
396  case ISD::SRA:
397  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
398  DAG.getConstant(8, dl, VT));
399  ShiftAmount -= 8;
400  break;
401  default:
402  break;
403  }
404  else if (12 <= ShiftAmount)
405  switch (Op.getOpcode()) {
406  case ISD::SHL:
407  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
408  DAG.getConstant(12, dl, VT));
409  ShiftAmount -= 12;
410  break;
411  case ISD::SRL:
412  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
413  DAG.getConstant(12, dl, VT));
414  ShiftAmount -= 12;
415  break;
416  default:
417  break;
418  }
419  }
420 
421  while (ShiftAmount--) {
422  Victim = DAG.getNode(Opc8, dl, VT, Victim);
423  }
424 
425  return Victim;
426 }
427 
428 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
429  unsigned Opcode = Op->getOpcode();
430  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
431  "Invalid opcode for Div/Rem lowering");
432  bool IsSigned = (Opcode == ISD::SDIVREM);
433  EVT VT = Op->getValueType(0);
434  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
435 
436  RTLIB::Libcall LC;
437  switch (VT.getSimpleVT().SimpleTy) {
438  default:
439  llvm_unreachable("Unexpected request for libcall!");
440  case MVT::i8:
441  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
442  break;
443  case MVT::i16:
444  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
445  break;
446  case MVT::i32:
447  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
448  break;
449  }
450 
451  SDValue InChain = DAG.getEntryNode();
452 
454  TargetLowering::ArgListEntry Entry;
455  for (SDValue const &Value : Op->op_values()) {
456  Entry.Node = Value;
457  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
458  Entry.IsSExt = IsSigned;
459  Entry.IsZExt = !IsSigned;
460  Args.push_back(Entry);
461  }
462 
463  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
464  getPointerTy(DAG.getDataLayout()));
465 
466  Type *RetTy = (Type *)StructType::get(Ty, Ty);
467 
468  SDLoc dl(Op);
469  TargetLowering::CallLoweringInfo CLI(DAG);
470  CLI.setDebugLoc(dl)
471  .setChain(InChain)
472  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
473  .setInRegister()
474  .setSExtResult(IsSigned)
475  .setZExtResult(!IsSigned);
476 
477  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
478  return CallInfo.first;
479 }
480 
481 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
482  SelectionDAG &DAG) const {
483  auto DL = DAG.getDataLayout();
484 
485  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
486  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
487 
488  // Create the TargetGlobalAddress node, folding in the constant offset.
489  SDValue Result =
490  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
491  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
492 }
493 
494 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
495  SelectionDAG &DAG) const {
496  auto DL = DAG.getDataLayout();
497  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
498 
499  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
500 
501  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
502 }
503 
504 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
506  switch (CC) {
507  default:
508  llvm_unreachable("Unknown condition code!");
509  case ISD::SETEQ:
510  return AVRCC::COND_EQ;
511  case ISD::SETNE:
512  return AVRCC::COND_NE;
513  case ISD::SETGE:
514  return AVRCC::COND_GE;
515  case ISD::SETLT:
516  return AVRCC::COND_LT;
517  case ISD::SETUGE:
518  return AVRCC::COND_SH;
519  case ISD::SETULT:
520  return AVRCC::COND_LO;
521  }
522 }
523 
524 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
525 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
526  SelectionDAG &DAG, SDLoc DL) const {
527  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
528  "LHS and RHS have different types");
529  assert(((LHS.getSimpleValueType() == MVT::i16) ||
530  (LHS.getSimpleValueType() == MVT::i8)) &&
531  "invalid comparison type");
532 
533  SDValue Cmp;
534 
535  if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
536  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
537  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
538  DAG.getIntPtrConstant(0, DL));
539  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
540  DAG.getIntPtrConstant(1, DL));
541  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
542  DAG.getIntPtrConstant(0, DL));
543  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
544  DAG.getIntPtrConstant(1, DL));
545  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
546  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
547  } else {
548  // Generate ordinary 16-bit comparison.
549  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
550  }
551 
552  return Cmp;
553 }
554 
555 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
556 /// the given operands.
557 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
558  SDValue &AVRcc, SelectionDAG &DAG,
559  SDLoc DL) const {
560  SDValue Cmp;
561  EVT VT = LHS.getValueType();
562  bool UseTest = false;
563 
564  switch (CC) {
565  default:
566  break;
567  case ISD::SETLE: {
568  // Swap operands and reverse the branching condition.
569  std::swap(LHS, RHS);
570  CC = ISD::SETGE;
571  break;
572  }
573  case ISD::SETGT: {
574  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
575  switch (C->getSExtValue()) {
576  case -1: {
577  // When doing lhs > -1 use a tst instruction on the top part of lhs
578  // and use brpl instead of using a chain of cp/cpc.
579  UseTest = true;
580  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
581  break;
582  }
583  case 0: {
584  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
585  // __zero_reg__ in lhs.
586  RHS = LHS;
587  LHS = DAG.getConstant(0, DL, VT);
588  CC = ISD::SETLT;
589  break;
590  }
591  default: {
592  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
593  // us to fold the constant into the cmp instruction.
594  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
595  CC = ISD::SETGE;
596  break;
597  }
598  }
599  break;
600  }
601  // Swap operands and reverse the branching condition.
602  std::swap(LHS, RHS);
603  CC = ISD::SETLT;
604  break;
605  }
606  case ISD::SETLT: {
607  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
608  switch (C->getSExtValue()) {
609  case 1: {
610  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
611  // __zero_reg__ in lhs.
612  RHS = LHS;
613  LHS = DAG.getConstant(0, DL, VT);
614  CC = ISD::SETGE;
615  break;
616  }
617  case 0: {
618  // When doing lhs < 0 use a tst instruction on the top part of lhs
619  // and use brmi instead of using a chain of cp/cpc.
620  UseTest = true;
621  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
622  break;
623  }
624  }
625  }
626  break;
627  }
628  case ISD::SETULE: {
629  // Swap operands and reverse the branching condition.
630  std::swap(LHS, RHS);
631  CC = ISD::SETUGE;
632  break;
633  }
634  case ISD::SETUGT: {
635  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
636  // fold the constant into the cmp instruction.
637  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
638  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
639  CC = ISD::SETUGE;
640  break;
641  }
642  // Swap operands and reverse the branching condition.
643  std::swap(LHS, RHS);
644  CC = ISD::SETULT;
645  break;
646  }
647  }
648 
649  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
650  // using the default and/or/xor expansion code which is much longer.
651  if (VT == MVT::i32) {
652  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
653  DAG.getIntPtrConstant(0, DL));
654  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
655  DAG.getIntPtrConstant(1, DL));
656  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
657  DAG.getIntPtrConstant(0, DL));
658  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
659  DAG.getIntPtrConstant(1, DL));
660 
661  if (UseTest) {
662  // When using tst we only care about the highest part.
663  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
664  DAG.getIntPtrConstant(1, DL));
665  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
666  } else {
667  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
668  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
669  }
670  } else if (VT == MVT::i64) {
671  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
672  DAG.getIntPtrConstant(0, DL));
673  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
674  DAG.getIntPtrConstant(1, DL));
675 
676  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
677  DAG.getIntPtrConstant(0, DL));
678  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
679  DAG.getIntPtrConstant(1, DL));
680  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
681  DAG.getIntPtrConstant(0, DL));
682  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
683  DAG.getIntPtrConstant(1, DL));
684 
685  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
686  DAG.getIntPtrConstant(0, DL));
687  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
688  DAG.getIntPtrConstant(1, DL));
689 
690  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
691  DAG.getIntPtrConstant(0, DL));
692  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
693  DAG.getIntPtrConstant(1, DL));
694  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
695  DAG.getIntPtrConstant(0, DL));
696  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
697  DAG.getIntPtrConstant(1, DL));
698 
699  if (UseTest) {
700  // When using tst we only care about the highest part.
701  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
702  DAG.getIntPtrConstant(1, DL));
703  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
704  } else {
705  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
706  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
707  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
708  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
709  }
710  } else if (VT == MVT::i8 || VT == MVT::i16) {
711  if (UseTest) {
712  // When using tst we only care about the highest part.
713  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
714  (VT == MVT::i8)
715  ? LHS
716  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
717  LHS, DAG.getIntPtrConstant(1, DL)));
718  } else {
719  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
720  }
721  } else {
722  llvm_unreachable("Invalid comparison size");
723  }
724 
725  // When using a test instruction AVRcc is already set.
726  if (!UseTest) {
727  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
728  }
729 
730  return Cmp;
731 }
732 
733 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
734  SDValue Chain = Op.getOperand(0);
735  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
736  SDValue LHS = Op.getOperand(2);
737  SDValue RHS = Op.getOperand(3);
738  SDValue Dest = Op.getOperand(4);
739  SDLoc dl(Op);
740 
741  SDValue TargetCC;
742  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
743 
744  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
745  Cmp);
746 }
747 
748 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
749  SDValue LHS = Op.getOperand(0);
750  SDValue RHS = Op.getOperand(1);
751  SDValue TrueV = Op.getOperand(2);
752  SDValue FalseV = Op.getOperand(3);
753  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
754  SDLoc dl(Op);
755 
756  SDValue TargetCC;
757  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
758 
759  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
760  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
761 
762  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
763 }
764 
765 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
766  SDValue LHS = Op.getOperand(0);
767  SDValue RHS = Op.getOperand(1);
768  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
769  SDLoc DL(Op);
770 
771  SDValue TargetCC;
772  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
773 
774  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
775  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
776  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
777  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
778 
779  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
780 }
781 
782 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
783  const MachineFunction &MF = DAG.getMachineFunction();
784  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
785  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
786  auto DL = DAG.getDataLayout();
787  SDLoc dl(Op);
788 
789  // Vastart just stores the address of the VarArgsFrameIndex slot into the
790  // memory location argument.
791  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
792 
793  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
794  MachinePointerInfo(SV));
795 }
796 
798  switch (Op.getOpcode()) {
799  default:
800  llvm_unreachable("Don't know how to custom lower this!");
801  case ISD::SHL:
802  case ISD::SRA:
803  case ISD::SRL:
804  case ISD::ROTL:
805  case ISD::ROTR:
806  return LowerShifts(Op, DAG);
807  case ISD::GlobalAddress:
808  return LowerGlobalAddress(Op, DAG);
809  case ISD::BlockAddress:
810  return LowerBlockAddress(Op, DAG);
811  case ISD::BR_CC:
812  return LowerBR_CC(Op, DAG);
813  case ISD::SELECT_CC:
814  return LowerSELECT_CC(Op, DAG);
815  case ISD::SETCC:
816  return LowerSETCC(Op, DAG);
817  case ISD::VASTART:
818  return LowerVASTART(Op, DAG);
819  case ISD::SDIVREM:
820  case ISD::UDIVREM:
821  return LowerDivRem(Op, DAG);
822  }
823 
824  return SDValue();
825 }
826 
827 /// Replace a node with an illegal result type
828 /// with a new node built out of custom code.
831  SelectionDAG &DAG) const {
832  SDLoc DL(N);
833 
834  switch (N->getOpcode()) {
835  case ISD::ADD: {
836  // Convert add (x, imm) into sub (x, -imm).
837  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
838  SDValue Sub = DAG.getNode(
839  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
840  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
841  Results.push_back(Sub);
842  }
843  break;
844  }
845  default: {
846  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
847 
848  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
849  Results.push_back(Res.getValue(I));
850 
851  break;
852  }
853  }
854 }
855 
856 /// Return true if the addressing mode represented
857 /// by AM is legal for this target, for a load/store of the specified type.
859  const AddrMode &AM, Type *Ty,
860  unsigned AS,
861  Instruction *I) const {
862  int64_t Offs = AM.BaseOffs;
863 
864  // Allow absolute addresses.
865  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
866  return true;
867  }
868 
869  // Flash memory instructions only allow zero offsets.
870  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
871  return false;
872  }
873 
874  // Allow reg+<6bit> offset.
875  if (Offs < 0)
876  Offs = -Offs;
877  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
878  return true;
879  }
880 
881  return false;
882 }
883 
884 /// Returns true by value, base pointer and
885 /// offset pointer and addressing mode by reference if the node's address
886 /// can be legally represented as pre-indexed load / store address.
888  SDValue &Offset,
890  SelectionDAG &DAG) const {
891  EVT VT;
892  const SDNode *Op;
893  SDLoc DL(N);
894 
895  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
896  VT = LD->getMemoryVT();
897  Op = LD->getBasePtr().getNode();
898  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
899  return false;
901  return false;
902  }
903  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
904  VT = ST->getMemoryVT();
905  Op = ST->getBasePtr().getNode();
907  return false;
908  }
909  } else {
910  return false;
911  }
912 
913  if (VT != MVT::i8 && VT != MVT::i16) {
914  return false;
915  }
916 
917  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
918  return false;
919  }
920 
921  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
922  int RHSC = RHS->getSExtValue();
923  if (Op->getOpcode() == ISD::SUB)
924  RHSC = -RHSC;
925 
926  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
927  return false;
928  }
929 
930  Base = Op->getOperand(0);
931  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
932  AM = ISD::PRE_DEC;
933 
934  return true;
935  }
936 
937  return false;
938 }
939 
940 /// Returns true by value, base pointer and
941 /// offset pointer and addressing mode by reference if this node can be
942 /// combined with a load / store to form a post-indexed load / store.
944  SDValue &Base,
945  SDValue &Offset,
947  SelectionDAG &DAG) const {
948  EVT VT;
949  SDLoc DL(N);
950 
951  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
952  VT = LD->getMemoryVT();
953  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
954  return false;
955  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
956  VT = ST->getMemoryVT();
958  return false;
959  }
960  } else {
961  return false;
962  }
963 
964  if (VT != MVT::i8 && VT != MVT::i16) {
965  return false;
966  }
967 
968  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
969  return false;
970  }
971 
972  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
973  int RHSC = RHS->getSExtValue();
974  if (Op->getOpcode() == ISD::SUB)
975  RHSC = -RHSC;
976  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
977  return false;
978  }
979 
980  Base = Op->getOperand(0);
981  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
982  AM = ISD::POST_INC;
983 
984  return true;
985  }
986 
987  return false;
988 }
989 
991  const GlobalAddressSDNode *GA) const {
992  return true;
993 }
994 
995 //===----------------------------------------------------------------------===//
996 // Formal Arguments Calling Convention Implementation
997 //===----------------------------------------------------------------------===//
998 
999 #include "AVRGenCallingConv.inc"
1000 
1001 /// Registers for calling conventions, ordered in reverse as required by ABI.
1002 /// Both arrays must be of the same length.
1003 static const MCPhysReg RegList8[] = {
1004  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1005  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1006  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1007 static const MCPhysReg RegList16[] = {
1008  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1009  AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1010  AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1011  AVR::R11R10, AVR::R10R9, AVR::R9R8};
1012 
1013 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
1014  "8-bit and 16-bit register arrays must be of equal length");
1015 
1016 /// Analyze incoming and outgoing function arguments. We need custom C++ code
1017 /// to handle special constraints in the ABI.
1018 /// In addition, all pieces of a certain argument have to be passed either
1019 /// using registers or the stack but never mixing both.
1020 template <typename ArgT>
1021 static void
1023  const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
1024  SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
1025  unsigned NumArgs = Args.size();
1026  // This is the index of the last used register, in RegList*.
1027  // -1 means R26 (R26 is never actually used in CC).
1028  int RegLastIdx = -1;
1029  // Once a value is passed to the stack it will always be used
1030  bool UseStack = false;
1031  for (unsigned i = 0; i != NumArgs;) {
1032  MVT VT = Args[i].VT;
1033  // We have to count the number of bytes for each function argument, that is
1034  // those Args with the same OrigArgIndex. This is important in case the
1035  // function takes an aggregate type.
1036  // Current argument will be between [i..j).
1037  unsigned ArgIndex = Args[i].OrigArgIndex;
1038  unsigned TotalBytes = VT.getStoreSize();
1039  unsigned j = i + 1;
1040  for (; j != NumArgs; ++j) {
1041  if (Args[j].OrigArgIndex != ArgIndex)
1042  break;
1043  TotalBytes += Args[j].VT.getStoreSize();
1044  }
1045  // Round up to even number of bytes.
1046  TotalBytes = alignTo(TotalBytes, 2);
1047  // Skip zero sized arguments
1048  if (TotalBytes == 0)
1049  continue;
1050  // The index of the first register to be used
1051  unsigned RegIdx = RegLastIdx + TotalBytes;
1052  RegLastIdx = RegIdx;
1053  // If there are not enough registers, use the stack
1054  if (RegIdx >= array_lengthof(RegList8)) {
1055  UseStack = true;
1056  }
1057  for (; i != j; ++i) {
1058  MVT VT = Args[i].VT;
1059 
1060  if (UseStack) {
1061  auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1062  unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1063  TD->getABITypeAlign(evt));
1064  CCInfo.addLoc(
1066  } else {
1067  unsigned Reg;
1068  if (VT == MVT::i8) {
1069  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1070  } else if (VT == MVT::i16) {
1071  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1072  } else {
1074  "calling convention can only manage i8 and i16 types");
1075  }
1076  assert(Reg && "register not available in calling convention");
1077  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1078  // Registers inside a particular argument are sorted in increasing order
1079  // (remember the array is reversed).
1080  RegIdx -= VT.getStoreSize();
1081  }
1082  }
1083  }
1084 }
1085 
1086 /// Count the total number of bytes needed to pass or return these arguments.
1087 template <typename ArgT>
1088 static unsigned
1090  unsigned TotalBytes = 0;
1091 
1092  for (const ArgT &Arg : Args) {
1093  TotalBytes += Arg.VT.getStoreSize();
1094  }
1095  return TotalBytes;
1096 }
1097 
1098 /// Analyze incoming and outgoing value of returning from a function.
1099 /// The algorithm is similar to analyzeArguments, but there can only be
1100 /// one value, possibly an aggregate, and it is limited to 8 bytes.
1101 template <typename ArgT>
1103  CCState &CCInfo) {
1104  unsigned NumArgs = Args.size();
1105  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1106  // CanLowerReturn() guarantees this assertion.
1107  assert(TotalBytes <= 8 &&
1108  "return values greater than 8 bytes cannot be lowered");
1109 
1110  // GCC-ABI says that the size is rounded up to the next even number,
1111  // but actually once it is more than 4 it will always round up to 8.
1112  if (TotalBytes > 4) {
1113  TotalBytes = 8;
1114  } else {
1115  TotalBytes = alignTo(TotalBytes, 2);
1116  }
1117 
1118  // The index of the first register to use.
1119  int RegIdx = TotalBytes - 1;
1120  for (unsigned i = 0; i != NumArgs; ++i) {
1121  MVT VT = Args[i].VT;
1122  unsigned Reg;
1123  if (VT == MVT::i8) {
1124  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1125  } else if (VT == MVT::i16) {
1126  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1127  } else {
1128  llvm_unreachable("calling convention can only manage i8 and i16 types");
1129  }
1130  assert(Reg && "register not available in calling convention");
1131  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1132  // Registers sort in increasing order
1133  RegIdx -= VT.getStoreSize();
1134  }
1135 }
1136 
1137 SDValue AVRTargetLowering::LowerFormalArguments(
1138  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1139  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1140  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1141  MachineFunction &MF = DAG.getMachineFunction();
1142  MachineFrameInfo &MFI = MF.getFrameInfo();
1143  auto DL = DAG.getDataLayout();
1144 
1145  // Assign locations to all of the incoming arguments.
1146  SmallVector<CCValAssign, 16> ArgLocs;
1147  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1148  *DAG.getContext());
1149 
1150  // Variadic functions do not need all the analysis below.
1151  if (isVarArg) {
1152  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1153  } else {
1154  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1155  }
1156 
1157  SDValue ArgValue;
1158  for (CCValAssign &VA : ArgLocs) {
1159 
1160  // Arguments stored on registers.
1161  if (VA.isRegLoc()) {
1162  EVT RegVT = VA.getLocVT();
1163  const TargetRegisterClass *RC;
1164  if (RegVT == MVT::i8) {
1165  RC = &AVR::GPR8RegClass;
1166  } else if (RegVT == MVT::i16) {
1167  RC = &AVR::DREGSRegClass;
1168  } else {
1169  llvm_unreachable("Unknown argument type!");
1170  }
1171 
1172  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1173  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1174 
1175  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1176  // following code will handle zexts or sexts generated by other
1177  // front ends. Otherwise:
1178  // If this is an 8 bit value, it is really passed promoted
1179  // to 16 bits. Insert an assert[sz]ext to capture this, then
1180  // truncate to the right size.
1181  switch (VA.getLocInfo()) {
1182  default:
1183  llvm_unreachable("Unknown loc info!");
1184  case CCValAssign::Full:
1185  break;
1186  case CCValAssign::BCvt:
1187  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1188  break;
1189  case CCValAssign::SExt:
1190  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1191  DAG.getValueType(VA.getValVT()));
1192  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1193  break;
1194  case CCValAssign::ZExt:
1195  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1196  DAG.getValueType(VA.getValVT()));
1197  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1198  break;
1199  }
1200 
1201  InVals.push_back(ArgValue);
1202  } else {
1203  // Sanity check.
1204  assert(VA.isMemLoc());
1205 
1206  EVT LocVT = VA.getLocVT();
1207 
1208  // Create the frame index object for this incoming parameter.
1209  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1210  VA.getLocMemOffset(), true);
1211 
1212  // Create the SelectionDAG nodes corresponding to a load
1213  // from this parameter.
1214  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1215  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1217  }
1218  }
1219 
1220  // If the function takes variable number of arguments, make a frame index for
1221  // the start of the first vararg value... for expansion of llvm.va_start.
1222  if (isVarArg) {
1223  unsigned StackSize = CCInfo.getNextStackOffset();
1224  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1225 
1226  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1227  }
1228 
1229  return Chain;
1230 }
1231 
1232 //===----------------------------------------------------------------------===//
1233 // Call Calling Convention Implementation
1234 //===----------------------------------------------------------------------===//
1235 
1236 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1237  SmallVectorImpl<SDValue> &InVals) const {
1238  SelectionDAG &DAG = CLI.DAG;
1239  SDLoc &DL = CLI.DL;
1240  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1241  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1242  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1243  SDValue Chain = CLI.Chain;
1244  SDValue Callee = CLI.Callee;
1245  bool &isTailCall = CLI.IsTailCall;
1246  CallingConv::ID CallConv = CLI.CallConv;
1247  bool isVarArg = CLI.IsVarArg;
1248 
1249  MachineFunction &MF = DAG.getMachineFunction();
1250 
1251  // AVR does not yet support tail call optimization.
1252  isTailCall = false;
1253 
1254  // Analyze operands of the call, assigning locations to each operand.
1255  SmallVector<CCValAssign, 16> ArgLocs;
1256  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1257  *DAG.getContext());
1258 
1259  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1260  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1261  // node so that legalize doesn't hack it.
1262  const Function *F = nullptr;
1263  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1264  const GlobalValue *GV = G->getGlobal();
1265 
1266  F = cast<Function>(GV);
1267  Callee =
1268  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1269  } else if (const ExternalSymbolSDNode *ES =
1270  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1271  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1272  getPointerTy(DAG.getDataLayout()));
1273  }
1274 
1275  // Variadic functions do not need all the analysis below.
1276  if (isVarArg) {
1277  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1278  } else {
1279  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1280  }
1281 
1282  // Get a count of how many bytes are to be pushed on the stack.
1283  unsigned NumBytes = CCInfo.getNextStackOffset();
1284 
1285  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1286 
1287  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1288 
1289  // First, walk the register assignments, inserting copies.
1290  unsigned AI, AE;
1291  bool HasStackArgs = false;
1292  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1293  CCValAssign &VA = ArgLocs[AI];
1294  EVT RegVT = VA.getLocVT();
1295  SDValue Arg = OutVals[AI];
1296 
1297  // Promote the value if needed. With Clang this should not happen.
1298  switch (VA.getLocInfo()) {
1299  default:
1300  llvm_unreachable("Unknown loc info!");
1301  case CCValAssign::Full:
1302  break;
1303  case CCValAssign::SExt:
1304  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1305  break;
1306  case CCValAssign::ZExt:
1307  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1308  break;
1309  case CCValAssign::AExt:
1310  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1311  break;
1312  case CCValAssign::BCvt:
1313  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1314  break;
1315  }
1316 
1317  // Stop when we encounter a stack argument, we need to process them
1318  // in reverse order in the loop below.
1319  if (VA.isMemLoc()) {
1320  HasStackArgs = true;
1321  break;
1322  }
1323 
1324  // Arguments that can be passed on registers must be kept in the RegsToPass
1325  // vector.
1326  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1327  }
1328 
1329  // Second, stack arguments have to walked.
1330  // Previously this code created chained stores but those chained stores appear
1331  // to be unchained in the legalization phase. Therefore, do not attempt to
1332  // chain them here. In fact, chaining them here somehow causes the first and
1333  // second store to be reversed which is the exact opposite of the intended
1334  // effect.
1335  if (HasStackArgs) {
1336  SmallVector<SDValue, 8> MemOpChains;
1337  for (; AI != AE; AI++) {
1338  CCValAssign &VA = ArgLocs[AI];
1339  SDValue Arg = OutVals[AI];
1340 
1341  assert(VA.isMemLoc());
1342 
1343  // SP points to one stack slot further so add one to adjust it.
1344  SDValue PtrOff = DAG.getNode(
1345  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1346  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1347  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1348 
1349  MemOpChains.push_back(
1350  DAG.getStore(Chain, DL, Arg, PtrOff,
1351  MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1352  }
1353 
1354  if (!MemOpChains.empty())
1355  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1356  }
1357 
1358  // Build a sequence of copy-to-reg nodes chained together with token chain and
1359  // flag operands which copy the outgoing args into registers. The InFlag in
1360  // necessary since all emited instructions must be stuck together.
1361  SDValue InFlag;
1362  for (auto Reg : RegsToPass) {
1363  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1364  InFlag = Chain.getValue(1);
1365  }
1366 
1367  // Returns a chain & a flag for retval copy to use.
1368  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1369  SmallVector<SDValue, 8> Ops;
1370  Ops.push_back(Chain);
1371  Ops.push_back(Callee);
1372 
1373  // Add argument registers to the end of the list so that they are known live
1374  // into the call.
1375  for (auto Reg : RegsToPass) {
1376  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1377  }
1378 
1379  // Add a register mask operand representing the call-preserved registers.
1380  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1381  const uint32_t *Mask =
1382  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1383  assert(Mask && "Missing call preserved mask for calling convention");
1384  Ops.push_back(DAG.getRegisterMask(Mask));
1385 
1386  if (InFlag.getNode()) {
1387  Ops.push_back(InFlag);
1388  }
1389 
1390  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1391  InFlag = Chain.getValue(1);
1392 
1393  // Create the CALLSEQ_END node.
1394  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1395  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1396 
1397  if (!Ins.empty()) {
1398  InFlag = Chain.getValue(1);
1399  }
1400 
1401  // Handle result values, copying them out of physregs into vregs that we
1402  // return.
1403  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1404  InVals);
1405 }
1406 
1407 /// Lower the result values of a call into the
1408 /// appropriate copies out of appropriate physical registers.
1409 ///
1410 SDValue AVRTargetLowering::LowerCallResult(
1411  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1412  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1413  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1414 
1415  // Assign locations to each value returned by this call.
1416  SmallVector<CCValAssign, 16> RVLocs;
1417  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1418  *DAG.getContext());
1419 
1420  // Handle runtime calling convs.
1421  if (CallConv == CallingConv::AVR_BUILTIN) {
1422  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1423  } else {
1424  analyzeReturnValues(Ins, CCInfo);
1425  }
1426 
1427  // Copy all of the result registers out of their specified physreg.
1428  for (CCValAssign const &RVLoc : RVLocs) {
1429  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1430  InFlag)
1431  .getValue(1);
1432  InFlag = Chain.getValue(2);
1433  InVals.push_back(Chain.getValue(0));
1434  }
1435 
1436  return Chain;
1437 }
1438 
1439 //===----------------------------------------------------------------------===//
1440 // Return Value Calling Convention Implementation
1441 //===----------------------------------------------------------------------===//
1442 
1443 bool AVRTargetLowering::CanLowerReturn(
1444  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1445  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1446  if (CallConv == CallingConv::AVR_BUILTIN) {
1447  SmallVector<CCValAssign, 16> RVLocs;
1448  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1449  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1450  }
1451 
1452  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1453  return TotalBytes <= 8;
1454 }
1455 
1456 SDValue
1457 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1458  bool isVarArg,
1459  const SmallVectorImpl<ISD::OutputArg> &Outs,
1460  const SmallVectorImpl<SDValue> &OutVals,
1461  const SDLoc &dl, SelectionDAG &DAG) const {
1462  // CCValAssign - represent the assignment of the return value to locations.
1463  SmallVector<CCValAssign, 16> RVLocs;
1464 
1465  // CCState - Info about the registers and stack slot.
1466  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1467  *DAG.getContext());
1468 
1469  MachineFunction &MF = DAG.getMachineFunction();
1470 
1471  // Analyze return values.
1472  if (CallConv == CallingConv::AVR_BUILTIN) {
1473  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1474  } else {
1475  analyzeReturnValues(Outs, CCInfo);
1476  }
1477 
1478  SDValue Flag;
1479  SmallVector<SDValue, 4> RetOps(1, Chain);
1480  // Copy the result values into the output registers.
1481  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1482  CCValAssign &VA = RVLocs[i];
1483  assert(VA.isRegLoc() && "Can only return in registers!");
1484 
1485  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1486 
1487  // Guarantee that all emitted copies are stuck together with flags.
1488  Flag = Chain.getValue(1);
1489  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1490  }
1491 
1492  // Don't emit the ret/reti instruction when the naked attribute is present in
1493  // the function being compiled.
1494  if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1495  return Chain;
1496  }
1497 
1498  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1499 
1500  unsigned RetOpc =
1501  AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
1502 
1503  RetOps[0] = Chain; // Update chain.
1504 
1505  if (Flag.getNode()) {
1506  RetOps.push_back(Flag);
1507  }
1508 
1509  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1510 }
1511 
1512 //===----------------------------------------------------------------------===//
1513 // Custom Inserters
1514 //===----------------------------------------------------------------------===//
1515 
1516 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1517  MachineBasicBlock *BB) const {
1518  unsigned Opc;
1519  const TargetRegisterClass *RC;
1520  bool HasRepeatedOperand = false;
1521  MachineFunction *F = BB->getParent();
1522  MachineRegisterInfo &RI = F->getRegInfo();
1523  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1524  DebugLoc dl = MI.getDebugLoc();
1525 
1526  switch (MI.getOpcode()) {
1527  default:
1528  llvm_unreachable("Invalid shift opcode!");
1529  case AVR::Lsl8:
1530  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1531  RC = &AVR::GPR8RegClass;
1532  HasRepeatedOperand = true;
1533  break;
1534  case AVR::Lsl16:
1535  Opc = AVR::LSLWRd;
1536  RC = &AVR::DREGSRegClass;
1537  break;
1538  case AVR::Asr8:
1539  Opc = AVR::ASRRd;
1540  RC = &AVR::GPR8RegClass;
1541  break;
1542  case AVR::Asr16:
1543  Opc = AVR::ASRWRd;
1544  RC = &AVR::DREGSRegClass;
1545  break;
1546  case AVR::Lsr8:
1547  Opc = AVR::LSRRd;
1548  RC = &AVR::GPR8RegClass;
1549  break;
1550  case AVR::Lsr16:
1551  Opc = AVR::LSRWRd;
1552  RC = &AVR::DREGSRegClass;
1553  break;
1554  case AVR::Rol8:
1555  Opc = AVR::ROLBRd;
1556  RC = &AVR::GPR8RegClass;
1557  break;
1558  case AVR::Rol16:
1559  Opc = AVR::ROLWRd;
1560  RC = &AVR::DREGSRegClass;
1561  break;
1562  case AVR::Ror8:
1563  Opc = AVR::RORBRd;
1564  RC = &AVR::GPR8RegClass;
1565  break;
1566  case AVR::Ror16:
1567  Opc = AVR::RORWRd;
1568  RC = &AVR::DREGSRegClass;
1569  break;
1570  }
1571 
1572  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1573 
1575  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1576  ;
1577  if (I != F->end())
1578  ++I;
1579 
1580  // Create loop block.
1581  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1582  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1583  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1584 
1585  F->insert(I, LoopBB);
1586  F->insert(I, CheckBB);
1587  F->insert(I, RemBB);
1588 
1589  // Update machine-CFG edges by transferring all successors of the current
1590  // block to the block containing instructions after shift.
1591  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1592  BB->end());
1593  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1594 
1595  // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1596  BB->addSuccessor(CheckBB);
1597  LoopBB->addSuccessor(CheckBB);
1598  CheckBB->addSuccessor(LoopBB);
1599  CheckBB->addSuccessor(RemBB);
1600 
1601  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1602  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1603  Register ShiftReg = RI.createVirtualRegister(RC);
1604  Register ShiftReg2 = RI.createVirtualRegister(RC);
1605  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1606  Register SrcReg = MI.getOperand(1).getReg();
1607  Register DstReg = MI.getOperand(0).getReg();
1608 
1609  // BB:
1610  // rjmp CheckBB
1611  BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1612 
1613  // LoopBB:
1614  // ShiftReg2 = shift ShiftReg
1615  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1616  if (HasRepeatedOperand)
1617  ShiftMI.addReg(ShiftReg);
1618 
1619  // CheckBB:
1620  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1621  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1622  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1623  // ShiftAmt2 = ShiftAmt - 1;
1624  // if (ShiftAmt2 >= 0) goto LoopBB;
1625  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1626  .addReg(SrcReg)
1627  .addMBB(BB)
1628  .addReg(ShiftReg2)
1629  .addMBB(LoopBB);
1630  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1631  .addReg(ShiftAmtSrcReg)
1632  .addMBB(BB)
1633  .addReg(ShiftAmtReg2)
1634  .addMBB(LoopBB);
1635  BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1636  .addReg(SrcReg)
1637  .addMBB(BB)
1638  .addReg(ShiftReg2)
1639  .addMBB(LoopBB);
1640 
1641  BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1642  BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1643 
1644  MI.eraseFromParent(); // The pseudo instruction is gone now.
1645  return RemBB;
1646 }
1647 
1649  if (I->getOpcode() == AVR::COPY) {
1650  Register SrcReg = I->getOperand(1).getReg();
1651  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1652  }
1653 
1654  return false;
1655 }
1656 
1657 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1658 // after the result has been evacuated. This is probably not the best way to do
1659 // it, but it works for now.
1660 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1661  MachineBasicBlock *BB) const {
1662  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1664  ++I; // in any case insert *after* the mul instruction
1665  if (isCopyMulResult(I))
1666  ++I;
1667  if (isCopyMulResult(I))
1668  ++I;
1669  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1670  .addReg(AVR::R1)
1671  .addReg(AVR::R1);
1672  return BB;
1673 }
1674 
1675 MachineBasicBlock *
1677  MachineBasicBlock *MBB) const {
1678  int Opc = MI.getOpcode();
1679 
1680  // Pseudo shift instructions with a non constant shift amount are expanded
1681  // into a loop.
1682  switch (Opc) {
1683  case AVR::Lsl8:
1684  case AVR::Lsl16:
1685  case AVR::Lsr8:
1686  case AVR::Lsr16:
1687  case AVR::Rol8:
1688  case AVR::Rol16:
1689  case AVR::Ror8:
1690  case AVR::Ror16:
1691  case AVR::Asr8:
1692  case AVR::Asr16:
1693  return insertShift(MI, MBB);
1694  case AVR::MULRdRr:
1695  case AVR::MULSRdRr:
1696  return insertMul(MI, MBB);
1697  }
1698 
1699  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1700  "Unexpected instr type to insert");
1701 
1702  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1703  ->getParent()
1704  ->getSubtarget()
1705  .getInstrInfo();
1706  DebugLoc dl = MI.getDebugLoc();
1707 
1708  // To "insert" a SELECT instruction, we insert the diamond
1709  // control-flow pattern. The incoming instruction knows the
1710  // destination vreg to set, the condition code register to branch
1711  // on, the true/false values to select between, and a branch opcode
1712  // to use.
1713 
1714  MachineFunction *MF = MBB->getParent();
1715  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1716  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1717 
1718  // If the current basic block falls through to another basic block,
1719  // we must insert an unconditional branch to the fallthrough destination
1720  // if we are to insert basic blocks at the prior fallthrough point.
1721  if (FallThrough != nullptr) {
1722  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1723  }
1724 
1725  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1726  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1727 
1729  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
1730  ;
1731  if (I != MF->end())
1732  ++I;
1733  MF->insert(I, trueMBB);
1734  MF->insert(I, falseMBB);
1735 
1736  // Transfer remaining instructions and all successors of the current
1737  // block to the block which will contain the Phi node for the
1738  // select.
1739  trueMBB->splice(trueMBB->begin(), MBB,
1740  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1742 
1743  AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1744  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1745  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1746  MBB->addSuccessor(falseMBB);
1747  MBB->addSuccessor(trueMBB);
1748 
1749  // Unconditionally flow back to the true block
1750  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1751  falseMBB->addSuccessor(trueMBB);
1752 
1753  // Set up the Phi node to determine where we came from
1754  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
1755  MI.getOperand(0).getReg())
1756  .addReg(MI.getOperand(1).getReg())
1757  .addMBB(MBB)
1758  .addReg(MI.getOperand(2).getReg())
1759  .addMBB(falseMBB);
1760 
1761  MI.eraseFromParent(); // The pseudo instruction is gone now.
1762  return trueMBB;
1763 }
1764 
1765 //===----------------------------------------------------------------------===//
1766 // Inline Asm Support
1767 //===----------------------------------------------------------------------===//
1768 
1771  if (Constraint.size() == 1) {
1772  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1773  switch (Constraint[0]) {
1774  default:
1775  break;
1776  case 'a': // Simple upper registers
1777  case 'b': // Base pointer registers pairs
1778  case 'd': // Upper register
1779  case 'l': // Lower registers
1780  case 'e': // Pointer register pairs
1781  case 'q': // Stack pointer register
1782  case 'r': // Any register
1783  case 'w': // Special upper register pairs
1784  return C_RegisterClass;
1785  case 't': // Temporary register
1786  case 'x':
1787  case 'X': // Pointer register pair X
1788  case 'y':
1789  case 'Y': // Pointer register pair Y
1790  case 'z':
1791  case 'Z': // Pointer register pair Z
1792  return C_Register;
1793  case 'Q': // A memory address based on Y or Z pointer with displacement.
1794  return C_Memory;
1795  case 'G': // Floating point constant
1796  case 'I': // 6-bit positive integer constant
1797  case 'J': // 6-bit negative integer constant
1798  case 'K': // Integer constant (Range: 2)
1799  case 'L': // Integer constant (Range: 0)
1800  case 'M': // 8-bit integer constant
1801  case 'N': // Integer constant (Range: -1)
1802  case 'O': // Integer constant (Range: 8, 16, 24)
1803  case 'P': // Integer constant (Range: 1)
1804  case 'R': // Integer constant (Range: -6 to 5)x
1805  return C_Immediate;
1806  }
1807  }
1808 
1809  return TargetLowering::getConstraintType(Constraint);
1810 }
1811 
1812 unsigned
1814  // Not sure if this is actually the right thing to do, but we got to do
1815  // *something* [agnat]
1816  switch (ConstraintCode[0]) {
1817  case 'Q':
1818  return InlineAsm::Constraint_Q;
1819  }
1820  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1821 }
1822 
1825  AsmOperandInfo &info, const char *constraint) const {
1826  ConstraintWeight weight = CW_Invalid;
1827  Value *CallOperandVal = info.CallOperandVal;
1828 
1829  // If we don't have a value, we can't do a match,
1830  // but allow it at the lowest weight.
1831  // (this behaviour has been copied from the ARM backend)
1832  if (!CallOperandVal) {
1833  return CW_Default;
1834  }
1835 
1836  // Look at the constraint type.
1837  switch (*constraint) {
1838  default:
1840  break;
1841  case 'd':
1842  case 'r':
1843  case 'l':
1844  weight = CW_Register;
1845  break;
1846  case 'a':
1847  case 'b':
1848  case 'e':
1849  case 'q':
1850  case 't':
1851  case 'w':
1852  case 'x':
1853  case 'X':
1854  case 'y':
1855  case 'Y':
1856  case 'z':
1857  case 'Z':
1858  weight = CW_SpecificReg;
1859  break;
1860  case 'G':
1861  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1862  if (C->isZero()) {
1863  weight = CW_Constant;
1864  }
1865  }
1866  break;
1867  case 'I':
1868  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1869  if (isUInt<6>(C->getZExtValue())) {
1870  weight = CW_Constant;
1871  }
1872  }
1873  break;
1874  case 'J':
1875  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1876  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1877  weight = CW_Constant;
1878  }
1879  }
1880  break;
1881  case 'K':
1882  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1883  if (C->getZExtValue() == 2) {
1884  weight = CW_Constant;
1885  }
1886  }
1887  break;
1888  case 'L':
1889  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1890  if (C->getZExtValue() == 0) {
1891  weight = CW_Constant;
1892  }
1893  }
1894  break;
1895  case 'M':
1896  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1897  if (isUInt<8>(C->getZExtValue())) {
1898  weight = CW_Constant;
1899  }
1900  }
1901  break;
1902  case 'N':
1903  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1904  if (C->getSExtValue() == -1) {
1905  weight = CW_Constant;
1906  }
1907  }
1908  break;
1909  case 'O':
1910  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1911  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1912  (C->getZExtValue() == 24)) {
1913  weight = CW_Constant;
1914  }
1915  }
1916  break;
1917  case 'P':
1918  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1919  if (C->getZExtValue() == 1) {
1920  weight = CW_Constant;
1921  }
1922  }
1923  break;
1924  case 'R':
1925  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1926  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1927  weight = CW_Constant;
1928  }
1929  }
1930  break;
1931  case 'Q':
1932  weight = CW_Memory;
1933  break;
1934  }
1935 
1936  return weight;
1937 }
1938 
1939 std::pair<unsigned, const TargetRegisterClass *>
1941  StringRef Constraint,
1942  MVT VT) const {
1943  if (Constraint.size() == 1) {
1944  switch (Constraint[0]) {
1945  case 'a': // Simple upper registers r16..r23.
1946  if (VT == MVT::i8)
1947  return std::make_pair(0U, &AVR::LD8loRegClass);
1948  else if (VT == MVT::i16)
1949  return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
1950  break;
1951  case 'b': // Base pointer registers: y, z.
1952  if (VT == MVT::i8 || VT == MVT::i16)
1953  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1954  break;
1955  case 'd': // Upper registers r16..r31.
1956  if (VT == MVT::i8)
1957  return std::make_pair(0U, &AVR::LD8RegClass);
1958  else if (VT == MVT::i16)
1959  return std::make_pair(0U, &AVR::DLDREGSRegClass);
1960  break;
1961  case 'l': // Lower registers r0..r15.
1962  if (VT == MVT::i8)
1963  return std::make_pair(0U, &AVR::GPR8loRegClass);
1964  else if (VT == MVT::i16)
1965  return std::make_pair(0U, &AVR::DREGSloRegClass);
1966  break;
1967  case 'e': // Pointer register pairs: x, y, z.
1968  if (VT == MVT::i8 || VT == MVT::i16)
1969  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1970  break;
1971  case 'q': // Stack pointer register: SPH:SPL.
1972  return std::make_pair(0U, &AVR::GPRSPRegClass);
1973  case 'r': // Any register: r0..r31.
1974  if (VT == MVT::i8)
1975  return std::make_pair(0U, &AVR::GPR8RegClass);
1976  else if (VT == MVT::i16)
1977  return std::make_pair(0U, &AVR::DREGSRegClass);
1978  break;
1979  case 't': // Temporary register: r0.
1980  if (VT == MVT::i8)
1981  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1982  break;
1983  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1984  if (VT == MVT::i8 || VT == MVT::i16)
1985  return std::make_pair(0U, &AVR::IWREGSRegClass);
1986  break;
1987  case 'x': // Pointer register pair X: r27:r26.
1988  case 'X':
1989  if (VT == MVT::i8 || VT == MVT::i16)
1990  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1991  break;
1992  case 'y': // Pointer register pair Y: r29:r28.
1993  case 'Y':
1994  if (VT == MVT::i8 || VT == MVT::i16)
1995  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1996  break;
1997  case 'z': // Pointer register pair Z: r31:r30.
1998  case 'Z':
1999  if (VT == MVT::i8 || VT == MVT::i16)
2000  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2001  break;
2002  default:
2003  break;
2004  }
2005  }
2006 
2008  Subtarget.getRegisterInfo(), Constraint, VT);
2009 }
2010 
2012  std::string &Constraint,
2013  std::vector<SDValue> &Ops,
2014  SelectionDAG &DAG) const {
2015  SDValue Result(0, 0);
2016  SDLoc DL(Op);
2017  EVT Ty = Op.getValueType();
2018 
2019  // Currently only support length 1 constraints.
2020  if (Constraint.length() != 1) {
2021  return;
2022  }
2023 
2024  char ConstraintLetter = Constraint[0];
2025  switch (ConstraintLetter) {
2026  default:
2027  break;
2028  // Deal with integers first:
2029  case 'I':
2030  case 'J':
2031  case 'K':
2032  case 'L':
2033  case 'M':
2034  case 'N':
2035  case 'O':
2036  case 'P':
2037  case 'R': {
2038  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2039  if (!C) {
2040  return;
2041  }
2042 
2043  int64_t CVal64 = C->getSExtValue();
2044  uint64_t CUVal64 = C->getZExtValue();
2045  switch (ConstraintLetter) {
2046  case 'I': // 0..63
2047  if (!isUInt<6>(CUVal64))
2048  return;
2049  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2050  break;
2051  case 'J': // -63..0
2052  if (CVal64 < -63 || CVal64 > 0)
2053  return;
2054  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2055  break;
2056  case 'K': // 2
2057  if (CUVal64 != 2)
2058  return;
2059  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2060  break;
2061  case 'L': // 0
2062  if (CUVal64 != 0)
2063  return;
2064  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2065  break;
2066  case 'M': // 0..255
2067  if (!isUInt<8>(CUVal64))
2068  return;
2069  // i8 type may be printed as a negative number,
2070  // e.g. 254 would be printed as -2,
2071  // so we force it to i16 at least.
2072  if (Ty.getSimpleVT() == MVT::i8) {
2073  Ty = MVT::i16;
2074  }
2075  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2076  break;
2077  case 'N': // -1
2078  if (CVal64 != -1)
2079  return;
2080  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2081  break;
2082  case 'O': // 8, 16, 24
2083  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2084  return;
2085  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2086  break;
2087  case 'P': // 1
2088  if (CUVal64 != 1)
2089  return;
2090  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2091  break;
2092  case 'R': // -6..5
2093  if (CVal64 < -6 || CVal64 > 5)
2094  return;
2095  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2096  break;
2097  }
2098 
2099  break;
2100  }
2101  case 'G':
2102  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2103  if (!FC || !FC->isZero())
2104  return;
2105  // Soften float to i8 0
2106  Result = DAG.getTargetConstant(0, DL, MVT::i8);
2107  break;
2108  }
2109 
2110  if (Result.getNode()) {
2111  Ops.push_back(Result);
2112  return;
2113  }
2114 
2115  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2116 }
2117 
2119  const MachineFunction &MF) const {
2120  Register Reg;
2121 
2122  if (VT == LLT::scalar(8)) {
2124  .Case("r0", AVR::R0)
2125  .Case("r1", AVR::R1)
2126  .Default(0);
2127  } else {
2129  .Case("r0", AVR::R1R0)
2130  .Case("sp", AVR::SP)
2131  .Default(0);
2132  }
2133 
2134  if (Reg)
2135  return Reg;
2136 
2138  Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2139 }
2140 
2141 } // end of namespace llvm
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1374
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:990
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1556
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2134
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1385
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1072
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1310
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:47
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:197
llvm::StructType::get
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:408
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1382
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:35
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:848
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1386
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:1813
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:4889
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:265
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4155
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:946
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1341
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1150
llvm::Function
Definition: Function.h:62
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:234
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1310
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:666
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:931
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:253
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1381
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1012
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:814
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:51
llvm::AVR::ProgramMemory
@ ProgramMemory
Definition: AVR.h:42
ErrorHandling.h
llvm::isCopyMulResult
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
Definition: AVRISelLowering.cpp:1648
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:2857
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4176
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2281
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:69
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetLowering::C_Memory
@ C_Memory
Definition: TargetLowering.h:4158
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1376
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:715
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2333
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:831
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::AVRISD::ASRWN
@ ASRWN
Word arithmetic shift right N bits.
Definition: AVRISelLowering.h:46
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2299
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9538
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:62
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:49
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:887
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:829
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2874
STLExtras.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1041
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1341
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSLWN
@ LSLWN
Word logical shift left N bits.
Definition: AVRISelLowering.h:40
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:956
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:794
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:660
llvm::analyzeReturnValues
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo)
Analyze incoming and outgoing value of returning from a function.
Definition: AVRISelLowering.cpp:1102
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1411
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:751
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:963
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:694
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1121
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:44
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:66
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1383
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:747
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2363
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1395
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3187
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:66
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2181
llvm::Instruction
Definition: Instruction.h:45
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:36
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:826
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1149
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2236
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:2011
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4156
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:257
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:812
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4159
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2129
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:38
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1676
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:1824
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1373
llvm::Sched::RegPressure
@ RegPressure
Definition: TargetLowering.h:101
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:64
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1310
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2198
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::TargetLowering::CW_SpecificReg
@ CW_SpecificReg
Definition: TargetLowering.h:4173
NODE
#define NODE(name)
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1770
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:53
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1147
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1605
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:198
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::getTotalArgumentsSizeInBytes
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
Definition: AVRISelLowering.cpp:1089
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2147
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1146
llvm::TargetLowering::CW_Register
@ CW_Register
Definition: TargetLowering.h:4174
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8345
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1125
llvm::AVRISD::LSRBN
@ LSRBN
Byte logical shift right N bits.
Definition: AVRISelLowering.h:42
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4181
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:415
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:102
AVRTargetMachine.h
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:797
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2309
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:48
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1341
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:1940
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3745
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:615
llvm::AVRISD::LSRWN
@ LSRWN
Word logical shift right N bits.
Definition: AVRISelLowering.h:43
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::AVRSubtarget::supportsMultiplication
bool supportsMultiplication() const
Definition: AVRSubtarget.h:79
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:858
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1375
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
AVRMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:943
llvm::TargetLowering::CW_Memory
@ CW_Memory
Definition: TargetLowering.h:4175
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:716
llvm::RegList8
static const MCPhysReg RegList8[]
Registers for calling conventions, ordered in reverse as required by ABI.
Definition: AVRISelLowering.cpp:1003
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1042
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4177
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:35
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:182
llvm::ReplayInlineScope::Function
@ Function
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:58
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:41
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
AVRSubtarget.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4519
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2361
uint32_t
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:4598
llvm::AVRISD::ASRBN
@ ASRBN
Byte arithmetic shift right N bits.
Definition: AVRISelLowering.h:45
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2217
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1139
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1341
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4157
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:304
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::RegList16
static const MCPhysReg RegList16[]
Definition: AVRISelLowering.cpp:1007
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
j
return j(j<< 16)
llvm::AArch64_AM::ASR
@ ASR
Definition: AArch64AddressingModes.h:37
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1384
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2362
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2205
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2227
uint16_t
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2364
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4164
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:425
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:201
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:963
llvm::analyzeArguments
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo)
Analyze incoming and outgoing function arguments.
Definition: AVRISelLowering.cpp:1022
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:233
StringSwitch.h
AVR.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4166
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2852
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1037
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::intCCToAVRCC
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Definition: AVRISelLowering.cpp:505
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:717
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::CallingConv::AVR_BUILTIN
@ AVR_BUILTIN
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:199
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2115
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:79
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:199
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2118
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1285
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2003
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4256
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:667
llvm::AVRInstrInfo
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2360
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:50
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:614
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:890
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:60
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:637
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1032
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2879
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1008
AVRISelLowering.h
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1021
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:661
llvm::AVRISD::LSLBN
@ LSLBN
Byte logical shift left N bits.
Definition: AVRISelLowering.h:39
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4458
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:669
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1148
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
llvm::AVR::isProgramMemoryAccess
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:49
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:503
TargetLoweringObjectFileImpl.h
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:52