LLVM  13.0.0git
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRSubtarget.h"
30 #include "AVRTargetMachine.h"
32 
33 namespace llvm {
34 
36  const AVRSubtarget &STI)
37  : TargetLowering(TM), Subtarget(STI) {
38  // Set up the register classes.
39  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41 
42  // Compute derived properties from the register classes.
44 
50 
53 
58 
59  for (MVT VT : MVT::integer_valuetypes()) {
60  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63  }
64  }
65 
67 
68  for (MVT VT : MVT::integer_valuetypes()) {
73  }
74 
75  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76  // revert into a sub since we don't have an add with immediate instruction.
79 
80  // our shift instructions are only able to shift 1 bit at a time, so handle
81  // this in a custom way.
91 
96 
102 
113 
115 
116  // Add support for postincrement and predecrement load/stores.
125 
127 
132 
133  // Atomic operations which must be lowered to rtlib calls
134  for (MVT VT : MVT::integer_valuetypes()) {
142  }
143 
144  // Division/remainder
153 
154  // Make division and modulus custom
161 
162  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
165 
166  // Expand 16 bit multiplications.
169 
170  // Expand multiplications to libcalls when there is
171  // no hardware MUL.
175  }
176 
177  for (MVT VT : MVT::integer_valuetypes()) {
180  }
181 
182  for (MVT VT : MVT::integer_valuetypes()) {
186  }
187 
188  for (MVT VT : MVT::integer_valuetypes()) {
190  // TODO: The generated code is pretty poor. Investigate using the
191  // same "shift and subtract with carry" trick that we do for
192  // extending 8-bit to 16-bit. This may require infrastructure
193  // improvements in how we treat 16-bit "registers" to be feasible.
194  }
195 
196  // Division rtlib functions (not supported), use divmod functions instead
197  setLibcallName(RTLIB::SDIV_I8, nullptr);
198  setLibcallName(RTLIB::SDIV_I16, nullptr);
199  setLibcallName(RTLIB::SDIV_I32, nullptr);
200  setLibcallName(RTLIB::UDIV_I8, nullptr);
201  setLibcallName(RTLIB::UDIV_I16, nullptr);
202  setLibcallName(RTLIB::UDIV_I32, nullptr);
203 
204  // Modulus rtlib functions (not supported), use divmod functions instead
205  setLibcallName(RTLIB::SREM_I8, nullptr);
206  setLibcallName(RTLIB::SREM_I16, nullptr);
207  setLibcallName(RTLIB::SREM_I32, nullptr);
208  setLibcallName(RTLIB::UREM_I8, nullptr);
209  setLibcallName(RTLIB::UREM_I16, nullptr);
210  setLibcallName(RTLIB::UREM_I32, nullptr);
211 
212  // Division and modulus rtlib functions
213  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219 
220  // Several of the runtime library functions use a special calling conv
222  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
224  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225 
226  // Trigonometric rtlib functions
227  setLibcallName(RTLIB::SIN_F32, "sin");
228  setLibcallName(RTLIB::COS_F32, "cos");
229 
231  setMinimumJumpTableEntries(UINT_MAX);
232 }
233 
234 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235 #define NODE(name) \
236  case AVRISD::name: \
237  return #name
238 
239  switch (Opcode) {
240  default:
241  return nullptr;
242  NODE(RET_FLAG);
243  NODE(RETI_FLAG);
244  NODE(CALL);
245  NODE(WRAPPER);
246  NODE(LSL);
247  NODE(LSR);
248  NODE(ROL);
249  NODE(ROR);
250  NODE(ASR);
251  NODE(LSLLOOP);
252  NODE(LSRLOOP);
253  NODE(ROLLOOP);
254  NODE(RORLOOP);
255  NODE(ASRLOOP);
256  NODE(BRCOND);
257  NODE(CMP);
258  NODE(CMPC);
259  NODE(TST);
260  NODE(SELECT_CC);
261 #undef NODE
262  }
263 }
264 
266  EVT VT) const {
267  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
268  return MVT::i8;
269 }
270 
271 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272  //:TODO: this function has to be completely rewritten to produce optimal
273  // code, for now it's producing very long but correct code.
274  unsigned Opc8;
275  const SDNode *N = Op.getNode();
276  EVT VT = Op.getValueType();
277  SDLoc dl(N);
279  "Expected power-of-2 shift amount");
280 
281  // Expand non-constant shifts to loops.
282  if (!isa<ConstantSDNode>(N->getOperand(1))) {
283  switch (Op.getOpcode()) {
284  default:
285  llvm_unreachable("Invalid shift opcode!");
286  case ISD::SHL:
287  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288  N->getOperand(1));
289  case ISD::SRL:
290  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291  N->getOperand(1));
292  case ISD::ROTL: {
293  SDValue Amt = N->getOperand(1);
294  EVT AmtVT = Amt.getValueType();
295  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298  }
299  case ISD::ROTR: {
300  SDValue Amt = N->getOperand(1);
301  EVT AmtVT = Amt.getValueType();
302  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305  }
306  case ISD::SRA:
307  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308  N->getOperand(1));
309  }
310  }
311 
312  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313  SDValue Victim = N->getOperand(0);
314 
315  switch (Op.getOpcode()) {
316  case ISD::SRA:
317  Opc8 = AVRISD::ASR;
318  break;
319  case ISD::ROTL:
320  Opc8 = AVRISD::ROL;
321  ShiftAmount = ShiftAmount % VT.getSizeInBits();
322  break;
323  case ISD::ROTR:
324  Opc8 = AVRISD::ROR;
325  ShiftAmount = ShiftAmount % VT.getSizeInBits();
326  break;
327  case ISD::SRL:
328  Opc8 = AVRISD::LSR;
329  break;
330  case ISD::SHL:
331  Opc8 = AVRISD::LSL;
332  break;
333  default:
334  llvm_unreachable("Invalid shift opcode");
335  }
336 
337  // Optimize int8/int16 shifts.
338  if (VT.getSizeInBits() == 8) {
339  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340  // Optimize LSL when 4 <= ShiftAmount <= 6.
341  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
342  Victim =
343  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
344  ShiftAmount -= 4;
345  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
346  ShiftAmount < 7) {
347  // Optimize LSR when 4 <= ShiftAmount <= 6.
348  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
349  Victim =
350  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
351  ShiftAmount -= 4;
352  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
353  // Optimize LSL when ShiftAmount == 7.
354  Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim);
355  ShiftAmount = 0;
356  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
357  // Optimize LSR when ShiftAmount == 7.
358  Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim);
359  ShiftAmount = 0;
360  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
361  // Optimize ASR when ShiftAmount == 7.
362  Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
363  ShiftAmount = 0;
364  }
365  } else if (VT.getSizeInBits() == 16) {
366  if (4 <= ShiftAmount && ShiftAmount < 8)
367  switch (Op.getOpcode()) {
368  case ISD::SHL:
369  Victim = DAG.getNode(AVRISD::LSL4, dl, VT, Victim);
370  ShiftAmount -= 4;
371  break;
372  case ISD::SRL:
373  Victim = DAG.getNode(AVRISD::LSR4, dl, VT, Victim);
374  ShiftAmount -= 4;
375  break;
376  default:
377  break;
378  }
379  else if (8 <= ShiftAmount && ShiftAmount < 12)
380  switch (Op.getOpcode()) {
381  case ISD::SHL:
382  Victim = DAG.getNode(AVRISD::LSL8, dl, VT, Victim);
383  ShiftAmount -= 8;
384  break;
385  case ISD::SRL:
386  Victim = DAG.getNode(AVRISD::LSR8, dl, VT, Victim);
387  ShiftAmount -= 8;
388  break;
389  case ISD::SRA:
390  Victim = DAG.getNode(AVRISD::ASR8, dl, VT, Victim);
391  ShiftAmount -= 8;
392  break;
393  default:
394  break;
395  }
396  else if (12 <= ShiftAmount)
397  switch (Op.getOpcode()) {
398  case ISD::SHL:
399  Victim = DAG.getNode(AVRISD::LSL12, dl, VT, Victim);
400  ShiftAmount -= 12;
401  break;
402  case ISD::SRL:
403  Victim = DAG.getNode(AVRISD::LSR12, dl, VT, Victim);
404  ShiftAmount -= 12;
405  break;
406  default:
407  break;
408  }
409  }
410 
411  while (ShiftAmount--) {
412  Victim = DAG.getNode(Opc8, dl, VT, Victim);
413  }
414 
415  return Victim;
416 }
417 
418 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
419  unsigned Opcode = Op->getOpcode();
420  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
421  "Invalid opcode for Div/Rem lowering");
422  bool IsSigned = (Opcode == ISD::SDIVREM);
423  EVT VT = Op->getValueType(0);
424  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
425 
426  RTLIB::Libcall LC;
427  switch (VT.getSimpleVT().SimpleTy) {
428  default:
429  llvm_unreachable("Unexpected request for libcall!");
430  case MVT::i8:
431  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
432  break;
433  case MVT::i16:
434  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
435  break;
436  case MVT::i32:
437  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
438  break;
439  }
440 
441  SDValue InChain = DAG.getEntryNode();
442 
444  TargetLowering::ArgListEntry Entry;
445  for (SDValue const &Value : Op->op_values()) {
446  Entry.Node = Value;
447  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
448  Entry.IsSExt = IsSigned;
449  Entry.IsZExt = !IsSigned;
450  Args.push_back(Entry);
451  }
452 
453  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
454  getPointerTy(DAG.getDataLayout()));
455 
456  Type *RetTy = (Type *)StructType::get(Ty, Ty);
457 
458  SDLoc dl(Op);
459  TargetLowering::CallLoweringInfo CLI(DAG);
460  CLI.setDebugLoc(dl)
461  .setChain(InChain)
462  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
463  .setInRegister()
464  .setSExtResult(IsSigned)
465  .setZExtResult(!IsSigned);
466 
467  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
468  return CallInfo.first;
469 }
470 
471 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
472  SelectionDAG &DAG) const {
473  auto DL = DAG.getDataLayout();
474 
475  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
476  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
477 
478  // Create the TargetGlobalAddress node, folding in the constant offset.
479  SDValue Result =
480  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
481  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
482 }
483 
484 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
485  SelectionDAG &DAG) const {
486  auto DL = DAG.getDataLayout();
487  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
488 
489  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
490 
491  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
492 }
493 
494 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
496  switch (CC) {
497  default:
498  llvm_unreachable("Unknown condition code!");
499  case ISD::SETEQ:
500  return AVRCC::COND_EQ;
501  case ISD::SETNE:
502  return AVRCC::COND_NE;
503  case ISD::SETGE:
504  return AVRCC::COND_GE;
505  case ISD::SETLT:
506  return AVRCC::COND_LT;
507  case ISD::SETUGE:
508  return AVRCC::COND_SH;
509  case ISD::SETULT:
510  return AVRCC::COND_LO;
511  }
512 }
513 
514 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
515 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
516  SelectionDAG &DAG, SDLoc DL) const {
517  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
518  "LHS and RHS have different types");
519  assert(((LHS.getSimpleValueType() == MVT::i16) ||
520  (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type");
521 
522  SDValue Cmp;
523 
524  if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
525  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
526  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
527  DAG.getIntPtrConstant(0, DL));
528  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
529  DAG.getIntPtrConstant(1, DL));
530  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
531  DAG.getIntPtrConstant(0, DL));
532  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
533  DAG.getIntPtrConstant(1, DL));
534  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
535  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
536  } else {
537  // Generate ordinary 16-bit comparison.
538  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
539  }
540 
541  return Cmp;
542 }
543 
544 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
545 /// the given operands.
546 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
547  SDValue &AVRcc, SelectionDAG &DAG,
548  SDLoc DL) const {
549  SDValue Cmp;
550  EVT VT = LHS.getValueType();
551  bool UseTest = false;
552 
553  switch (CC) {
554  default:
555  break;
556  case ISD::SETLE: {
557  // Swap operands and reverse the branching condition.
558  std::swap(LHS, RHS);
559  CC = ISD::SETGE;
560  break;
561  }
562  case ISD::SETGT: {
563  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
564  switch (C->getSExtValue()) {
565  case -1: {
566  // When doing lhs > -1 use a tst instruction on the top part of lhs
567  // and use brpl instead of using a chain of cp/cpc.
568  UseTest = true;
569  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
570  break;
571  }
572  case 0: {
573  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
574  // __zero_reg__ in lhs.
575  RHS = LHS;
576  LHS = DAG.getConstant(0, DL, VT);
577  CC = ISD::SETLT;
578  break;
579  }
580  default: {
581  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
582  // us to fold the constant into the cmp instruction.
583  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
584  CC = ISD::SETGE;
585  break;
586  }
587  }
588  break;
589  }
590  // Swap operands and reverse the branching condition.
591  std::swap(LHS, RHS);
592  CC = ISD::SETLT;
593  break;
594  }
595  case ISD::SETLT: {
596  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
597  switch (C->getSExtValue()) {
598  case 1: {
599  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
600  // __zero_reg__ in lhs.
601  RHS = LHS;
602  LHS = DAG.getConstant(0, DL, VT);
603  CC = ISD::SETGE;
604  break;
605  }
606  case 0: {
607  // When doing lhs < 0 use a tst instruction on the top part of lhs
608  // and use brmi instead of using a chain of cp/cpc.
609  UseTest = true;
610  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
611  break;
612  }
613  }
614  }
615  break;
616  }
617  case ISD::SETULE: {
618  // Swap operands and reverse the branching condition.
619  std::swap(LHS, RHS);
620  CC = ISD::SETUGE;
621  break;
622  }
623  case ISD::SETUGT: {
624  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
625  // fold the constant into the cmp instruction.
626  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
627  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
628  CC = ISD::SETUGE;
629  break;
630  }
631  // Swap operands and reverse the branching condition.
632  std::swap(LHS, RHS);
633  CC = ISD::SETULT;
634  break;
635  }
636  }
637 
638  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
639  // using the default and/or/xor expansion code which is much longer.
640  if (VT == MVT::i32) {
641  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
642  DAG.getIntPtrConstant(0, DL));
643  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
644  DAG.getIntPtrConstant(1, DL));
645  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
646  DAG.getIntPtrConstant(0, DL));
647  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
648  DAG.getIntPtrConstant(1, DL));
649 
650  if (UseTest) {
651  // When using tst we only care about the highest part.
652  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
653  DAG.getIntPtrConstant(1, DL));
654  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
655  } else {
656  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
657  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
658  }
659  } else if (VT == MVT::i64) {
660  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
661  DAG.getIntPtrConstant(0, DL));
662  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
663  DAG.getIntPtrConstant(1, DL));
664 
665  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
666  DAG.getIntPtrConstant(0, DL));
667  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
668  DAG.getIntPtrConstant(1, DL));
669  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
670  DAG.getIntPtrConstant(0, DL));
671  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
672  DAG.getIntPtrConstant(1, DL));
673 
674  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
675  DAG.getIntPtrConstant(0, DL));
676  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
677  DAG.getIntPtrConstant(1, DL));
678 
679  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
680  DAG.getIntPtrConstant(0, DL));
681  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
682  DAG.getIntPtrConstant(1, DL));
683  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
684  DAG.getIntPtrConstant(0, DL));
685  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
686  DAG.getIntPtrConstant(1, DL));
687 
688  if (UseTest) {
689  // When using tst we only care about the highest part.
690  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
691  DAG.getIntPtrConstant(1, DL));
692  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
693  } else {
694  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
695  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
696  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
697  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
698  }
699  } else if (VT == MVT::i8 || VT == MVT::i16) {
700  if (UseTest) {
701  // When using tst we only care about the highest part.
702  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
703  (VT == MVT::i8)
704  ? LHS
705  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
706  LHS, DAG.getIntPtrConstant(1, DL)));
707  } else {
708  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
709  }
710  } else {
711  llvm_unreachable("Invalid comparison size");
712  }
713 
714  // When using a test instruction AVRcc is already set.
715  if (!UseTest) {
716  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
717  }
718 
719  return Cmp;
720 }
721 
722 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
723  SDValue Chain = Op.getOperand(0);
724  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
725  SDValue LHS = Op.getOperand(2);
726  SDValue RHS = Op.getOperand(3);
727  SDValue Dest = Op.getOperand(4);
728  SDLoc dl(Op);
729 
730  SDValue TargetCC;
731  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
732 
733  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
734  Cmp);
735 }
736 
737 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
738  SDValue LHS = Op.getOperand(0);
739  SDValue RHS = Op.getOperand(1);
740  SDValue TrueV = Op.getOperand(2);
741  SDValue FalseV = Op.getOperand(3);
742  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
743  SDLoc dl(Op);
744 
745  SDValue TargetCC;
746  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
747 
748  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
749  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
750 
751  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
752 }
753 
754 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
755  SDValue LHS = Op.getOperand(0);
756  SDValue RHS = Op.getOperand(1);
757  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
758  SDLoc DL(Op);
759 
760  SDValue TargetCC;
761  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
762 
763  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
764  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
765  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
766  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
767 
768  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
769 }
770 
771 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
772  const MachineFunction &MF = DAG.getMachineFunction();
773  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
774  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
775  auto DL = DAG.getDataLayout();
776  SDLoc dl(Op);
777 
778  // Vastart just stores the address of the VarArgsFrameIndex slot into the
779  // memory location argument.
780  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
781 
782  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
783  MachinePointerInfo(SV));
784 }
785 
787  switch (Op.getOpcode()) {
788  default:
789  llvm_unreachable("Don't know how to custom lower this!");
790  case ISD::SHL:
791  case ISD::SRA:
792  case ISD::SRL:
793  case ISD::ROTL:
794  case ISD::ROTR:
795  return LowerShifts(Op, DAG);
796  case ISD::GlobalAddress:
797  return LowerGlobalAddress(Op, DAG);
798  case ISD::BlockAddress:
799  return LowerBlockAddress(Op, DAG);
800  case ISD::BR_CC:
801  return LowerBR_CC(Op, DAG);
802  case ISD::SELECT_CC:
803  return LowerSELECT_CC(Op, DAG);
804  case ISD::SETCC:
805  return LowerSETCC(Op, DAG);
806  case ISD::VASTART:
807  return LowerVASTART(Op, DAG);
808  case ISD::SDIVREM:
809  case ISD::UDIVREM:
810  return LowerDivRem(Op, DAG);
811  }
812 
813  return SDValue();
814 }
815 
816 /// Replace a node with an illegal result type
817 /// with a new node built out of custom code.
820  SelectionDAG &DAG) const {
821  SDLoc DL(N);
822 
823  switch (N->getOpcode()) {
824  case ISD::ADD: {
825  // Convert add (x, imm) into sub (x, -imm).
826  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
827  SDValue Sub = DAG.getNode(
828  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
829  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
830  Results.push_back(Sub);
831  }
832  break;
833  }
834  default: {
835  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
836 
837  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
838  Results.push_back(Res.getValue(I));
839 
840  break;
841  }
842  }
843 }
844 
845 /// Return true if the addressing mode represented
846 /// by AM is legal for this target, for a load/store of the specified type.
848  const AddrMode &AM, Type *Ty,
849  unsigned AS, Instruction *I) const {
850  int64_t Offs = AM.BaseOffs;
851 
852  // Allow absolute addresses.
853  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
854  return true;
855  }
856 
857  // Flash memory instructions only allow zero offsets.
858  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
859  return false;
860  }
861 
862  // Allow reg+<6bit> offset.
863  if (Offs < 0)
864  Offs = -Offs;
865  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
866  return true;
867  }
868 
869  return false;
870 }
871 
872 /// Returns true by value, base pointer and
873 /// offset pointer and addressing mode by reference if the node's address
874 /// can be legally represented as pre-indexed load / store address.
876  SDValue &Offset,
878  SelectionDAG &DAG) const {
879  EVT VT;
880  const SDNode *Op;
881  SDLoc DL(N);
882 
883  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
884  VT = LD->getMemoryVT();
885  Op = LD->getBasePtr().getNode();
886  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
887  return false;
889  return false;
890  }
891  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
892  VT = ST->getMemoryVT();
893  Op = ST->getBasePtr().getNode();
895  return false;
896  }
897  } else {
898  return false;
899  }
900 
901  if (VT != MVT::i8 && VT != MVT::i16) {
902  return false;
903  }
904 
905  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
906  return false;
907  }
908 
909  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
910  int RHSC = RHS->getSExtValue();
911  if (Op->getOpcode() == ISD::SUB)
912  RHSC = -RHSC;
913 
914  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
915  return false;
916  }
917 
918  Base = Op->getOperand(0);
919  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
920  AM = ISD::PRE_DEC;
921 
922  return true;
923  }
924 
925  return false;
926 }
927 
928 /// Returns true by value, base pointer and
929 /// offset pointer and addressing mode by reference if this node can be
930 /// combined with a load / store to form a post-indexed load / store.
932  SDValue &Base,
933  SDValue &Offset,
935  SelectionDAG &DAG) const {
936  EVT VT;
937  SDLoc DL(N);
938 
939  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
940  VT = LD->getMemoryVT();
941  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
942  return false;
943  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
944  VT = ST->getMemoryVT();
946  return false;
947  }
948  } else {
949  return false;
950  }
951 
952  if (VT != MVT::i8 && VT != MVT::i16) {
953  return false;
954  }
955 
956  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
957  return false;
958  }
959 
960  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
961  int RHSC = RHS->getSExtValue();
962  if (Op->getOpcode() == ISD::SUB)
963  RHSC = -RHSC;
964  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
965  return false;
966  }
967 
968  Base = Op->getOperand(0);
969  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
970  AM = ISD::POST_INC;
971 
972  return true;
973  }
974 
975  return false;
976 }
977 
979  const GlobalAddressSDNode *GA) const {
980  return true;
981 }
982 
983 //===----------------------------------------------------------------------===//
984 // Formal Arguments Calling Convention Implementation
985 //===----------------------------------------------------------------------===//
986 
987 #include "AVRGenCallingConv.inc"
988 
989 /// Registers for calling conventions, ordered in reverse as required by ABI.
990 /// Both arrays must be of the same length.
991 static const MCPhysReg RegList8[] = {
992  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
993  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
994  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
995 static const MCPhysReg RegList16[] = {
996  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
997  AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
998  AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
999  AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
1000  AVR::R10R9, AVR::R9R8};
1001 
1002 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
1003  "8-bit and 16-bit register arrays must be of equal length");
1004 
1005 /// Analyze incoming and outgoing function arguments. We need custom C++ code
1006 /// to handle special constraints in the ABI.
1007 /// In addition, all pieces of a certain argument have to be passed either
1008 /// using registers or the stack but never mixing both.
1009 template <typename ArgT>
1010 static void
1012  const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
1013  SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
1014  unsigned NumArgs = Args.size();
1015  // This is the index of the last used register, in RegList*.
1016  // -1 means R26 (R26 is never actually used in CC).
1017  int RegLastIdx = -1;
1018  // Once a value is passed to the stack it will always be used
1019  bool UseStack = false;
1020  for (unsigned i = 0; i != NumArgs;) {
1021  MVT VT = Args[i].VT;
1022  // We have to count the number of bytes for each function argument, that is
1023  // those Args with the same OrigArgIndex. This is important in case the
1024  // function takes an aggregate type.
1025  // Current argument will be between [i..j).
1026  unsigned ArgIndex = Args[i].OrigArgIndex;
1027  unsigned TotalBytes = VT.getStoreSize();
1028  unsigned j = i + 1;
1029  for (; j != NumArgs; ++j) {
1030  if (Args[j].OrigArgIndex != ArgIndex)
1031  break;
1032  TotalBytes += Args[j].VT.getStoreSize();
1033  }
1034  // Round up to even number of bytes.
1035  TotalBytes = alignTo(TotalBytes, 2);
1036  // Skip zero sized arguments
1037  if (TotalBytes == 0)
1038  continue;
1039  // The index of the first register to be used
1040  unsigned RegIdx = RegLastIdx + TotalBytes;
1041  RegLastIdx = RegIdx;
1042  // If there are not enough registers, use the stack
1043  if (RegIdx >= array_lengthof(RegList8)) {
1044  UseStack = true;
1045  }
1046  for (; i != j; ++i) {
1047  MVT VT = Args[i].VT;
1048 
1049  if (UseStack) {
1050  auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1051  unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1052  TD->getABITypeAlign(evt));
1053  CCInfo.addLoc(
1055  } else {
1056  unsigned Reg;
1057  if (VT == MVT::i8) {
1058  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1059  } else if (VT == MVT::i16) {
1060  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1061  } else {
1063  "calling convention can only manage i8 and i16 types");
1064  }
1065  assert(Reg && "register not available in calling convention");
1066  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1067  // Registers inside a particular argument are sorted in increasing order
1068  // (remember the array is reversed).
1069  RegIdx -= VT.getStoreSize();
1070  }
1071  }
1072  }
1073 }
1074 
1075 /// Count the total number of bytes needed to pass or return these arguments.
1076 template <typename ArgT>
1078  unsigned TotalBytes = 0;
1079 
1080  for (const ArgT& Arg : Args) {
1081  TotalBytes += Arg.VT.getStoreSize();
1082  }
1083  return TotalBytes;
1084 }
1085 
1086 /// Analyze incoming and outgoing value of returning from a function.
1087 /// The algorithm is similar to analyzeArguments, but there can only be
1088 /// one value, possibly an aggregate, and it is limited to 8 bytes.
1089 template <typename ArgT>
1091  CCState &CCInfo) {
1092  unsigned NumArgs = Args.size();
1093  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1094  // CanLowerReturn() guarantees this assertion.
1095  assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered");
1096 
1097  // GCC-ABI says that the size is rounded up to the next even number,
1098  // but actually once it is more than 4 it will always round up to 8.
1099  if (TotalBytes > 4) {
1100  TotalBytes = 8;
1101  } else {
1102  TotalBytes = alignTo(TotalBytes, 2);
1103  }
1104 
1105  // The index of the first register to use.
1106  int RegIdx = TotalBytes - 1;
1107  for (unsigned i = 0; i != NumArgs; ++i) {
1108  MVT VT = Args[i].VT;
1109  unsigned Reg;
1110  if (VT == MVT::i8) {
1111  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1112  } else if (VT == MVT::i16) {
1113  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1114  } else {
1115  llvm_unreachable("calling convention can only manage i8 and i16 types");
1116  }
1117  assert(Reg && "register not available in calling convention");
1118  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1119  // Registers sort in increasing order
1120  RegIdx -= VT.getStoreSize();
1121  }
1122 }
1123 
1124 SDValue AVRTargetLowering::LowerFormalArguments(
1125  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1126  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1127  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1128  MachineFunction &MF = DAG.getMachineFunction();
1129  MachineFrameInfo &MFI = MF.getFrameInfo();
1130  auto DL = DAG.getDataLayout();
1131 
1132  // Assign locations to all of the incoming arguments.
1133  SmallVector<CCValAssign, 16> ArgLocs;
1134  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1135  *DAG.getContext());
1136 
1137  // Variadic functions do not need all the analysis below.
1138  if (isVarArg) {
1139  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1140  } else {
1141  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1142  }
1143 
1144  SDValue ArgValue;
1145  for (CCValAssign &VA : ArgLocs) {
1146 
1147  // Arguments stored on registers.
1148  if (VA.isRegLoc()) {
1149  EVT RegVT = VA.getLocVT();
1150  const TargetRegisterClass *RC;
1151  if (RegVT == MVT::i8) {
1152  RC = &AVR::GPR8RegClass;
1153  } else if (RegVT == MVT::i16) {
1154  RC = &AVR::DREGSRegClass;
1155  } else {
1156  llvm_unreachable("Unknown argument type!");
1157  }
1158 
1159  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1160  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1161 
1162  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1163  // following code will handle zexts or sexts generated by other
1164  // front ends. Otherwise:
1165  // If this is an 8 bit value, it is really passed promoted
1166  // to 16 bits. Insert an assert[sz]ext to capture this, then
1167  // truncate to the right size.
1168  switch (VA.getLocInfo()) {
1169  default:
1170  llvm_unreachable("Unknown loc info!");
1171  case CCValAssign::Full:
1172  break;
1173  case CCValAssign::BCvt:
1174  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1175  break;
1176  case CCValAssign::SExt:
1177  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1178  DAG.getValueType(VA.getValVT()));
1179  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1180  break;
1181  case CCValAssign::ZExt:
1182  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1183  DAG.getValueType(VA.getValVT()));
1184  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1185  break;
1186  }
1187 
1188  InVals.push_back(ArgValue);
1189  } else {
1190  // Sanity check.
1191  assert(VA.isMemLoc());
1192 
1193  EVT LocVT = VA.getLocVT();
1194 
1195  // Create the frame index object for this incoming parameter.
1196  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1197  VA.getLocMemOffset(), true);
1198 
1199  // Create the SelectionDAG nodes corresponding to a load
1200  // from this parameter.
1201  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1202  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1204  }
1205  }
1206 
1207  // If the function takes variable number of arguments, make a frame index for
1208  // the start of the first vararg value... for expansion of llvm.va_start.
1209  if (isVarArg) {
1210  unsigned StackSize = CCInfo.getNextStackOffset();
1211  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1212 
1213  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1214  }
1215 
1216  return Chain;
1217 }
1218 
1219 //===----------------------------------------------------------------------===//
1220 // Call Calling Convention Implementation
1221 //===----------------------------------------------------------------------===//
1222 
1223 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1224  SmallVectorImpl<SDValue> &InVals) const {
1225  SelectionDAG &DAG = CLI.DAG;
1226  SDLoc &DL = CLI.DL;
1227  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1228  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1229  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1230  SDValue Chain = CLI.Chain;
1231  SDValue Callee = CLI.Callee;
1232  bool &isTailCall = CLI.IsTailCall;
1233  CallingConv::ID CallConv = CLI.CallConv;
1234  bool isVarArg = CLI.IsVarArg;
1235 
1236  MachineFunction &MF = DAG.getMachineFunction();
1237 
1238  // AVR does not yet support tail call optimization.
1239  isTailCall = false;
1240 
1241  // Analyze operands of the call, assigning locations to each operand.
1242  SmallVector<CCValAssign, 16> ArgLocs;
1243  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1244  *DAG.getContext());
1245 
1246  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1247  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1248  // node so that legalize doesn't hack it.
1249  const Function *F = nullptr;
1250  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1251  const GlobalValue *GV = G->getGlobal();
1252 
1253  F = cast<Function>(GV);
1254  Callee =
1255  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1256  } else if (const ExternalSymbolSDNode *ES =
1257  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1258  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1259  getPointerTy(DAG.getDataLayout()));
1260  }
1261 
1262  // Variadic functions do not need all the analysis below.
1263  if (isVarArg) {
1264  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1265  } else {
1266  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1267  }
1268 
1269  // Get a count of how many bytes are to be pushed on the stack.
1270  unsigned NumBytes = CCInfo.getNextStackOffset();
1271 
1272  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1273 
1274  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1275 
1276  // First, walk the register assignments, inserting copies.
1277  unsigned AI, AE;
1278  bool HasStackArgs = false;
1279  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1280  CCValAssign &VA = ArgLocs[AI];
1281  EVT RegVT = VA.getLocVT();
1282  SDValue Arg = OutVals[AI];
1283 
1284  // Promote the value if needed. With Clang this should not happen.
1285  switch (VA.getLocInfo()) {
1286  default:
1287  llvm_unreachable("Unknown loc info!");
1288  case CCValAssign::Full:
1289  break;
1290  case CCValAssign::SExt:
1291  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1292  break;
1293  case CCValAssign::ZExt:
1294  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1295  break;
1296  case CCValAssign::AExt:
1297  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1298  break;
1299  case CCValAssign::BCvt:
1300  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1301  break;
1302  }
1303 
1304  // Stop when we encounter a stack argument, we need to process them
1305  // in reverse order in the loop below.
1306  if (VA.isMemLoc()) {
1307  HasStackArgs = true;
1308  break;
1309  }
1310 
1311  // Arguments that can be passed on registers must be kept in the RegsToPass
1312  // vector.
1313  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1314  }
1315 
1316  // Second, stack arguments have to walked in reverse order by inserting
1317  // chained stores, this ensures their order is not changed by the scheduler
1318  // and that the push instruction sequence generated is correct, otherwise they
1319  // can be freely intermixed.
1320  if (HasStackArgs) {
1321  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1322  unsigned Loc = AI - 1;
1323  CCValAssign &VA = ArgLocs[Loc];
1324  SDValue Arg = OutVals[Loc];
1325 
1326  assert(VA.isMemLoc());
1327 
1328  // SP points to one stack slot further so add one to adjust it.
1329  SDValue PtrOff = DAG.getNode(
1330  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1331  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1332  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1333 
1334  Chain =
1335  DAG.getStore(Chain, DL, Arg, PtrOff,
1336  MachinePointerInfo::getStack(MF, VA.getLocMemOffset()));
1337  }
1338  }
1339 
1340  // Build a sequence of copy-to-reg nodes chained together with token chain and
1341  // flag operands which copy the outgoing args into registers. The InFlag in
1342  // necessary since all emited instructions must be stuck together.
1343  SDValue InFlag;
1344  for (auto Reg : RegsToPass) {
1345  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1346  InFlag = Chain.getValue(1);
1347  }
1348 
1349  // Returns a chain & a flag for retval copy to use.
1350  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1351  SmallVector<SDValue, 8> Ops;
1352  Ops.push_back(Chain);
1353  Ops.push_back(Callee);
1354 
1355  // Add argument registers to the end of the list so that they are known live
1356  // into the call.
1357  for (auto Reg : RegsToPass) {
1358  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1359  }
1360 
1361  // Add a register mask operand representing the call-preserved registers.
1362  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1363  const uint32_t *Mask =
1364  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1365  assert(Mask && "Missing call preserved mask for calling convention");
1366  Ops.push_back(DAG.getRegisterMask(Mask));
1367 
1368  if (InFlag.getNode()) {
1369  Ops.push_back(InFlag);
1370  }
1371 
1372  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1373  InFlag = Chain.getValue(1);
1374 
1375  // Create the CALLSEQ_END node.
1376  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1377  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1378 
1379  if (!Ins.empty()) {
1380  InFlag = Chain.getValue(1);
1381  }
1382 
1383  // Handle result values, copying them out of physregs into vregs that we
1384  // return.
1385  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1386  InVals);
1387 }
1388 
1389 /// Lower the result values of a call into the
1390 /// appropriate copies out of appropriate physical registers.
1391 ///
1392 SDValue AVRTargetLowering::LowerCallResult(
1393  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1394  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1395  SmallVectorImpl<SDValue> &InVals) const {
1396 
1397  // Assign locations to each value returned by this call.
1398  SmallVector<CCValAssign, 16> RVLocs;
1399  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1400  *DAG.getContext());
1401 
1402  // Handle runtime calling convs.
1403  if (CallConv == CallingConv::AVR_BUILTIN) {
1404  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1405  } else {
1406  analyzeReturnValues(Ins, CCInfo);
1407  }
1408 
1409  // Copy all of the result registers out of their specified physreg.
1410  for (CCValAssign const &RVLoc : RVLocs) {
1411  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1412  InFlag)
1413  .getValue(1);
1414  InFlag = Chain.getValue(2);
1415  InVals.push_back(Chain.getValue(0));
1416  }
1417 
1418  return Chain;
1419 }
1420 
1421 //===----------------------------------------------------------------------===//
1422 // Return Value Calling Convention Implementation
1423 //===----------------------------------------------------------------------===//
1424 
1425 bool AVRTargetLowering::CanLowerReturn(
1426  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1427  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1428  if (CallConv == CallingConv::AVR_BUILTIN) {
1429  SmallVector<CCValAssign, 16> RVLocs;
1430  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1431  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1432  }
1433 
1434  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1435  return TotalBytes <= 8;
1436 }
1437 
1438 SDValue
1439 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1440  bool isVarArg,
1441  const SmallVectorImpl<ISD::OutputArg> &Outs,
1442  const SmallVectorImpl<SDValue> &OutVals,
1443  const SDLoc &dl, SelectionDAG &DAG) const {
1444  // CCValAssign - represent the assignment of the return value to locations.
1445  SmallVector<CCValAssign, 16> RVLocs;
1446 
1447  // CCState - Info about the registers and stack slot.
1448  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1449  *DAG.getContext());
1450 
1451  MachineFunction &MF = DAG.getMachineFunction();
1452 
1453  // Analyze return values.
1454  if (CallConv == CallingConv::AVR_BUILTIN) {
1455  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1456  } else {
1457  analyzeReturnValues(Outs, CCInfo);
1458  }
1459 
1460  SDValue Flag;
1461  SmallVector<SDValue, 4> RetOps(1, Chain);
1462  // Copy the result values into the output registers.
1463  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1464  CCValAssign &VA = RVLocs[i];
1465  assert(VA.isRegLoc() && "Can only return in registers!");
1466 
1467  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1468 
1469  // Guarantee that all emitted copies are stuck together with flags.
1470  Flag = Chain.getValue(1);
1471  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1472  }
1473 
1474  // Don't emit the ret/reti instruction when the naked attribute is present in
1475  // the function being compiled.
1476  if (MF.getFunction().getAttributes().hasAttribute(
1477  AttributeList::FunctionIndex, Attribute::Naked)) {
1478  return Chain;
1479  }
1480 
1481  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1482 
1483  unsigned RetOpc =
1484  AFI->isInterruptOrSignalHandler()
1486  : AVRISD::RET_FLAG;
1487 
1488  RetOps[0] = Chain; // Update chain.
1489 
1490  if (Flag.getNode()) {
1491  RetOps.push_back(Flag);
1492  }
1493 
1494  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1495 }
1496 
1497 //===----------------------------------------------------------------------===//
1498 // Custom Inserters
1499 //===----------------------------------------------------------------------===//
1500 
1501 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1502  MachineBasicBlock *BB) const {
1503  unsigned Opc;
1504  const TargetRegisterClass *RC;
1505  bool HasRepeatedOperand = false;
1506  MachineFunction *F = BB->getParent();
1507  MachineRegisterInfo &RI = F->getRegInfo();
1508  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1509  DebugLoc dl = MI.getDebugLoc();
1510 
1511  switch (MI.getOpcode()) {
1512  default:
1513  llvm_unreachable("Invalid shift opcode!");
1514  case AVR::Lsl8:
1515  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1516  RC = &AVR::GPR8RegClass;
1517  HasRepeatedOperand = true;
1518  break;
1519  case AVR::Lsl16:
1520  Opc = AVR::LSLWRd;
1521  RC = &AVR::DREGSRegClass;
1522  break;
1523  case AVR::Asr8:
1524  Opc = AVR::ASRRd;
1525  RC = &AVR::GPR8RegClass;
1526  break;
1527  case AVR::Asr16:
1528  Opc = AVR::ASRWRd;
1529  RC = &AVR::DREGSRegClass;
1530  break;
1531  case AVR::Lsr8:
1532  Opc = AVR::LSRRd;
1533  RC = &AVR::GPR8RegClass;
1534  break;
1535  case AVR::Lsr16:
1536  Opc = AVR::LSRWRd;
1537  RC = &AVR::DREGSRegClass;
1538  break;
1539  case AVR::Rol8:
1540  Opc = AVR::ROLBRd;
1541  RC = &AVR::GPR8RegClass;
1542  break;
1543  case AVR::Rol16:
1544  Opc = AVR::ROLWRd;
1545  RC = &AVR::DREGSRegClass;
1546  break;
1547  case AVR::Ror8:
1548  Opc = AVR::RORBRd;
1549  RC = &AVR::GPR8RegClass;
1550  break;
1551  case AVR::Ror16:
1552  Opc = AVR::RORWRd;
1553  RC = &AVR::DREGSRegClass;
1554  break;
1555  }
1556 
1557  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1558 
1560  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1561  if (I != F->end()) ++I;
1562 
1563  // Create loop block.
1564  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1565  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1566  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1567 
1568  F->insert(I, LoopBB);
1569  F->insert(I, CheckBB);
1570  F->insert(I, RemBB);
1571 
1572  // Update machine-CFG edges by transferring all successors of the current
1573  // block to the block containing instructions after shift.
1574  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1575  BB->end());
1576  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1577 
1578  // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1579  BB->addSuccessor(CheckBB);
1580  LoopBB->addSuccessor(CheckBB);
1581  CheckBB->addSuccessor(LoopBB);
1582  CheckBB->addSuccessor(RemBB);
1583 
1584  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1585  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1586  Register ShiftReg = RI.createVirtualRegister(RC);
1587  Register ShiftReg2 = RI.createVirtualRegister(RC);
1588  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1589  Register SrcReg = MI.getOperand(1).getReg();
1590  Register DstReg = MI.getOperand(0).getReg();
1591 
1592  // BB:
1593  // rjmp CheckBB
1594  BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1595 
1596  // LoopBB:
1597  // ShiftReg2 = shift ShiftReg
1598  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1599  if (HasRepeatedOperand)
1600  ShiftMI.addReg(ShiftReg);
1601 
1602  // CheckBB:
1603  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1604  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1605  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1606  // ShiftAmt2 = ShiftAmt - 1;
1607  // if (ShiftAmt2 >= 0) goto LoopBB;
1608  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1609  .addReg(SrcReg)
1610  .addMBB(BB)
1611  .addReg(ShiftReg2)
1612  .addMBB(LoopBB);
1613  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1614  .addReg(ShiftAmtSrcReg)
1615  .addMBB(BB)
1616  .addReg(ShiftAmtReg2)
1617  .addMBB(LoopBB);
1618  BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1619  .addReg(SrcReg)
1620  .addMBB(BB)
1621  .addReg(ShiftReg2)
1622  .addMBB(LoopBB);
1623 
1624  BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2)
1625  .addReg(ShiftAmtReg);
1626  BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1627 
1628  MI.eraseFromParent(); // The pseudo instruction is gone now.
1629  return RemBB;
1630 }
1631 
1633  if (I->getOpcode() == AVR::COPY) {
1634  Register SrcReg = I->getOperand(1).getReg();
1635  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1636  }
1637 
1638  return false;
1639 }
1640 
1641 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1642 // after the result has been evacuated. This is probably not the best way to do
1643 // it, but it works for now.
1644 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1645  MachineBasicBlock *BB) const {
1646  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1648  ++I; // in any case insert *after* the mul instruction
1649  if (isCopyMulResult(I))
1650  ++I;
1651  if (isCopyMulResult(I))
1652  ++I;
1653  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1654  .addReg(AVR::R1)
1655  .addReg(AVR::R1);
1656  return BB;
1657 }
1658 
1659 MachineBasicBlock *
1661  MachineBasicBlock *MBB) const {
1662  int Opc = MI.getOpcode();
1663 
1664  // Pseudo shift instructions with a non constant shift amount are expanded
1665  // into a loop.
1666  switch (Opc) {
1667  case AVR::Lsl8:
1668  case AVR::Lsl16:
1669  case AVR::Lsr8:
1670  case AVR::Lsr16:
1671  case AVR::Rol8:
1672  case AVR::Rol16:
1673  case AVR::Ror8:
1674  case AVR::Ror16:
1675  case AVR::Asr8:
1676  case AVR::Asr16:
1677  return insertShift(MI, MBB);
1678  case AVR::MULRdRr:
1679  case AVR::MULSRdRr:
1680  return insertMul(MI, MBB);
1681  }
1682 
1683  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1684  "Unexpected instr type to insert");
1685 
1686  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1687  ->getParent()
1688  ->getSubtarget()
1689  .getInstrInfo();
1690  DebugLoc dl = MI.getDebugLoc();
1691 
1692  // To "insert" a SELECT instruction, we insert the diamond
1693  // control-flow pattern. The incoming instruction knows the
1694  // destination vreg to set, the condition code register to branch
1695  // on, the true/false values to select between, and a branch opcode
1696  // to use.
1697 
1698  MachineFunction *MF = MBB->getParent();
1699  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1700  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1701 
1702  // If the current basic block falls through to another basic block,
1703  // we must insert an unconditional branch to the fallthrough destination
1704  // if we are to insert basic blocks at the prior fallthrough point.
1705  if (FallThrough != nullptr) {
1706  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1707  }
1708 
1709  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1710  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1711 
1713  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1714  if (I != MF->end()) ++I;
1715  MF->insert(I, trueMBB);
1716  MF->insert(I, falseMBB);
1717 
1718  // Transfer remaining instructions and all successors of the current
1719  // block to the block which will contain the Phi node for the
1720  // select.
1721  trueMBB->splice(trueMBB->begin(), MBB,
1722  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1724 
1725  AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1726  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1727  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1728  MBB->addSuccessor(falseMBB);
1729  MBB->addSuccessor(trueMBB);
1730 
1731  // Unconditionally flow back to the true block
1732  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1733  falseMBB->addSuccessor(trueMBB);
1734 
1735  // Set up the Phi node to determine where we came from
1736  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1737  .addReg(MI.getOperand(1).getReg())
1738  .addMBB(MBB)
1739  .addReg(MI.getOperand(2).getReg())
1740  .addMBB(falseMBB) ;
1741 
1742  MI.eraseFromParent(); // The pseudo instruction is gone now.
1743  return trueMBB;
1744 }
1745 
1746 //===----------------------------------------------------------------------===//
1747 // Inline Asm Support
1748 //===----------------------------------------------------------------------===//
1749 
1752  if (Constraint.size() == 1) {
1753  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1754  switch (Constraint[0]) {
1755  default:
1756  break;
1757  case 'a': // Simple upper registers
1758  case 'b': // Base pointer registers pairs
1759  case 'd': // Upper register
1760  case 'l': // Lower registers
1761  case 'e': // Pointer register pairs
1762  case 'q': // Stack pointer register
1763  case 'r': // Any register
1764  case 'w': // Special upper register pairs
1765  return C_RegisterClass;
1766  case 't': // Temporary register
1767  case 'x': case 'X': // Pointer register pair X
1768  case 'y': case 'Y': // Pointer register pair Y
1769  case 'z': case 'Z': // Pointer register pair Z
1770  return C_Register;
1771  case 'Q': // A memory address based on Y or Z pointer with displacement.
1772  return C_Memory;
1773  case 'G': // Floating point constant
1774  case 'I': // 6-bit positive integer constant
1775  case 'J': // 6-bit negative integer constant
1776  case 'K': // Integer constant (Range: 2)
1777  case 'L': // Integer constant (Range: 0)
1778  case 'M': // 8-bit integer constant
1779  case 'N': // Integer constant (Range: -1)
1780  case 'O': // Integer constant (Range: 8, 16, 24)
1781  case 'P': // Integer constant (Range: 1)
1782  case 'R': // Integer constant (Range: -6 to 5)x
1783  return C_Immediate;
1784  }
1785  }
1786 
1787  return TargetLowering::getConstraintType(Constraint);
1788 }
1789 
1790 unsigned
1792  // Not sure if this is actually the right thing to do, but we got to do
1793  // *something* [agnat]
1794  switch (ConstraintCode[0]) {
1795  case 'Q':
1796  return InlineAsm::Constraint_Q;
1797  }
1798  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1799 }
1800 
1803  AsmOperandInfo &info, const char *constraint) const {
1804  ConstraintWeight weight = CW_Invalid;
1805  Value *CallOperandVal = info.CallOperandVal;
1806 
1807  // If we don't have a value, we can't do a match,
1808  // but allow it at the lowest weight.
1809  // (this behaviour has been copied from the ARM backend)
1810  if (!CallOperandVal) {
1811  return CW_Default;
1812  }
1813 
1814  // Look at the constraint type.
1815  switch (*constraint) {
1816  default:
1818  break;
1819  case 'd':
1820  case 'r':
1821  case 'l':
1822  weight = CW_Register;
1823  break;
1824  case 'a':
1825  case 'b':
1826  case 'e':
1827  case 'q':
1828  case 't':
1829  case 'w':
1830  case 'x': case 'X':
1831  case 'y': case 'Y':
1832  case 'z': case 'Z':
1833  weight = CW_SpecificReg;
1834  break;
1835  case 'G':
1836  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1837  if (C->isZero()) {
1838  weight = CW_Constant;
1839  }
1840  }
1841  break;
1842  case 'I':
1843  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1844  if (isUInt<6>(C->getZExtValue())) {
1845  weight = CW_Constant;
1846  }
1847  }
1848  break;
1849  case 'J':
1850  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1851  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1852  weight = CW_Constant;
1853  }
1854  }
1855  break;
1856  case 'K':
1857  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1858  if (C->getZExtValue() == 2) {
1859  weight = CW_Constant;
1860  }
1861  }
1862  break;
1863  case 'L':
1864  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1865  if (C->getZExtValue() == 0) {
1866  weight = CW_Constant;
1867  }
1868  }
1869  break;
1870  case 'M':
1871  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1872  if (isUInt<8>(C->getZExtValue())) {
1873  weight = CW_Constant;
1874  }
1875  }
1876  break;
1877  case 'N':
1878  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1879  if (C->getSExtValue() == -1) {
1880  weight = CW_Constant;
1881  }
1882  }
1883  break;
1884  case 'O':
1885  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1886  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1887  (C->getZExtValue() == 24)) {
1888  weight = CW_Constant;
1889  }
1890  }
1891  break;
1892  case 'P':
1893  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1894  if (C->getZExtValue() == 1) {
1895  weight = CW_Constant;
1896  }
1897  }
1898  break;
1899  case 'R':
1900  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1901  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1902  weight = CW_Constant;
1903  }
1904  }
1905  break;
1906  case 'Q':
1907  weight = CW_Memory;
1908  break;
1909  }
1910 
1911  return weight;
1912 }
1913 
1914 std::pair<unsigned, const TargetRegisterClass *>
1916  StringRef Constraint,
1917  MVT VT) const {
1918  // We only support i8 and i16.
1919  //
1920  //:FIXME: remove this assert for now since it gets sometimes executed
1921  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1922 
1923  if (Constraint.size() == 1) {
1924  switch (Constraint[0]) {
1925  case 'a': // Simple upper registers r16..r23.
1926  return std::make_pair(0U, &AVR::LD8loRegClass);
1927  case 'b': // Base pointer registers: y, z.
1928  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1929  case 'd': // Upper registers r16..r31.
1930  return std::make_pair(0U, &AVR::LD8RegClass);
1931  case 'l': // Lower registers r0..r15.
1932  return std::make_pair(0U, &AVR::GPR8loRegClass);
1933  case 'e': // Pointer register pairs: x, y, z.
1934  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1935  case 'q': // Stack pointer register: SPH:SPL.
1936  return std::make_pair(0U, &AVR::GPRSPRegClass);
1937  case 'r': // Any register: r0..r31.
1938  if (VT == MVT::i8)
1939  return std::make_pair(0U, &AVR::GPR8RegClass);
1940 
1941  return std::make_pair(0U, &AVR::DREGSRegClass);
1942  case 't': // Temporary register: r0.
1943  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1944  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1945  return std::make_pair(0U, &AVR::IWREGSRegClass);
1946  case 'x': // Pointer register pair X: r27:r26.
1947  case 'X':
1948  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1949  case 'y': // Pointer register pair Y: r29:r28.
1950  case 'Y':
1951  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1952  case 'z': // Pointer register pair Z: r31:r30.
1953  case 'Z':
1954  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1955  default:
1956  break;
1957  }
1958  }
1959 
1961  Subtarget.getRegisterInfo(), Constraint, VT);
1962 }
1963 
1965  std::string &Constraint,
1966  std::vector<SDValue> &Ops,
1967  SelectionDAG &DAG) const {
1968  SDValue Result(0, 0);
1969  SDLoc DL(Op);
1970  EVT Ty = Op.getValueType();
1971 
1972  // Currently only support length 1 constraints.
1973  if (Constraint.length() != 1) {
1974  return;
1975  }
1976 
1977  char ConstraintLetter = Constraint[0];
1978  switch (ConstraintLetter) {
1979  default:
1980  break;
1981  // Deal with integers first:
1982  case 'I':
1983  case 'J':
1984  case 'K':
1985  case 'L':
1986  case 'M':
1987  case 'N':
1988  case 'O':
1989  case 'P':
1990  case 'R': {
1991  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1992  if (!C) {
1993  return;
1994  }
1995 
1996  int64_t CVal64 = C->getSExtValue();
1997  uint64_t CUVal64 = C->getZExtValue();
1998  switch (ConstraintLetter) {
1999  case 'I': // 0..63
2000  if (!isUInt<6>(CUVal64))
2001  return;
2002  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2003  break;
2004  case 'J': // -63..0
2005  if (CVal64 < -63 || CVal64 > 0)
2006  return;
2007  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2008  break;
2009  case 'K': // 2
2010  if (CUVal64 != 2)
2011  return;
2012  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2013  break;
2014  case 'L': // 0
2015  if (CUVal64 != 0)
2016  return;
2017  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2018  break;
2019  case 'M': // 0..255
2020  if (!isUInt<8>(CUVal64))
2021  return;
2022  // i8 type may be printed as a negative number,
2023  // e.g. 254 would be printed as -2,
2024  // so we force it to i16 at least.
2025  if (Ty.getSimpleVT() == MVT::i8) {
2026  Ty = MVT::i16;
2027  }
2028  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2029  break;
2030  case 'N': // -1
2031  if (CVal64 != -1)
2032  return;
2033  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2034  break;
2035  case 'O': // 8, 16, 24
2036  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2037  return;
2038  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2039  break;
2040  case 'P': // 1
2041  if (CUVal64 != 1)
2042  return;
2043  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2044  break;
2045  case 'R': // -6..5
2046  if (CVal64 < -6 || CVal64 > 5)
2047  return;
2048  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2049  break;
2050  }
2051 
2052  break;
2053  }
2054  case 'G':
2055  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2056  if (!FC || !FC->isZero())
2057  return;
2058  // Soften float to i8 0
2059  Result = DAG.getTargetConstant(0, DL, MVT::i8);
2060  break;
2061  }
2062 
2063  if (Result.getNode()) {
2064  Ops.push_back(Result);
2065  return;
2066  }
2067 
2068  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2069 }
2070 
2072  const MachineFunction &MF) const {
2073  Register Reg;
2074 
2075  if (VT == LLT::scalar(8)) {
2077  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
2078  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
2079  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
2080  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
2081  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
2082  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
2083  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
2084  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
2085  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2086  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2087  .Case("r30", AVR::R30).Case("r31", AVR::R31)
2088  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2089  .Default(0);
2090  } else {
2092  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2093  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2094  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2095  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2096  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2097  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2098  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2099  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2100  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2101  .Default(0);
2102  }
2103 
2104  if (Reg)
2105  return Reg;
2106 
2107  report_fatal_error("Invalid register name global variable");
2108 }
2109 
2110 } // end of namespace llvm
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
i
i
Definition: README.txt:29
llvm::AVRISD::LSR8
@ LSR8
Logical shift right 8 bits.
Definition: AVRISelLowering.h:44
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1354
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:978
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1532
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2094
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1365
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1022
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1290
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:51
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:194
llvm::StructType::get
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:366
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1362
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:34
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:838
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1366
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:1791
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:4840
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:265
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4103
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:936
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1321
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:59
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1136
llvm::Function
Definition: Function.h:61
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:249
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:234
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1290
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:656
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:921
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:253
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:262
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1361
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1002
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:742
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:55
llvm::AVR::ProgramMemory
@ ProgramMemory
Definition: AVR.h:40
ErrorHandling.h
llvm::isCopyMulResult
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
Definition: AVRISelLowering.cpp:1632
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:2813
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4124
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2251
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:73
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:249
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::TargetLowering::C_Memory
@ C_Memory
Definition: TargetLowering.h:4106
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1356
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:705
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2295
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:759
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:692
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::MVT::integer_valuetypes
static mvt_range integer_valuetypes()
Definition: MachineValueType.h:1372
llvm::AVRISD::LSL8
@ LSL8
Logical shift left 8 bits.
Definition: AVRISelLowering.h:40
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2261
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9280
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:66
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:53
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:875
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:851
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:818
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2830
STLExtras.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1031
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1321
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:946
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:722
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:650
llvm::analyzeReturnValues
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo)
Analyze incoming and outgoing value of returning from a function.
Definition: AVRISelLowering.cpp:1090
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:745
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:953
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:71
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:684
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:658
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:669
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:46
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:66
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1363
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:737
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2325
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1347
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:70
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:725
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:648
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:249
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2141
llvm::Instruction
Definition: Instruction.h:45
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:35
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:825
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1135
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2198
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:1964
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4104
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:257
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:740
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4107
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2089
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1325
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:37
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1660
llvm::AVRISD::ASR7
@ ASR7
Arithmetic shift right 7 bits.
Definition: AVRISelLowering.h:50
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:1802
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1353
llvm::Sched::RegPressure
@ RegPressure
Definition: TargetLowering.h:100
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:68
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1290
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:77
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2158
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::TargetLowering::CW_SpecificReg
@ CW_SpecificReg
Definition: TargetLowering.h:4121
NODE
#define NODE(name)
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:67
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1751
llvm::AVRISD::ASR8
@ ASR8
Arithmetic shift right 8 bits.
Definition: AVRISelLowering.h:47
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:57
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1133
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1575
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:60
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:195
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::getTotalArgumentsSizeInBytes
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
Definition: AVRISelLowering.cpp:1077
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2107
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1132
llvm::TargetLowering::CW_Register
@ CW_Register
Definition: TargetLowering.h:4122
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:7818
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1111
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4129
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:414
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:102
AVRTargetMachine.h
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:786
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2279
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:52
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1321
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:1915
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3694
llvm::AVRISD::LSL7
@ LSL7
Logical shift left 7 bits.
Definition: AVRISelLowering.h:48
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:612
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::AVRSubtarget::supportsMultiplication
bool supportsMultiplication() const
Definition: AVRSubtarget.h:71
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:847
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1355
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:64
AVRMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:931
llvm::TargetLowering::CW_Memory
@ CW_Memory
Definition: TargetLowering.h:4123
R6
#define R6(n)
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:706
llvm::RegList8
static const MCPhysReg RegList8[]
Registers for calling conventions, ordered in reverse as required by ABI.
Definition: AVRISelLowering.cpp:991
llvm::AVRISD::LSL4
@ LSL4
Logical shift left 4 bits.
Definition: AVRISelLowering.h:39
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1032
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4125
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:35
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:187
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:62
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:42
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:149
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
AVRSubtarget.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4471
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:863
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:237
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:244
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2323
uint32_t
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AVRISD::LSR12
@ LSR12
Logical shift right 12 bits.
Definition: AVRISelLowering.h:45
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:243
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:4550
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2178
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1125
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1321
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:301
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
llvm::RegList16
static const MCPhysReg RegList16[]
Definition: AVRISelLowering.cpp:995
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
j
return j(j<< 16)
llvm::AArch64_AM::ASR
@ ASR
Definition: AArch64AddressingModes.h:36
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1364
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2324
llvm::AVRISD::LSR7
@ LSR7
Logical shift right 7 bits.
Definition: AVRISelLowering.h:49
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2166
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1688
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2189
uint16_t
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2326
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4112
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:425
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:198
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:263
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:235
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:955
llvm::analyzeArguments
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo)
Analyze incoming and outgoing function arguments.
Definition: AVRISelLowering.cpp:1011
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:230
StringSwitch.h
AVR.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4114
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2808
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1027
llvm::CallingConv::AVR_BUILTIN
@ AVR_BUILTIN
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:194
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::intCCToAVRCC
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Definition: AVRISelLowering.cpp:495
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:707
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::AttributeList::FunctionIndex
@ FunctionIndex
Definition: Attributes.h:389
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2075
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:45
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:647
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:79
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:238
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:196
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2071
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1255
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:273
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1969
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:649
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4204
llvm::AVRISD::LSL12
@ LSL12
Logical shift left 12 bits.
Definition: AVRISelLowering.h:41
llvm::AVRISD::LSR4
@ LSR4
Logical shift right 4 bits.
Definition: AVRISelLowering.h:43
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:657
llvm::AVRInstrInfo
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2322
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:54
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:611
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:884
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:64
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:637
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1022
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:248
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2835
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:998
AVRISelLowering.h
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:272
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:651
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4410
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:343
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:659
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1134
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:215
llvm::AVR::isProgramMemoryAccess
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:47
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:498
TargetLoweringObjectFileImpl.h
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:56