59 SP::I0,
SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85 SP::I0,
SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
109 "Can't handle non-64 bits locations");
117 if (LocVT ==
MVT::i64 && Offset < 6*8)
119 Reg = SP::I0 + Offset/8;
120 else if (LocVT ==
MVT::f64 && Offset < 16*8)
122 Reg = SP::D0 + Offset/8;
123 else if (LocVT ==
MVT::f32 && Offset < 16*8)
125 Reg = SP::F1 + Offset/4;
126 else if (LocVT ==
MVT::f128 && Offset < 16*8)
128 Reg = SP::Q0 + Offset/16;
155 if (LocVT ==
MVT::f32 && Offset < 16*8) {
162 if (LocVT ==
MVT::i32 && Offset < 6*8) {
164 unsigned Reg = SP::I0 + Offset/8;
181 #include "SparcGenCallingConv.inc"
187 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
189 if (
Reg >= SP::I0 &&
Reg <= SP::I7)
190 return Reg - SP::I0 + SP::O0;
229 for (
unsigned i = 0, realRVLocIdx = 0;
231 ++
i, ++realRVLocIdx) {
263 unsigned RetAddrOffset = 8;
283 RetOps.push_back(
Flag);
314 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
343 if (
i+1 < RVLocs.size() && RVLocs[
i+1].getLocReg() == VA.
getLocReg()) {
362 RetOps.push_back(
Flag);
399 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i, ++InIdx) {
402 if (
Ins[InIdx].Flags.isSRet()) {
410 InVals.push_back(
Arg);
433 &SP::IntRegsRegClass);
443 InVals.push_back(WholeValue);
456 InVals.push_back(
Arg);
468 if (Offset % 8 == 0) {
475 InVals.push_back(
Load);
499 InVals.push_back(WholeValue);
517 InVals.push_back(
Load);
535 SP::I0,
SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
538 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
540 if (NumAllocated == 6)
544 ArgOffset = 68+4*NumAllocated;
550 std::vector<SDValue> OutChains;
552 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
566 if (!OutChains.empty()) {
567 OutChains.push_back(Chain);
589 const unsigned ArgArea = 128;
591 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
626 InVals.push_back(
Arg);
640 Offset += 8 - ValSize;
668 for (; ArgOffset < 6*8; ArgOffset += 8) {
678 if (!OutChains.empty())
695 return Call->hasFnAttr(Attribute::ReturnsTwice);
699 CalleeFn = dyn_cast<Function>(
G->getGlobal());
701 dyn_cast<ExternalSymbolSDNode>(
Callee)) {
704 const char *CalleeName =
E->getSymbol();
705 CalleeFn =
M->getFunction(CalleeName);
718 auto &Outs = CLI.
Outs;
722 if (Caller.getFnAttribute(
"disable-tail-calls").getValueAsString() ==
"true")
731 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
736 for (
auto &
Arg : Outs)
737 if (
Arg.Flags.isByVal())
771 ArgsSize = (ArgsSize+7) & ~7;
777 for (
unsigned i = 0,
e = Outs.size();
i !=
e; ++
i) {
791 Chain = DAG.
getMemcpy(Chain, dl, FIPtr,
Arg, SizeNode, Alignment,
796 ByValArgs.push_back(FIPtr);
800 ByValArgs.push_back(nullVal);
804 assert(!isTailCall || ArgsSize == 0);
813 bool hasStructRetAttr =
false;
814 unsigned SRetArgSize = 0;
816 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0,
e = ArgLocs.size();
826 Arg = ByValArgs[byvalArgIdx++];
860 MemOpChains.push_back(
862 hasStructRetAttr =
true;
864 assert(Outs[realArgIdx].OrigArgIndex == 0);
876 if (Offset % 8 == 0) {
880 MemOpChains.push_back(
903 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Part0));
907 RegsToPass.push_back(std::make_pair(NextVA.
getLocReg(), Part1));
914 MemOpChains.push_back(
923 MemOpChains.push_back(
928 MemOpChains.push_back(
938 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
942 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
953 MemOpChains.push_back(
959 if (!MemOpChains.empty())
967 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
990 Ops.push_back(Chain);
992 if (hasStructRetAttr)
994 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
998 Ops.push_back(DAG.
getRegister(
Reg, RegsToPass[
i].second.getValueType()));
1005 ?
TRI->getRTCallPreservedMask(CallConv)
1007 assert(
Mask &&
"Missing call preserved mask for calling convention");
1011 Ops.push_back(InFlag);
1033 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
1038 Chain = Lo.getValue(1);
1039 InFlag = Lo.getValue(2);
1044 Chain = Hi.getValue(1);
1045 InFlag = Hi.getValue(2);
1048 InVals.push_back(Vec);
1052 RVLocs[
i].getValVT(), InFlag)
1055 InVals.push_back(Chain.
getValue(0));
1068 .
Case(
"i4", SP::I4).
Case(
"i5", SP::I5).
Case(
"i6", SP::I6).
Case(
"i7", SP::I7)
1069 .
Case(
"o0", SP::O0).
Case(
"o1", SP::O1).
Case(
"o2", SP::O2).
Case(
"o3", SP::O3)
1070 .
Case(
"o4", SP::O4).
Case(
"o5", SP::O5).
Case(
"o6", SP::O6).
Case(
"o7", SP::O7)
1073 .
Case(
"g0", SP::G0).
Case(
"g1", SP::G1).
Case(
"g2", SP::G2).
Case(
"g3", SP::G3)
1074 .
Case(
"g4", SP::G4).
Case(
"g5", SP::G5).
Case(
"g6", SP::G6).
Case(
"g7", SP::G7)
1093 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1109 unsigned argSize = (ValTy ==
MVT::f64) ? 8 : 16;
1110 unsigned Offset = argSize * (VA.
getLocReg() - firstReg);
1111 assert(Offset < 16*8 &&
"Offset out of range, bad register enum?");
1115 unsigned IReg = SP::I0 + Offset/8;
1161 ArgsSize =
alignTo(ArgsSize, 16);
1182 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
1214 unsigned Offset = 8 * (VA.
getLocReg() - SP::I0);
1245 if (
i+1 < ArgLocs.size() && ArgLocs[
i+1].isRegLoc() &&
1246 ArgLocs[
i+1].getLocReg() == VA.
getLocReg()) {
1268 MemOpChains.push_back(
1273 if (!MemOpChains.empty())
1281 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
1283 RegsToPass[
i].first, RegsToPass[
i].second, InGlue);
1301 Ops.push_back(Chain);
1303 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i)
1305 RegsToPass[
i].second.getValueType()));
1310 ((hasReturnsTwice) ?
TRI->getRTCallPreservedMask(CLI.
CallConv)
1313 assert(
Mask &&
"Missing call preserved mask for calling convention");
1319 Ops.push_back(InGlue);
1342 CLI.
Ins[0].Flags.setInReg();
1347 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
1390 InVals.push_back(RV);
1637 if (Subtarget->
isV9())
1671 if (!Subtarget->
isV9()) {
1779 if (Subtarget->
isV9()) {
1921 const APInt &DemandedElts,
1923 unsigned Depth)
const {
1927 switch (
Op.getOpcode()) {
1955 SPCC = cast<ConstantSDNode>(
LHS.getOperand(2))->getZExtValue();
1967 GA->getValueType(0),
1968 GA->getOffset(), TF);
1972 CP->getAlign(),
CP->getOffset(), TF);
1982 ES->getValueType(0), TF);
1990 unsigned HiTF,
unsigned LoTF,
1993 EVT VT =
Op.getValueType();
2119 assert(
Mask &&
"Missing call preserved mask for calling convention");
2185 EVT ArgVT =
Arg.getValueType();
2202 Args.push_back(Entry);
2208 const char *LibFuncName,
2209 unsigned numArgs)
const {
2218 Type *RetTyABI = RetTy;
2227 Entry.Node = RetPtr;
2230 Entry.IsSRet =
true;
2231 Entry.IndirectType = RetTy;
2233 Entry.IsReturned =
false;
2234 Args.push_back(Entry);
2238 assert(
Op->getNumOperands() >= numArgs &&
"Not enough operands!");
2239 for (
unsigned i = 0,
e = numArgs;
i !=
e; ++
i) {
2249 if (RetTyABI == RetTy)
2262 unsigned &SPCC,
const SDLoc &
DL,
2265 const char *
LibCall =
nullptr;
2362 if (
Op.getOperand(0).getValueType() ==
MVT::f64)
2366 if (
Op.getOperand(0).getValueType() ==
MVT::f32)
2396 EVT VT =
Op.getValueType();
2403 ? RTLIB::FPTOSINT_F128_I32
2404 : RTLIB::FPTOSINT_F128_I64);
2425 EVT OpVT =
Op.getOperand(0).getValueType();
2434 ? RTLIB::SINTTOFP_I32_F128
2435 : RTLIB::SINTTOFP_I64_F128);
2446 return DAG.
getNode(opcode, dl,
Op.getValueType(), Tmp);
2453 EVT VT =
Op.getValueType();
2457 if (
Op.getOperand(0).getValueType() !=
MVT::f128 ||
2465 ? RTLIB::FPTOUINT_F128_I32
2466 : RTLIB::FPTOUINT_F128_I64),
2474 EVT OpVT =
Op.getOperand(0).getValueType();
2484 ? RTLIB::UINTTOFP_I32_F128
2485 : RTLIB::UINTTOFP_I64_F128),
2498 unsigned Opc, SPCC = ~0U;
2506 if (
LHS.getValueType().isInteger()) {
2535 unsigned Opc, SPCC = ~0U;
2542 if (
LHS.getValueType().isInteger()) {
2577 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2578 return DAG.
getStore(
Op.getOperand(0),
DL, Offset,
Op.getOperand(1),
2584 EVT VT = Node->getValueType(0);
2585 SDValue InChain = Node->getOperand(0);
2586 SDValue VAListPtr = Node->getOperand(1);
2588 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2611 cast<ConstantSDNode>(
Op.getOperand(2))->getMaybeAlignValue();
2613 EVT VT = Size->getValueType(0);
2622 "over-aligned dynamic alloca not supported.");
2627 unsigned regSpillArea;
2657 unsigned SPReg = SP::O6;
2666 SDValue Ops[2] = { NewVal, Chain };
2680 bool AlwaysFlush =
false) {
2684 EVT VT =
Op.getValueType();
2686 unsigned FrameReg = SP::I6;
2697 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2714 uint64_t depth =
Op.getConstantOperandVal(0);
2730 EVT VT =
Op.getValueType();
2732 uint64_t depth =
Op.getConstantOperandVal(0);
2745 unsigned Offset = (Subtarget->
is64Bit()) ? 120 : 60;
2903 &&
"invalid opcode");
2963 bool hasChain =
false;
2964 unsigned hiOpc =
Op.getOpcode();
2965 switch (
Op.getOpcode()) {
2975 Lo = DAG.
getNode(
Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2978 Lo = DAG.
getNode(
Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2980 SDValue Hi = DAG.
getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2981 SDValue Carry = Hi.getValue(1);
2989 SDValue Ops[2] = { Dst, Carry };
2998 unsigned opcode =
Op.getOpcode();
3007 if (
LHS.getValueType() != VT)
3025 CallOptions.
setSExt(isSigned);
3027 RTLIB::MUL_I128, WideVT,
3028 Args, CallOptions, dl).first;
3044 assert(MulResult->
use_empty() &&
"Illegally typed node still in use!");
3046 SDValue Ops[2] = { BottomHalf, TopHalf } ;
3062 unsigned IntNo = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
3066 case Intrinsic::thread_pointer: {
3077 bool isV9 = Subtarget->
isV9();
3079 switch (
Op.getOpcode()) {
3138 APInt V =
C->getValueAPF().bitcastToAPInt();
3151 if (isa<ConstantFPSDNode>(Src) &&
N->getSimpleValueType(0) ==
MVT::v2i32 &&
3152 Src.getSimpleValueType() ==
MVT::f64)
3160 switch (
N->getOpcode()) {
3172 switch (
MI.getOpcode()) {
3174 case SP::SELECT_CC_Int_ICC:
3175 case SP::SELECT_CC_FP_ICC:
3176 case SP::SELECT_CC_DFP_ICC:
3177 case SP::SELECT_CC_QFP_ICC:
3179 case SP::SELECT_CC_Int_XCC:
3180 case SP::SELECT_CC_FP_XCC:
3181 case SP::SELECT_CC_DFP_XCC:
3182 case SP::SELECT_CC_QFP_XCC:
3184 case SP::SELECT_CC_Int_FCC:
3185 case SP::SELECT_CC_FP_FCC:
3186 case SP::SELECT_CC_DFP_FCC:
3187 case SP::SELECT_CC_QFP_FCC:
3194 unsigned BROpcode)
const {
3217 F->insert(It, IfFalseMBB);
3218 F->insert(It, SinkMBB);
3238 MI.getOperand(0).getReg())
3244 MI.eraseFromParent();
3256 if (Constraint.
size() == 1) {
3257 switch (Constraint[0]) {
3273 const char *constraint)
const {
3275 Value *CallOperandVal =
info.CallOperandVal;
3278 if (!CallOperandVal)
3282 switch (*constraint) {
3288 if (isInt<13>(
C->getSExtValue()))
3300 std::string &Constraint,
3301 std::vector<SDValue> &Ops,
3306 if (Constraint.length() > 1)
3309 char ConstraintLetter = Constraint[0];
3310 switch (ConstraintLetter) {
3314 if (isInt<13>(
C->getSExtValue())) {
3323 if (Result.getNode()) {
3324 Ops.push_back(Result);
3330 std::pair<unsigned, const TargetRegisterClass *>
3334 if (Constraint.
empty())
3335 return std::make_pair(0U,
nullptr);
3337 if (Constraint.
size() == 1) {
3338 switch (Constraint[0]) {
3341 return std::make_pair(0U, &SP::IntPairRegClass);
3342 else if (Subtarget->
is64Bit())
3343 return std::make_pair(0U, &SP::I64RegsRegClass);
3345 return std::make_pair(0U, &SP::IntRegsRegClass);
3348 return std::make_pair(0U, &SP::FPRegsRegClass);
3350 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3352 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3354 return std::make_pair(0U,
nullptr);
3357 return std::make_pair(0U, &SP::FPRegsRegClass);
3359 return std::make_pair(0U, &SP::DFPRegsRegClass);
3361 return std::make_pair(0U, &SP::QFPRegsRegClass);
3363 return std::make_pair(0U,
nullptr);
3367 if (Constraint.
front() !=
'{')
3368 return std::make_pair(0U,
nullptr);
3370 assert(Constraint.
back() ==
'}' &&
"Not a brace enclosed constraint?");
3373 return std::make_pair(0U,
nullptr);
3375 unsigned long long RegNo;
3384 return std::make_pair(0U,
nullptr);
3385 const char RegTypes[] = {
'g',
'o',
'l',
'i'};
3386 char RegType = RegTypes[RegNo / 8];
3387 char RegIndex =
'0' + (RegNo % 8);
3388 char Tmp[] = {
'{', RegType, RegIndex,
'}', 0};
3395 if (VT ==
MVT::f64 && (RegNo % 2 == 0)) {
3398 }
else if (VT ==
MVT::f128 && (RegNo % 4 == 0)) {
3402 return std::make_pair(0U,
nullptr);
3408 if (!ResultPair.second)
3409 return std::make_pair(0U,
nullptr);
3413 assert(ResultPair.second == &SP::IntRegsRegClass &&
3414 "Unexpected register class");
3415 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3435 switch (
N->getOpcode()) {
3437 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
3442 if (
N->getOperand(0).getValueType() !=
MVT::f128
3446 ? RTLIB::FPTOSINT_F128_I64
3447 : RTLIB::FPTOUINT_F128_I64);
3461 Results.push_back(
N->getOperand(0));
3468 ||
N->getOperand(0).getValueType() !=
MVT::i64)
3472 ? RTLIB::SINTTOFP_I64_F128
3473 : RTLIB::UINTTOFP_I64_F128);