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80 printv(
unsigned r) : R(r) {}
116 unsigned n = RC.Bits.size();
124 bool ConstRef =
false;
126 for (
unsigned i = 1,
n = RC.Bits.size();
i <
n; ++
i) {
131 if (!IsRef && V == SV)
147 unsigned Count =
i - Start;
151 OS <<
'-' <<
i-1 <<
"]:";
154 << SV.
RefI.
Pos+(Count-1) <<
']';
159 SeqRef = ConstRef =
false;
163 unsigned Count =
n - Start;
165 OS <<
"]:" << RC[Start];
167 OS <<
'-' <<
n-1 <<
"]:";
171 << SV.
RefI.
Pos+(Count-1) <<
']';
183 for (
const std::pair<unsigned, RegisterCell>
P : Map)
205 bool Changed =
false;
208 Changed |= Bits[
i].meet(RCV,
BitRef(SelfR,
i));
230 Bits[
i] = RC[
i+(
W-
B)];
241 RC.Bits[
i-
B] = Bits[
i];
247 RC.Bits[
i] = Bits[
i+
B];
249 RC.Bits[
i+(
W-
B)] = Bits[
i];
267 Bits[
i] = Bits[
W-Sh+
i];
270 Bits[
i+Sh] = Tmp.Bits[
i];
288 Bits[
i+
W] = RC.Bits[
i];
296 while (
C <
W && Bits[
C] == V)
305 while (
C <
W && Bits[
W-(
C+1)] == V)
312 if (RC.Bits.size() !=
W)
315 if (Bits[
i] != RC[
i])
321 for (
unsigned i = 0,
n =
width();
i <
n; ++
i) {
364 CellMapType::const_iterator
F =
M.find(RR.
Reg);
369 return F->second.extract(
M);
382 assert(RR.
Sub == 0 &&
"Unexpected sub-register in definition");
391 if (!A[
i].
is(0) && !A[
i].
is(1))
425 assert((
unsigned)BW == A.getBitWidth() &&
"BitWidth overflow");
439 for (
I = 0;
I <
W; ++
I) {
442 if (!V1.
num() || !
V2.num())
444 unsigned S = bool(V1) + bool(
V2) + Carry;
455 else if (
V2.is(Carry))
472 for (
I = 0;
I <
W; ++
I) {
475 if (!V1.
num() || !
V2.num())
477 unsigned S = bool(V1) - bool(
V2) - Borrow;
560 else if (V1.
is(0) ||
V2.is(0))
578 if (V1.
is(1) ||
V2.is(1))
648 if ((
C < AW && A1[AW-1-
C].num()) ||
C == AW)
658 if ((
C < AW && A1[
C].num()) ||
C == AW)
670 Res.
fill(FromN,
W, Sign);
699 assert(AtN < W1 && AtN+W2 <= W1);
708 assert(Sub == 0 &&
"Generic BitTracker::mask called for Sub != 0");
710 assert(
W > 0 &&
"Cannot generate mask for empty register");
722 unsigned Opc =
MI.getOpcode();
724 case TargetOpcode::REG_SEQUENCE: {
728 unsigned SS =
MI.getOperand(2).getImm();
730 unsigned ST =
MI.getOperand(4).getImm();
741 case TargetOpcode::COPY: {
765 bool BT::UseQueueType::Cmp::operator()(
const MachineInstr *InstA,
782 auto F = Dist.find(
MI);
787 unsigned D = std::distance(
I,
E);
788 Dist.insert(std::make_pair(
MI,
D));
792 return getDist(InstA) > getDist(InstB);
803 assert(MD.
getSubReg() == 0 &&
"Unexpected sub-register in definition");
804 RegisterRef DefRR(MD);
807 RegisterCell DefC = ME.
getCell(DefRR, Map);
811 bool Changed =
false;
815 int PredN =
PB->getNumber();
819 if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
821 dbgs() <<
" not executable\n";
826 RegisterCell ResC = ME.
getCell(RU, Map);
829 <<
" cell: " << ResC <<
"\n";
830 Changed |= DefC.meet(ResC, DefRR.Reg);
836 <<
" cell: " << DefC <<
"\n";
838 visitUsesOf(DefRR.Reg);
845 if (
MI.isDebugInstr())
847 assert(!
MI.isBranch() &&
"Unexpected branch instruction");
854 if (!MO.isReg() || !MO.isUse())
858 <<
" cell: " << ME.
getCell(RU, Map) <<
"\n";
860 dbgs() <<
"Outputs:\n";
861 for (
const std::pair<const unsigned, RegisterCell> &
P : ResMap) {
862 RegisterRef RD(
P.first);
864 << ME.
getCell(RD, ResMap) <<
"\n";
872 if (!MO.isReg() || !MO.isDef())
875 assert(RD.Sub == 0 &&
"Unexpected sub-register in definition");
876 if (!RD.Reg.isVirtual())
879 bool Changed =
false;
880 if (!Eval || ResMap.count(RD.Reg) == 0) {
884 if (RefC != ME.
getCell(RD, Map)) {
889 RegisterCell DefC = ME.
getCell(RD, Map);
890 RegisterCell ResC = ME.
getCell(RD, ResMap);
898 for (
uint16_t i = 0, w = DefC.width();
i < w; ++
i) {
899 BitValue &V = DefC[
i];
921 bool FallsThrough =
true, DefaultToAll =
false;
922 int ThisN =
B.getNumber();
929 assert(
MI.isBranch() &&
"Expecting branch instruction");
930 InstrExec.insert(&
MI);
931 bool Eval = ME.
evaluate(
MI, Map, BTs, FallsThrough);
938 dbgs() <<
" failed to evaluate: will add all CFG successors\n";
939 }
else if (!DefaultToAll) {
942 dbgs() <<
" adding targets:";
946 dbgs() <<
"\n falls through\n";
948 dbgs() <<
"\n does not fall through\n";
950 Targets.insert(BTs.begin(), BTs.end());
953 }
while (FallsThrough && It != End);
955 if (
B.mayHaveInlineAsmBr())
969 if (Next != MF.
end())
970 Targets.insert(&*Next);
978 FlowQ.push(CFGEdge(ThisN,
TB->getNumber()));
1001 assert(Map.count(OldRR.
Reg) > 0 &&
"OldRR not present in map");
1007 assert((OME-OMB == NME-NMB) &&
1008 "Substituting registers of different lengths");
1009 for (std::pair<const unsigned, RegisterCell> &
P : Map) {
1026 int BN =
B->getNumber();
1028 return ReachedBB.
count(BN);
1034 assert(!
MI.isBranch() &&
"Only non-branches are allowed");
1035 InstrExec.insert(&
MI);
1042 while (!FlowQ.empty())
1054 void BT::runEdgeQueue(
BitVector &BlockScanned) {
1055 while (!FlowQ.empty()) {
1056 CFGEdge Edge = FlowQ.front();
1059 if (EdgeExec.count(Edge))
1061 EdgeExec.insert(Edge);
1062 ReachedBB.
insert(Edge.second);
1067 while (It != End && It->isPHI()) {
1069 InstrExec.insert(&PI);
1076 if (BlockScanned[Edge.second])
1078 BlockScanned[Edge.second] =
true;
1081 while (It != End && !It->isBranch()) {
1083 InstrExec.insert(&
MI);
1090 if (Next != MF.
end() &&
B.isSuccessor(&*Next)) {
1091 int ThisN =
B.getNumber();
1092 int NextN = Next->getNumber();
1093 FlowQ.push(CFGEdge(ThisN, NextN));
1098 visitBranchesFrom(*It);
1103 void BT::runUseQueue() {
1104 while (!UseQ.empty()) {
1108 if (!InstrExec.count(&UseI))
1113 visitNonBranch(UseI);
1115 visitBranchesFrom(UseI);
1128 assert(
B.getNumber() >= 0 &&
"Disconnected block");
1129 unsigned BN =
B.getNumber();
1137 int EntryN = Entry->getNumber();
1139 FlowQ.push(CFGEdge(-1, EntryN));
1141 while (!FlowQ.empty() || !UseQ.empty()) {
1142 runEdgeQueue(BlockScanned);
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
void subst(RegisterRef OldRR, RegisterRef NewRR)
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
BitTracker(const MachineEvaluator &E, MachineFunction &F)
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
static RegisterCell top(uint16_t Width)
void reserve(size_t Size)
Grow the DenseSet so that it can contain at least NumEntries items before resizing again.
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
RegisterCell & regify(unsigned R)
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
bool meet(const RegisterCell &RC, Register SelfR)
virtual uint16_t getPhysRegBitWidth(MCRegister Reg) const
static RegisterCell ref(const RegisterCell &C)
const APInt & getValue() const
Return the constant as an APInt value reference.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Reg
All possible values of the reg field in the ModR/M byte.
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const
std::map< unsigned, RegisterCell > CellMapType
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
static RegisterCell self(unsigned Reg, uint16_t Width)
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
std::pair< iterator, bool > insert(const ValueT &V)
virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
RegisterCell extract(const BitMask &M) const
void visit(const MachineInstr &MI)
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is the shared class of boolean and integer constants.
bool is(unsigned T) const
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
virtual bool track(const TargetRegisterClass *RC) const
RegisterCell & rol(uint16_t Sh)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool operator==(const RegisterCell &RC) const
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
bool isInt(const RegisterCell &A) const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
uint64_t toInt(const RegisterCell &A) const
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
static BitValue self(const BitRef &Self=BitRef())
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
void print_cells(raw_ostream &OS) const
SetVector< const MachineBasicBlock * > BranchTargetList
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
RegisterCell eIMM(int64_t V, uint16_t W) const
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
uint16_t cl(bool B) const
RegisterCell eNOT(const RegisterCell &A1) const
Representation of each machine instruction.
void put(RegisterRef RR, const RegisterCell &RC)
RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
MachineRegisterInfo & MRI
uint16_t ct(bool B) const
virtual BitMask mask(Register Reg, unsigned Sub) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool reached(const MachineBasicBlock *B) const
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
RegisterCell & cat(const RegisterCell &RC)
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Class for arbitrary precision integers.
RegisterCell get(RegisterRef RR) const
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
const MachineBasicBlock * getParent() const
this could be done in SelectionDAGISel along with other special for
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Iterator for intrusive lists based on ilist_node.
uint16_t getRegBitWidth(const RegisterRef &RR) const
const TargetRegisterInfo & TRI
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
static BitValue ref(const BitValue &V)
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
unsigned getNumOperands() const
Retuns the total number of operands.
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Wrapper class representing physical registers. Should be passed by value.